Entries |
Document | Title | Date |
20080279327 | SHIFT REGISTER AND SHIFT REGISTER APPARATUS THEREOF - A shift register and a shift register apparatus are provided. The shift register includes a plurality of shift register apparatus, and each shift register apparatus comprises a pre-charge circuit, a pull-up circuit and a pull-down circuit. The pre-charge circuit is used for sampling an input signal according to a first clock signal and a second clock signal respectively and generate a first charging signal and a second charging signal respectively. The pull-up circuit is coupled to the pre-charge circuit. The pull-up circuit receives the third clock signal and the first charging signal to output an output signal accordingly. The pull-down circuit is coupled to the pre-charge circuit and the pull-up circuit. The pull-down circuit receives the fourth clock signal and the second charging signal to decide whether to couple the output signal to a common potential. | 11-13-2008 |
20090010379 | Shift register for a liquid crystal display - A shift register of the present disclosure switches on and off various transistors in order to reduce power consumption. A high input voltage source and a low input voltage source of the shift register are spaced apart from each other so as to reduce signal noise distortion between the voltage sources. The shift register may be employed in a liquid crystal display (LCD). | 01-08-2009 |
20090041177 | SHIFT REGISTER ARRAYS - A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node. | 02-12-2009 |
20090129534 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias. | 05-21-2009 |
20090213981 | LOW-POWER REGISTER ARRAY FOR FAST SHIFT OPERATIONS - A data register ( | 08-27-2009 |
20090262884 | SWITCH SET OF BI-DIRECTIONAL SHIFT REGISTER MODULE - A switch set used in a bi-directional shift register circuit includes a plurality of switch devices. Each switch device is controlled by corresponding control signals to switch the direction of the input signal. One of the switch devices includes a first switch unit for transmitting a shift register signal from a previous shift register to a shift register according to a first control signal, a second switch unit for transmitting a shift register signal from a next shift register to the shift register according to a second control signal. The first and the second control signals have the same frequency as the clock signal of the shift register circuit. | 10-22-2009 |
20090310734 | DRIVER CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE - To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor | 12-17-2009 |
20100111245 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region. | 05-06-2010 |
20100150301 | Shift Register and Level Controller - A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first timing signal and first voltage, respectively. The level controller includes an input unit, a charge storage unit, a second level lifting unit and a second level lowering unit. The input unit controls the third control signal to be equal to the first voltage at a node. The charge storage unit stores a voltage of the timing signal at the node. The second level lifting unit and second level lowering unit respectively control the second control signal to be equal to the third control signal and the first voltage to turn on and turn off the first level lowering unit. | 06-17-2010 |
20100183114 | Shift Register and Driving Method Thereof - A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this mariner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided | 07-22-2010 |
20100246750 | Semiconductor Device and Electronic Device Including Semiconductor Device - It is an object to suppress deterioration in characteristics of a transistor in a driver cricuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off. | 09-30-2010 |
20100303195 | GATE DRIVER HAVING AN OUTPUT ENABLE CONTROL CIRCUIT - A gate driver includes a shift register, a logic control circuit, and an output enable control circuit. The shift register generates a plurality of scan signals according to a vertical synchronous signal and a vertical clock signal. The output enable control circuit generates a second output enable signal according to the vertical synchronous signal, the vertical clock signal, and an output enable signal. After the vertical synchronous signal and the vertical clock signal are both triggered together for two times, the second output enable converts from a high level to a low level. The logic control circuit outputs the plurality of scan signals when the second output enable signal is at the low level. | 12-02-2010 |
20110002437 | SHIFT REGISTERS - A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal. | 01-06-2011 |
20110044423 | SHIFT REGISTER - A shift register includes a plurality of electrically connected shift units. Each shift unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit outputs a first signal to an output node according to the first signal and a voltage of a driving node. The pull-up driving drives the pull-up circuit according to an output voltage of the previous shift unit. The pull-down driving circuit outputs a low level voltage to the driving node and the output node according to the first signal and a second signal. The pull-down circuit resets the pull-up driving circuit according to the voltage of the output node and outputs the low level voltage to the output node and the driving node according to a third signal and a fourth signal. | 02-24-2011 |
20110058640 | SHIFT REGISTER UNIT AND GATE DRIVE DEVICE FOR LIQUID CRYSTAL DISPLAY - An embodiment of the present invention discloses a shift register unit and a gate drive device for a liquid crystal display. The shift register unit, on the basis of a structure of 12 transistors and 1 capacitor in the prior art, enables both the drain of the seventh thin film transistor and the gate and the drain of the ninth thin film transistor being connected to the second clock signal input terminal, such that a leakage current would not be generated among the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor and the tenth thin film transistor when a high level signal is outputted from the shift register unit, thus power consumption of the shift register unit may be reduced. | 03-10-2011 |
20110069806 | PULL-DOWN CONTROL CIRCUIT AND SHIFT REGISTER OF USING SAME - The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T | 03-24-2011 |
20110122988 | Semiconductor device and shift register circuit - A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level. | 05-26-2011 |
20110142191 | SHIFT REGISTER CIRCUIT - A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit. | 06-16-2011 |
20110150169 | SHIFT REGISTER - A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor is electrically coupled to a predetermined voltage, the source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the drain/source of the dual-gate transistor is electrically coupled to the clock signal. The pull-down circuit pulls a potential at the first gate and another potential at the output terminal down to a power supply potential during the pull-up circuit is disabled | 06-23-2011 |
20110176653 | LOW CONSUMPTION FLIP-FLOP CIRCUIT WITH DATA RETENTION AND METHOD THEREOF - The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated. | 07-21-2011 |
20110255652 | SHIFT REGISTER - An exemplary shift register includes a control circuit and an output circuit. The control circuit is electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal. A logic low level of the first clock pulse signal is lower than a level of the power supply voltage. The output circuit is subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal. The second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage. | 10-20-2011 |
20110274234 | SHIFT REGISTER - A shift register of at least one embodiment of the present invention is a shift register supported by an insulative substrate, wherein: the shift register includes a plurality of stages each sequentially outputting output signals; each of the plurality of stages includes a first transistor for outputting the output signals, and a plurality of second transistors whose source region or drain region is electrically connected to a gate electrode of the first transistor; and the plurality of second transistors include a multi-channel transistor having an active layer including at least two channel regions, a source region and a drain region. This improves characteristics of a shift register forming a monolithic gate driver. | 11-10-2011 |
20110274235 | SHIFT REGISTER - A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops. | 11-10-2011 |
20110280362 | SHIFT REGISTER - A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line. | 11-17-2011 |
20110286571 | SHIFT REGISTER WITH EMBEDDED BIDIRECTIONAL SCANNING FUNCTION - The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively. | 11-24-2011 |
20120027160 | SHIFT REGISTER CIRCUIT - A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region. | 02-02-2012 |
20120082287 | SHIFT REGISTER - A shift register of the present invention is a shift register supported by an insulative substrate, wherein: the shift register includes a plurality of stages each sequentially outputting output signals from an output terminal; each of the plurality of stages includes a first transistor (MA) for pulling up a potential of the output terminal, a plurality of second transistors (ME and MF) whose source region or drain region is electrically connected to a gate electrode of the first transistor (MA), and at least one third transistor (MCd) receiving a clock signal supplied to a gate electrode thereof; and the at least one third transistor (MCd) includes a multi-channel transistor (MCd) having an active layer including at least two channel regions, a source region and a drain region. This improves characteristics of a shift register forming a monolithic gate driver. | 04-05-2012 |
20120087459 | Shift Register And Display Device - To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element. | 04-12-2012 |
20120087460 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a circuit including a plurality of thin film transistors and at least one diode (D | 04-12-2012 |
20120099696 | SHIFT REGISTER, ELECTRONIC DEVICE, CONTROL METHOD AND SOFTWARE PROGRAM PRODUCT - Disclosed is a shift register ( | 04-26-2012 |
20120121061 | SHIFT REGISTER - A shift register according to the present invention is supported on an insulating substrate and has multiple stages that sequentially shift an output signal from one stage to the next. Each of those stages has a circuit | 05-17-2012 |
20120163528 | SHIFT REGISTER - Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node. | 06-28-2012 |
20120170706 | DATA DRIVER AND DISPLAY APPARATUS USING THE SAME INCLUDING CLOCK CONTROL CIRCUIT AND SHIFT REGISTER CIRCUIT - A circuit includes a first shift register configured to be reset with a reset signal, to shift a first pulse signal and output the shifted first pulse signal as a second pulse signal, and a second shift register configured to be reset with the first pulse signal, to shift the second pulse signal and to output the shifted second pulse signal as a third pulse signal. | 07-05-2012 |
20120207266 | SHIFT REGISTER CIRCUIT - A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit. | 08-16-2012 |
20120213323 | SHIFT REGISTER WITH LOW POWER CONSUMPTION - A shift register comprising a plurality of shift register stages {S | 08-23-2012 |
20120294411 | SHIFT REGISTER AND ROW-SCAN DRIVING CIRCUIT - The present invention discloses a shift register and a row-scan driving circuit including the same, the shift register comprising a first thin film transistor, a second thin film transistor used as an evaluating transistor, a third thin film transistor, a fourth thin film transistor used as a resetting transistor, a first capacitor and a reset voltage controlling unit, wherein the reset voltage controlling unit is used to control the gate voltage of the fourth thin film transistor, so that the gate voltage of the fourth thin film transistor is pulled down to a low level corresponding to a voltage input from a low voltage signal input when a signal input from a first clock signal input is at low level, a signal input from a second clock signal input is at high level and a signal input from a signal input is at high level. | 11-22-2012 |
20120307959 | SHIFT REGISTER - In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T | 12-06-2012 |
20130010916 | Gate Driving Circuit - Disclosed herein is a gate driving circuit including a first clock generator to sequentially output n output clock pulses, a second clock generator to sequentially output n output control clock pulses, and a shift register to receive the n output clock pulses and the n output control clock pulses and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th output clock pulses output during adjacent periods overlap with one another, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k−a)-th output clock pulse, a high section of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th output clock pulse falls during the high section of the output control clock pulses not overlapping with that of the k-th output clock pulse. | 01-10-2013 |
20130016804 | SHIFT REGISTERAANM AHN; Jung-EunAACI GyeongbukAACO KRAAGP AHN; Jung-Eun Gyeongbuk KRAANM Jung; Bo-YoungAACI Gumi-siAACO KRAAGP Jung; Bo-Young Gumi-si KRAANM Chae; Ji-EunAACI Gumi-siAACO KRAAGP Chae; Ji-Eun Gumi-si KR - A shift register is discussed in which a pull-up switching device is turned off positively in a period in which no scan pulse is forwarded for securing drive stability and prevents a picture quality from becoming poor. The shift register in one embodiment includes stages having any one of first and second start pulses, and any one of first to fourth clock pulses to forward a scan pulse in succession, wherein the first and second start pulses are in gate high voltage states for two horizontal periods, with the second start pulse forwarded with a delay of one horizontal period than the first start pulse. The first to fourth clock pulses are in gate high voltages for two horizontal periods, with one horizontal period delay to one another. | 01-17-2013 |
20130028370 | SHIFT REGISTER - A shift register is formed by connecting unit circuits | 01-31-2013 |
20130044854 | SHIFT REGISTER AND DISPLAY DEVICE - Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal. | 02-21-2013 |
20130070891 | SHIFT REGISTER OF LCD DEVICES - A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage. | 03-21-2013 |
20130077735 | SHIFT REGISTER CIRCUIT - A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode are formed from the same layer. | 03-28-2013 |
20130108006 | SHIFT REGISTER CIRCUIT | 05-02-2013 |
20130121456 | DRIVER CIRCUIT, DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT, AND ELECTRONIC APPLIANCE INCLUDING THE DISPLAY DEVICE - An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit. | 05-16-2013 |
20130136224 | SHIFT REGISTER, GATE DRIVER, AND DISPLAY DEVICE - The present invention relates to a display device field, and provides a shift register, a gate driver, and a display device. The shift register comprises an input programming unit, a latch unit, an output programming unit and an inverting output unit; the input programming unit is connected to the input end of the latch unit to program the input end of the latch unit; the latch unit is used for latching the output signal, and a non-inverting output end and an inverting output end of the latch unit are connected through the output programming unit; the output programming unit is connected to the output end of the latch unit to program the output end of the latch unit; the inverting output unit is connected to the inverting output end of the latch unit and is used for generating a inverting output signal of the shift register. | 05-30-2013 |
20130156148 | FLIP FLOP, SHIFT REGISTER, DRIVER CIRCUIT, AND DISPLAY DEVICE - A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initialization section controlling the discharge section and the second output section. This makes it possible to realize a shift register capable of performing an all-ON operation regardless of clock signals. | 06-20-2013 |
20130170606 | SHIFT REGISTER - A shift register includes unit circuits connected in multiple stages, each of the unit circuits includes: a final buffer unit having an output transistor; and a signal A generating unit which supplies a first signal to a gate of the output transistor, the signal A generating unit includes: a capacitor; a transistor which switches conduction and non-conduction between the gate the output transistor and one of electrodes of the capacitor by a voltage from a clock signal line; a transistor which switches conduction and non-conduction between the other of the electrodes of the capacitor and the clock signal line by a voltage from an input line; and a transistor having a gate connected to a fixed power supply line, and which switches conduction and non-conduction between the one electrode of the first capacitor and the input line. | 07-04-2013 |
20130177128 | SHIFT REGISTER AND METHOD THEREOF - Shift register and method thereof are provided. The proposed shift register includes a first to a third transistors, each of which has a first terminal, a second terminal and a control terminal, wherein the second terminal of the first transistor, the control terminal of the second transistor and the first terminal of the third transistor are electrically connected to a node, and the first terminal of the first transistor is electrically connected to the control terminal of the first transistor. | 07-11-2013 |
20130223584 | Semiconductor Device - A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included. | 08-29-2013 |
20130243149 | SEMICONDUCTOR DEVICE AND SHIFT REGISTER - Data can be stored even when the supply of a power source voltage is stopped. A semiconductor device includes a logic circuit to which a data signal is input through an input terminal; a capacitor having a pair of electrodes, one of which is supplied with a high power source potential or a low power source potential and the other of which is supplied with a potential of the input terminal of the logic circuit, so that data of the data signal is written as stored data to the capacitor; and a transistor for controlling conduction between the input terminal of the logic circuit and the other of the pair of electrodes of the capacitor, thereby controlling rewriting, storing, and reading of the stored data. The off-state current per micrometer of channel width of the transistor is lower than or equal to 100 zA. | 09-19-2013 |
20130243150 | SHIFT REGISTER - A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node. | 09-19-2013 |
20130251091 | PULSE OUTPUT CIRCUIT, SHIFT REGISTER AND ELECTRONIC EQUIPMENT - A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs | 09-26-2013 |
20130266113 | BUFFER CIRCUIT AND BUFFER CIRCUIT DRIVING METHOD - A buffer circuit driving method for driving a buffer circuit including: an output terminal; a first transistor connected to a signal source of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal; and a second transistor connected to a voltage source that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal, includes: causing the first transistor to switch to a conducting state in a period where the clock signal is of the first voltage; and causing the first transistor and the second transistor to switch to the conducting state in a period where the clock signal is of the second voltage, following the period where the clock signal is of the first voltage. | 10-10-2013 |
20130272486 | SHIFT REGISTER CIRCUIT USING A SWITCH DEVICE - A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage. | 10-17-2013 |
20130301792 | SHIFT REGISTER - A shift register is discussed in which a pull-up switching device is turned off positively in a period in which no scan pulse is forwarded for securing drive stability and prevents a picture quality from becoming poor. The shift register in one embodiment includes stages having any one of first and second start pulses, and any one of first to fourth clock pulses to forward a scan pulse in succession, wherein the first and second start pulses are in gate high voltage states for two horizontal periods, with the second start pulse forwarded with a delay of one horizontal period than the first start pulse. The first to fourth clock pulses are in gate high voltages for two horizontal periods, with one horizontal period delay to one another. | 11-14-2013 |
20130301793 | SHIFT REGISTER CIRCUIT - An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period). | 11-14-2013 |
20130308743 | SHIFT REGISTER CIRCUIT, DISPLAY PANEL, AND ELECTRONIC APPARATUS - Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor. | 11-21-2013 |
20130322592 | PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER - To provide a pulse signal output circuit and a shift register which have lower power consumption, are not easily changed over time, and have a longer lifetime. A pulse signal output circuit includes a first input signal generation circuit; a second input signal generation circuit; an output circuit which includes a first transistor and a second transistor and outputs a pulse signal in response to a signal output from the first and second input signal generation circuits; a monitor circuit which obtains the threshold voltages of the first and second transistors; and a power supply output circuit which generates a power supply potential raised by a potential higher than or equal to a potential which is equal to or substantially equal to the threshold voltage and supplies the power supply potential to the first and second input signal generation circuits. A shift register includes the pulse signal output circuit. | 12-05-2013 |
20130329850 | SHIFT REGISTER AND ONE-OF-MANY SHIFT REGISTER - A shift register has a first latch and a second latch and a first output circuit and a second output circuit. The first latch and the second latch are series-connected. The latches are implemented to take over a signal state applied to their data inputs in a transparent state and to maintain the taken-over signal state in a non-transparent operating state. Clock inputs of the latches are switched such that the second latch is in the transparent operating state when the first latch is in the non-transparent operating state and vice versa. The first output circuit is implemented to provide a predetermined level independent of the signal state existing in the first latch at a first shift register output of the shift register in the transparent operating state and to provide a level depending on the signal state stored in the first latch in the non-transparent operating state of the first latch. The second output circuit is implemented to provide a predetermined level independent of the signal state existing in the second latch at a second shift register output of the shift register in the transparent operating state of the second latch and to provide a level depending on the signal state stored in the second latch in the non-transparent operating state of the second latch. | 12-12-2013 |
20140023174 | SHIFT REGISTER - A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line. | 01-23-2014 |
20140037043 | GATE DRIVING CIRCUIT AND DISPLAY DEVICE USING THE SAME - An embodiments herein relate to a gate driving circuit and display device which include a plurality of shift registers. The gate driving circuit comprises: a plurality of shift registers, wherein each of the shift registers includes a plurality of stages which sequentially output a gate signal, wherein the stages of a kth shift register are activated when a kth SR selection signal generated as a first logic level voltage is input, and the stages of the kth shift register are not activated when the kth SR selection signal generated as a second logic level voltage is input, wherein k is a natural number equal to or less than the number of the shift registers. | 02-06-2014 |
20140044228 | Shift Register - Disclosed herein is a shift register which is capable of preventing leakage of charges at a set node which occurs when the duty ratio of a scan pulse is small, so as to normally output a scan pulse. The shift register includes a plurality of stages for sequentially generating outputs thereof. Each of the stages includes a carry output unit for outputting a carry pulse to drive at least one of a downstream stage and an upstream stage, and a scan output unit for outputting a scan pulse to drive a gate line. Each of the outputs generated from the stages includes the carry pulse and the scan pulse. The carry pulse and the scan pulse are paired to correspond to each other. The paired carry pulse and scan pulse have different durations. | 02-13-2014 |
20140064436 | Shift Register, Driving Circuit, And Display Apparatus - The present disclosure provides a shift register for delaying and outputting a received startup voltage and meanwhile outputting a voltage inverse to the delayed startup voltage. The shift register including: a voltage shifting module ( | 03-06-2014 |
20140064437 | SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING APPARATUS AND DISPLAY APPARATUS - A shift register and driving method thereof, a gate driving apparatus and a display apparatus, the shift register comprises a pulling-up unit( | 03-06-2014 |
20140064438 | Shift Register, Gate Driving Circuit And Display - A shift register, comprising a plurality of shift register sub-units connected in cascade, each of the plurality of shift register sub-units comprising first to third TFTs, an eleventh TFT, a first capacitor and a first reset control module for controlling the second TFT to be turned on or off. Besides the shift register sub-unit at a first stage, for each of the shift register sub-units at other stages, the second TFT gate control terminal thereof is connected to the third TFT gate control terminal of the shift register sub-unit at a previous stage. Accordingly, a gate driving circuit comprising the shift register and a display comprising the gate driving circuit are provided. Compared with the prior art, reliability of the shift register is highly improved and area occupied by the shift register is smaller. | 03-06-2014 |
20140072092 | SHIFT REGISTER - A shift register includes a plurality of stages for sequentially outputting A-scan pulses and B-scan pulses. At least one of the stages includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse based on the voltage at the B-set node, the voltage at the B-reset node and any one B1-clock pulse, and a scan output controller for generating a corresponding one of the A-scan pulses and a corresponding one of the B-scan pulses. | 03-13-2014 |
20140079173 | SHIFTING REGISTER UNIT, SHIFTING REGISTER, DISPLAY APPARATUS AND DRIVING METHOD THEREOF - The embodiments of the present invention provide a shifting register unit, a shifting register, a display apparatus and a driving method thereof, which can solve the problem that the displaying lines close to the bottom of a display panel can not operate normally due to the accumulation of the delays present in the existing shifting register unit and the problem that the lifespan of the third thin-film transistor is affected by the frequent switching-on thereof. The technical solutions allows the trigger signal of the (n+1)th shifting register unit stage to be provided by the first clock signal transmitted from the INPUT_NEXT terminal of the nth shifting register stage, and it can avoid the delay due to the trigger signal of the (n+1)th shifting register unit stage being provided by an output signal of the nth shifting register unit stage, and it can solve the technical problem that the display lines close to the bottom of the display panel can not operate normally due to the accumulation of the delays. Further, after the nth shifting register unit stage outputs the output signal and before the next input signal arrives, the pull-down node remains at high-level under the alternating control of the two clock signals. Thereby, it can be ensured that the pull-up node PU and the output terminal continue to be discharged, and thus the problem that the lifespan of the third thin-film transistor is affected by the frequent switching-on thereof can be solved. | 03-20-2014 |
20140079174 | SHIFT REGISTER CIRCUIT - An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period). | 03-20-2014 |
20140086379 | DRIVING CIRCUIT, SHIFTING REGISTER, GATE DRIVER, ARRAY SUBSTRATE AND DISPLAY DEVICE - The disclosure relates to the field of liquid crystal display, and provides a driving circuit, a shifting register, a gate driver, an array substrate and a display device. The driving circuit comprises a pull-up module, a first pull-down module, a second pull-down module, a pull-up driving module, a pull-down driving module and a resetting module, wherein the first pull-down module outputs a switching-off signal to the output terminal according to a signal input from the clock retarding signal input terminal and a signal at a pull-down node; a second pull-down module, when the signal input from the signal input terminal is at a low level, outputs a switching-off signal to the pull-up node and the output terminal according to a signal input from a clock signal input terminal; wherein when the signal input from the signal input terminal is at a high level, the signal input from the clock retarding signal input terminal is also at a high level, and the signal input from the clock signal input terminal and that input from the clock retarding signal input terminal are opposite in phase. The driving circuit according to the disclosure can effectively remove the defect of the threshold voltage drifting due to the gate being applied to a bias voltage stress, and can also decrease the noise of the output voltage. | 03-27-2014 |
20140093027 | SHIFT REGISTER - A shift register includes a plurality of stages, each of which outputs a carry pulse and a scan pulse. An nth one of the stages includes a carry output switching device controlled by a voltage applied to a set node and connected between a carry clock transfer line transferring any one of i carry clock pulses and a carry output terminal of the nth stage, a scan output switching device controlled by the voltage applied to the set node and connected between a scan clock transfer line transferring any one of j scan clock pulses and a scan output terminal of the nth stage, and a stabilization switching device controlled by any one of the i carry clock pulses and connected between a carry output terminal of an (n−p)th one of the stages and the set node or between a start transfer line and the set node. | 04-03-2014 |
20140093028 | SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, SHIFT REGISTER AND DISPLAY APPARATUS - The present disclosure relates to a shift register unit and a driving method thereof, a shift register and a display apparatus. The shift register unit includes a carry signal output terminal(CA(n)); a driving signal output terminal(OUT(n)); a staged output module( | 04-03-2014 |
20140105351 | SHIFT REGISTER - A shift register includes a plurality of shift register circuits, where an Nth shift register circuit of the shift register includes a driving unit, a boost unit, a pull up unit, and a key pull down unit. The driving unit is for providing a gate signal, a first boost control signal, and a first transmission control signal according a first driving signal and a high frequency clock signal. The boost unit is for boosting the voltage of the first driving signal according to a first boost signal. The pull up unit is for providing a second driving signal according to the first transmission control signal and the gate signal, and is for providing a second boost signal according to the first boost control signal and a second boost control signal. The key pull down unit is for pulling down the first driving signal according to a second transmission control signal. | 04-17-2014 |
20140119490 | SHIFT REGISTER, METHOD FOR DRIVING THE SAME, AND ARRAY SUBSTRATE - The disclosure relates to a shift register, a method for driving the same, an array substrate and a display apparatus, for reducing the wiring space as required by the shift register. The shift register comprising a control unit and a plurality of output sub-units, wherein the control unit comprises a plurality of output terminals which output gate line control signals sequentially according to the control timing sequence during a first preset time period, and output the gate line control signals sequentially according to the control timing sequence during a second preset time period in an order opposite to or identical to an order in which the gate line control signals are output during the first preset time period; each of the output sub-units is connected to a corresponding output terminal of the control unit, and divides the gate line control signal output from the connected output terminal into at least a first gate line control signal and a second gate line control signal, and outputs the first gate line control signal and the second gate line control signal respectively. | 05-01-2014 |
20140119491 | SHIFT REGISTER AND METHOD FOR DRIVING THE SAME, GATE DRIVING DEVICE AND DISPLAY DEVICE - The embodiments of the present invention provide a shift register and a method for driving the same, a gate driving device and a display device. A charging unit, a pull-up unit, a pull-down unit, a gate signal input terminal, a DC low level signal input terminal, a gate signal output terminal and a first, a second, a third, a fourth clock signal input terminals are arranged in the shift register, so that the gate driving structure is simplified and the power consumption of the gate driving is reduced. | 05-01-2014 |
20140119492 | SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT, ARRAY SUBSTRATE AND DISPLAY APPARATUS - A shift register unit, a gate driving circuit, an array substrate and a display apparatus are disclosed to reduce noises generated at an output of a next stage shift register unit caused by an output of a pervious stage shift register unit. The shift register unit at each stage comprises at least a signal inputting terminal INPUT, a signal outputting terminal OUTPUT and a capacitor CAP connected with the outputting terminal OUTPUT so as to provide an output signal to the outputting terminal OUTPUT, wherein the shift register unit further comprises a switch located between the capacitor CAP and the outputting terminal OUTPUT, and the switch is in a turned-off state when the capacitor CAP is charged. | 05-01-2014 |
20140119493 | SHIFT REGISTER AND GATE DRIVING DEVICE ON ARRAY SUBSTRATE - Provided are a shift register and a gate driving device on array substrate for eliminating noise at an output terminal of the shift register and improving the operating stability thereof. The shift register comprises an input module for supplying an input signal to a pull-up node, wherein the pull-up node serves as an output node of the input module; a pull-up module for storing the input signal and supplies a first clock signal to the output terminal; a reset module for supplying a negative voltage of a power supply to the pull-up node; a first pull-down control module for supplying the negative voltage to a first pull-down node; a second pull-down control module for supplying the negative voltage to a second pull-down node; and a pull-down module for supplying the negative voltage to the pull-up node, and for supplying the negative voltage to the output terminal. | 05-01-2014 |
20140126684 | SHIFT REGISTER, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS - The present disclosure relates to a field of liquid crystal display, and discloses a shift register, a gate driving circuit and a display apparatus, wherein the shift register comprises a precharging module, a pulling-up module, a pulling-down driving module, a pulling-down module and a resetting module, each shift register may perform a bi-directional scanning, that is, it may scan not only forward but also backward, so that a cost for producing the liquid crystal display including the shift registers is reduced, and a manufacturing efficiency is increased. | 05-08-2014 |
20140169518 | SHIFT RGISTER UNIT, GATE DRIVER, AND DISPLAY DEVICE - Provided are a shift register unit, a gate driver and a display device. The shift register unit comprises: a pull-up control module, a pull-up module, a reset module, and a denoise module for holding a signal output from the first output terminal when the signal has a level higher than a first preset threshold and outputting the held signal from a second output terminal when a signal output from a denoise control signal output terminal has a level higher than a second preset threshold. The signal output from the first output terminal is filtered by using the signal output from the first output terminal and the signal output from the denoise control signal output terminal, and thus burrs in the signal output from the first output terminal are eliminated, that is, noise is eliminated, solving the problem that a defective display picture due to the noise in the output signal. | 06-19-2014 |
20140177780 | SHIFT REGISTER AND THE DRIVING METHOD THEREOF, GATE DRIVING APPARATUS AND DISPLAY APPARATUS - The present invention provides a shift register, a driving method, a gate driving apparatus and a display apparatus. Said shift register comprises a pull-up unit, a reset unit, a pull-down unit and a signal output; the pull-up unit is connected to said signal output and pulls up an output signal; the reset unit is connected to a control end of said pull-up unit and said signal output respectively and resets the potential of the control end of said pull-up unit after said output signal is at high level; the pull-down unit is connected to a control end of said pull-up unit and said signal output respectively and pulls down the potential of the control end of said pull-up unit and said output signal after said reset unit has reset the potential of the control end of said pull-up unit, so that said pull-up unit switches off. | 06-26-2014 |
20140185737 | SHIFT REGISTER - A shift register includes a plurality of stages each for outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes k A-sub-stages each for controlling a voltage at an A-set node and a voltage at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse. | 07-03-2014 |
20140241488 | SHIFT REGISTER - A shift register includes a plurality of stages each outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node. The voltage at the at least one A-reset node and any one A-clock pulse, at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse. | 08-28-2014 |
20140254743 | SHIFT REGISTER - Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node. | 09-11-2014 |
20140254744 | Liquid Crystal Display Device and Electronic Device Including the Same - A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring. | 09-11-2014 |
20140321599 | GATE SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME - Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, and a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame. | 10-30-2014 |
20140355731 | SHIFT REGISTER CIRCUIT AND DRIVING METHOD THEREOF | 12-04-2014 |
20140355732 | Shift Register Circuit - A shift register is disclosed. The shift register circuit includes a pull up control circuit configured to provide a pull up control signal; a first pull up circuit configured to provide a sensor driving signal in response to the pull up control signal and a second clock signal; a second pull up circuit configured to provide a gate driving signal in response to a first clock signal, the pull up control signal and the second clock signal; a first pull down control circuit configured to output a first pull down control signal; a first pull down circuit configured to pull down the pull up control signal, the sensor driving signal and the gate driving signal in response to the first pull down control signal; and a main pull down circuit configured to pull down the pull up control signal and the gate driving signal. | 12-04-2014 |
20140369457 | SHIFT REGISTER CIRCUIT - A shift register circuit includes a first pull-down control circuit, a first pull-down circuit electrically connecting to the first pull-down control circuit, a first inversed pulse signal coupling circuit outputting a first inversed pulse signal, a first pull-up circuit outputting a first gate control signal, and a first main pull-down circuit electrically connecting to the first pull-up circuit. The first pull-up circuit receives a first driving signal and a first pulse signal to output the first gate control signal. The first inversed pulse signal coupling circuit duly outputs the first inversed pulse signal to compensate a surge occurring in the first driving signal. | 12-18-2014 |
20140376682 | SHIFT REGISTER - Disclosed is a shift register capable of stably generating an output even when the threadhold voltage of a pull-down switching element is raised due to degradation of the pull-down switching element. The shift register includes a plurality of stages each comprising a node controller comprising an inverter to control a voltage at a reset node in accordance with a voltage at a set node, and an output unit to output a scan pulse based on at least one of the voltage at the set node and the voltage at the reset node. The shift register further includes an inverter voltage controller for controlling a high-level inverter voltage supplied to each inverter of the stages based on the voltage at at least one reset node in at least one of the stages. | 12-25-2014 |
20150049853 | Shift Register Circuit - A shift register circuit includes first-type and second-type shift registers, each comprising a pull-down control circuit, a pull-down circuit, a key pull-down circuit, a 3D-mode pull-up circuit, and a 2D-mode pull-up circuit. The pull-down circuit is connected to the pull-down control circuit. The key pull-down circuit, connected to the pull-down circuit, pulls down a driving signal and a gate control signal. When the 2D-mode pull-up circuit operates, a first-type shift register generates a driving signal for a second-type shift register. When the 3D-mode pull-up circuit operates, a first-type shift register generates another driving signal for another first-type shift register. | 02-19-2015 |
20150302935 | SHIFT REGISTER UNIT, GATE DRIVING APPARATUS AND DISPLAY DEVICE - Provided is a shift register unit, a gate driving apparatus and a display device capable of increasing a lifespan of a shift register. The shift register unit according to the present disclosure includes: a first thin film field effect transistor, a drain thereof connected with a first signal terminal, a source thereof connected with the outputting node at the present stage, a gate thereof connected with a first node; a second thin film field effect transistor, a drain thereof connected with the first signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the first node; a third thin film field effect transistor, a drain thereof connected with a second signal terminal, a source thereof connected with the outputting node at the present stage, and a gate thereof connected with a second node; a fourth thin film field effect transistor, a drain thereof connected with the second signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the second node; and a node voltage control module, configured to control the first node and the second node to be in a high potential state alternatively when the shift register unit is in a pulling-down phase. The present disclosure increases the lifespan of the shift register. | 10-22-2015 |
20150302936 | SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE - The present invention provides a shift register unit, a gate driving circuit and a display device. The shift register unit comprises: an input module for, in response to turn-on level input via the shift register input terminal, providing turn-on level to the first node and providing turn-off level to the second node; a pull-up module for, in response to turn-on level of the first node, providing a clock signal to the shift register output terminal, and also used for, in response to turn-on level output by the shift register output terminal, providing turn-off level to the second node; a reset module for, in response to turn-on level input via the reset signal input terminal, providing the turn-on level to the second node; and a pull-down module for, in response to turn-on level of the second node, providing turn-off level to the shift register output terminal and the first node. | 10-22-2015 |
20150318052 | SHIFT REGISTER UNIT, GATE DRIVE CIRCUIT AND DISPLAY DEVICE - According to this disclosure, a shift register unit includes a pull-up control module, a pull-up module, a pull-down control module and a pull-down module, wherein the pull-up module is adapted to provide a transmission signal output terminal with a first clock signal inputted from a first clock signal input terminal according to the pull-up control signal, and provide a gate drive signal output terminal with a first direct current supply voltage according to the pull-up control signal and the first clock signal inputted from the first clock signal input terminal. | 11-05-2015 |
20150318053 | GATE DRIVING CIRCUIT, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure discloses a gate driving circuit including multi-stage shift registers, and an output side switch element which is controlled by the second clock signal to be turned on or off. The output side switch element is located between an input terminal and an output terminal of each stage shift register. An output terminal of the (N+2)-th stage shift register is coupled to a reset terminal of the N-th stage shift register. | 11-05-2015 |
20150325181 | GATE DRIVING CIRCUIT, GATE DRIVING METHOD AND DISPLAY DEVICE - The present disclosure discloses a gate driving circuit, a gate driving method and a display device. The gate driving circuit includes a plurality of cascaded shift register units for outputting gate driving signals, each of the gate driving signals being output by a gate driving signal output terminal of each shift register unit; the gate driving circuit further includes: a gate driving control unit connected with the shift register unit for controlling the gate driving signal to be transmitted to N rows of pixel circuits time-divisionally, wherein N is a positive integer greater than or equal to 2. | 11-12-2015 |
20150325312 | SHIFT REGISTER, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire. | 11-12-2015 |
20150332621 | SEMICONDUCTOR STRUCTURE, DISPLAY PANEL AND CONTROL METHOD THEREOF - A semiconductor structure is provided. A first conductive layer is formed between a substrate and a first insulating layer. A semiconductor layer is disposed over the first insulating layer. A second conductive layer is formed between a semiconductor layer and a second insulating layer and includes a first segment and a second segment. A third conductive layer is disposed over the second insulating layer. The first insulating layer, the semiconductor layer, the first segment and the second segment constitute a first transistor. The third conductive layer, the semiconductor layer, the first segment and the second segment constitute a second transistor. During a first period, the first and third conductive layers receive a first voltage level and a second voltage level respectively. During a second period, the first and third conductive layers receive a third voltage level and a fourth voltage level respectively. | 11-19-2015 |
20150332649 | MULTI-PHASE GATE DRIVER AND DISPLAY PANEL USING THE SAME - A multi-phase gate driver includes a start/end signal generator circuit and X shift register modules. The start/end signal generator circuit is configured to sequentially output N start signals and N end signals according to a first control signal, a second control signal and N groups of clock signals. Each start and end signals have a delay relative to the previous one. Each group of clock signals includes a first clock signal and a second clock signal, which are inverted to each other. The X shift register modules are electrically coupled to the start/end signal generator circuit and each includes N shift register units. The Mth shift register unit of the first shift register module outputs a gate signal according to the Mth group of clock signals, the Mth start signal, and the gate signal outputted from the Mth shift register unit in the second shift register module. | 11-19-2015 |
20150332784 | SHIFT REGISTER UNIT, SHIFT REGISTER, GATE DRIVE CIRCUIT AND DISPLAY APPARATUS - To provide a shift register unit, which comprises a positive control signal input terminal, a reverse control signal input terminal, a first thin film transistor, a second thin film transistor, a positive input terminal, a reverse input terminal, a pull-up module and a first reset module, a gate of the first thin film transistor is connected with the positive input terminal, a first electrode of the first thin film transistor is connected with the positive control signal input terminal, a second electrode of the first thin film transistor is connected with a pull-up node of the pull-up module, a gate of the second thin film transistor is connected with the reverse input terminal, a first electrode of the second thin film transistor is connected with the pull-up node of the pull-up module, a second electrode of the second thin film transistor is connected with the reverse control signal input terminal. | 11-19-2015 |
20160012911 | SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND METHOD, DISPLAY APPARATUS | 01-14-2016 |
20160019977 | TFT-LCD, DRIVING DEVICE AND MANUFACTURING METHOD THEREOF - An embodiment of the disclosed technology provides a driving device for a thin film transistor liquid crystal display (TFT-LCD) and a method for manufacturing the same. The driving device comprises at least one first TFT and at least one second TFT formed a base substrate, wherein load of the first TFT is larger than load of the second TFT, the first TFT is of a top-gate configuration, and the second TFT is of a bottom-gate configuration. | 01-21-2016 |
20160027527 | SHIFT REGISTER - A shift register is configured by connecting unit circuits | 01-28-2016 |
20160042807 | SHIFT REGISTER AND DISPLAY DEVICE - The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop. | 02-11-2016 |
20160125954 | SHIFT REGISTER AND A GATE DRIVING DEVICE - The present invention discloses a shift registor and a gate driving device, the shift register comprising: an input module for providing an input signal to a pull-up node; an output module for storing the input signal and providing a first clock signal to an output terminal; a reset module for providing a level signal to the pull-up node; a pull-up module for providing a second clock signal to a pull-down node; a first pull-down module for providing the level signal to the pull-down node; and a second pull-down module for providing the level signal to the pull-up node and providing the level signal to the output terminal. | 05-05-2016 |
20160125955 | Shift Register, Driving Method Thereof and Gate Driving Circuit - A shift register, driving method thereof and a gate driving circuit are disclosed, wherein the shift register comprises an input module, a reset module, a first output module, a second output module and a control module. The shift register uses the first clock signal to control the second node, and then controls the signal output by the signal output terminal by alternate high/low levels of the second node and the second clock signal, such that the signal output terminal can always output signals to eliminate noises and stabilize row output signals. In addition, since the second node has alternate high/low levels, the life span of the shift register can be protected. | 05-05-2016 |
20160133337 | SHIFT REGISTER UNIT, SHIFT REGISTER, GATE DRIVE CIRCUIT AND DISPLAY DEVICE - A shift register unit, a shift register, a gate drive circuit and a display device, the shift register unit, comprising: an input module; an output module configured to output a first clock signal of a first clock signal terminal to an output terminal of the shift register unit according to a potential of the pull-up node at an output phase; a reset module configured to pull down the potentials of the pull-up node and the output terminal of the shift register unit according to a reset signal at a reset phase; and a pull-down module configured to pull down the potentials of the pull-up node and the output terminal according to a second clock signal of a second clock signal terminal at a pull-down phase. Compared to the related art, the structure of the shift register unit provided by the present disclosure is simpler. | 05-12-2016 |
20160189797 | SHIFT REGISTER, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A semiconductor device and the like with low power consumption can be provided. A shift register in which a plurality of register circuits are connected to each other in series. The plurality of register circuits each include a flip-flop circuit. An operation of the flip-flop circuit of the register circuit in one stage is determined by a clock signal, an output signal of the register circuit in the previous stage, an output signal of the register circuit in the one stage, and an output signal of the register circuit in the next stage. Data stored in the flip-flop circuits in the register circuits in stages that are two or more stages before the one stage and in the register circuits in stages that are two or more stages after the one stage are not rewritten. | 06-30-2016 |
20160189798 | SHIFT REGISTER - A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit. | 06-30-2016 |
20160189799 | GATE DRIVE CIRCUIT AND DRIVE METHOD FOR THE SAME - A gate drive circuit is disclosed. The drive circuit includes M cascaded shift registers, where M is a natural number, and a clock controller configured to generate two reverse-phase clock signals. The drive circuit also includes a high level controller configured to generate a high level signal, and a low level controller configured to generate a low level signal, where one of the high level controller and the low level controller is configured to generate an initial pulse signal during an initial stage. The drive circuit also includes a start unit cascaded with the M shift registers, where the start unit is configured to provide a start signal to the shift registers. | 06-30-2016 |
20160203876 | SHIFT REGISTER | 07-14-2016 |