Class / Patent application number | Description | Number of patent applications / Date published |
377047000 | Pulse multiplication or division | 40 |
20080219399 | Frequency Divider With Symmetrical Output - There is disclosed an apparatus for dividing the frequency of an input signal by an integer N. First and second means may divide the frequency of the input signal by a factor of N and then by a factor of 2. An output of the first means and an output of the second means may be combined by an exclusive OR gate. Third means may be used to control the relative phase of the outputs from the first and second means such that the output from the first means and the output of the second means differ in phase by one-quarter cycle or 90 degrees. | 09-11-2008 |
20080260089 | Quadrature Divide-By-Three Frequency Divider and Low Voltage Muller C Element - A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This frequency divider can be used in frequency synthesisers and as quadrature local oscillator generator. | 10-23-2008 |
20090022260 | BINARY FREQUENCY DIVIDER - A binary frequency divider includes a counter paced by an input signal, means for comparing a counting value with first and second threshold values and supplying first and second control signals synchronized with variation edges of a first type of the input signal. The divider includes means for supplying at least one third control signal shifted by a half-period of the input signal in relation to one of the first or second control signals, and control means for generating the output signal using control signals chosen according to the value of at least one least significant bit of the division setpoint. Application is mainly but not exclusively to UHF transponders. | 01-22-2009 |
20090122950 | AFSM circuit and method for low jitter PLL CMOS programmable divider - A frequency divider ( | 05-14-2009 |
20090154637 | High speed hybrid structure counter having synchronous timing and asynchronous counter cells - A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal. | 06-18-2009 |
20090168947 | PROGRAMMABLE INTEGER AND FRACTIONAL FREQUENCY DIVIDER - A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor. | 07-02-2009 |
20090296878 | FREQUENCY DIVIDER - A frequency divider including a first frequency-dividing unit, a second frequency-dividing unit, a selecting unit, and a counting unit is provided. The first frequency-dividing unit receives an input signal and divides a frequency of the input signal for outputting a plurality of phase signals, wherein phases of the phase signals are mutually different. The selecting unit is connected to the first frequency-dividing unit for selecting one of the phase signals according to a control signal, so as to output an inner signal. The second frequency-dividing unit is coupled to the selecting unit for dividing a frequency of the inner signal to serve an output signal. The counting unit is coupled to the selecting unit for counting the inner signal and outputting a counting result as the control signal. Therefore, the output signal with about 50% duty cycle can be provided. | 12-03-2009 |
20090296879 | COUNTER/DIVIDER, AND PHASE LOCKED LOOP INCLUDING SUCH COUNTER/DIVIDER - A counter/divider where the counter/divider comprises a: a pre-scaler operable in a first mode to divide an input signal by M and in a second mode to divide the input signal by N, where N is greater than M; a first programmable counter, and a second programmable counter; and where the first and second programmable counters are responsive to an output of the pre-scaler and an output of the first counter controls whether the pre-scaler operates in the first mode or the second mode, wherein the first counter is operable to count to greater than one. | 12-03-2009 |
20100046693 | LOW POWER RADIO FREQUENCY DIVIDER - In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal. The MMD circuit may also include a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal. The cascade of divide-by-2-or-3 cells and the pulse stretching circuit may be implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits. Each divide-by-2-or-3 cell may be organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop. | 02-25-2010 |
20100054390 | PROGRAMMABLE FREQUENCY DIVIDER AND FREQUENCY DIVIDING METHOD THEREOF - Provided are a programmable frequency divider, more particularly, a programmable frequency divider which is a core module of a frequency synthesizer using a Phase Locked Loop (PLL) for generating very high frequencies. | 03-04-2010 |
20100111244 | HIGH SPEED, SYMMETRICAL PRESCALER - Over the years, ring counter and prescalers have been used in a variety of microelectronic applications, including Phased Locked Loops or PLLs. All of these applications have experienced both decreases in size and increases in speed. As a result, current-mode logic or CML has come into use in some high speed applications, calling for alternative designs for components such as prescalers. Here, a divide-by-three prescaler is described that uses internal states from mater-slave flip-flop pairs and that is well-suited for microelectronics that employ CML. | 05-06-2010 |
20100128836 | SYMMETRY CORRECTED HIGH FREQUENCY DIGITAL DIVIDER - A clock frequency divider for odd numbered divide ratios. The divider clocks two counters in parallel from a reference clock to be divided. One counter is loaded with the divide ratio and the other counter is loaded with the divide ratio except for the least significant bit. The second counter will set a latch when its count has elapsed. The first counter will reset the latch when its count has elapsed and will reload the counters. The latch is used for the divided output, but passes through a retiming circuit. The retiming circuit delays the output edge by one reference clock edge when the least significant bit indicates an odd numbered divide ratio. | 05-27-2010 |
20100128837 | SYSTEM AND A METHOD FOR GENERATING TIME BASES IN LOW POWER DOMAIN - A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter. | 05-27-2010 |
20100195785 | METHOD AND DEVICE FOR DIVIDING A FREQUENCY SIGNAL - A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency. | 08-05-2010 |
20100215139 | COUNTERS AND EXEMPLARY APPLICATIONS - Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C | 08-26-2010 |
20100254506 | Counter and Frequency Divider Thereof - A frequency divider includes a transmission gate, a first inverter, a first switch circuit, a second switch circuit, and a second inverter. The transmission gate transmits a clock signal according to an inverted enable signal. The first inverter inverts the clock signal outputted from the transmission gate. The first switch circuit generates a first control signal according to the inverted clock signal and an output signal of the frequency divider. The second switch circuit generates a second control signal according to the clock signal, the inverted clock signal, and the first control signal. The second inverter inverts the second control signal to generate the output signal. The frequency of the clock signal is a multiple of the frequency of the output signal. | 10-07-2010 |
20110150168 | CLOCK GENERATOR AND DETA-SIGMA MODULATER THEREOF - A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator. | 06-23-2011 |
20110311018 | PULSE TYPE LAYER-ID DETECTOR FOR 3D-IC AND METHOD OF THE SAME - A 3D-IC detector for each layer of a stacked device comprises a pulse generator to receive an initial signal and generate a pulse-in signal to a next stage detector. A latch is coupled to the pulse generator to receive an output signal from the pulse generator and generate a layer identifying signal. A counter is coupled to previous stage detector and the initial signal to perform a counting operation; and an adder coupled to the counter to add a number to a counting output from the counter and input added signal to the pulse generator. | 12-22-2011 |
20130182816 | CLOCK DIVIDER CIRCUIT - In one embodiment, a clock divider circuit preserves characteristics of both a rising edge and a falling edge of a source clock. The clock divider circuit may include a counter, a flip-flop, and an output. The counter is configured to divide a source clock signal into a divided clock signal. The flip-flop is configured to receive the divided clock signal and an inverse of the source clock signal to trigger the flip-flop. The output includes a logic gate configured to output a final clock signal based on a logical union of an output of the flip-flop and the divided clock signal. The final clock signal includes the jitter from the falling edge of the source clock and the jitter from the rising edge of the source clock. | 07-18-2013 |
20130182817 | TIMING GENERATION CIRCUIT - The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal. | 07-18-2013 |
20130216017 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 08-22-2013 |
20130251090 | CLOCK DIVIDER CIRCUIT - A clock divider circuit. The clock divider receives m input clock signals each of the same frequency. Each input clock signal after the first has a phase offset of 2π/m from the previous input clock signal. The clock divider divides the frequency of the input clock signals by an integer of division K. The clock divider includes a counter that receives the first input clock signal and provides one or more count signals. The clock divider also includes m flip-flops, of which a first flip-flop receives the first input clock signal at its clock input and provides a first clock output signal. Each flip-flop after the first receives an input clock signal at its clock input and provides a clock output signal, each clock output signal after the first having a 2πK/m phase offset from the previous clock output signal. | 09-26-2013 |
20140211906 | CLOCK SIGNAL RATE MANAGEMENT CIRCUIT - A prescalar counter may be configured to repeatedly increment once for each cycle of a clock signal at a first frequency and reset upon reaching a threshold counter value. The prescalar counter may also include toggling logic configured to generate a clock pulse of a global time base signal upon each reset of the prescalar counter. A frequency divider may be configured to divide the global time base signal into a plurality of separate clock signals with each of the separate clock signals having a different frequency. The frequency divider may also be configured to provide, to each of a plurality of timers, one of the separate clock signals. | 07-31-2014 |
20150030117 | Shift frequency divider circuit - A shift frequency divider circuit includes: an inverter; N−1 registers; and N−2 logic gates; wherein each reset terminal of the register is connected to a system reset signal terminal; an output terminal of the inverter is respectively connected to an input terminal of the No. 1 register and input terminals of all the logic gates; all the logic gates are respectively connected between output terminals and input terminals of the No. 1 register to the No. N−1 register, and the output terminal of the No. 1 register is connected to another input terminal of the No. 1 logic gate, an output terminal of the No. 1 logic gate is connected to the input terminal of the No. 2 register; an output terminal of the No. N−2 logic gate is connected to the input terminal of the No. N−1 register. | 01-29-2015 |
20150043702 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 02-12-2015 |
20160013794 | LOW POWER DIVIDE-BY-SEVEN DIVIDER | 01-14-2016 |
377048000 | Multiplication or division by a fraction | 14 |
20080285704 | PROGRAMMABLE INTEGER AND FRACTIONAL FREQUENCY DIVIDER - A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor. | 11-20-2008 |
20090067567 | FRACTIONAL FREQUENCY DIVIDER - A divide-by-N/(N+0.5) frequency divider is disclosed. Two pairs of flip-flops are respectively triggered by an input clock and an inverted input clock, and a frequency-dividing selector is used to select one output of the two pairs of flip-flops as frequency-divided output signal. Two latches are respectively triggered by the input clock and the inverted input clock, and a modulus selector is used to select one output of the two latches. A modulus logic circuit determines being in either N frequency-dividing mode or (N+0.5) frequency-dividing mode based on a modulus control signal. A frequency-dividing logic circuit receives output of the modulus logic circuit and an inverted frequency-divided output signal to swallow half the input clock per output cycle in the (N+0.5) frequency-dividing mode, therefore obtaining division resolution of half the input clock. | 03-12-2009 |
20090213980 | MULTI-MODULUS DIVIDER WITH EXTENDED AND CONTINUOUS DIVISION RANGE - A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal. The predetermined divider cell corresponds to the determination result. | 08-27-2009 |
20110200161 | DIFFERENTIAL QUADRATURE DIVIDE-BY-THREE CIRCUIT WITH DUAL FEEDBACK PATH - A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals. | 08-18-2011 |
20110200162 | CLOCK FREQUENCY DIVIDER CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK FREQUENCY DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD - To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal. | 08-18-2011 |
20110222644 | CLOCK FREQUENCY DIVIDER CIRCUIT AND CLOCK FREQUENCY DIVISION METHOD - A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by a clock having a different frequency, and includes a mask control circuit | 09-15-2011 |
20110235772 | SYSTEMS AND METHODS FOR PROVIDING A CLOCK SIGNAL - Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled. | 09-29-2011 |
20110249786 | DIVIDER CIRCUIT - A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage. | 10-13-2011 |
20120275559 | Method and Apparatus for Clock Frequency Division - The present invention discloses a method and apparatus for clock frequency division, the method comprises: determining a current frequency division coefficient in real time according to input clock signals and output clock information; then, performing counting on the input clock signals according to an integer portion and a decimal portion of the frequency division coefficient and a decimal scale threshold of the decimal portion; and performing accumulation on the decimal portion according to the counting result; finally, controlling the output clock according to the counting result and the accumulation result. With the method and the apparatus, output signals can be adjusted dynamically according to input signals, and the bit width of the integer portion and the decimal portion of the frequency division coefficient and the decimal scale threshold of the decimal portion can be increased on demand, so that the precision of the frequency division coefficient can be adjusted. | 11-01-2012 |
20120314833 | Integer and Half Clock Step Division Digital Variable Clock Divider - A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio. | 12-13-2012 |
20130243148 | Integer and Half Clock Step Division Digital Variable Clock Divider - A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer. | 09-19-2013 |
20140003569 | PROGRAMMABLE LOW POWER MULTI-MODULUS DIVIDER WITH 50/50 DUTY CYCLE | 01-02-2014 |
20140003570 | FREQUENCY DIVIDER WITH IMPROVED LINEARITY FOR A FRACTIONAL-N SYNTHESIZER USING A MULTI-MODULUS PRESCALER | 01-02-2014 |
20140185736 | DIGITAL FRACTIONAL FREQUENCY DIVIDER - A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal. | 07-03-2014 |