Class / Patent application number | Description | Number of patent applications / Date published |
377026000 | Including memory | 10 |
20090086880 | COUNTER USING SHIFT FOR ENHANCED ENDURANCE - A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cells from an initial value up to a preset bound in each of a plurality of successive iterations, and to shift the bits of the count code that are respectively stored in the memory cells in each of the iterations relative to a preceding iteration. | 04-02-2009 |
20090116611 | SPACE AND POWER EFFICIENT HYBRID COUNTERS ARRAY - A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received. | 05-07-2009 |
20100290580 | METHOD AND APPARATUS FOR CALIBRATING A COUNTING CIRCUIT - Timing circuitry may use control circuitry to control calibration circuitry to calibrate a counter so that an adder and a calibration period counter are not required. Concatenation circuitry may be used to concatenate a portion of the counter value and the calibration value to provide a calibrated value to the counter. The results from match circuitry may be used to provide status and control information to a calibration history bit and to an enable circuit. The counter may be an up counter or a down counter. | 11-18-2010 |
20110103540 | MULTIPLE BASE COUNTER REPRESENTATION - A method comprises loading by logic a storage location with a count value. The count value comprises a plurality of upper order bits and a plurality of lower order bits. The method further comprises detecting, by said logic, an event and, based on detecting the event, sequentially changing the count value with the lower order bits changing according to base- | 05-05-2011 |
20110206176 | TRIGGER CIRCUITS AND EVENT COUNTERS FOR AN IC - Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred. | 08-25-2011 |
20120230460 | Method to Implement a Monotonic Counter with Reduced Flash Part Wear - A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicates a first one of the increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter. | 09-13-2012 |
20120321032 | Bit Scan Circuits and Method in Non-volatile Memory - A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train. | 12-20-2012 |
20130028369 | NON-VOLATILE MEMORY COUNTER - A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially. | 01-31-2013 |
20130156146 | Trigger Circuits and Event Counters for an IC - Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred. | 06-20-2013 |
20140037042 | INTEGRATED NON-VOLATILE MONOTONIC COUNTERS - Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described. | 02-06-2014 |