Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


Phase locked loop

Subclass of:

375 - Pulse or digital communications

375354000 - SYNCHRONIZERS

375371000 - Phase displacement, slip or jitter correction

375373000 - Phase locking

Patent class list (only not empty are listed)

Deeper subclasses:

Entries
DocumentTitleDate
20080240328Jitter detection circuit and jitter detection method - A jitter detection circuit comprises: an oscillation circuit; a measurement period setting circuit for outputting a measurement period signal based on a measurement period specifying signal, said measurement period setting circuit receiving the output clock from a PLL circuit; a counter for counting the number of clock cycles output from the oscillation circuit over the period during which the measurement period signal is being output; a reference count value determining circuit for setting a reference count value for the number of clock cycles output from the oscillation circuit over the period during which the measurement period signal is being output; and an error detection circuit for detecting the jitter error of the PLL circuit based on the maximum count value and minimum count value counted by the counter, and the reference count value.10-02-2008
20080298533Frequency synchronization - Systems and methods related to digital frequency locked looping to synchronize frequencies between the local signal from a local oscillator and a reference clock signal from a remote oscillator. A reference counter increments its count for every pulse in the reference clock signal. The value in the reference counter is compared to a configurable reference value. Whenever a match between the reference counter value and the reference value occurs, a hit signal is generated and the reference counter value is reinitialized. Concurrent with the above, a feedback counter increments for every pulse from the local signal. When the hit signal is generated, the value in the feedback counter is compared to a configurable feedback value (by subtraction) to generate a difference value. The difference value is then converted to a frequency adjust signal for use in either increasing or decreasing the frequency of the local oscillator. The hit signal also reinitializes the feedback counter.12-04-2008
20120170699METHOD TO DECREASE LOCKTIME IN A PHASE LOCKED LOOP - A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.07-05-2012
20100020910PHASE-LOCKED LOOP SYSTEM WITH A PHASE-ERROR SPREADING CIRCUIT - A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.01-28-2010
20090285344Phase Locked Loop with Temperature and Process Compensation - Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.11-19-2009
20080285699COMMUNICATION SYSTEM USING MULTI-PHASE CLOCK SIGNALS - A communication system using multi-phase clock signals. The communication system includes a transmitter and a receiver. The transmitter outputs first data and a clock signal based on first multi-phase clock signals, and performs a coarse lock operation on the clock signal in response to a bit lock detection signal indicating whether or not the first data are bit-locked. The receiver receives the first data and the clock signal from the transmitter, generates second multi-phase clock signals based on the clock signal, generates second data by sampling the first data based on the second multi-phase clock signals, and performs a fine lock operation on the second multi-phase clock signals in response to the bit lock detection signal. Therefore, a jitter noise may be reduced and a size of a multi-phase clock generator included in the receiver may be reduced.11-20-2008
20100074388SYSTEMS AND METHODS FOR A PLL-ADJUSTED REFERENCE CLOCK - A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.03-25-2010
20090168944LOW PASS FILTER AND LOCK DETECTOR CIRCUIT - A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.07-02-2009
20100074387Frequency to Phase Converter with Uniform Sampling for all Digital Phase Locked Loops - This disclosure relates to systems and methods for frequency to phase conversion using uniform sampling, where a uniform or constant clock period is used.03-25-2010
20090190706Substrate module having an embedded phase-locked loop, integerated system using the same, and fabricating method thereof - A substrate module having an embedded phase-locked loop is cooperated with at least one function unit mounted thereon for forming an integrated system. The substrate module includes a base, a multi-layer structure, a built-in circuit unit, and an external circuit unit. The built-in circuit unit is integrated inside the multi-layer structure and the multi-layer structure is formed in the base. The external circuit unit is mounted on the upper surface of the base and is electrically coupled to the built-in circuit unit for jointly forming a phase-locked loop, so as to cooperate with the function unit.07-30-2009
20090154629CLOCK REPRODUCING AND TIMING METHOD IN A SYSTEM HAVING A PLURALITY OF DEVICES - A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.06-18-2009
20100067636Baseband Phase-Locked Loop - An example method includes receiving a phase correction signal representing a phase difference between a source signal and a reference signal, generating a first control voltage from the phase correction signal using a charge pump circuit, generating a second control voltage from the phase correction signal in response to a digitally filtered version of the phase correction signal, wherein the second control voltage corrects for an offset error present in the first control voltage, calculating a VCO control signal based on a linear combination of the first and the second control voltages; and generating the source signal in response to the VCO control signal.03-18-2010
20100067634COMMUNICATIONS DEVICE USING MEASURED FREQUENCY OFFSET OVER TIME TO ADJUST PHASE AND FREQUENCY TRACKING - The communications device includes a phase and frequency tracking loop having a signal input and an adjustable loop filter that establishes a predetermined tracking loop bandwidth for samples of communication signals received at the signal input and processed within the tracking loop. A tracking loop update circuit updates loop filter operating parameters and is operative with the loop filter for increasing or decreasing the tracking loop bandwidth of the phase and frequency tracking loop based on the dynamics of the frequency offset of measured samples from the output of the loop filter over time.03-18-2010
20080198958APPARATUS AND METHOD FOR COMPENSATING FOR PHASE JUMP OF REFERENCE SIGNAL IN DIGITAL PHASE-LOCKED LOOP/FREQUENCY-LOCKED LOOP - An apparatus and method for compensating for a phase jump of a reference signal in a digital Phase-Locked Loop (PLL)/Frequency-Locked Loop (FLL) are provided. The apparatus includes a phase discriminator for comparing a phase of an external clock signal (i.e., the reference signal) with a phase of an internal clock signal to determine a phase difference between the two signals, a phase jump compensator for detecting a phase jump moment by using the phase difference, for estimating a previous phase jump value according to a current phase difference upon detecting a phase jump, and for correcting the phase difference by using a phase jump correction value obtained in the estimation process, and a Low Pass Filter (LPF) for filtering a high-frequency component of the corrected phase difference. Accordingly, reliable synchronization can be achieved over an E08-21-2008
20090092215DATA RELAY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.04-09-2009
20080205570Unlock Mode in Source Synchronous Receivers - A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.08-28-2008
20090135979METHOD AND DEVICE FOR PROCESSING THE FREQUENCY SHIFT OF THE CARRIER FREQUENCY OF A SIGNAL MODULATED WITH A QUADRATURE CONTINUOUS SINGLE-CARRIER MODULATION - A frequency shift of a carrier frequency of an input signal is estimated with a frequency estimator in order to obtain an estimate value. Then, the estimate of the frequency shift is refined, and the carrier frequency is corrected in consequence, with a phase-locked loop that is initialized with the estimate value. The phase-locked loop has a locking frequency range that is narrower than a locking frequency range of the frequency estimator.05-28-2009
20090268859SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN A DIGITAL PHASE LOCKED LOOP (DPLL) - An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.10-29-2009
20090010372Modulation apparatus capable of correcting non-linearity of voltage controlled oscillator - A modulation apparatus 01-08-2009
20080317187Interpolative All-Digital Phase Locked Loop - An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.12-25-2008
20080317186Controlling phase locked loop - A method and apparatus for controlling phase locked loop are provided. The apparatus comprises a voltage controlled oscillator configured to generate an output signal with a frequency proportional to a control voltage fed into the oscillator; an analog loop filter connected to the oscillator and configured to form the control voltage for the oscillator; a charge pump configured to generate a current pulse into the loop filter; a phase-frequency detector operationally connected to the charge pump and configured to form waveforms, based on a reference signal and a feedback signal, the feedback signal being proportional to the output signal of the oscillator; and a controller configured to modulate the feedback signal on the basis of the frequency or phase error of the output signal of the voltage controlled oscillator and the reference signal.12-25-2008
20080317185DUAL PHASE LOCKED LOOP (PLL) ARCHITECTURE FOR MULTI-MODE OPERATION IN COMMUNICATION SYSTEMS - The clock generating portion of a communication system includes a low-power, high-jitter phase locked loop (PLL) and a high-power, low-jitter PLL. Control logic within the chip allows for selective switching between the low-power and high-power PLL for receiving the broadcast signals, such as mobile TV signals. The switching may occur in a manner that is dependent on the conditions of the wireless channel and/or the complexity of the modulation scheme being used. The switching may be used to provide an oscillating signal from one or both of the PLLs to a receiver to be used to receive communication signals. The control logic may power off one of the PLLs to save power when not in use.12-25-2008
20100296615DYNAMIC PHASE TRACKING USING EDGE DETECTION - Methods and apparatus of phase tracking are described. Decisions regarding phase location of an oversampled portion of a data signal are based on the content of the data signal. In one example, a phase decision threshold is dynamically variable based on whether a predetermined number of edges is detected in the data signal.11-25-2010
20080240327Semiconductor memory device capable of controlling tAC timing and method for operating the same - A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The delay locked loop circuit produces delay locked clock signals through a delay locking operation. The tAC control unit adjusts a delay value of the delay locked clock signals in order to control a tAC timing, thereby generating output reference signals. The reference signal generating unit produces a latch reference signal in response to the delay locked clock signals. The data output block latches data in response to the latch reference signal and for outputting the latched data in response to the output reference signals.10-02-2008
20110299644Emission Suppression for Wireless Communication Devices - A method may include synchronizing an output of a phase-locked loop to a signal received at its input. The method may further include suppressing emission at a potentially problematic channel by applying at least one of a first gain and a first resistance of the phase-locked loop for a communication at the potentially problematic channel, wherein at least one of the first gain and the first resistance are different from a second gain and a second resistance applied for communications at channels other than potentially problematic channels.12-08-2011
20110293055CIRCUIT FOR GENERATING A CLOCK DATA RECOVERY PHASE LOCKED INDICATOR AND METHOD THEREOF - A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.12-01-2011
20090103674Data transmission system and method thereof - A data transmission system includes a transmitter and a receiver. The transmitter mixes an original clock signal and an original data signal to generate and output a hybrid differential signal, the hybrid differential signal having multiple clock pulses and multiple data pulses. At lease one data pulse occurs between two clock pulses, and the period between two clock pulses corresponds to the frequency of the original clock signal. The clock pulses and the data pulses have different differential swings. The receiver receives the hybrid differential signal via a bus and generates a recovered clock signal and a recovered data signal based on the hybrid differential signal. The hybrid differential signal, the original clock signal and the original data signal are reduced swing differential signals.04-23-2009
20080310574Semiconductor memory device - A semiconductor memory device stably performs a read operation at a high frequency, thereby reducing a current consumption. The semiconductor memory device is capable of performing the read operation stably by controlling a data eye. The semiconductor memory device includes an output unit and a data eye control unit. The output unit outputs data in synchronization with clock signals. The data eye control unit controls a data eye of the data output by the output unit.12-18-2008
20090141846Receiving apparatus and receiving method - A receiving apparatus that can be connected to a transmitting apparatus through a plurality of transmission lines includes: a first clock generation section that generates a first clock based on a signal from a first transmission line which is one of the plurality of transmission lines; a first demodulation section that demodulates the signal from the first transmission line based on the timing of the first clock; a second clock generation section that controls the phase of the first clock based on the phase of a signal from a second transmission line which is one of the plurality of transmission lines and is different from the first transmission line to generate a second clock; and a second demodulation section that demodulates a signal from the second transmission line based on the timing of the second clock.06-04-2009
20090245450PLL circuit - Disclosed herein is a phase-locked loop circuit including: a voltage controlled oscillator; a variable frequency divider circuit for frequency-dividing an oscillating signal of the voltage controlled oscillator into a 1/N (N is an integer) frequency; a phase comparator circuit for comparing phases of a frequency-divided signal and a reference signal of a reference frequency with each other; a charge pump circuit for outputting a charge pump current changed in pulse width; a loop filter for being supplied with the charge pump current and outputting a direct-current voltage changed in level; and a control circuit for calculating a value of the charge pump current as a function of the oscillating frequency of the voltage controlled oscillator and a coefficient for setting a phase locked loop band, and setting the value of the charge pump current in the charge pump circuit.10-01-2009
20090168943CLOCK GENERATION DEVICES AND METHODS - A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.07-02-2009
20090147904Frequency Lock Stability in Device Using Overlapping VCO Bands - A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.06-11-2009
20090147903COMMUNICATION SYSTEM, RECEIVING APPARATUS, AND RECEIVING METHOD - A communication system includes a transmission apparatus for transmitting a plurality of serial data signals that are synchronized in phase with one another and a clock signal that is synchronized in frequency with the serial data signals; and a receiving apparatus for receiving a plurality of serial data signals and the clock signal transmitted from the transmission apparatus. The receiving apparatus includes a phase synchronization circuit configured to roughly adjust the frequency in accordance with the received clock signal and then generate a reproduction clock that is synchronized in phase with one serial data signal among the plurality of serial data signals, and a phase shifter configured to shift the phase from the reproduction clock and lock the phase to another serial signal.06-11-2009
20090310730Frequency Detector and Phase Locked Loop Having the Same - A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.12-17-2009
20090310729Circuit for correcting an output clock frequency in a receiving device - An output clock correction circuit (12-17-2009
20100086094Delay-Locked loop With Dynamically Biased Charge Pump - A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.04-08-2010
20100086093Wireless Clock Regeneration And Synchronization - A method and apparatus are described for regenerating a local clock within a wireless module and synchronizing the local clock with a wireless host clock. For one embodiment, the wireless module generates a local clock, counts the cycles of the clock during a common timing reference period maintained wirelessly between the wireless module and the host, receives a count of the host clock during the same common timing reference period, and adjusts the local clock signal based upon a comparison of the two counts. For one embodiment, the wireless module further receives timing references from the host and, in addition, receives packets of audio samples from the host accompanied by a timestamp, the timestamp based upon the host timing reference, and outputs the audio sample at the time designated by the timestamp.04-08-2010
20090262879DLL circuit with wide-frequency locking range and error-locking-avoiding function - A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the delay period of time of the voltage control delay circuit analogically. In the locking period, the DLL circuit utilizes the delay time of the delay units, which is decided in the evaluation period, along with the voltage control delay circuit, to lock phase of the reference clock signal. In this way, the stability of the delay period of time of the voltage control delay circuit increases.10-22-2009
20110170645METHOD FOR SWITCHING MASTER/SLAVE TIMING IN A 1000BASE-T LINK WITHOUT TRAFFIC DISRUPTION - A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.07-14-2011
20090262878SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL) - A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.10-22-2009
20090262877Computation spreading utilizing dithering for spur reduction in a digital phase lock loop - A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.10-22-2009
20090110136BANG-BANG PHASE DETECTOR WITH SUB-RATE CLOCK - The present invention describes methods and circuitry for a sub-rate bang-bang phase detector, in which the reference clock has frequency that is a fraction of the bit rate of the received data stream. The sub-rate bang-bang phase detector is enabled by multiple phases of the reference clock.04-30-2009
20090274255METHOD AND APPARATUS FOR STABILIZING CLOCK - A method and an apparatus for stabilizing a clock are provided. The apparatus for stabilizing a clock includes: a phase locked loop (PLL) module, configured to receive a filtered phase difference signal from a digital filtering module and output an output clock; a phase discrimination module, configured to receive an output feedback clock, and generate a phase difference signal reflecting a phase difference between the output feedback clock and the input clock; the digital filtering module, configured to receive the phase difference signal from the phase discrimination module, and generate the filtered phase difference signal after filtering the phase difference signal, then send the filtered phase difference signal to the PLL module. A division ratio of the PLL module is adjusted according to the filtered phase difference signal till the phase difference between the input clock and the output feedback clock maintains a stable state.11-05-2009
20090296870COMMUNICATION SYSTEMS AND CLOCK GENERATION CIRCUITS THEREOF WITH REFERENCE SOURCE SWITCHING - A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL switches to generate the output clock signal according to a second clock signal.12-03-2009
20090296869COMMUNICATION SYSTEMS, CLOCK GENERATION CIRCUITS THEREOF, AND METHOD FOR GENERATING CLOCK SIGNAL - A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.12-03-2009
20090103675Linear phase interpolator and phase detector - A novel interpolating phase detector for use in a multiphase PLL is described comprising an array of individual phase comparators, all operating at essentially the same operating point which permits the circuits to be designed simultaneously for high speed and for low power consumption. Two adjacent phase outputs of a multi-phase VCO may be selected and interpolated in between, by selectively attaching a variable number of phase comparators to each phase output and summing their phase error outputs. By varying the number of phase comparators attached to each phase output, interpolation can be achieved with high linearity.04-23-2009
20100111241Digital Phase Lock Loop with Multi-Phase Master Clock - A digital phase lock loop circuit with reduced jitter at the output is disclosed. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.05-06-2010
20090003504Method for frequency compensation in timing recovery - A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first and second estimates of the phase error in a timing signal. A controller receives the first estimate and provides a signal to an NCO. An output from the NCO provides feedback to the error detector to complete a first order feedback loop, providing a first estimate phase error compensation. An integrator receives the second estimate and provides an output estimate for frequency offset of the timing signal that is received by the controller and the sign and magnitude of the integrated phase error are calibrated to provide a frequency offset. The controller determines a number of additional updates to the NCO required to minimize jitter and reduce word-length.01-01-2009
20090003505Apparatus and Method for Processing Oscillation Signals in Wireless Communication System Based Tdd - The present invention is an oscillating apparatus and a method for Time Division Duplex (TDD) in a wireless communication system. In a Phase-Locked Loop (PLL) synthesizer applied to the wireless communication system, an oscillation signal generating from a PLL circuit is output by way of an isolation unit in which a capacitor for Direct Current (DC) blocking and a predetermined isolator are combined to form one body. Hence, the oscillation signal isolated from a subsequent circuit through the isolation unit is not affected by the effect of switching noises that flow from a Radio Frequency (RF) switch or into a power amplifier of a transmitter during switching between each Down Link (DL) frame and each Up Link (UL) frame, and therefore the performance of a system can be improved.01-01-2009
20090003502Bit pattern synchronization in acquired waveforms - A waveform processing system performs operations that may include identifying a location of a specified bit pattern within a coherently sampled repeating pattern input signal. In some examples, multiple periods of a repeating pattern signal are acquired using coherent sampling techniques such as, for example, coherent interleaved sampling (CIS). In such examples, the sampled waveform may be converted to a binary pattern that can be searched to locate a match to a predetermined or user-specified bit pattern. In one illustrative example, the identified location may be used to display the sampled waveform. In another example, the identified location may be used to measure pattern-dependent jitter of the sampled waveform.01-01-2009
20090003501Offset Error Mitigation in a Phase-Locked Loop Circuit with a Digital Loop Filter - A phase-locked loop circuit comprises an analog section, a digital section and a digital offset mitigation circuit. The analog section is subject to offset error and comprises an analog phase comparator and an analog-to-digital converter. The digital section comprises a digital loop filter and a digitally-controlled frequency-generating circuit. The digital loop filter is connected to receive a digital difference signal from the analog-to-digital converter. The digital offset mitigation circuit is operable in response to the digital difference signal to mitigate the offset error of the analog section.01-01-2009
20090097606METHODS FOR MULTI-CHANNEL DATA DETECTION PHASE LOCKED LOOP FREQUENCY ERROR COMBINATION - Frequency error combination for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving frequency error information of a signal relevant to a phase locked loop with respect to each channel; combining the received error signal information and generating a combined error signal, weighting the received error signal information from each channel, for example with reliability information. The combined frequency error signal is applied to at least one channel phase locked loop.04-16-2009
20080285698DIGITAL FORCED OSCILLATION BY DIRECT DIGITAL SYNTHESIS - An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.11-20-2008
20080212730PLL/DLL dual loop data synchronization - A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.09-04-2008
20080267337LOW WANDER TIMING GENERATION AND RECOVERY - The present invention teaches a variety of timing generation and recovery schemes for providing high precision clock synchronization in cascaded communications systems where each point of communication has a unique clock. To accomplish the high precision, one embodiment of the present invention teaches quantizing information related to phase relation between a master clock at the transmitter and a network link clock. This quantized phase information can be transmitted with very little bandwidth, recovered and the receiver and used to recover the timing information with high precision.10-30-2008
20080267336SYNCHRONIZING CIRCUIT AND CONTROLLING METHOD THEREOF - Disclosed herein is synchronizing circuit including: a numerically controlled oscillating section; a phase rotating section; a phase error estimating section; a loop filter; and a gain controlling section; wherein the gain controlling section controls the gain so as to suppress an effect of a phase error in an immediate main signal section in a known start section from a start of the known section to a predetermined symbol.10-30-2008
20080267335CLOCK DATA RECOVERY CIRCUIT - A clock data recovery circuit. The clock data recovery circuit comprises a transmission line, a phase locked loop, a voltage controlled oscillator, a phase selector, and a D flip-flop. The transmission line receives an input signal. The phase locked loop receives the input signal via the transmission line and a reference clock and generates a first clock signal. The voltage controlled oscillator receives the input signal via the transmission line and a control voltage from an internal node of the phase locked loop, and generates a clock signal. The phase selector receives the input signal via the transmission line and the clock signal from the voltage controlled oscillator, and generates a clock output signal. The D flip-flop receives the input signal via the transmission line and the clock output signal, and generates a data output signal.10-30-2008
20090190709PHASE LOCKED LOOP CALIBRATION - A method for controlling a modulation signal for modulating a phase locked loop. A scaling control signal for scaling the modulation signal is generated using the error signal of the phase locked loop. The scaling control signal is adjusted when the modulation signal and the phase of the modulation signal have the same sign.07-30-2009
20080232531Multi-Channel Timing Recovery System - The present invention, in particular embodiments, is directed to methods, apparatuses and systems that provide global timing error information derived from timing error information of each data channel. This is achieved, in part, by summing the timing error information from all the data channels and integrating and scaling the resulting sum. The integrated, scaled sum is then added to the proportional and integral timing information of each individual data channel. By doing so, incorrect timing error estimates are averaged out. Additionally, when severe noise and dropouts (loss of data signal) at an individual data channel occur, that channel may rely on the global timing error information. In some implementations, that individual data channel's timing error information contribution can be excluded from the global timing error information.09-25-2008
20090161809Method and Apparatus for Variable Frame Rate - A method and apparatus for adjusting to a frame rate. The method displays the video frames with varying rates. The method comprising the steps of detecting a change in the frame rate, calculating the FREQ of the frame, adjusting the phase-locked loop utilizing the calculated FREQ, and utilizing the adjusted phase-locked loop output as the pixel clock to display the frame.06-25-2009
20090129526PHASE-LOCKED LOOP CIRCUIT AND CORRESPONDING CONTROL METHOD - A phase-locked loop circuit includes a phase frequency detector, a loop filter, a voltage-controlled oscillator, an N/N+1 times frequency-divider and a controller. The phase frequency detector is configured for receiving a reference frequency and a feedback frequency, and comparing the reference frequency and the feedback frequency to output an adjust signal based on the comparison result. The loop filter is configured for filtering out noise from the adjust signal. The voltage-controlled oscillator is configured for sending an oscillating frequency and adjusting the oscillating frequency based on the adjust signal. The voltage-controlled oscillator, the N/N+1 times frequency-divider and the phase frequency detector composes a feedback loop for sending out the feedback frequency. The controller is configured for controlling the N/N+1 times frequency-divider to divide the oscillating frequency by N during a first period and divide the oscillating frequency by N+1 during a second period for obtain the feedback frequency.05-21-2009
20090129525APPARATUS AND METHOD FOR PHASE LOCKED LOOP - The PLL (Phase Locked Loop) apparatus and the PLL method are disclosed, wherein an output clock signal is counted in response to a reference clock signal to detect a frequency offset value and divide the output clock signal by a prescribed value to generate a phase detection value in response to the reference clock signal, generating a frequency error value to adjust a frequency of the output clock signal if the frequency offset value is not between a prescribed frequency offset maximum value and a predetermined frequency offset minimum value, and generating a phase error value in response to the phase detection value to adjust a phase of the output clock signal if the frequency offset value is in between a prescribed frequency offset maximum value and a prescribed frequency offset minimum value.05-21-2009
20120069944Frequency Synchronization Using Clock Recovery Loop with Adaptive Packet Filtering - An endpoint or other communication device of a communication system includes a clock recovery loop having a phase error estimator. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery loop is configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device. The phase error estimator comprises a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop.03-22-2012
20090185650BEAMFORMING IN MIMO COMMUNICATION SYSTEMS - A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.07-23-2009
20080317188Digital Phase Locked Loop with Integer Channel Mitigation - An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.12-25-2008
20080317189BINARY RIPPLE COUNTER SAMPLING WITH ADJUSTABLE DELAYS - The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.12-25-2008
20080317190SYSTEM FOR DECODING BIT STREAM PRINTED ON SURFACE - A system for decoding coded data printed in ink on a surface. The coded data includes an encoded bit stream and associated redundancy data, and a registration structure of clock tracks indicative of a position of the coded data in the direction perpendicular to an alignment direction and two alignment lines for each clock track. The system has a store for storing the coded data and a decoder for determining a codeword format for the coded data, reading the coded data from the store using the determined format, correcting errors in the encoded bit stream, and writing the corrected data to the store. The coded data is read so as to de-interleave the encoded bit stream and redundancy data into codewords. The decoder uses an alignment PLL to determine a position of the alignment lines so as to determine the position of each respective track and update the alignment PLL.12-25-2008
20090074126Systems and methods for data recovery in an input circuit receiving digital data at a high rate - Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data when the phase between the incoming data and the receiver clock varies relatively slowly. Embodiments comprise a fast tracking loop performs to track the data when the phase between the incoming data and the receiver clock varies rapidly. The fine tracking loop adjusts the phase of a receiver clock to track the data eye of the data. The fast tracking loop over-samples the data and then chooses the sample that best represents the data. In some embodiments, the data recovery circuit can switch between receiving data from the fine tracking loop and receiving data from the fast tracking loop.03-19-2009
20090086875Digital spread spectrum method based on precise phase delta-sigma algorithm - A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals; quantizing a spread spectrum profile associated with the spread spectrum parameter; mapping the quantized profile; generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal; dividing a phase signal of the plurality of phase signals with the integer control signal; synchronizing the divided phase signal using the phase control signal; and providing a reference clock for a spread spectrum clock generator based on the synchronizing.04-02-2009
20090052602Systems and Methods for Improved Timing Recovery - Various embodiments of the present invention provide systems and methods for improved timing recovery. As one example, some embodiments of the present invention provide timing recovery circuits that include an error signal and a digital phase lock loop circuit. The error signal indicates a difference between the predicted sample time and an ideal sample time. The digital phase lock loop is operable to apply an adjustment value such that a subsequent sample time is moved toward the ideal sample time. Further, the digital phase lock loop circuit includes an adjustment limit circuit that is operable to limit the adjustment value.02-26-2009
20090097609Error Compensation Method, Digital Phase Error Cancellation Module, and ADPLL thereof - Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error o a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.04-16-2009
20090097608PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME - A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.04-16-2009
20110228889Repeater Architecture with Single Clock Multiplier Unit - A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.09-22-2011
20090097607METHOD AND SYSTEM OF DETECTING AND LOCKING TO MULTI-STANDARD VIDEO STREAMS - A video processing system includes a video detection circuit for determining the clock frequency of an incoming video signal. Using the determined clock frequency, adjustments are made in a phase lock loop to enable a quick lock onto the clock frequency of the incoming video signal.04-16-2009
20090245449SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR CLOCK DATA RECOVERY - A clock data recovery circuit of an interpolator type capable of corresponding to multi-rate data without increasing the bandwidth of the interpolator. A clock generated by an interpolator is divided to generate a recovery clock. A pointer that controls the phase of the clock generated by the interpolator uses the clock before division, and the other circuits are operated by the recovery clock after division.10-01-2009
20080260087MULTI-BAND BURST-MODE CLOCK AND DATA RECOVERY CIRCUIT - A clock and data recovery circuit is disclosed and comprises a first gated voltage-controlled oscillator, a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop. The first GVCO receives a data signal and a reference voltage to generate a first clock signal and a second clock signal based on the data signal. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the frequency of the first clock signal and the second clock signal at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second clock signal or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The double-edge-triggered D flip-flop comprises a data input terminal receiving the output signal from the matching circuit, a clock input terminal receiving the output signal from the multiplexer, and an output terminal outputting a recovered data signal.10-23-2008
20090316849METHOD AND SYSTEM FOR RF SIGNAL GENERATION UTILIZING A SYNCHRONOUS MULTI-MODULUS DIVIDER - Aspects of a method and system for RF signal generation utilizing a synchronous multi-modulus divider are provided. In this regard, a feedback signal of a PLL may be generated by clocking a counter with an RF signal output by the PLL and toggling the feedback signal each time a determined value of the counter is reached. Moreover, updates of each register in the counter and transitions of the feedback signal may be synchronous with the RF signal output by the PLL. The PLL may be part of a cellular transmitter and/or receiver which may communicate over an EDGE network. A counting sequence of the counter may be determined, at least in part, by an output of a εΣ modulator. In this regard, a first counting sequence may be utilized when an output of the ΔΣ modulator may be asserted and a second counting sequence may be utilized when the output of ΔΣ modulator may be de-asserted.12-24-2009
20090316848APPARATUS FOR GENERATING CLOCK SIGNAL WITH JITTER AND TEST APPARATUS INCLUDING THE SAME - The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal oscillator (VCXO) for generating an output signal including jitter components based on a driving power source having a specific waveform and a controlled voltage, a phase comparator for calculating a phase difference of a reference signal and the output signal, and a loop filter for generating the controlled voltage based on the phase difference calculated by the phase comparator. Accordingly, the PLL circuit unit generates a clock signal including jitter, so that the complexity and manufacturing cost of the apparatus can be reduced.12-24-2009
20090116603USB frequency synchronizing apparatus and method of synchronizing frequencies - A universal series bus (USB) frequency synchronous apparatus using a start of frame (SOF) signal generated by a master device to mark a reference interval is disclosed. The frequency synchronizing apparatus includes a frequency divider, a counter unit with a default pulse number, an arithmetic unit, and an adjusting unit. The frequency divider divides a high frequency signal by a variable frequency factor to generate a lock frequency signal. The counter is used to detect a pulse number of the lock frequency signal at a reference interval and obtain a pulse difference between the default pulse number and the detected pulse number of the lock frequency signal.05-07-2009
20100183109PHASE LOCKED LOOP CAPABLE OF FAST LOCKING - A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal. The variable frequency divider determines a value of the variable divisor in accordance with the digital output to reduce the phase difference between the divided feedback signal and the reference signal .07-22-2010
20090003503Frequency detector for VCO band selection - In general, in one aspect, the disclosure describes an apparatus including a multi-band voltage controlled oscillator (VCO), a phase lock loop (PLL) reference clock to track a specific time frame, and an auto band selector (ABS) to count number of VCO output clock periods that occur during the specific time frame for different bands and to select an appropriate band to provide a desired frequency output based on counter results.01-01-2009
20130216014AUTOMATIC DETECTION AND COMPENSATION OF FREQUENCY OFFSET IN POINT-TO-POINT COMMUNICATION - Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.08-22-2013
20100124302METHODS FOR DETERMINING A REFERENCE SIGNAL AT ANY LOCATION ALONG A TRANSMISSION MEDIA05-20-2010
20100195779PHASE LOCKED LOOP CIRCUIT AND RECEIVER USING THE SAME - A phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is acquired by multiplying the frequency of a reference signal by a ratio represented by the sum of a first fraction and a second fraction, the circuit includes a controlled oscillator including the same number of stages of annularly connected amplifiers as a number which is obtained by dividing, by 2, a least common multiple of a denominator of the first fraction, a denominator of the second fraction and 2, the same number of multiphase signals as the least common multiple being extractable from the controlled oscillator, the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, one of the multiphase signals being output as the output signal.08-05-2010
20090074127PHASE LOCKING METHOD AND APPARATUS - A phase locking method and apparatus by which a phase of an input signal is locked using the input signal and a clock signal, where the phase locking method includes generating n multi-phase clock signals using the clock signal where n is an integer, generating n multi-phase input signals from the input signal corresponding to each of the n multi-phase clock signals, generating n error signals, that is, one for each of the n multi-phase input signals, extracting a low-frequency component from one of the generated n error signals or from a summation result of the generated n error signals, adding the extracted low-frequency component to each of the n error signals, and selecting one of the n error signals to which the low-frequency component is added in response to the clock signal and outputting the selected error signal used to generate the clock signal.03-19-2009
20080310573POLAR MODULATION / ONE-POINT FREQUENCY MODULATION WITH FLEXIBLE REFERENCE FREQUENCY - Apparatuses and methods for operating a modulation system using a flexible reference frequency signal are disclosed. A modulation system uses a phase-locked loop (PLL). An internal reference signal source is configured to provide an internal reference signal having an internal frequency that is substantially independent of the reference frequency. A frequency signal source is configured to provide a plurality of first samples of the frequency signal taken at a first sampling frequency according to the internal reference signal. A resampling device is configured to receive and resample the plurality of first samples to generate a plurality of second samples taken at a second sampling frequency according to the reference frequency. A loop gain compensation device is configured to receive the reference frequency and apply an offset gain to inversely offset a change in PLL loop gain responsive to a change in the reference frequency.12-18-2008
20080304610Frequency Reacquisition in a Clock and Data Recovery Device - A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired.12-11-2008
20080279324Frequency jittering control for varying the switching frequency of a power supply - A frequency jittering circuit modulates a hysteretic band of an oscillator such that the clock generated by the oscillator has a jitter frequency, and thus a switching mode power supply operative on the clock will have a jittering switching frequency.11-13-2008
20080267334Method and Apparatus for Providing a Soft Clock Re-Sync For Subscriber Line Interface Cards - A first clock signal is generated by a first circuit and a second clock signal is generated by an auxiliary clock circuit. A switch controls whether the first clock signal or the second clock signal is provided to a subscriber line integrated circuit (SLIC). The SLIC is operable to generate a line voltage within predetermined tolerances on a loop line at a customer premises if the SLIC is receiving the first clock signal or the second clock signal. A resync signal is sent to the SLIC to cause it to resync with the first clock signal without going through a reset operation.10-30-2008
20110122983FREQUENCY LOCKED FEEDBACK LOOP FOR WIRELESS COMMUNICATIONS - A method and systems for a frequency locked feedback loop for wireless communications are provided. The method includes applying dither modulation from a harmonic modulator to modulated data at a transmit source, and mixing the dither modulation at a dither modulation frequency with the modulated data at a wireless carrier frequency to produce a modulated signal. The method also includes filtering and splitting the modulated signal using a bandpass filter to produce a wireless output signal and a feedback signal. The method further includes determining a frequency error in the feedback signal as a function of alignment of the wireless carrier frequency to a target frequency in a frequency response of the bandpass filter. The method additionally includes adjusting the wireless carrier frequency in response to the frequency error to establish a frequency lock between the wireless carrier frequency and the target frequency.05-26-2011
20100303187AUTOMATICALLY SYNCHRONIZING RING OSCILLATOR FREQUENCY OF A RECEIVER - A ring oscillator in a receiver in a multimedia network is adjusted to compensate for factors that may decrease its accuracy over time using a link training signal from a transmitter device in the network. An incoming signal having a known frequency is received at a receiver or sink device from a transmitter, the signal may be a link training signal used for configuring a link between the two devices. In the receiver, an internally generated clock signal is created, the signal having an internal frequency. The incoming signal and the internally generated clock signal are input into a frequency detector which outputs frequency comparison-based data. The internal frequency is based on the comparison-based data such that it is adjusted to be closer to the known frequency of the incoming signal.12-02-2010
20090213974Method for agile region and band conscious frequency planning for wireless transceivers - A technique for agile region and band conscious frequency planning for wireless transceivers in which a comparison frequency is selected for generating a local oscillator signal. The comparison frequency (F08-27-2009
20090129524SPREAD SPECTRUM CLOCK GENERATORS - Spread spectrum clock generators. A phase lock loop generates an output clock according to a first input clock and a second input clock, a delay line is coupled between the first input clock and the phase lock loop. A modulation unit provides a modulation signal to control the delay line thereby modulating phase of the first input clock, such that frequency of the output clock generated by the phase lock loop varies periodically.05-21-2009
20110007859PHASE-LOCKED LOOP CIRCUIT AND COMMUNICATION APPARATUS - A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.01-13-2011
20090067563FREQUENCY SYNTHESIZER, COUPLED DIVIDE-BY-N CIRCUIT, CURRENT-REUSE MULTIPLY-BY-M CIRCUIT - A frequency synthesizer is provided in the present invention. The frequency synthesizer includes a single phase-locked loop having a reference frequency signal input, a first output, a second output and a pair of divide-by-N circuits coupled with each other and electrically connected to the second output; a multiply-by-M circuit having a first input electrically connected to the first output and a third output; and a combination of a buffer and a mixer having a second input electrically connected to the second output and a third input electrically connected to the third output generating a frequency signal output.03-12-2009
20110243291SYNCHRONOUS TRANSFER OF STREAMING DATA IN A DISTRIBUTED ANTENNA SYSTEM - Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium. The method comprises receiving a modulated signal that includes the encoded binary data stream and extracting the encoded binary data stream. The method further comprises generating a recovered clock signal that is phase locked to the encoded binary data stream, generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal, and integrating the error signal to generate a signal to control a voltage controlled oscillator. The method further comprises generating a stable recovered clock signal and producing at least one output clock by scaling the stable recovered clock signal frequency.10-06-2011
20110116586Transmitting Apparatus Operative at a Plurality of Different Bands and Associated Method - A transmitting apparatus operative at a plurality of different bands includes at least a modulator, an intermediate frequency (IF) filter, and an offset phase-locked-loop (OPLL). Regardless at which one of the frequency bands the transmitting apparatus operates, a divisor of at least one frequency divider included within the OPLL is fixed, and a signal, which is outputted by a controllable oscillator and received by an offset mixer included within the OPLL, corresponds to a substantially fixed frequency.05-19-2011
20110116587PHASE LOCKED LOOP AND SATELLITE COMMUNICATION TERMINAL USING THE SAME - A phase locked loop includes: a loop filter; a voltage controlled oscillating unit configured to output a frequency varying according to an output voltage of the loop filter; a frequency down-converting unit configured to down-convert an output frequency of the voltage controlled oscillating unit according to a band of the output frequency of the voltage controlled oscillating unit; and a frequency divider configured to divide a frequency down-converted by the frequency down-converting unit. The output frequency of the voltage controlled oscillating unit varies according to the output voltage of the loop filter and a control signal compensating the frequency down-converted by the frequency down-converting unit.05-19-2011
20090016477Signal timing phase selection and timing acquisition apparatus and techniques - Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.01-15-2009
20110243290PHASE-LOCKED LOOP - A PLL circuit (10-06-2011
20090323880SYNCHRONIZATION OF REAL TIME DATA WITHIN DETERMINISTIC CLOCK EDGE - Techniques are disclosed for reducing clock slip in a system where real time data is transmitted over a wireless network. A wireless frame synchronization signal can be received from a remote device. The synchronization signal can be used to reset the clock that drives the wireless transmission of data, the clock that drives the analog to digital converter and/or a clock that drives a digital to analog converter.12-31-2009
20080304609PHASE/FREQUENCY ESTIMATOR-BASED PHASE LOCKED LOOP - A phase/frequency estimator-based phase locked loop (PFE-PLL) may be use to obtain a phase and frequency estimation by using an algebraic summer, a gain block and a (co)sine waveform generator. The apparatus and methods of the present invention may provide the phase estimation of an input signal from which a frequency of the signal is estimated by a derivative function. Unlike conventional phase lock loop systems, which may use a multiplier to perform complex calculations on an input and a feedback signal to develop a demodulated voltage output, the present invention may use a simple algebraic summer to provide an error signal and output a phase and a frequency estimation of the input signal.12-11-2008
20100054386METHODS AND APPARATUS FOR SERIALIZER/DESERIALIZER TRANSMITTER SYNCHRONIZATION - Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.03-04-2010
20110176647CIRCUIT, SYSTEM AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER - An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.07-21-2011
20120201338TWO POINT MODULATION DIGITAL PHASE LOCKED LOOP - A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.08-09-2012
20080253493Clock and data recovery circuit - The phase detector compares the phases of a synchronous clock signal and serial data and outputs a phase error signal corresponding to a comparison result. The second integrator performs integration of the phase error signal to obtain a phase correction control signal for tracking phase shift of the serial data. The first integrator performs integration of the phase error signal in each smoothing period with a predetermined length to obtain a smoothed error signal. The pattern generator generates a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a predetermined length and outputs the pattern as a frequency correction control signal. The first integrator receives the frequency correction control signal which is fed back and changes the length of the smoothing period according to the direction of a change in the frequency of generating the frequency correction control signal.10-16-2008
20100020911Phase Compensated Renormalizable Dynamic Phase Locked Loop - A variable bandwidth phase locked loop (PLL) includes renormalizable circuitry configured to allow a gain of the PLL to be changed without causing a disturbance, and a phase compensation circuit configured to adjust a final output phase of the PLL based on parameter changes supplied to the PLL.01-28-2010
20090147902ALL DIGITAL PHASE-LOCKED LOOP WITH WIDELY LOCKED FREQUENCY - An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CK06-11-2009
20080205571System and Method for Time Aligning Signals in Transmitters - A system and method for time aligning signals in transmitters. A transmitter includes a first signal path coupled to a first data input, a second signal path coupled to a second data input, an error signal energy source coupled to the first and second signal paths, the error signal energy source generates an error signal responsive to a time alignment difference between a first data stream and a second data stream, a time alignment circuit coupled to the error signal energy source, to the first and second data inputs, the time alignment circuit generates a digital control word responsive to the error signal, to the first and second data streams, and a timing adjust unit coupled to the time alignment circuit, to the first and second signal paths, the timing adjust unit inserts a delay proportional to the digital control word in either signal paths.08-28-2008
20090141845DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES - In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal.06-04-2009
20110080985Synchronization Distribution in Microwave Backhaul Networks - In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.04-07-2011
20100310031MULTI-RATE DIGITAL PHASE LOCKED LOOP - A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption.12-09-2010
20080273648Means To Reduce The PLL Phase Bump Caused By A Missing Clock Pulse - A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.11-06-2008
20100111240Method to Track a Target Frequency of an Input Signal - A digital demodulator adapted in a receiver and a digital demodulation method are provided. The digital demodulator comprises: a phase splitter, a complex multiplier, an AFC, a limiter, a phase detector, a re-tracker, a post-multiplier and an oscillator. The phase splitter generates a complex signal from the input signal. The complex multiplier multiplies the complex signal by both first and second phase signals to generate first and second base band signals. The AFC generates a first output signal. The limiter generates a trend signal and the re-tracker generates a tuning signal from the first output signal. The phase detector multiplies the trend and second base signal and adjusts the multiplied signal based on the tuning signal. The oscillator generates the first and second phase signals according to the output of the phase detector. The post-multiplier multiplies the trend signal by the first and second base band signals for output.05-06-2010
20100158183Frequency Synchronization Using First and Second Frequency Error Estimators - An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.06-24-2010
20100067635MEASURING AND REGENERATING A VARIABLE PULSE WIDTH - A system and process for receiving a variable pulse width signal and measuring and serially sending the measurements to a receiver that deserializes and regenerates the variable pulse width signal. Data bits may be embedded with the variable pulse width clock measurements and serially sent out. The measurements are illustratively accomplished using a reference clock and a phase locked loop.03-18-2010
20090175397Method, System and Apparatus for Reducing Power Consumption at Low to Midrange Resolution Settings - A method for reducing power consumption in an information handling system (IHS) where the method includes receiving main data through a main link, wherein the main link provides at least one data lane. The IHS also receives a reference clock corresponding to the main data through an auxiliary channel and provides the reference clock to a first phase-lock loop, wherein the first phase-lock loop outputs a stream clock.07-09-2009
20090175399DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER - A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.07-09-2009
20100020912CLOCK SYNCHRONISER - A clock synchroniser, for generating a local clock signal synchronised to a received clock signal, is described and claimed, along with a corresponding clock synchronisation method. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. Preferably, the clock comparison circuit compares the periods of the local and received clock signals.01-28-2010
20090190708Frequency Synthesis Using Upconversion PLL Processes - Techniques for frequency synthesis using upconversion PLL processes are described herein.07-30-2009
20100158184ADAPTABLE PHASE LOCK LOOP TRANSFER FUNCTION FOR DIGITAL VIDEO INTERFACE - A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.06-24-2010
20080285697SYSTEM FOR PROVIDING OPEN-LOOP QUADRATURE CLOCK GENERATION - A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.11-20-2008
20120307949Burst Mode Clock and Data Recovery Circuit and Method - Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.12-06-2012
20110110475Method and Apparatus to Reduce Wander for Network Timing Reference Distribution - A network component comprising a first adaptation component, a second adaptation component, a system Phase-Locked-Loop (PLL) coupled to the first adaptation component, a comparison and voting logic component coupled to the first adaptation component and the system PLL component, a compensation logic component coupled to the comparison and voting logic component, and a positive/negative delay component coupled to the second adaptation component and the compensation logic component. Also disclosed is a network component comprising a comparison and voting logic function block configured to compare a plurality of internal timing references in a system PLL synchronization area, a compensation logic function block configured to calculate an offset value if any of the internal references substantially deviates from an expected value in a deterministic outcome, and a delay function block configured to add the calculated offset value to a timing reference that is forwarded to a subsequent node.05-12-2011
20100054387SYNCHRONIZING DEVICE FOR USB REAL-TIME AUDIO DATA TRANSMISSION - The present invention discloses a synchronizing device for real-time USB audio data transmission, comprising: a first adder unit, a start-of-frame countdown unit, a phase-locked loop circuit, a frequency divider, a second adder unit, a third adder unit, a fourth adder unit, a frame calibrating register unit, a calibrating mapping unit and a calibrating pulse generating unit. A start-of-frame token sent by the USB host is used as a 1-ms reference cycle so that a high-frequency clock passes through the frequency divider to issue a first clock. The first clock signal has a constant clock number in a USB start-of-frame. The absolute time is automatically adjusted according to the duration of a previous start-of-frame. Therefore, asynchronicity of data transmission between the USB host and external devices can be overcome.03-04-2010
20120008726DELAY LOCKED LOOP - A delay locked loop includes a delay amount setting unit configured to set a delay amount of an external clock signal, a coarse delay unit configured to primarily delay the external clock signal by the set delay amount based on a first unit duration which is a unit delay amount of the coarse delay unit; and a fine delay unit configured to secondarily finely delay the primarily delayed clock signal based on a second unit duration, which is a unit delay amount of the fine delay unit and smaller than the first unit duration.01-12-2012
20090175398I/Q IMBALANCE ESTIMATION AND CORRECTION IN A COMMUNICATION SYSTEM - Certain aspects and embodiments provide for accurate measurement and estimation of imbalances between in-phase (I) and quadrature (Q) components of a complex baseband signal. The accuracy of I/Q phase imbalance estimates may be enhanced by conducting them on a transmitter and a receiver that are connected via a local, loopback connection and by removing cross-spectrum interference in transferred packets. Once these accurate I/Q phase imbalances are determined, they may be used to adjust a signal processed by the transmitter or the receiver to increase the performance and data throughput of communications using the signal.07-09-2009
20090190707Frequency Ratio Detection - A system and method are provided for determining a frequency ratio in a phase-locked loop (PLL) circuit feedback path. The method accepts a reference signal having a predetermined first frequency and a PLL output signal having a non-predetermined second frequency. The reference signal cycles are counted, creating a first binary count. Likewise, the PLL output signal cycles are counted, creating a second binary count. The second binary count is sampled at an interval responsive to the first binary count, and a right-shifted second binary count is supplied as a ratio of the second frequency divided by the first frequency. More explicitly, the sampling is performed when a first binary count sampling threshold of 207-30-2009
20090086876Start up circuit for delay locked loop - An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.04-02-2009
20120155589FREQUENCY ACQUISITION UTILIZING A TRAINING PATTERN WITH FIXED EDGE DENSITY - A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.06-21-2012
20110075782STREAM CLOCK RECOVERY IN HIGH DEFINITION MULTIMEDIA DIGITAL SYSTEM - The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.03-31-2011
20110075781CONTINUOUS-RATE CLOCK RECOVERY CIRCUIT - A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.03-31-2011
20100172457METHOD AND CIRCUIT FOR RECEIVING DATA - The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.07-08-2010
20100246739METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS - A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.09-30-2010
20100208857PHASE-LOCKED LOOP CIRCUIT AND RELATED PHASE LOCKING METHOD - A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.08-19-2010
20120076252SYNCHRONIZING CIRCUIT, SYNCHRONIZING METHOD, AND RECEIVING SYSTEM - Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.03-29-2012
20120177163POWER-EFFICIENT DIGRF INTERFACE - A method in a communication device includes exchanging data between a Baseband Integrated Circuit (BBIC) and a Radio Frequency Integrated Circuit (RFIC) over a digital interface having a variable clock rate. The clock rate of the digital interface is modified during a communication session conducted by the communication device.07-12-2012
20100272222PLL MODULATION CIRCUIT, RADIO TRANSMISSION DEVICE, AND RADIO COMMUNICATION DEVICE - Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band. The PLL modulation circuit (10-28-2010
20100008460Synchronous de-skew with programmable latency for multi-lane high speed serial interface - A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.01-14-2010
20080298532AUDIO CLOCK REGENERATOR WITH PRECISELY TRACKING MECHANISM - In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock. The tracking circuit tunes the frequency of the crystal clock based on the extracted relationship.12-04-2008
20120328065Methods and Devices for Implementing All-Digital Phase Locked Loop - An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.12-27-2012
20100202579SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD - There is provided a signal processing apparatus includes a sampling clock generator for generating a sampling clock by delaying, a phase of a driving clock having the same frequency as a carrier-wave; a logic data generator for generating logic data in synchronization with the driving clock, that the logic data are generated by using the driving clock generated to sample a modulation signal obtained by shifting a phase of the carrier-wave; a sampling bit-string generator for generating a sampling bit-string by shifting the logic data; a phase-error data generator for using a bit-string corresponding to one cycle of the carrier-wave extracted from the sampling bit-string to generate phase-error data between a phase of the bit-string and the phase of the carrier-wave; and an extraction position determination unit for determining, based on the phase-error data, an extraction position of the bit-string having a phase similar that of the carrier-wave.08-12-2010
20080292040PHASE LOCKED LOOP APPARATUS WITH ADJUSTABLE PHASE SHIFT - The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.11-27-2008
20110158368LOOP BANDWIDTH ENHANCEMENT TECHNIQUE FOR A DIGITAL PLL AND A HF DIVIDER THAT ENABLES THIS TECHNIQUE - A method of operating a phase locked loop (FIG. 06-30-2011
20110158367DUAL FREQUENCY TRACKING LOOP FOR OFDMA SYSTEMS - Methods and apparatus for correcting frequency errors between a carrier frequency of a signal received by a wireless device and a reference frequency local to the device. For certain aspects, such a method generally includes receiving a signal in a receiver having an LO producing a reference frequency, a radio frequency (RF) phase-locked loop (PLL), and a digital rotator, estimating a frequency difference between a carrier frequency of the received signal and the LO reference frequency, and applying the estimated frequency difference to the RF PLL and the digital rotator.06-30-2011
20080253494Clock and data recovery circuit - The phase detector compares the phase of a synchronous clock signal from the clock interpolator with the phase of serial data and outputs a phase error signal corresponding to a comparison result. The first integrator performs integration of the phase error signal and obtains a phase correction control signal for tracking phase shift of the serial data. The second integrator further performs integration of the phase correction control signal and obtains an up/down signal. The pattern generator generates a frequency correction control signal for tracking frequency shift of the serial data from the up/down signal. The product of the pattern length of the pattern generator and the count width of the second integrator is equal to or larger than a threshold that becomes larger as the count width of the first integrator is larger.10-16-2008
20080253492CIRCUIT AND METHOD FOR CONTROLLING MIXED MODE CONTROLLED OSCILLATOR AND CDR CIRCUIT USING THE SAME - A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.10-16-2008
20080226009CLOCK AND DATA RECOVERY CIRCUIT AND COMMUNICATIONS APPARATUS INCLUDING THE CLOCK AND DATA RECOVERY CIRCUIT - A clock and data recovery circuit that includes a unit to output N-phase clocks each of which has a phase shifted from the others by a time T09-18-2008
20080212729Low Jitter Clock Recovery from a Digital Baseband Data Signal Transmitted Over a Wireless Medium - A system and method of transmitting a data stream from a data source over a baseband wireless communication system to one or more receivers. The receivers simultaneously recover the data and clock signals of the original data stream from the wireless transmitted data so that the data stream can be provided by the receivers to a data sink at the same rate as the original data stream, with low jitter performance.09-04-2008
20130114771Minimization of Spurs Generated from a Free Running Oscillator - Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include adjusting the free-running oscillator to prevent the oscillation frequency from drifting so that the spurs are eliminated. Performance data generated when the communications device engages a communications channel that is known not to generate spurs is compared to performance data generated when the communications device engages a desired communications channel. The free-running oscillator is adjusted until the two types of performance data are matched. Other methods include adjusting the dithering module of the PLL to prevent the oscillation frequency from drifting so that the spurs are eliminated.05-09-2013
20080198959Fractional Frequency Divider PLL Device and Control Method Thereof - In the following B cycles, the second frequency-divided signal fA is maintained at a low level, while the third frequency-divided signal fB is maintained at a high level. The three-modulus prescaler 08-21-2008
20130148769WIRELESS APPARATUS - A wireless apparatus includes a clock generation PLL circuit of a digital baseband section. A variable output regulator receives as an input a VCO control voltage for controlling an oscillation frequency of a VCO in the PLL circuit, varies an output voltage in accordance with the VCO control voltage, and supplies, as a supply voltage, the output voltage to a power terminal of a high frequency circuit, such as an amplifier. The VCO control voltage changes in accordance with temperature or process variations, and the supply voltage of the high frequency circuit is controlled in accordance with the VCO control voltage. For this reason, performance deterioration ascribable to the temperature or process variations can be compensated for.06-13-2013
20100303186Synchronization circuit, synchronization method, and reception system - Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.12-02-2010
20110311012METHOD AND DATA TRANSCEIVING SYSTEM FOR GENERATING REFERENCE CLOCK SIGNAL - A method and a data transceiving system for generating a reference clock signal are provided. The data transceiving system comprises a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver. The voltage controlled oscillator is used to generate a reference clock signal. The PLL unit is used to increase a clock frequency of the reference clock signal to generate a PLL clock signal. The data receiver is used to compare the PLL clock signal with a clock signal of an input data stream, so as to output a voltage adjusting signal to the voltage controlled oscillator. The voltage controlled oscillator adjusts the clock frequency of the reference clock signal to be generated according to the reference clock signal, so as to lock the clock frequency of the PLL clock signal to a base frequency of the clock signal of the input data stream.12-22-2011
20120008727WIDE BAND CLOCK DATA RECOVERY - The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.01-12-2012

Patent applications in class Phase locked loop