Entries |
Document | Title | Date |
20080198956 | METHOD AND APPARATUS FOR SIGNAL SYNCHRONIZING - A synchronizer and a method for synchronizing a communication signal are presented. The synchronizer comprises a first unit arranged for receiving a plurality of inputs. The plurality of inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal. The first unit being configured for stretching the communication signal according to the indicative of the destination clock period and indicative of the source clock period. The synchronizer is further provided with a second unit. The second unit is configured for operating according to the indicative of destination clock period. The output of the first unit is provided to the second unit. The second unit is configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain. | 08-21-2008 |
20080205564 | CLOCK RECOVERY APPARATUS - A clock recovery apparatus for generating a recovery clock from received data may include, but is not limited to, first and second oscillators. The first oscillator generates a first signal having a first frequency. The first signal synchronizes with the received data when the received data has a first level. The second oscillator is connected in series to the first oscillator. The second oscillator generates a second signal as the recovery clock when the first signal has a second level. The second signal has a second frequency. The second signal synchronizes with the first signal. | 08-28-2008 |
20080226003 | Method and Device for Synchronizing Rectilinear or Quasi-Rectilinear Links in the Presence of Interference - A method of synchronizing a substantially rectilinear signal being propagated through an unknown channel, in the presence of unknown substantially rectilinear interferences, received by an array of N sensors, in which a known training sequence s(nT) is used comprising K symbols and sampled at the symbol rate T (s(nT), 0≦n≦{tilde over (K)}1), characterized in that, based on observations x((n+l/p)T) over the duration of the training sequence, where p=T/Te is an integer and Te the sampling period, a virtual observation vector X((n+l/p)T)=[x((n+l/p)T) | 09-18-2008 |
20080232521 | Method of transmitting data in a communication system - A method of transmitting over a network a signal comprising a plurality of data elements the method comprising; receiving the signal at a terminal; determining a transmission delay of at least one data element; estimating a first component of the transmission delay; determining a second component of the transmission delay by removing the first component of the transmission delay from the transmission delay; and determining a receiver delay to be applied between receiving at the terminal and outputting from the terminal one of said plurality of data elements, in dependence on the second component of the transmission delay. | 09-25-2008 |
20080247496 | Early HSS Rx Data Sampling - In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted. | 10-09-2008 |
20080260082 | TRAINING PATTERN FOR A BIASED CLOCK RECOVERY TRACKING LOOP - Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data. | 10-23-2008 |
20080267328 | SYSTEM AND METHOD FOR MANAGING TIME IN AUTOMATIC CONTROL EQUIPMENT - The present invention relates to a time management method implemented in automatic control equipment, based on a system which comprises:
| 10-30-2008 |
20080273640 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 11-06-2008 |
20080292037 | Master Side Communication Apparatus and Slave Side Communication Apparatus - A master side communication apparatus and a slave side communication apparatus wherein the structure of a receiving part of the slave side communication apparatus is simplified to achieve a reduced size, a reduced power consumption and a reduced cost. The master side communication apparatus performs a communication in synchronism with the slave side communication apparatus having no synchronization timing adjusting function. A transport signal generating timing adjusting part of the master side communication apparatus acquires, from the slave side communication apparatus, synchronization signal generation timing information used when the slave side communication apparatus receives the transport signal from the master side communication apparatus. The transport signal generating timing adjusting part varies and adjusts, based on the acquired information, the transmission timing of the signal to be transmitted to the slave side communication apparatus. A transmitting part transmits the transport signal at the adjust transmission timing. The occurrence timing of the transport signal is varied and adjusted until the slave side communication apparatus becomes able to receive the transport signal from the master side communication apparatus. | 11-27-2008 |
20080310567 | METHOD FOR IMPROVING SYNCHRONIZATION AND INFORMATION TRANSMISSION IN A COMMUNICATION SYSTEM - The present invention relates to a method for improving synchronization and information transmission in a communication system, including: generating a signal with a time symmetric property based on a uniquely identifiable sequence c(l) from a set of sequences, sending the signal over a communication channel, receiving the signal, calculating and storing a correlation, finding the delay that result in a maximum correlation magnitude, detecting the unique sequence c(l) from the set of sequences. The method is distinguished by: generating the signal with a centrally symmetric part, s(k), the centrally symmetric part s(k) being symmetric in the shape of the absolute value thereof, storing the reverse differential correlation D(p) from a block of N received signal samples r(k), k=0, 1, . . . , N−1. The present invention also relates to a transmitter unit and a receiver unit of a communication system, and a radio communication system. | 12-18-2008 |
20090003500 | CIRCUIT FOR OUTPUTTING DATA OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus can include a clock synchronization unit (which is driven by a power supply voltage) that can be configured to receive data and output first synchronization data and second synchronization data in synchronization with a clock; a voltage converting unit that can be configured to convert the first and second synchronization data, which can swing between the power supply voltage and a ground voltage, into first and second converted data, which can swing between an I/O power supply voltage and the ground voltage; and a data output driver, which is driven by the I/O power supply voltage, for outputting the first converted data and the second converted data as output data. | 01-01-2009 |
20090034667 | METHOD AND DEVICE FOR PROVIDING TIMING INFORMATION IN A WIRELESS COMMUNICATION SYSTEM - A method and a device of providing timing information within a wireless communication system is described. The timing information is extracted from a received transmit signal. The inventive method comprises the steps of providing a training signal on the receiver side relating to a known signal portion of the transmit signal, scaling the training signal, quantizing the scaled training signal, correlating one or more parts of the received transmit signal with the scaled training signal to obtain one or more correlation results, and determining the timing information on the basis of the correlation results. | 02-05-2009 |
20090034668 | METHOD AND APPARATUS FOR SYNCHRONIZING A RECEIVER - Various embodiments generally relate to a method for synchronizing a receiver, said method including receiving a stream that includes a cyclic extension, estimating a size of the cyclic extension, extracting an amount of the stream according to the estimated size, and comparing the extracted amount to the stream to determine thereby a portion of the stream likely to include a symbol start point. | 02-05-2009 |
20090034669 | PERIODIC CALIBRATION FOR COMMUNICATION CHANNELS BY DRIFT TRACKING - A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2 | 02-05-2009 |
20090034670 | METHOD OF GENERATING AN INDEX VALUE - A method of generating an index value associated with a primary synchronization code within a communication signal includes splitting a sampled communication signal into even and odd samples. The even and odd samples are correlated with a primary synchronization code of the communication signal and complex values of the even and odd samples are generated. Signal strength values for the even and odd samples are approximated and the approximate signal strength values within a frame of the communication signal are accumulated. A highest accumulated signal strength value is assigned as an index value. | 02-05-2009 |
20090041169 | PULSE MODULATION TYPE TRANSMITTER APPARATUS AND PULSE MODULATION TYPE RECEIVER APPARATUS - A pulse modulation type transmitter apparatus and a pulse modulation type receiver apparatus wherein both a fast synchronization establishment and a low power consumption of a synchronizing part can be achieved at the same time and wherein the data transmission/reception can be performed soon after a commencement of communication, and further a fast data transmission and a low power consumption can be achieved. A first template signal ( | 02-12-2009 |
20090052598 | METHOD AND DEVICE FOR PROVIDING TIMING INFORMATION IN A WIRELESS COMMUNICATION SYSTEM - A method and a device of providing timing information within a wireless communication system is described. The timing information is extracted from a received transmit signal. The inventive method comprises the steps of providing a training signal on the receiver side relating to a known signal portion of the transmit signal, scaling the training signal, quantizing the scaled training signal, correlating one or more parts of the received transmit signal with the scaled training signal to obtain one or more correlation results, and determining the timing information on the basis of the correlation results. | 02-26-2009 |
20090052599 | TRANSMITTER AND TRANSMITTER/RECEIVER - The present invention provides a transmitter capable of reducing the occurrence of noise when switching from the SD signal to the HD signal, for example. A microcomputer ( | 02-26-2009 |
20090074121 | METHOD FOR EXTRACTING CLOCK IN CLOCK DATA RECOVERY SYSTEM - A method for extracting a clock in a clock data recovery system is provided. The method includes following steps. First, a serial link transmission data is sampled for a number of times, and a number of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated. | 03-19-2009 |
20090092210 | System and Method of Real Time Synchronization through a Communication System - A communication system, network, interface, and port architecture are provided for transferring data via a network. The network can be configured by connecting ports in a daisy chain arrangement to achieve a ring architecture or topology. The network transmits data according to a specific protocol. A first port transmits frames containing frame count information which is divided into several pieces, with each piece being transmitted in a single frame. A second port receives the frames, stores them in a frame buffer, and reassembles the frame count information from a plurality of frames. | 04-09-2009 |
20090097602 | APPARATUS AND METHOD FOR NON-CONTACT SENSING USING TEMPORAL MEASURES - An embodiment of the invention relates to a sampling circuit comprising at least one clock, a reference trace, a sensor trace adapted to be connected to a sensing element, and a device to measure a length of delay between a reference signal transmission time of a reference signal transmitting through the reference trace and a sensed signal transmission time of a sensed signal transmitting through the sensor trace, wherein the length of delay is determined by counting the number of burst tones occurring during the length of delay. | 04-16-2009 |
20090103671 | Low Power Fast Impulse Radio Synchronization - A method for synchronizing on a pulsed waveform sequence including pulsed waveforms. An impulse radio receiver is provided including a radio frequency (RF) front end connected to a demodulator, and the demodulator is connected to a processing unit. Power is provided to at least a portion of an RF component such as the RF front end and/or the demodulator, during time windows sufficient for testing an hypothesis regarding timing of the pulsed waveforms. The powering is controlled by the processing unit. Preferably, testing the hypothesis includes accumulating a signal of the pulsed waveforms, correlating with the pulsed waveforms, or accumulating the correlation result of the pulsed waveforms. Preferably, others functions of the receiver are powered or enabled subsequent to the testing. Preferably, the impulse radio receiver is an ultra-wide band receiver. | 04-23-2009 |
20090110128 | SYNCHRONIZATION ACQUIRING DEVICE AND SYNCHRONIZATION ACQUIRING METHOD - A synchronization acquiring device and method for realizing synchronization acquisition at high speed equivalent to that of parallel search with a simple constitution similar to that of series search. A synchronization acquiring device ( | 04-30-2009 |
20090110129 | SYNCHRONOUS RECTIFYING CIRCUIT FOR OFFLINE POWER CONVERTER - A synchronous rectifying circuit is provided for power converter. An integrated synchronous rectifier has a rectifying terminal, a ground terminal a first input terminal and a second input terminal. The rectifying terminal is coupled to secondary side of a transformer. The ground terminal coupled to output of the power converter. A power transistor is connected between the rectifying terminal and the ground terminal. The first input terminal and the second input terminal are coupled to receive a pulse signal for turning on/off the power transistor. A pulse-signal generation circuit includes an input terminal coupled to receive the switching signal for switching the transformer of the power converter. A first output terminal and a second output terminal of the pulse-signal generation circuit generate the pulse signal. An isolation device is coupled between the first input terminal and the second input terminal, and the first output terminal and the second output terminal. | 04-30-2009 |
20090110130 | METHOD AND CIRCUIT FOR CHANGING MODES WITHOUT DEDICATED CONTROL PIN - A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated. | 04-30-2009 |
20090110131 | Assessing Noise on a Communication Channel - A system and method involve transceiving successive first and second synchronization signals defining endpoints of a frame. A digital signal is transceived by a modulating time interval between portions of the first and second synchronization signals. A first data pulse is transceived during the frame. A relative position in the frame of the first data pulse represents a first analog signal. | 04-30-2009 |
20090110132 | SYSTEM AND METHOD FOR RE-SYNCHRONIZATION OF A PSS SESSION TO AN MBMS SESSION - An accurate indication of a re-synchronization point/time in streamed media content is provided to allow playout of the streamed media content from or at a desired point/time when a client or receiver switches from multimedia broadcast multicast service (MBMS) to packet switch stream (PSS) service. Various parameters, e.g., synchronization source (SSRC) and real-time protocol (RTP) timestamp, of a last received media RTP packet is signaled to a receiver. Alternatively, the SSRC and sequence number of the last received media RTP packet is signaled to the receiver, or the SSRC, the RTP timestamp, and the sequence number of the last received media RTP packet is signaled to the receiver. Also, a UTC clock time can be calculated based upon the last received real-time control protocol (RTCP) sender report (SR) and the timestamp of the last received media RTP packet in order to effectuate proper synchronization between MBMS and PSS servers. | 04-30-2009 |
20090110133 | DISTRIBUTED TRANSLATOR WITH RECEIVED SIGNAL SYNCHRONIZATION AND METHOD THEREOF - A distributed translator and an operation method of the distributed translator are proposed. The distributed translator includes: a demodulator demodulating a received signal to extract a transport stream and synchronization information from the received signal; a modulator generating an output frame based on the synchronization information to modulate the output frame; and a transmitter transmitting the modulated output frame according to a transmission timing. | 04-30-2009 |
20090116596 | LOW POWER, HIGH SPEED RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT - A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal. | 05-07-2009 |
20090116597 | Variability-Aware Asynchronous Scheme for High-Performance Communication Between an Asynchronous Circuit and a Synchronous Circuit - A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained. | 05-07-2009 |
20090122934 | Timing Measurement For Checking Probes - A system and a method for the transmission of signals representative of an event include a first low frequency clock ( | 05-14-2009 |
20090135974 | IMPULSE WAVEFORM GENERATING APPARATUS AND RADIO-FREQUENCY PULSE WAVEFORM GENERATING APPARATUS - An impulse waveform generating apparatus includes a multistage delay pulse signal generating part for generating a plurality of delay pulse signals by a timing signal; a signal source signal generating part for generating a signal source signal indicating the frequency component of an impulse waveform signal by the delay pulse signals; an envelope formation signal generating part for generating an envelope formation signal indicating the amplitude component of the impulse waveform signal by the delay pulse signals; and a mixer part for multiplying the signal source signal by the envelope formation signal to generate a prescribed impulse waveform signal. The impulse waveform generating apparatus generates the impulse waveform signal from the timing signal. Therefore, the circuit arrangement requires no digital-to-analog converter, the operational frequency of each element can be reduced, and the power consumption can be reduced. | 05-28-2009 |
20090141842 | Clock signal transmission method in radio communication apparatus, and radio communication apparatus - A radio communication apparatus includes a transmission clock signal generation part, when a harmonic component of a first clock signal used by a clock signal using part agrees with a reception frequency of the radio communication apparatus, generating a second clock signal different from the first clock signal; a clock signal transmission part transmitting the second clock signal, generated by the transmission clock signal generation part, for the clock signal using part, and a use clock signal generation part generating the first clock signal from the second clock signal, transmitted by the clock signal transmission part, and provide the generated first clock signal to the clock signal using part. | 06-04-2009 |
20090147895 | Efficient channel estimate based timing recovery - A module and method for channel estimate based timing recovery comprises a timing estimation module, a channel estimation module communicably coupled to the timing estimation module, a conversion module communicably coupled to the timing estimation module and to the channel estimation module, and an analog pulse shaping filter communicably coupled to the conversion module, wherein: the analog pulse shaping filter receives an analog signal and outputs a filtered analog signal, the conversion module receives the filtered analog signal and outputs a 1/T rate signal to the channel estimation module, the channel estimation module outputs a 1/T Channel Impulse Response (CIR) estimate to the timing estimation module, and the timing estimation module outputs a timing estimate to the conversion module, wherein the timing estimate is used in conjunction with an output of the conversion module to provide the 1/T rate signal. | 06-11-2009 |
20090147896 | SERIALIZER-DESERIALIZER CIRCUIT WITH MULTI-FORMAT AND MULTI-DATA RATE CAPABILITY - The present invention provides a serializer/deserializer (SERDES) circuit that can cover both client- and network-side interfaces for high-speed data rates. The present invention leverages commonality between the client and network (also known as line) side, and accommodates differences in a flexible manner. In one exemplary embodiment, the present invention provides a four-channel implementation to meet the requirement of both interfaces. The SERDES circuit can be capable of supporting both 40 Gb/s and 56 Gb/s data rates, can include an integrated DQPSK pre-coder and I/Q input/output signals, and can support RZ clock recovery. Additionally, the SERDES circuit can include differential coding support, electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like. | 06-11-2009 |
20090154623 | Frame-Synchronization Method and Device - A frame synchronization method and device. The method determines the frame start position D. That position D is the same as a position of a window H sliding along the received frame T | 06-18-2009 |
20090154624 | METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING A TIMING CORRECTION MESSAGE IN A WIRELESS COMMUNICATION SYSTEM - A method for transmitting a timing correction message in a wireless communication system, the method comprising, Generating the timing correction message comprising a 8-bit MessageID field and a 2-bit NumSectors field wherein, the NumSectors field indicates the number of sector records in the message and a 16 bit TimingCorrection field wherein, the TimingCorrection indicates the timing correction on the sector and last 15 bits indicate the magnitude of timing correction in units of ⅛ chips and transmitting the timing correction message over a communication link. | 06-18-2009 |
20090161806 | Microcontroller clock calibration using data transmission from an accurate third party - Systems and methods are provided for calibrating the internal oscillator of a microcontroller from a remote clock source. In some embodiments, an electronic device can request timing information from a third party device using a timing independent signal. The timing information received from the third party device may be used to calibrate the microcontroller clock of the electronic device. In some embodiments, the internal oscillator may be calibrated based on timing information received from multiple third party devices. Once calibrated, the microcontroller may initiate timing dependent communication with other electronic devices using a timing dependent protocol, such as a serial protocol. | 06-25-2009 |
20090161807 | Receiving Apparatus - A receiving apparatus includes a first receiver, a second receiver, a received signal synthesizer connected to the first and second receivers, a synchronizing signal synthesizer connected to the first and second receivers, and a synchronization detector connected to the synchronizing signal synthesizer. In this structure, synchronization determination is performed using a synchronizing signal of either the first or second receiver, and diversity reception is performed using the received signals of the first and second receivers. | 06-25-2009 |
20090168933 | Apparatus and Method for Clock Synchronization - Techniques for synchronizing clocks are disclosed. According to one aspect of the present invention, a pair of dividing coefficients a | 07-02-2009 |
20090168934 | Timing Recovery Circuit and Method Thereof - In the implementation of timing recovery in conventional communication systems, significant errors are generated from modulo operations under certain extreme conditions by taking input signals of a slicer as datum points. In order to prevent such errors, the input signal of a modulo processing circuit is taken as the datum point in place of the input signal of a slicer. This technique could also be applied to communication systems adopting the minimum mean-square error algorithm, the zero-forcing algorithm, or other relevant algorithms. | 07-02-2009 |
20090202025 | MOBILE WIRELESS COMMUNICATION APPARATUS, WIRELESS COMMUNICATION APPARATUS AND COMMUNICATION PROCESSING METHOD - Both a pre-word (PW) and a sync word (SW) are used to establish a synchronization or only the sync word (SW) is used to establish a synchronization in accordance with an operational status related to the synchronization in a mobile wireless communication apparatus. For example, during an initial synchronization with a control channel ( | 08-13-2009 |
20090207957 | Clock recovery circuit - A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting. In addition, the sampling and holding circuit with resetting receives a burst transmission end signal and resets the held value to an initial value. | 08-20-2009 |
20090220036 | DATA INTERFACE AND METHOD OF SEEKING SYNCHRONIZATION - The present invention provides for method of seeking synchronization at a data interface between a transmitting element and a receiving element, and to related transmitting and receiving elements of the interface, in which the clock frequency of both elements is the same but which exhibit a phase difference, also known as mesochronous clock domains, the method including the steps of, prior to data transfer at the interface, delivering a strobe signal generated at the transmitting element to the receiving element, generating a strobe signal at the receiving element and synchronizing the same to the strobe signal received from the transmitting element, and maintaining the synchronized strobe signal generated at the receiving element for the sampling of data appearing at the interface from the transmitting element. | 09-03-2009 |
20090220037 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 09-03-2009 |
20090238317 | APPARATUS AND METHOD FOR TRANSFERRING A SIGNAL FROM A FAST CLOCK DOMAIN TO A SLOW CLOCK DOMAIN - A circuit is provided for transferring a signal from a fast clock domain to a slow clock domain. The circuit includes a fast clock domain configured to receive an input signal and, responsively, transfer an intermediate signal. The circuit also a slow clock domain configured to receive the transferred intermediate signal from the fast clock domain and, responsively, generate an output signal. The circuit further includes a first synchronizer disposed in the slow clock domain and a second synchronizer disposed in the fast clock domain. The first synchronizer, operating with a slow clock, is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal. The second synchronizer, operating with a fast clock, is configured to receive a feedback signal from the first synchronizer for acknowledging synchronization of the output signal to the input signal. | 09-24-2009 |
20090245445 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing. | 10-01-2009 |
20090257537 | DATA RECOVERY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS THAT MINIMIZES JITTER DURING DATA TRANSMISSION - A data recovery circuit that minimizes jitter during data transmission is presented. The data recovery circuit includes a data dividing unit, a data sampling unit, a data selecting unit, and a data recovery unit. The data dividing unit is for dividing external data to generate multiple-division data. The data sampling unit is for sampling the multiple-division data at a first time and a second time to generate sampling data. The data selecting unit is for selecting one of the data sampled at the first time or the second time from the sampling data in accordance to whether the sampling data is transited to output the selected one as selection data. The data recovery unit is for recovering the selection data to internal data in the same logic level as the logic level of the external data. | 10-15-2009 |
20090268858 | DUAL CLOCK SPREAD FOR LOW CLOCK EMISSIONS WITH RECOVERY - A method and apparatus provides for the generation and recovery of a stable clock signal having harmonic emission suppressions using dual spread spectrum clock signals. The transmission frequencies of non-mixed, spread spectrum lower frequency clock signals may be varied and, upon receipt of these non-mixed signals, they are mixed into sum and difference signals. The sum signal thus generated is representative of the desired clock signal to be recovered. Such conditioning of the non-mixed signals need only occur within the receiver, thereby allow the channel that transmits the non-mixed lower frequency clock signals to the receiver to be lower bandwidth than would be required to carry the final, recovered, and higher frequency clock signal produced by the receiver. | 10-29-2009 |
20090279649 | DATA SYNCHRONIZATION METHOD AND RELATED APPARATUS FOR A DISPLAY DEVICE - A data synchronization method for a transmitter of a display device includes utilizing a plurality of first signaling line sets to couple the transmitter and a plurality of receivers in a dedicated type manner, transmitting a synchronization signal to the plurality of receivers according to a transistor-to-transistor logic signal form, transmitting a synchronization start-up signal to the plurality of receivers via the plurality of first signaling line sets a first time later after the synchronization signal is transmitted, and then transmitting a data signal to the plurality of receivers via the plurality of first signaling line sets a second time later after the synchronization start-up signal is transmitted. The synchronization signal has a longer effective time than the synchronization start-up signal. | 11-12-2009 |
20090304134 | DEVICE AND METHOD OF SYNCHRONIZING SIGNALS - A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer. | 12-10-2009 |
20090304135 | SYNCHRONOUS CLOCK GENERATION APPARATUS AND SYNCHRONOUS CLOCK GENERATION METHOD - A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration. | 12-10-2009 |
20090316845 | ASYNCHRONOUS MULTI-CLOCK SYSTEM - A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry. | 12-24-2009 |
20090323875 | Method for Data Synchronization - A method, apparatus, and system for a data synchronizer/serial link receiver that performs the alignment of the sampling clock used to retime asynchronous customer data by the application of a negative delay onto the system clock whereas the value of the applied negative delay is derived from the analysis of a temperature code obtained by a tapped delay line in conjunction with the application of preceding replica delay lines for the in-phase and quadrature clock signals. | 12-31-2009 |
20090323876 | ADAPTIVE SYNCHRONIZATION CIRCUIT - Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and control signals between a first time domain and a second time domain, where the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain. Additionally, the synchronization circuit includes control logic, coupled to the synchronization stages, which is configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization. | 12-31-2009 |
20100002817 | METHOD AND APPARATUS FOR ADAPTIVE TIMING SYNCHRONIZATION IN A COMMUNICATION NETWORK - An adaptive timing synchronization process dynamically adapts timing synchronization parameters for both wide and local area channels based on channel estimates. Timing synchronization parameters are dynamically adapted according to C/I estimates calculated from WID/LID energies. The timing synchronization algorithm | 01-07-2010 |
20100002818 | Electronic apparatus, clock apparatus, and clock control apparatus - An electronic apparatus input and/or output a signal from and/or an external apparatus. The electronic apparatus includes: a clock section in which a frequency is set and which gives a clock signal having the set frequency; an input-output section which inputs and/or outputs the signal according to the clock signal given from the clock section; a frequency detecting section which detects a frequency of a signal given from the external apparatus; and a frequency setting section which determines the frequency of the clock signal based on the frequency detected by the frequency detecting section, and sets the frequency in the clock section. | 01-07-2010 |
20100008456 | Method And System For Compensating Asymmetrical Delays - A method and a data-transmission system for transmitting data encoded in a signal between a transmitting user and a receiving user of the data-transmission system via a network structure of the data-transmission system. The data encoded in the signal are serially transmitted bit-by-bit in data frames having a defined structure. Each bit of the data encoded in the signal is sampled in the receiving user. Due to the transmission via the network structure, the signal is delayed asymmetrically. To compensate for the asymmetrical delay on the physical layer in the transmission channel, it is provided that the asymmetrical delay of the signal is determined at at least one point in the network structure, and is at least partially compensated prior to the receiving user sampling the bits of the data encoded in the signal. A measuring and compensating device is provided to measure and compensate for the asymmetrical delay. | 01-14-2010 |
20100014620 | METHOD AND APPARATUS FOR HIGH SPEED LVDS COMMUNICATION - A method and system communicates payload data over a plurality of low voltage differential signaling (LVDS) channels ( | 01-21-2010 |
20100027728 | INFORMATION PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND SIGNAL TRANSMISSION METHOD - An information processing device includes: a signal receiving portion that receives a signal in which input data that contains first and second bit values different from one another is encoded such that the first bit value is expressed by first amplitude values and the second bit value is expressed by second amplitude values different from the first amplitude values, and such that the same amplitude value does not occur twice in succession and the polarities of the amplitude values are inverted with each cycle; a clock signal extraction portion that extracts a clock signal by detecting polarity inversions in the received signal; a clock signal subtraction portion that subtracts the extracted clock signal from the received signal; and an input data decoding portion that decodes the input data by determining the first and second bit values based on an amplitude value of the signal obtained by subtracting the clock signal. | 02-04-2010 |
20100074383 | TIMESTAMPING METHOD AND APPARATUS FOR PRECISE NETWORK SYNCHRONIZATION - A timestamping apparatus for network synchronization includes a recovery unit and a timestamping unit. The recovery unit extracts a recovery clock operating at an operation frequency of a transmission terminal from a sync signal received from the transmission terminal. The timestamping unit measures a timestamp value of an arrival time of the sync signal by measuring a phase difference between the recovery clock and a local clock of a receiving terminal. | 03-25-2010 |
20100080331 | METHOD AND APPARATUS FOR INTEGRATED CLOCK MISMATCH COMPENSATION AND PACKET LOSS CONCEALMENT - An apparatus and method for processing data are disclosed. The apparatus may include a receiver clock, and a processing system configured to use the receiver clock to receive data from a transmitter, the data being generated with a transmitter clock in the transmitter, wherein the processing system is further configured to estimate a mismatch between the transmitter and receiver clocks, and to determine whether to modify the data based on the estimated mismatch. | 04-01-2010 |
20100086089 | SEMICONDUCTOR INTEGRATED CIRCUIT AND COMMUNICATION SYSTEM - Disclosed is a semiconductor integrated circuit for generating a frequency division clock signal that approximates a desired clock signal without increasing a size thereof. The semiconductor integrated circuit masks, for each programmable cycle, a clock signal to be supplied to a transmission clock generation unit | 04-08-2010 |
20100086090 | CLOCK-DATA RECOVERY AND METHOD FOR BINARY SIGNALING USING LOW RESOLUTION ADC - A binary signal detection based on low resolution ADC includes: a variable-gain amplifier for amplifying an input signal with a gain factor controlled by a gain setting to generate an amplified signal; an ADC for converting the amplified signal into a converter output in accordance with a timing provided by a recovered clock, wherein the converter output has N levels; a timing detection circuit for generating a timing error signal based on the converter output; a filter for filtering the timing error signal to generate a control signal; a controllable oscillator for generating the recovered clock under a control of the control voltage; an automatic gain control for processing the converter data to set the gain setting to control the gain factor; and a data recovery circuit for generate a recovered data based on the converter output. | 04-08-2010 |
20100091921 | FAST POWERING-UP OF DATA COMMUICATION SYSTEM - A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up. | 04-15-2010 |
20100098200 | METHOD AND APPARATUS FOR MANAGING FREQUENCIES USED BY DEVICES - The illustrative embodiments described herein are directed to a method and apparatus for managing frequencies used by devices. In one embodiment, the process detects a set of frequencies from a set of devices to form a set of assigned frequencies. The process may also detect a first frequency used by a first device. The process may determine whether the first frequency interferes with the set of assigned frequencies. The process may also identify an unassigned frequency for use by the first device in response to determining whether the first frequency interferes with the set of assigned frequencies. | 04-22-2010 |
20100098201 | I/O Link with configurable forwarded and derived clocks - An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal. | 04-22-2010 |
20100128829 | Carrier Separation Frequency Error Adjustment for UL Multiple Carrier Operation - One or more carrier signals in a multiple-carrier UE transmitter are frequency-adjusted to account for an estimated error in the separation frequency between the transmitted carrier signals. The adjustment is applied when generating the UL signals for the respective carrier frequencies in digital baseband of the UE. In one embodiment, one or more of the modulators that apply the carrier separation frequency additionally apply a frequency correction. In another embodiment, first mixers apply the carrier separation frequency to each different carrier signal. One or more carrier signal paths include a second mixer applying a frequency correction to the carrier signal. The RF modulation frequency may also be adjusted to partially compensate for the estimated carrier separation frequency error. | 05-27-2010 |
20100128830 | DATA TRANSFER SYSTEM - A data transfer system which can surely transfer data between two function circuits which operate synchronously with different clock frequencies. A data loading signal is generated just before timing when edges of two clocks of different frequencies coincide. Only information data received by the function circuit on a transfer data reception side within an existence period of the data loading signal is determined to be valid. | 05-27-2010 |
20100158177 | LOW JITTER AND HIGH BANDWIDTH CLOCK DATA RECOVERY - A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase. | 06-24-2010 |
20100166127 | APPARATUSES FOR TRANSMITTING AND RECEIVING DATA - An apparatus for transmitting data comprises a clock signal generator generating clock signals; and a transmitter generating transmitting signals having same sized and shaped differential signals, i.e., the clock signals and data signals, subsequent to a strobe signal having common components different from those of the data signals. Accordingly, even though the distortion occurs in the strobe signal during transmission, the clock signal and the data signal can easily be recovered within a give action margin, and timing skew error variation between the clock signal and the data signal can be minimized by noise occurring in the transmission path, whereby the data signal can be transmitted at a higher frequency. Since the clock signal is recovered using the strobe signal, an area occupied by a circuit built in the apparatus for receiving data and used for recovery of the clock signal can be reduced. | 07-01-2010 |
20100166128 | RECEIVER FOR CLOCK RECONSTITUTION - A receiver for clock reconstitution in a semiconductor field includes a termination resistor arranged between two input stages, to which a pair of input signals are input, the termination resistor including a first resistor and a second resistor; a strobe signal generator for generating a strobe signal, using a first signal corresponding to a differential voltage output from a node between the first resistor and the second resistor; and a clock reconstitutor for generating a clock signal in response to the strobe signal generated from the strobe signal generator. | 07-01-2010 |
20100166129 | DATA TRANSMITTING DEVICE AND DATA RECEIVING DEVICE - A data transmitting device and a data receiving device are disclosed. The data transmitting device may include a clock signal generator for generating a clock signal, and a transmitter for generating a transmission signal having the clock signal inserted in a data signal, wherein the clock signal has only a single differential element, and the data signal has two differential elements with an amplitude identical to an amplitude of the clock signal. The clock signal may be embedded and the clock signal may be restored by using the common element of the data signal without any auxiliary reference voltage. As a result, only the data signal line may be used between the data transmitting device and the data receiving device, to reduce the number of transmitting lines. Furthermore, the data transmitting and receiving devices according to embodiments will not need a reference voltage. As a result, the clock signal may be restored smoothly even if the size of the data signal is changing. Further, the amplitude of the clock signal included in the data signal is identical with the amplitude of the data signal. As a result, additional power consumption and EMI may be reduced. | 07-01-2010 |
20100183107 | BURST MODE RECEIVER - A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result. | 07-22-2010 |
20100189206 | Precise Clock Synchronization - A method for clock synchronization includes computing an offset value between a local clock time of a real-time clock circuit and a reference clock time, and loading the offset value into a register that is associated with the real-time clock circuit. The local clock time is then summed with the value in the register so as to give an adjusted value of the local clock time that is synchronized with the reference clock. | 07-29-2010 |
20100202577 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 08-12-2010 |
20100208855 | SYSTEM AND METHOD OF ADAPTING PRECURSOR TAP COEFFICIENT - A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response. | 08-19-2010 |
20100215133 | METHODS AND SYSTEMS FOR COMBINING TIMING SIGNALS FOR TRANSMISSION OVER A SERIAL INTERFACE - Apparatus, systems, and methods are provided for transmitting messages over a serial interface. A method comprises receiving a first signal at a first time and receiving a second signal at a second time, the second time being after the first time. If a difference between the second time and the first time is less than a threshold time period, the method comprises generating a first message that is representative of the first signal and the second signal and transmitting the first message over the serial interface. In accordance with one embodiment, the threshold time period is equal to one half of an interface acquisition delay time period associated with the serial interface. | 08-26-2010 |
20100220827 | DATA COMMUNICATION SYSTEM AND RECEIVING DEVICE - A data communication system comprises a transmitting device which transmits data and a receiving device which receives the data. The transmitting device comprises a clock generating circuit and a transmitting unit. The clock generating circuit generates a clock having a temperature characteristic in that a clock frequency varies with temperature. The transmitting unit transmits data generated in synchronization with the clock to the receiving device. The receiving device comprises a receiving unit, a detecting unit, a storage unit, and a calculating unit. The receiving unit receives the data. The detecting unit detects the clock frequency from the data. The storage unit stores temperature characteristic information regarding the temperature characteristic of the clock frequency. The calculating unit calculates a temperature corresponding to the clock frequency based on the clock frequency and the temperature characteristic information. | 09-02-2010 |
20100232557 | TRANSMISSION TIMING CONTROL SYSTEM AND METHOD, AND MOBILE STATION FOR USE THEREIN - It is an object of the present invention to hold the detecting range of a timing correlator in a base station to the minimum required and to reduce the circuit scale and power requirement of the timing correlator. Before a mobile station transmits a data signal, it transmits a signal referred to as a preamble signal to measure the transmission timing to the base station. If the base station detects the preamble signal with a timing correlator having a limited circuit scale, then the base station transmits a transmission permission signal to the mobile station. If the mobile station fails to receive the transmission permission signal over a given period of time after it has transmitted the preamble signal, then the mobile station retransmits the preamble signal at a changed transmission timing based on the received electric power of a control signal transmitted continuously from the base station and information included in the control signal. The mobile station repeatedly retransmits the preamble signal until it receives the transmission permission signal. If the mobile station receives the transmission permission signal from the base station, then the mobile station transmits a data signal at the transmission timing of the preamble signal transmitted immediately prior to the reception of the transmission permission signal. | 09-16-2010 |
20100246735 | ASYNCHRONOUS DATA RECOVERY METHODS AND APPARATUS - Embodiments of data recovery apparatus include oscillators, edge detection circuitry, and data storage. The oscillators generate data detection signals, which convey first series of pulses during time periods for which a serial bit stream conveys a logical 1, and second series of pulses during time periods for which the serial bit stream conveys a logical 0. The edge detection circuitry detects transition edges of the first and second series of pulses, and generates data storage signals that include first indications of detected transition edges in the first series of pulses and second indications of detected transition edges in the second series of pulses. In response to receiving a first indication, a logical 1 is written into an unmasked subset of data storage bit locations. In response to receiving a second indication, a logical 0 is written into the unmasked subset of bit locations. | 09-30-2010 |
20100278291 | SYSTEM AND METHOD FOR ADVANCED ADAPTIVE PSEUDOWIRE - A system and method for separating clock recovery for a pseudowire communication. An incoming signal is received for a pseudowire communication. The incoming signal is separated into a first signal and a second signal. Packets within the first signal are ordered in a first register. A clock signal is extracted from the second signal in a second register to generate a modified clock signal. A delay is incurred during generating of the modified clock signal. The first signal is communicated utilizing the modified clock signal. | 11-04-2010 |
20100290571 | Inter-device adaptable interfacing clock skewing - Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT. | 11-18-2010 |
20100303184 | Demodulator and communication apparatus - Disclosed herein is a demodulator, including: a frequency synchronization section adapted to synchronize a frequency of a local oscillation signal to be produced on the demodulator side with a local oscillation frequency of a modulation signal transmitting from a modulator side; a demodulation signal production section adapted to produce a demodulation signal based on the local oscillation signal synchronized by the frequency synchronization section and the modulation signal transmitted from the modulator; and a direct current correction section adapted to detect a direct current voltage of the demodulation signal from the demodulation signal produced by the demodulation signal production section and correct the direct current voltage of the demodulation signal so that the direct current voltage becomes equal to a reference voltage set in advance. | 12-02-2010 |
20100310028 | Remote Monitoring and Calibration of System Reference Clock Using Network Timing Reference - A system and method for calibrating a local radio reference clock for a radio operating in a radio network having a network reference clock. The method comprises determining at the radio an offset between the local clock and the network clock, placing the local clock in a calibration mode, and calibrating the local clock using a radio link to reduce the offset. | 12-09-2010 |
20100322365 | SYSTEM AND METHOD FOR SYNCHRONIZING MULTI-CLOCK DOMAINS - A universal synchronizer for preventing signals from first clock domain from causing metastability in sampling registers operating in a second clock domain. A first synchronization flip-flop receives a primary signal from the first clock domain and a second synchronization flip-flop generates a secondary signal synchronized with the second clock domain. Notably, logic is applied to intermediate signals passed between the first synchronization flip-flop and the second synchronization flip-flop. | 12-23-2010 |
20110007855 | Clock Data Recovery Circuit Capable of Generating Clock Signal Synchronized with Data Signal - A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase. | 01-13-2011 |
20110033016 | METHOD AND APPARATUS FOR PROVIDING CARRIER SYNCHRONIZATION IN DIGITAL BROADCAST AND INTERACTIVE SYSTEMS - An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system. | 02-10-2011 |
20110051870 | COMMUNICATION SYSTEM HAVING COMMUNICATION DEVICES CAPABLE OF SYNCHRONOUS COMMUNICATION THEREBETWEEN - There is provided a communication system that includes master and slave communication ECUs. The master communication ECU sends a clock signal to a clock communication line, with which the communication ECUs synchronize with each other when sending and receiving data. The master and slave communication ECUs then receive the clock signal through the clock line. The ECUs use the received clock signal as a reference timing, which is designated as a transmission/reception reference, and send or receive data to/from data communication lines. | 03-03-2011 |
20110058634 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 03-10-2011 |
20110075778 | METHODS FOR CONTROLLING A MAIN CLOCK SOURCE SHARED BETWEEN DIFFERENT WIRELESS COMMUNICATIONS MODULES AND APPARATUSES USING THE SAME - A communications apparatus is provided. A first wireless communications module provides a first wireless communications service and communicates with a first communications device in compliance with a first protocol. A second wireless communications module provides a second wireless communications service and communicates with a second communications device in compliance with a second protocol. A clock source is shared by the first and the second communications modules and provides a reference clock to the first and the second communications modules. The first wireless communications module detects a request from the second wireless communications module for activating the clock source, determines whether the reference clock has been stably generated by the clock source, and adjusts an electrical characteristic of the clock source to facilitate the reference clock output from the clock source to achieve a target frequency when the reference clock has not been stably generated. | 03-31-2011 |
20110075779 | PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS - A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop. | 03-31-2011 |
20110090997 | METHOD FOR TRANSMITTING SYNCHRONIZATION CHANNEL USING MULTI-ANTENNA - A method for transmitting a synchronization channel using multi-antenna is disclosed. In a method for transmitting a synchronization channel for using a synchronization channel as a phase reference when decoding a broadcast channel, the method includes using a pre-decided shift value for each antenna, wherein the shift value is pre-decided with a user equipment, so as to apply circular shifts to sequences of the synchronization channel, and transmitting the sequences having the circular shifts applied thereto from a base station to the user equipment. Herein, space frequency/time block codes (SFBC/STBC) may be applied to the broadcast channel. In performing time/frequency domain synchronization in the synchronization channel, regardless of the number of transmission antennae used by the base station when transmitting signals, the synchronization process may be performed. Also, multi-antenna gain may be obtained when transmitting the synchronization channel. Furthermore, channel estimation may be performed for each antenna, and by applying transmission diversity methods to the BCH/control channel/data channel and so on, the performance of the present invention may also be enhanced. | 04-21-2011 |
20110096880 | Lossless Transfer Of Events Across Clock Domains - Transfer circuits ( | 04-28-2011 |
20110096881 | Method and Device for Clock Data Recovery - A method for the recovery of a clock signal from a data signal, wherein the edges of the data signal and the clock signal are each presented by an ordered sequence of timing points, comprising determining missing edges in the sequence of data-signal edges, inserting new data-signal edges (D | 04-28-2011 |
20110122978 | SERIAL PERIPHERAL INTERFACE HAVING A REDUCED NUMBER OF CONNECTING LINES - An electronic communication system including at least one first communication unit and one second communication unit which are connected to one another by means of at least one first data line. The communication system has a data transmission protocol according to which, in at least one first data transmission mode for synchronized data transmission, the first communication unit transmits a data request signal or a clock signal to the second communication unit via the first data line at least once and the second communication unit transmits a data signal to the first communication unit via the first data line in response to the data request signal or the clock signal. | 05-26-2011 |
20110135046 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A SYNCHRONIZER - A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface. | 06-09-2011 |
20110150156 | METHOD FOR GENERATING A PREAMBLE SEQUENCE AND A METHOD FOR DETERMINING A CYCLIC SHIFT - A method for generating a preamble sequence and determining a cyclic shift. The method includes: when set a piece of root sequence can only generate one preamble sequence and there is no cyclic shift restriction, setting the cyclic shift step length N | 06-23-2011 |
20110164710 | TRANSMISSION TIMING ADJUSTMENT IN RADIO SYSTEMS - A method of adjusting the transmission time of a signal in a radio link, the method being performed by a transmitter configured to transmit the signal over the radio link to a receiver and comprising the steps of ascertaining an accuracy that the receiver assumes for the transmitter's clock, calculating an assumed drift of the transmitter's clock based on the assumed accuracy of that clock and the time since a previous correlation between the transmitter's clock and the receiver's clock; and transmitting the signal at a time dependent on the assumed drift. | 07-07-2011 |
20110176646 | METHOD AND SYSTEM FOR DETERMINING BIT STREAM ZONE STATISTICS - An input bit stream is received and zone statistics such as zones count, zones center bit positions, and zones lengths are determined, where a zone is a set of non-transitioning bits in the input bit stream. Beginning and ending bit positions for each zone are determined simultaneously, and each beginning bit position is associated with an ending bit position. Zone statistics are calculated using the determined beginning and appropriate ending bit positions. | 07-21-2011 |
20110188619 | Electronic circuit, electronic apparatus, and digital signal processing method - A local timing circuit receives a reference timing signal and generates a multi-phase timing signal for output to a digital signal processing circuit. | 08-04-2011 |
20110188620 | Method and Apparatus for Providing a Synthetic System - A method and apparatus of providing a configurable computer system capable of being modeled are disclosed. The system, in one embodiment, includes a configurable component and a clock distributor. The configurable component includes multiple programmable devices arranged in a predefined configuration. The predefined configuration, for example, is a cubical shape having multiple neighboring nodes. The configurable component is capable of being modeled in accordance with policies from a system program for data transmission. The clock distributor further includes a first clock element, which provides long-term accuracy, and a second clock element, which provides short-term accuracy. | 08-04-2011 |
20110206172 | COARSE TIME SYNCHRONIZATION - A system for determining the burst start timing of a signal includes logic configured to receive the signal, generate correlation moduli and generate a first timing output based on the correlation moduli. The logic may also be configured to receive operating mode information and timing information and generate search controls. The logic may further be configured to identify a maximum of the correlation moduli using the search controls and determine a second timing output associated with the maximum correlation modulus. The second timing output represents a more accurate approximation of a burst start time than the first timing output. | 08-25-2011 |
20110216860 | COMMUNICATION METHOD - A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each of processors in a parallel computer start a previous process before a collective communication phase in which communications are performed at a same time among the processors through a inter-processor network. Each processor executes a synchronization command in advance at a time when a portion of the previous process for a predetermined time t is left. The inter-processor synchronization control section transmits a synchronization completion notice to each processor, if a synchronization condition is met. For the period, each processor executes the previous process in parallel. Then, the plurality of processors enter the collective communication phase. | 09-08-2011 |
20110216861 | CIRCUITRY SYSTEM AND METHOD FOR CONNECTING SYNCHRONOUS CLOCK DOMAINS OF THE CIRCUITRY SYSTEM - A clock domain separation device and a method for operating the device is provided for separating two clock domains of a bus system in a system-on-chip (SoC). The clock domain separation device is a hardware module that acts as a guarding between the two clock domains that contain either bus end, and is generally applicable with handshake-type bus protocols. The clock domain separation module allows for each clock domain to switch its clock on and off independently from the state of the other clock domains, without risking data loss or protocol violation. | 09-08-2011 |
20110235762 | SYMBOL TIMING SYNCHRONIZATION METHODS AND APPARATUS - Embodiments include methods and apparatus for performing symbol timing synchronization for a symbol-bearing signal. The symbol-bearing signal is sampled to produce a plurality of symbol samples. First-direction interpolation processes are performed on the plurality of symbol samples in a first temporal direction, where the first temporal direction is a direction from a first sampling time towards a second sampling time. In addition, second-direction interpolation processes are performed on the symbol samples in a second temporal direction, where the second temporal direction is a direction from the second sampling time towards the first sampling time, resulting in a set of interpolated symbol samples. | 09-29-2011 |
20110249780 | OFDM Frame Synchronisation Method and System - An OFDM frame synchronisation method in which the symbols of the preamble carry a code. The detection of the code allows the frame synchronization in presence of low SNR. | 10-13-2011 |
20110249781 | DEVICE FOR RECONSTRUCTING THE CLOCK OF AN NRZ SIGNAL, AND ASSOCIATED TRANSMISSION SYSTEM - The invention relates according to a first aspect to a device ( | 10-13-2011 |
20110261914 | Digital Modulator - The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal. | 10-27-2011 |
20110268233 | APPARATUS AND METHOD FOR TIMING OF SIGNALS - The invention relates to a method and an apparatus ( | 11-03-2011 |
20110268234 | METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING A TIMING CORRECTION MESSAGE IN A WIRELESS COMMUNICATION SYSTEM - A method for transmitting a timing correction message in a wireless communication system, the method comprising, Generating the timing correction message comprising a 8-bit MessageID field and a 2-bit NumSectors field wherein, the NumSectors field indicates the number of sector records in the message and a 16 bit TimingCorrection field wherein, the TimingCorrection indicates the timing correction on the sector and last 15 bits indicate the magnitude of timing correction in units of 1/8 chips and transmitting the timing correction message over a communication link. | 11-03-2011 |
20110274226 | SYNCHRONIZATION PROCESSING CIRCUIT AND SYNCHRONIZATION PROCESSING METHOD IN WIRELESS COMMUNICATION SYSTEM - In a synchronization processing circuit in a wireless communication system, a correlation operation unit is designed to have a parallel structure which can be restructured to improve flexibility in order to cope with various synchronization processings in a plurality of radio systems. | 11-10-2011 |
20110280353 | Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock - The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator. | 11-17-2011 |
20110280354 | FRAME TIMING CONTROLLER AND FRAME TIMING CONTROL METHOD FOR TRIGGERING AT LEAST RECEIVER IN MOBILE STATION TO START RECEIVING TRANSMITTED INFORMATION OF BASE STATION BY REFERRING TO AT LEAST FRAME POINTER - A frame timing controller includes a timer, a frame timing control unit, and a frame pointer processing circuit. The timer is arranged to generate a timer value according to a first clock signal with a first clock frequency. The frame timing control unit is for triggering at least a receiver to start receiving transmitted information of a base station according to at least a frame pointer and the timer value, wherein the receiver processes an input signal to generate first samples at a first sampling rate corresponding to a sampling clock frequency and processes the first samples to generate an output signal including second samples at a second sampling rate corresponding to a second clock frequency of a second clock signal different from the sampling clock frequency. The frame pointer processing circuit is for generating and updating the frame pointer according to the output signal of the receiver. | 11-17-2011 |
20110311009 | PATTERN AGNOSTIC ON-DIE SCOPE - An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream. | 12-22-2011 |
20120002771 | RECEIVER, SEMICONDUCTOR DEVICE, AND SIGNAL TRANSMISSION METHOD - A receiver comprises: a reception coil through which flow a current of a polarity corresponding to data is allowed to flow by flowing a current through a transmission coil for every rising edge or falling edge of a clock signal relating to transmission of data, and generates a signal induced by means of electromagnetic induction by flowing the current through the transmission coil; a transition detection circuit which detects a level transition of a signal generated in the reception coil; and a clock recovery circuit which recovers the clock signal based on the detection result of the transition detection circuit. | 01-05-2012 |
20120027143 | CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF - One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock. | 02-02-2012 |
20120027144 | MULTI-PHASE CLOCK SWITCHING DEVICE AND METHOD THEREOF - A multi-phase clock switching device includes a plurality of phase selection circuits. The phase selection circuit is used to receive a plurality of phase clock signals and determine how to output the phase clock signals to generate an output signal according to a switching signal. The phase selection circuit includes a selection unit and a protection unit. The selection unit receives at least a phase clock signal and determines how to output a phase clock signal according to the at least a phase clock signal and a selection signal. The protection unit determines how to generate the selection signal according to the phase clock signal and the switching signal. | 02-02-2012 |
20120082279 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 04-05-2012 |
20120087452 | Techniques for Adjusting Clock Signals to Compensate for Noise - A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs. | 04-12-2012 |
20120099687 | METHOD AND SYSTEM OF SYNCHRONIZING DATA TO REFERENCE TIME SIGNAL WITH DATA RESAMPLING - A device receives a data signal and a reference timing signal provided from a first clock. The device includes a sample clock that operates independently from the first clock, wherein the sample clock outputs a sample clock signal that is asynchronous with the reference timing signal; a sampler for sampling a data signal in accordance with the sample clock signal and outputting a sampled data signal; and a resampler for resampling the sampled data signal according to a resampling ratio and outputting a resampled data signal such that a number of data samples in the resampled data signal within a synchronization time interval defined with respect to the reference timing signal equals a nominal number of data samples that would occur in the sampled data signal within the synchronization time interval when the sample clock signal was synchronized to the reference timing signal. | 04-26-2012 |
20120106687 | Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions - A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew. | 05-03-2012 |
20120114086 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips. | 05-10-2012 |
20120121049 | INITIAL PHASE ESTIMATOR TO ACCELERATE CARRIER PHASE RECOVERY - Methods for accelerating a fine carrier phase and frequency offset recovery algorithm in a receiver of a communication system are provided. More specifically, a method for estimating and compensating for an initial phase offset of a received signal provided. Computing an initial phase shift and compensating for it can reduce the time needed to provide fine estimation and compensation for carrier phase and frequency offset. Furthermore, computing an initial phase shift and compensating for it also can improve system performance by reducing the non-linearity that otherwise would be introduced into the system by fine carrier phase and frequency offset algorithms. | 05-17-2012 |
20120121050 | Method and Apparatus for Analog Pulse Pile-Up Rejection - A method and apparatus for pulse pile-up rejection are disclosed. The apparatus comprises a delay value application constituent configured to receive a threshold-crossing time value, and provide an adjustable value according to a delay value and the threshold-crossing time value; and a comparison constituent configured to receive a peak-occurrence time value and the adjustable value, compare the peak-occurrence time value with the adjustable value, indicate pulse acceptance if the peak-occurrence time value is less than or equal to the adjustable value, and indicate pulse rejection if the peak-occurrence time value is greater than the adjustable value. | 05-17-2012 |
20120128110 | METHOD AND SYSTEM FOR ELIMINATING IMPLEMENTATION TIMING IN SYNCHRONIZATION CIRCUITS - A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of dock input pins can be connected with at least two asynchronous dock domains of the synchronization circuit in order to measure a timing signal between the flip-flop latches crossing the asynchronous clock domain. A timing delay with respect to each bit pair of the asynchronous dock domain can be determined utilizing a static analysis approach during a layout phase in order to effectively synchronize the asynchronous dock domain. Each bit pair of the asynchronous dock domain can be checked via a static timing analysis tool in order to thereby improve functional accuracy of the synchronization circuit in a wide range of digital logic designs. | 05-24-2012 |
20120134455 | AIR INTERFACE SYNCHRONIZATION METHOD, APPARATUS AND SYSTEM - An air interface synchronization method is provided. The method includes that: a home-eNodeB which is not synchronized with an eNodeB, intercepts a synchronization subframe transmitted from the eNodeB and/or the home-eNodeB which was already synchronized with the eNodeB, a synchronization reference base station is selected from the base station which transmits the intercepted synchronization subframe, wherein the synchronization subframe includes a special synchronization channel for broadcasting synchronization sequence; the synchronization sequence is obtained, which is broadcasted in the special synchronization channel of the synchronization subframe transmitted by the synchronization reference station, and the synchronization with the synchronization base station is performed according to the synchronization sequence. Also, an air interface synchronization system, an eNodeB and a home-eNodeB are provided. The problem in prior art that the source is wasted in the process of synchronization is solved according to the method, the system, the eNodeB and the home-eNodeB. | 05-31-2012 |
20120155584 | SYNCHRONIZATION OF REMOTE CLOCKS - A system for synchronizing a first clock and a second clock includes a receiver associated with the first clock, configured to receive a remote pulse from the second clock. The remote pulse has a pulse repetition frequency and spectral characteristics that are known to the local clock. The system also includes a local pulse emitter configured to create a local pulse at the first clock, and optics configured to align the local pulse and the remote pulse. The system further includes an interferometer configured to create an interference pattern between the local pulse and the remote pulse. A controller is provided that is configured to calculate a time delay between the first clock and the second clock based on the interference pattern between the local pulse and the remote pulse. | 06-21-2012 |
20120155585 | SYSTEM AND METHOD FOR MULTIPLEXING A TIME-REFERENCE SIGNAL AND A FREQUENCY-REFERENCE SIGNAL - A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock. | 06-21-2012 |
20120163519 | CLOCK AND DATA RECOVERY UNIT WITHOUT AN EXTERNAL REFERENCE CLOCK - A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A reference clock generator supplies a reference clock signal to a clock and data recovery module that uses the reference clock as a tuning or reference signal to produce the recovered clock and recovered data signals. The reference clock generator modifies the reference clock signal so that its frequency corresponds, within a small tolerance, to the data rate of the serial data stream. The reference clock generator determines a beat frequency between a voltage-controlled oscillator clock signal and the data rate and adjusts the voltage-controlled oscillator frequency, from which the reference clock is generated, to lower the beat frequency below a divided down version of the voltage-controlled oscillator clock. | 06-28-2012 |
20120177158 | SYNCHRONIZATION CIRCUIT - A synchronization circuit includes a delay line, and a first loop and a second loop configured to share the delay line, and the second loop is activated when a number of unit delay cells used in the delay line is equal to or less than a predetermined number according to an operation of the first loop. | 07-12-2012 |
20120195400 | ESTIMATION AND COMPENSATION OF CLOCK VARIATION IN RECEIVED SIGNAL - A method and system for estimating and compensating for variation between a receiver clock and a transmitter clock, where a receiver utilizes a high frequency clock signal to generate a receiver clock and then adjusts the receiver clock to compensate for variations between the receiver and transmitter clocks. The adjusted receiver clock is used to sample nibble pulses in a received data frame. Counter based compensation of the receiver clock eliminates the need for the receiver to perform floating point calculations, improves the accuracy of nibble pulse sampling and also reduces area and power consumption of the device. | 08-02-2012 |
20120230454 | RECEIVER TRAINING WITH CYCLE SLIP DETECTION AND CORRECTION - In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used. | 09-13-2012 |
20120230455 | APPARATUS AND METHOD FOR DESKEWING SERIAL DATA TRANSMISSIONS - Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed. | 09-13-2012 |
20120236977 | Methods For Synchronizing Macro Cell And Small Cell Systems - Example embodiments are directed to a method including transmitting, by a small cell, a pilot signal to a user equipment (UE) based on a first training signal received from the UE, and receiving, by the small cell, a second training signal from the UE. The second training signal is offset by a time based on the pilot signal transmitted by the small cell. The time offset represents a difference in time between the UE receiving a reference signal transmitted by a macro cell and the UE receiving the pilot signal transmitted by the small cell. The small cell adjusts a local reference timing based on the second training signal. | 09-20-2012 |
20120263263 | MEDIA CLOCK NEGOTIATION - Media Clock Negotiation (MCN) Advertise packets may advertise one or more media clock streams. Each media clock stream may include values of a real-time clock sampled according to a first media clock. A second media clock may be recoverable from the media clock stream such that the second media clock is synchronized with the first media clock. One or more transmitters that receive the packets may determine whether the advertised media clock stream meets a set of media clock conditions. If the advertised media clock stream meets the set of media clock conditions, then the transmitter may add the advertised media clock stream to a set of qualified streams. Each transmitter may select a reference media clock stream from the set of qualified streams. By selecting the same reference media clock stream, media clocks at two or more transmitters may be synchronized. | 10-18-2012 |
20120328061 | METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR USING DISCOVERED CLOCK IN A FIRST COMMUNICATIONS PROTOCOL TO SYNCHRONIZE NETWORKING ACTIVITY IN A SECOND COMMUNICATIONS PROTOCOL - Method, apparatus, and computer program product example embodiments use native clock timing of a first wireless communications protocol to establish synchronization of a wireless network of a second wireless communications protocol. According to an example embodiment of the invention, a method comprises maintaining a native clock time in a first wireless communications protocol; activating one or more wireless messages in a second wireless communications protocol, based on the native clock time of the first wireless communications protocol; receiving a wireless message in the first wireless communications protocol; and transmitting one or more second wireless messages in the first wireless communications protocol, including information related to the native clock time, to enable a receiving apparatus to synchronize its activation of one or more messages in the second wireless communications protocol, with the one or more wireless messages activated in the second wireless communications protocol. | 12-27-2012 |
20130016801 | METHOD AND APPARATUS FOR GENERATING SECONDARY SYNCHRONIZATION SIGNALSAANM Xia; ShuqiangAACI ShenzhenAACO CNAAGP Xia; Shuqiang Shenzhen CNAANM Mi; DezhongAACI ShenzhenAACO CNAAGP Mi; Dezhong Shenzhen CN - The present invention provides a method and an apparatus for generating secondary synchronization signals, wherein the method comprises steps of: determining a value of iteration times M according to a total number N of cell ID groups or a cell ID group index N | 01-17-2013 |
20130022162 | MULTI-PHASE CLOCK GENERATOR - A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2 | 01-24-2013 |
20130058444 | Fault Tolerant Communications Over a Two-Wire Interface - Techniques are provided for fault-tolerant communications over a two-wire interface. A method for such communications includes iteratively initiating transfer of data between a master device and a slave device via a two-wire interface, and, prior to each iteration, transmitting a flushing bit-stream from the master device to the slave device. The flushing bit-stream is configured to align the operations of the slave device with the operations of the master device. | 03-07-2013 |
20130064336 | Data Synchronization Policies - Techniques for data synchronization policies are described. In one or more implementations, techniques may be employed to set data synchronization (“sync”) policies for devices in a data sync environment. The sync policies specify parameters for sync operations in the sync environment, such as how frequently data sync operations are performed, what types of data are synced to particular devices, how frequently particular types of data are synced, and so on. In implementations, the sync policies consider the number of devices that are participating in a sync environment and attributes of the devices in specifying parameters for sync operations. Data can be synchronized among devices in the sync environment based on the sync policies. | 03-14-2013 |
20130064337 | Method and Apparatus for Adaptive Hysteresis Timer Adjustments for Clock Gating - Apparatus and method for adaptive hysteresis timer adjustments for clock gating are disclosed. An apparatus comprises a transaction circuit configured to perform transactions. The apparatus further comprises a hysteresis timer having a hysteresis value and configured to start counting based on the hysteresis value when a transaction in the transaction circuit has been completed. The apparatus further comprises a hysteresis timer update circuit configured to monitor the hysteresis timer and the transaction circuit, store an adjustment state based on whether a new transaction is received before, coincident with or after the count of the hysteresis timer expires and adjust the hysteresis value based on the adjustment state. | 03-14-2013 |
20130070879 | GENERATING A REGULARLY SYNCHRONISED COUNT VALUE - A count value generator includes an input for receiving a synchronising count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronising frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronising frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronising count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value. | 03-21-2013 |
20130070880 | SYSTEM AND METHOD FOR DETERMINING A TIME FOR SAFELY SAMPLING A SIGNAL OF A CLOCK DOMAIN - A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained. | 03-21-2013 |
20130083877 | NON-COHERENT COMBINING DETECTION WITH REDUCED BUFFERING REQUIREMENTS - Certain aspects of the present disclosure provide techniques for reducing the amount of storage needed for detecting a primary synchronization signal (PSS). According to certain aspects, a user equipment may store a limited number of samples corresponding to the strongest peaks per PSS index and perform PSS detection based on an analysis of the limited number of stored samples. | 04-04-2013 |
20130094622 | SYSTEM AND METHOD FOR SYNCHRONIZATION OF NETWORKED FIRE ALARM PANELS - A system and method for synchronizing a plurality of networked fire alarm panels is disclosed. A plurality of fire panels (i.e., nodes) are arranged on a peer-to-peer network, such as a token ring network. One node is designated as a SyncHost, and the remaining nodes are periodically reset to the clock time associated with the SyncHost to ensure all nodes remain substantially synchronized to a single time. Upon alarm, the visual notification devices (i.e., strobe lights) of all the fire panels (nodes) will flash at substantially the same time. To accomplish the synchronization, the SyncHost sends periodic attendance polls around the network, noting the transit times of the polls. The nodes also note times associated with the polls. The SyncHost sends a sync message to the nodes, and each of the nodes resets its clock according to the sync message and internal compensations. Other embodiments are disclosed and claimed. | 04-18-2013 |
20130148768 | PREDICTABLE CODING DELAY OVER COMMUNICATIONS NETWORKS - A decoder includes a buffer configured to incrementally transport a synchronous data stream through a path of the decoder. A control circuit is configured to control a depth parameter associated with the buffer and to provide a substantially predictable delay of the synchronous data stream through the path of the decoder. | 06-13-2013 |
20130163706 | Clock and Data Recovery Circuit and Parallel Output Circuit - The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit. | 06-27-2013 |
20130182805 | RATE MATCHING METHOD AND APPARATUS - Embodiments of the present invention provide a rate matching method and apparatus. The method includes: receiving bit data of a first, a second, and a third input subblock, inserting dummy data into bit data in each subblock to respectively form even-numbered rows and odd-numbered rows of a matrix to be buffered for each subblock; inputting bit data of the even-numbered rows in the even-numbered row buffer and bit data of the odd-numbered rows in the odd-numbered row buffer of each subblock to a second buffer, and forming a matrix by using the bit data of the even-numbered rows and the bit data of the odd-numbered rows; controlling the second buffer to send data at the specified address; selecting data sent by the second buffer; and deleting the dummy data from the selected data to obtain valid output data. | 07-18-2013 |
20130195233 | TECHNIQUES FOR SYNCHRONIZING A CLOCK OF A WIRED CONNECTION WHEN TRANSMITTED OVER A WIRELESS CHANNEL - An apparatus and method for synchronizing a multimedia interface clock between a multimedia source device and a multimedia sink device connected over a wireless channel. The method comprises measuring a frequency of the source clock signal generated by the multimedia source device, wherein the measurement of the frequency is performed using a first reference clock signal; generating a frequency-stamp message including in part the measured frequency; encapsulating the frequency-stamp message in at least one packet; and transmitting the at least one packet to a wireless receiver connected to the multimedia sink device over the wireless channel. | 08-01-2013 |
20130223577 | METHOD, APPARATUS, AND SYSTEM FOR TIME SYNCHRONIZATION - A method, apparatus, and system for time synchronization are disclosed. The method comprising: obtaining a master sending time stamp, a slave receiving time stamp, a slave sending time stamp, and a master receiving time stamp; and adjusting the time of the slave clock according to the offset calculated from the time stamps to synchronize with the clock time of the master clock. With the present invention, in passband transmission systems that transmit signals continuously in units of symbols, the time synchronization is implemented between the master clock and the slave clock. | 08-29-2013 |
20130243136 | Method and Apparatus for Maintaining Synchronization in a Communication System - A central entity and/or a remote device in a communication system are designed to address the problem of maintaining upstream synchronization in the remote device after loss of the downstream signal. One issue of particular importance is maintaining upstream transmissions from the remote device in an S-CDMA (or perhaps S-TDMA) mode that do not degrade performance of the communication system via poor upstream timing or a need for re-ranging. By providing novel functionality at the central entity for synchronizing first and second downstream signals and/or by providing novel functionality at the remote device for determining a symbol clock offset between a first terminated downstream signal and a second re-acquired downstream signal, embodiments of the present invention facilitate maintenance of synchronization through the loss of the downstream signal, thereby minimizing the need for re-ranging and avoiding poorly timed upstream bursts. | 09-19-2013 |
20130243137 | MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK - A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller. | 09-19-2013 |
20130266103 | LOW-POWER HIGHLY-ACCURATE PASSIVE MULTIPHASE CLOCK GENERATION SCHEME BY USING POLYPHASE FILTERS - Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response. | 10-10-2013 |
20130294554 | EXTRACTING CLOCK INFORMATION FROM A SERIAL COMMUNICATIONS BUS FOR USE IN RF COMMUNICATIONS CIRCUITRY - The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both. | 11-07-2013 |
20130329842 | SYNCHRONIZER WITH A TIMING CLOSURE ENHANCEMENT - Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput. | 12-12-2013 |
20130343501 | PHYSICAL LAYER CHANNEL SYNCHRONIZATION METHOD FOR HIGH BIT-RATE CABLE TRANSMISSIONS - A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to many up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels. | 12-26-2013 |
20140003564 | MULTICHIP SYNCHRONIZATION SYSTEM | 01-02-2014 |
20140064420 | Method and System for Power Management in a Network Device Based on Multi-protocol Detection - A network device may comprise one or more circuits including a clock signal generator, an ADC, and a processor. The ADC may digitize a received signal across a range of frequencies that encompasses a first band of frequencies used for a first network and a second band of frequencies used for a second network. A sampling frequency of the ADC may be determined by a frequency of a clock signal output by the clock signal generator. The processor may determine whether the first network is active and whether the second network is active. The processor may configure the clock generator such that, when both of the first network and the second network are active, the clock signal is set to a first frequency, and when the first network is active and the second network is inactive, the clock signal is set to a second frequency. | 03-06-2014 |
20140079169 | RESONANT CLOCK AMPLIFIER WITH A DIGITALLY TUNABLE DELAY - A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency. | 03-20-2014 |
20140105339 | SIGNAL RECEIVER WITH MULTI-LEVEL SAMPLING - A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry. | 04-17-2014 |
20140112424 | METHOD AND SYSTEM FOR CLOCK RECOVERY WITH ADAPTIVE LOOP GAIN CONTROL - A method for phase recovery in a system that includes a clock recovery unit and an estimation unit. The clock recovery unit of the system has a first phase detector unit. The estimation unit has a second phase detector unit and it is configured to estimate a gain of the second phase detector unit. The estimation unit and the clock recovery unit are configured to operate in parallel. | 04-24-2014 |
20140133613 | APPARATUS AND METHODS FOR CLOCK ALIGNMENT FOR HIGH SPEED INTERFACES - Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources. | 05-15-2014 |
20140140456 | METHODS AND APPARATUS FOR ENABLING DISTRIBUTED FREQUENCY SYNCHRONIZATION - A method, an apparatus, and a computer program product for wireless communication are provided in connection with enabling distributed frequency synchronization based on a fastest node clock rate. In one example, a first UE is equipped to determine that a fastest clock rate is faster than an internal clock rate of the first UE by more than a first positive offset, and adjust the internal clock rate based on the determined fastest clock rate. In an aspect, the fastest clock rate is associated with a second UE of one or more other UEs from which synchronization signals may be received. In another example, a UE is equipped to obtain GPS based timing information, adjust an internal clock rate based on the GPS based timing information, and transmit a synchronization signal at an artificially earlier time in comparison to a scheduled time of transmission associated with the adjusted internal clock rate. | 05-22-2014 |
20140185723 | Signal Delay Estimator with Absolute Delay Amount and Direction Estimation - A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively. | 07-03-2014 |
20140185724 | SEQUENCE GENERATING METHOD FOR EFFICIENT DETECTION AND METHOD FOR TRANSMITTING AND RECEIVING SIGNALS USING THE SAME - A sequence generation method for allowing a reception end to effectively detect a sequence used for a specific channel of an OFDM communication system, and a signal transmission/reception method using the same are disclosed. During the sequence generation, an index is selected from among the index set having the conjugate symmetry property between indexes, and a specific part corresponding to the frequency “0” is omitted from a transmitted signal. In addition, a reception end can calculate a cross-correlation value between a received (Rx) signal and each sequence using only one cross-correlation calculation based on the conjugate symmetry property. | 07-03-2014 |
20140198888 | DISCRETE SIGNAL SYNCHRONIZATION BASED ON A KNOWN BIT PATTERN - Systems and methods for discrete signal synchronization based on a known bit pattern are described. In one aspect of the present subject matter, a discrete signal synchronization system is configured to synchronize a preprocessed discrete signal with a modified discrete signal. The system comprises a processor and a synchronization module coupled to the processor. The synchronization module comprises an extraction module and comparison module. The extraction module determines a bit pattern from the modified discrete signal using Discrete Wavelet Transformation (DWT) and Singular Value Decomposition (SVD). The comparison module compares the determined bit pattern with a known bit pattern of the preprocessed discrete signal and records a time point at which the determined bit pattern matches with the known bit pattern of the preprocessed discrete signal as a synchronization point. | 07-17-2014 |
20140205046 | SOURCE DEVICE, COMMUNICATION SYSTEM, METHOD OF CONTROLLING SOURCE DEVICE, AND METHOD OF CONTROLLING SINK DEVICE - A source device includes: a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of clock signals having different frequencies, the low clock signal having a frequency lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the clock signals, the high clock signal having a frequency higher than that of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data in accordance with a ratio between the frequencies of the high and low clock signals; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored data. | 07-24-2014 |
20140211893 | HIGH FREQUENCY SYNCHRONIZER - Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal. | 07-31-2014 |
20140211894 | DATA INTERFACE SYNCHRONIZATION - In one embodiment, an apparatus may include a de-serializer to convert serial data to parallel data, and a counter to provide an update signal based on a bit count of the serial data. The apparatus may further include a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal. The apparatus may further include an output unit to provide a validation indicator in response to the synchronization signal. | 07-31-2014 |
20140211895 | Frequency Division - A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal. | 07-31-2014 |
20140286466 | MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING - A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions. | 09-25-2014 |
20140301513 | NODE DEVICE AND METHOD FOR SYNCHRONIZING CLOCK TIMES - A node device includes a processor, a wireless RF circuit, a memory, and a timer. The processor measures a clock time. The wireless RF circuit receives a clock time information frame containing clock time information used for correcting the clock time. The memory stores a transmission processing time period, as a fixed value, from when a transmission source node device of the clock time information frame obtains the clock time information until when the transmission source node device transmits the clock time information frame. The timer measures a reception processing time period, which is a period of time from when the clock time information frame is received until when the clock time information is obtained. The node device sets to the processor a value obtained by adding the fixed value and the reception processing time period to the clock time information. | 10-09-2014 |
20140321585 | Method and Apparatus for Rapid Synchronization of Shift Register Related Symbol Sequences - A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism. | 10-30-2014 |
20140328441 | Synchronized Clock Event Report - The present application discloses monitoring a plurality of time inputs to detect a defined time event and providing a report of the plurality of time inputs for analysis in response to detecting the defined time event. To create the report, an event monitor records data relating to the plurality of time inputs in a temporary memory for a defined window of time. In response to detecting the defined time event, the event monitor transfers the data recorded in the temporary memory to a persistent memory and continues to record data relating to the plurality of time inputs to the persistent memory for a second defined window of time. The event monitor provides a report of the data relating to the plurality of time inputs stored in the persistent memory for analysis. | 11-06-2014 |
20140334581 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 11-13-2014 |
20140376674 | Frequency-Domain Frame Synchronization In Multi-Carrier Systems - Methods and systems are disclosed for frequency-domain frame synchronization for multi-carrier communication systems. Received signals are sampled and converted into frequency domain components associated with subcarriers within the multi-carrier communication signals. A sliding-window correlation (e.g., two-dimensional sliding window) is applied to the received symbols represented in the frequency domain to detect frame boundaries for multi-carrier signals. The sliding-window frame synchronization can be applied by itself or can be applied in combination with one or more additional frame synchronization stages. The disclosed embodiments are particularly useful for frame synchronization of multi-carrier signals in PLC (power line communication) systems. | 12-25-2014 |
20150016578 | CLOCK RECOVERY IN COMMUNICATION OF HIERARCHICALLY ENCAPSULATED SIGNALS - An apparatus includes a data flow circuit and a clock recovery circuit. The data flow circuit is configured to extract client data, which is encapsulated in an inner frame that is encapsulated in at least an outer frame, and to output the extracted client data in accordance with a client clock signal. The clock recovery circuit includes a first clock recovery module that is configured to recover a first clock signal that matches payload data in the outer frame, and a second clock recovery module that is configured to derive from the first clock signal a second clock signal that matches the client data in the inner frame, and to produce the client clock signal from the second clock signal, for use by the data flow circuit. | 01-15-2015 |
20150030111 | SYSTEM AND METHOD FOR GENERATING AN ESSENTIALLY SINUSOIDAL SYNCHRONIZATION PULSE - A reception system for a control unit in a vehicle having a voltage generator for generating a synchronization pulse which generates the synchronization pulse within predefined specification limits and having a predefined shape and a predefined time behavior, the reception system outputting the synchronization pulse for synchronizing a signal transmission via a data bus to at least one sensor, and a method for generating such a synchronization pulse. The voltage generator includes a voltage amplifier which generates the synchronization pulse generally as a sinusoidal oscillation based on a reference voltage. | 01-29-2015 |
20150043688 | METHOD, APPARATUS AND SYSTEM TO COMMUNICATE WITH A DEVICE - Described herein are implementations relating to a method for an apparatus to communicate with a device. One embodiment includes transmitting a clock signal to the device, receiving from the device, an asynchronous signal, and extracting information from the asynchronous signal based on the clock signal. In one embodiment the clock signal has a periodic elementary pattern. A period of the clock signal, in one embodiment encompasses, more than one clock cycle. Further disclosed are an apparatus to communicate with a device and a system for communication with a device. | 02-12-2015 |
20150043689 | CIRCUIT ARRANGEMENT AND METHOD FOR TRANSMITTING SIGNALS - On the basis
| 02-12-2015 |
20150043690 | CIRCUIT ARRANGEMENT AND METHOD FOR TRANSMITTING SIGNALS - On the basis
| 02-12-2015 |
20150043691 | CIRCUIT ARRANGEMENT AND METHOD FOR TRANSMITTING SIGNALS - On the basis
| 02-12-2015 |
20150043692 | CIRCUIT ARRANGEMENT AND METHOD FOR TRANSMITTING SIGNALS - On the basis | 02-12-2015 |
20150043693 | N-PHASE SIGNAL TRANSITION ALIGNMENT - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state. | 02-12-2015 |
20150043694 | METHOD AND APPARATUS FOR TRANSMITTING SYNCHRONIZATION SIGNALS IN AN OFDM BASED CELLULAR COMMUNICATION SYSTEM - A method and apparatus are provided for transmitting a synchronization signal for cell search in an Orthogonal Frequency Division Multiplexing (OFDM) communications system. The method includes identifying a primary synchronization sequence; identifying a secondary synchronization sequence associated with a cell identifier; mapping the primary synchronization sequence based on center subcarriers in a first OFDM symbol; mapping the secondary synchronization sequence based on the center subcarriers in a second OFDM symbol; transmitting the mapped primary synchronization sequence in the first OFDM symbol; and transmitting the mapped secondary synchronization sequence in the second OFDM symbol. The second OFDM symbol is adjacent to the first OFDM symbol, and the center subcarriers are part of a system bandwidth and a part of the center subcarriers is not used for mapping the secondary synchronization sequence. | 02-12-2015 |
20150049848 | RECEIVER CIRCUIT, COMMUNICATION SYSTEM, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING RECEIVER CIRCUIT - A receiver circuit etc. which can receive a high-speed signal is provided without providing a PLL circuit etc. A first receiver circuit for capturing an input signal at a plurality of capture timings determined based on a capture clock signal, includes a delay circuit configured to delay the input signal by a set delay time, and output the delayed input signal, a data latch circuit configured to capture the input signal delayed by the delay circuit at each capture timing, a data test circuit configured to test a latch signal captured by the data latch circuit, and a data test result register configured so that a test result value is set therein. The data test circuit compares the latch signal captured by the latch circuit at each capture timing with an expected value, and outputs the result of the comparison. | 02-19-2015 |
20150063510 | COMMUNICATION UNIT AND SLICED RADIO FREQUENCY MODULE THEREFOR - A communication unit includes at least one divider module arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal, and a plurality of sliced RF modules. Each of the plurality of sliced RF modules includes: an input for receiving a clock signal; a timing synchronisation module arranged to receive the divided representation of the RF signal and synchronise the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and at least one logic module operably coupled to the timing synchronisation module and arranged to receive the clock signal and a synchronised output from the timing synchronisation module. A combiner port is arranged to couple a number of synchronised outputs from the plurality of sliced RF modules. | 03-05-2015 |
20150063511 | TRANSMITTING DEVICE, SENDING DEVICE AND RECEIVING DEVICE - According to one embodiment, a transmitting device includes a wireless transmitting unit which wirelessly transmits data. The transmitting device includes a wireless receiving unit which receives the data wirelessly transmitted by the wireless transmitting unit. The transmitting device includes a synchronization signal outputting unit which outputs a synchronization signal to a signal transmitting medium of an electric conductor. The transmitting device includes a synchronization outputting unit which receives the synchronization signal from the signal transmitting medium and outputs a signal including the data received by the wireless receiving unit according to the synchronization signal. | 03-05-2015 |
20150078498 | METHOD FOR CHECKING THE OPERATION OF A PSI5 RECEPTION UNIT IN A MOTOR VEHICLE CONTROLLER, AND CORRESPONDING PSI5 RECEPTION UNIT - A method for checking the operation of a PSI5 reception unit in a motor vehicle controller is presented, wherein the PSI5 reception unit receives signals from a connected PSI5-compliant PSI5 transmission unit, wherein a check signal transmission unit is provided and this check signal transmission unit sends a prescribed check signal to the PSI5 reception unit at prescribed check times at which no signal can be expected from the PSI5 transmission unit, in particular—together with the sending of one or more synchronization pulses to the transmission unit—the check signal transmission unit sends the check signal in this defined period. | 03-19-2015 |
20150078499 | INTEGRATED PROCESSOR AND CDR CIRCUIT - A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate. | 03-19-2015 |
20150092898 | Receiver with enhanced clock and data recovery - A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler. | 04-02-2015 |
20150139373 | DATA TRANSFER BETWEEN CLOCK DOMAINS - An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means ( | 05-21-2015 |
20150139374 | SATELLITE RADIO-CONTROLLED WRISTWATCH - Power consumption when reception is carried out in response to a reception instruction by a user is reduced in a satellite radio-controlled wristwatch. A satellite radio-controlled wristwatch according to the present invention includes: a satellite radio wave reception unit including an antenna, a high frequency circuit, and a decoder circuit; a clock circuit; an operating member; and a controller for controlling timings of at least: an activation operation; an acquisition and tracking operation; and a time information acquisition operation, the controller being configured to: detect a reception instruction by a user; immediately start the activation operation when a delay time period from when the reception instruction is issued to an earliest time information receivable time point is longer than a first threshold value and shorter than a second threshold value; wait for arrival of an activation time point inversely calculated from the earliest time information receivable time point to start the activation operation when the delay time period is longer than the second threshold value; and wait for arrival of an activation time point inversely calculated from a next earliest time information receivable time point to start the activation operation when the delay time period is shorter than the first threshold value. | 05-21-2015 |
20150295700 | Time-Synchronizing a Group of Nodes - Systems and methods include receiving, values of one or more first external time variables from a first external node and values of one or more second external time variables from a second external node. The values of one or more local time variables of the local node are adjusted based at least upon the values of the one or more first external time variables and the values of the one or more second external time variables. | 10-15-2015 |
20150295703 | RF Carrier Synchronization and Phase Alignment Methods and Systems - A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase. | 10-15-2015 |
20150312020 | Apparatus for Synchronizing Clock Frequencies - An apparatus for synchronizing the clock frequencies of a first electronics unit arranged on the primary side, and a second electronics unit arranged on the secondary side. Associated with the first electronics unit is a clock signal producer, which produces a clock signal having a reference clock frequency, wherein a transmission unit is provided between the first electronics unit and the second electronics unit. A first control unit is provided, which operates the transmission unit with a clock frequency, which amounts to a fraction of the reference clock frequency of the first electronics unit, wherein a second control unit is provided, which couples the clock frequency out to the secondary side and, based on the out-coupled clock frequency, produces for the second electronics unit a clock frequency, which is synchronous with the reference clock frequency of the first electronics unit. | 10-29-2015 |
20150358119 | Method and device for reducing bit error rate in CDMA communication system - A method and a device for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system are described, wherein this method includes: a sample sequence I | 12-10-2015 |
20160056905 | Interface Device and Method for Exchanging User Data - An interface apparatus is provided for exchange of different time-critical user data between a host device and a divided medium, by way of a first interface and by way of a second interface, having a resource management device and a temporary memory device. The first interface works with a first clock pulse and the second interface works with a second clock pulse. The first interface and the second interface are connected with the temporary memory device. The resource management device is set up for controlling the exchange of the different time-critical user data between the first interface and the second interface, in such a manner that collisions of the different time-critical user data within the interface apparatus and/or on the divided medium are avoided, in order to allow deterministic behavior during exchange of the different time-critical user data. | 02-25-2016 |
20160080138 | METHOD AND APPARATUS FOR TIMING SYNCHRONIZATION IN A DISTRIBUTED TIMING SYSTEM - In one aspect of the teachings herein, a timing circuit detects the assertion of an incoming timing pulse signal at a timing resolution higher than that afforded by the sampling clock signal used to detect the assertion event. To do so, the timing circuit uses delay circuitry to obtain incrementally delayed versions of the incoming timing pulse signal or sampling clock signal. The delay increments are fractions of the sampling clock period and the timing circuit uses the delayed versions to determine a timing difference between actual assertion time of the incoming timing pulse signal and the sampling clock edge at which assertion of the incoming timing pulse signal is detected. In another aspect, a timing circuit uses similar delay techniques to control the timing of an outgoing timing pulse signal at a timing resolution higher than that afforded by the clock circuitry associated with generating the outgoing signal. | 03-17-2016 |
20160087785 | TIME SYNCHRONIZATION AND CONTROLLED ASYNCHRONIZATION OF REMOTE TRIGGER SIGNALS - A mechanism is disclosed for transmitting pulses onto respective cables so that the pulses arrive at the remote ends of the respective cables in synchronized (or controllably asynchronized) fashion. First, the round-trip time of flight of each cable is measured using speedy delivery pulses, i.e., pulses whose leading edges have exponential shape. Second, a calculation is performed to determine the input delay(s) between the pulses that would produce desired output delay(s). For example, it may be desirable that the pulses arrive at the respective remote ends at the same time, in which case the desired output delay(s) is (are) zero. Third, the same speedy delivery pulses are transmitted onto the respective cables so that the interpulse delay(s) conform to the computed input delay(s). Thus, the desired output delay(s) are achieved at the remote ends of the cables. | 03-24-2016 |
20160119112 | COMMUNICATION APPARATUS, TIME SYNCHRONIZATION SYSTEM, AND TIME SYNCHRONIZATION METHOD - A communication apparatus ( | 04-28-2016 |
20160119115 | METHOD FOR DETECTING IN A RECEIVER A TRANSMITTER LOCAL TIME - The method and apparatus for detecting in a receiver a transmitter local time, comprising determining a reference time for the transmitter local time; receiving from the transmitter a transmission time duration signal that elapsed on the transmitter since the reference time for the transmitter local time; and determining the transmitter local time based on the reference time for the transmitter local time and the received transmitter time duration. A time stamp signal based on the transmitter local time signal is generated at the receiver and is superimposed on the sensor data stream transmitted to the receiver. Consequently, the advantage is provided that a data stream can be transmitted without the incorporation of any time stamp. | 04-28-2016 |
20160142201 | SINGLE WIRE SYSTEM CLOCK SIGNAL GENERATION - This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal. | 05-19-2016 |
20160173266 | DESKEW FIFO BUFFER WITH SIMPLIFIED INITIALIZATION | 06-16-2016 |
20160182217 | COMMUNICATION DEVICE, PULSE SIGNAL DELAY ADJUSTMENT METHOD AND COMMUNICATION SYSTEM | 06-23-2016 |
20160380638 | CDR CONTROL CIRCUIT, CDR CIRCUIT, AND CDR CONTROL METHOD - A CDR control circuit detects a phase shift of input data that is taken in with a phase-adjusted clock, and generates phase control data that controls the phase of the clock based on the detected phase shift, the CDR control circuit includes a change detection circuit that detects an over-change in the phase shift; and a selection circuit that outputs the phase shift before the change, which is the phase shift before the time of detection of the over-change, as the phase shift for a predetermined period of time at the time of detection of the over-change, wherein during the predetermined period of time, the phase control data is generated based on the phase shift before change. | 12-29-2016 |
20170237548 | CIRCUIT ARRANGEMENT AND METHOD FOR CLOCK AND DATA RECOVERY | 08-17-2017 |