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Decision feedback equalizer

Subclass of:

375 - Pulse or digital communications

375229000 - EQUALIZERS

375230000 - Automatic

375232000 - Adaptive

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DocumentTitleDate
20130028311RECOVERABLE ETHERNET RECEIVER - The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.01-31-2013
20130028312JOINT DECISION FEEDBACK EQUALIZER AND TRELLIS DECODER - The present invention is directed to joint decision feedback equalizer (DFE) and Trellis decoder adaptable to an Ethernet transceiver. A Trellis coded modulation (TCM) decoder includes a one-dimensional branch metric unit (1D-BMU) configured to calculate 1D branch metrics; a four-dimensional branch metric unit (4D-BMU) configured to combine the 1D branch metrics to generate 4D branch metrics; an add-compare-select unit (ACSU) configured to perform add, compare and select (ACS) operations on the 4D branch metrics for each state to obtain path metrics; and a survivor memory unit (SMU) configured to store and keep track of symbols. A decision feedback unit (DFU) is coupled to receive the symbols from the SMU in order to estimate inter-symbol interference (ISI) quantity, which is then fed back to the 1D-BMU.01-31-2013
20130028313PARTIAL RESPONSE DECISION FEEDBACK EQUALIZER WITH DISTRIBUTED CONTROL - A multi-phase partial response equalizer is disclosed. The equalizer includes receiver circuitry to receive a data symbol over N bit intervals and to generate N sets of samples in response to N clock signals having different phases. A first storage stage is provided, including storage elements to store the sets of samples during a common clock interval. First and second selection circuits are respectively coupled to an input and an output of the first storage stage. An output storage stage is coupled to the second selection circuit to store an output sample. The first and second selection circuits, over multiple clock intervals, cooperatively select the output sample from one of the sets of samples based on a most recent previous output sample.01-31-2013
20080232454DECISION FEEDBACK EQUALIZATION WITH FRACTIONALLY-SPACED FEEDBACK DATA - A decision feedback equalizer (DFE) architecture uses feedback samples that are over-sampled with respect to the symbol rate. On-baud feedback samples are quantized with a slicer, while off-baud samples are linear, IIR samples. Both forward and feedback filters are fractionally-spaced, but adapted only at the baud instances.09-25-2008
20080260016Fully Adaptive Equalization for High Loss Communications Channels - An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a large number of communications channels.10-23-2008
20120183038TRANSMITTING CIRCUIT, RECEIVING CIRCUIT, AND COMMUNICATION SYSTEM EQUIPPED THEREWITH - In a related transmitting circuit employing electromagnetic induction that is used in a communication system, there is a problem in that, because only one inductor is used in the transmitting circuit, it is impossible to perform communication at a data rate higher than the self-resonant frequency of the inductor. A transmitting circuit according to an embodiment of the present invention is a transmitting circuit that drives an inductor to transmit data to a semiconductor chip insulated from a semiconductor chip on which the transmitting circuit is mounted, and includes a driving circuit that receives outgoing data transmitted at a data rate higher than the self-resonant frequency of the inductor and outputs an outgoing signal that drives the inductor at the data rate of the outgoing data.07-19-2012
20100080282RE-ADAPTION OF EQUALIZER PARAMETER TO CENTER A SAMPLE POINT IN A BAUD-RATE CLOCK AND DATA RECOVERY RECEIVER - An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.04-01-2010
20100080280DECISION FEEDBACK EQUALIZER WITH PARTIAL FEEDBACK EQUALIZER IN A VARIABLE SIDEBAND COMMUNICATIONS SYSTEM - In a receiver of a multi-leveled variable sideband communications system, a method is provided that comprises the steps of: dividing the receiver into a real portion and a complex portion; and providing a decision feedback equalizer (DFE) processing data substantially in the real portion.04-01-2010
20080285640RF Transmitter With Nonlinear Predistortion and Method Therefor - An RF transmitter (11-20-2008
20100074320APPARATUS FOR EQUALIZING DECISION FEEDBACK BASED ON CHANNEL PROPERTIES CHANGE AND METHOD THEREFOR - Provided is a decision feedback equalization apparatus including a channel estimation unit for estimating a channel on received signal based on the received signal and a training sequence; a channel matched filter for maximizing SNR from the channel estimated by the channel estimation unit to change channel characteristic of the received signal; a noncausal filter for approximating the channel changed by the channel matched filter from nonminimum phase channel to minimum phase channel; an equalizer input signal storage unit for storing received symbols passed through the channel matched filter and the noncausal filter; a channel equalization unit for performing a decision feedback equalization through filtering of a signal passed through the channel matched filter and the noncausal filter; a Trellis decoder for detecting symbol from a signal channel-equalized by the channel equalization unit; a mode selection unit for selecting a specific mode; an error signal calculator for comparing an output signal of the mode selected by the mode selection unit with an output signal of the channel equalization unit to calculate an error signal; and a tap coefficient updater for updating tap coefficients to the channel equalization unit by using the error signal from the error signal calculator, an output signal from the storage unit, and an output signal from the Trellis decoder.03-25-2010
20130077669Method of Compensating for Nonlinearity in a DFE-based Receiver - A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor α and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor α. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.03-28-2013
20130039407LOW-POWER DOWN-SAMPLED FLOATING TAP DECISION FEEDBACK EQUALIZATION - In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained IT resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with IT resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.02-14-2013
20090316770ADAPTIVE CONTROL OF A DECISION FEEDBACK EQUALIZER (DFE) - In one embodiment, a system includes one or more DFEs, each of which includes a feedback (FB) loop to compensate for distortion in an output signal that includes information recovered by a decision circuit from an input signal from a receiver. A first FB tap of a data DFE delays a first output signal of a first decision circuit by approximately 1.0 UIs and multiplies the 1.0-UI-delayed first output signal by a first data FB coefficient derived from a first boundary FB coefficient. A first FB tap of a boundary DFE delays the first output signal by approximately 1.5 UIs and multiplies the 1.5-UI-delayed first output signal by the first boundary FB coefficient, which corresponds to ISI at approximately 1.5 UIs of delay in the input signal.12-24-2009
20100046600Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.02-25-2010
20100046599APPARATUS AND METHOD FOR ACQUIRING INITIAL COEFFICIENT OF DECISION FEEDBACK EQUALIZER USING FAST FOURIER TRANSFORM - Provided is an apparatus and method for acquiring an initial coefficient of a DFE using an FFT. The apparatus includes a channel impulse response estimating unit for estimating a non-causal impulse response by delaying a received signal of a time domain and transforming it into frequency domain signals; a feedforward filter coefficient acquisition unit for extracting a predetermined number of signals from the non-causal channel impulse response signals estimated by the channel impulse response estimating unit, and transforming the same into frequency domain signals to acquire an initial coefficient of a feedforward filter; and a feedback filter coefficient acquisition unit for transforming the non-causal channel impulse response signals estimated by the channel impulse response estimating unit into frequency domain signals, multiplying the same by the initial coefficient of the feedforward filter, and transforming the results of multiplication into time domain signals to calculate an initial coefficient of a feedback filter.02-25-2010
20100046602System and Method For Deriving Symbol Timing - A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system is implemented by using a calculation that finds the timing phase error. The timing phase error is then averaged and controls a phase locked loop (PLL). This PLL in turn controls a voltage-controlled oscillator, which handles the modem receiver timing. A centroid calculation can be included to bias the voltage-controlled oscillator to push the equalizer coefficients back to the ideal position. The system can be implemented in either a point-to-point modem environment or a multi-point environment, for example, but not limited to, MVL or DMT. The voltage-controlled oscillator may also be implemented to control transmitter timing, so that the central office modem and the remote modem will operate more-or-less synchronously, reducing the need for large equalizer corrections at either end.02-25-2010
20100046601HIGH SPEED RECEIVE EQUALIZER ARCHITECTURE - Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.02-25-2010
20100046598Adaptation Of A Linear Equalizer Using A Virtual Decision Feedback Equalizer (VDFE) - A method and system of adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE) are disclosed. In one embodiment, a method of adjusting a setting of a linear equalizer includes determining a change to a decision feedback equalizer (DFE) tap weight value of a predefined metric according to a data signal and an error signal (e.g., the change may be generated according to an average of a specified plurality of data signals and the error signal); using the change in the DFE tap weight value to algorithmically generate a modification in a linear equalizer setting; and adjusting the linear equalizer setting. The linear equalizer is located in a feed-forward path and/or a feedback path of data transmission. The linear equalizer may be located in a transmitter and/or a receiver. The linear equalizer may be a continuous time linear equalizer and/or a Finite Impulse Response (FIR) linear equalizer.02-25-2010
20130034145EQUALIZATION DEVICE AND EQUALIZING METHOD THEREOF - An equalization device is arranged for equalizing a received signal, wherein the received signal may include a primary signal and at least one interference signal. The equalization device may include a transformation module, a serial-to-parallel converter, and an equalization module, wherein the transformation module may include a predictive decision feed-back equalizer, a first feed-back filter and an adder. The transformation module is arranged for generating a transformation signal according to the primary signal and the at least one interference signal of the received signal, wherein the transformation signal includes a transformed primary signal and at least one transformed interference signal. The serial-to-parallel converter is arranged for respectively converting the transformed primary signal and the transformed interference signal into a plurality of transformation signal sequences. The equalization module is arranged for respectively equalizing the plurality of transformation signal sequences so as to generate a plurality of equalized sequences.02-07-2013
20100135378Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing - A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.06-03-2010
20100111160 METHOD AND APPARATUS FOR MULTIPLE ANTENNA COMMUNICATIONS, COMPUTER PROGRAM PRODUCT THEREFOR - Embodiments of a method and an apparatus for detecting multiple complex-valued symbols belonging to discrete constellations. The method and apparatus is a detector that finds a closest vector, or a close approximation of it, to a received vector. The invention also gets (optimally, in case of two transmit sources) or closely approximates (for more than two transmit sources) the most likely sequences required for an optimal bit or symbol a-posteriori probability computation. Also part of the present invention is represented by Also embodiments of a method and an apparatus to determine a near-optimal ordering algorithms for the aforementioned purpose. The method and apparatus achieves optimal performance for two transmit antennas and achieves near-optimal performance for a higher number of antennas, with a lower complexity as compared to a maximum-likelihood detection method and apparatus. The method and apparatus are suitable for highly parallel hardware architectures.05-06-2010
20100103999PARTIAL RESPONSE DECISION-FEEDBACK EQUALIZATION WITH ADAPTATION BASED ON EDGE SAMPLES04-29-2010
20100104000ENHANCEMENT OF TRANSITION REGION EQUALIZATION IN A DECISION FEEDBACK EQUALIZER - A decision feedback equalizer includes an input path for receiving a bitstream with inter-symbol interference, and a feedback signal path is coupled to the input path for correcting a sampled value of an incoming bit of the bitstream based on inter-symbol interference of a preceding bit. The feedback signal path includes a controllable delay circuit for receiving the preceding bit. A feedback path controller is coupled to the controllable delay circuit to regulate a delay introduced to the preceding bit. The delay is a function of an accumulated value of data of early-late events of a sampling instant of the bitstream for different data pulse patterns.04-29-2010
20100103998DECISION FEEDBACK EQUALIZATION SCHEME WITH MINIMUM CORRECTION DELAY - A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.04-29-2010
20100142611DIGITAL COMMUNICATION SYSTEM AND METHOD - A digital communication system for transmitting and receiving video data signals and control data signals over a transmission line comprises an open-loop equalizer circuit and a control data extension circuit. The open-loop equalizer circuit is operable to receive video signals transmitted over the transmission line and output equalized video data signals. The control data extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the control data signal, and clamp the receive end of the transmission line during a negative transition of the control data signal.06-10-2010
20100329327EQUALIZER ADJUSTMENT METHOD AND ADAPTIVE EQUALIZER - An adaptive equalizer has an equalizer, a sampler, a code comparator, and an eye open/close determinator. The eye open/close determinator makes a determination as to whether a waveform of the input signal has an opening. The code comparator adjusts the equalizer characteristic, with reference to a sampling value by the sampler, and the determination as to whether the waveform has an opening.12-30-2010
20090316769DECISION FEEDBACK EQUALIZER (DFE) - In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.12-24-2009
20090041107Finite-length equalization over multi-input multi-output channels - A MIMO Decision Feedback Equalizer improves operation of a receiver by canceling the spatio-temporal interference effects caused by the MIMO channel memory with a set of FIR filters in both the feed-forward and the feedback MIMO filters. The coefficients of these FIR filters can be fashioned to provide a variety of controls by the designer.02-12-2009
20110058599GENERALIZED DECISION FEEDBACK EQUALIZER PRECODER WITH RECEIVER BEAMFORMING FOR MATRIX CALCULATIONS IN MULTI-USER MULTIPLE-INPUT MULTIPLE-OUTPUT WIRELESS TRANSMISSION SYSTEMS - To realize a GDFE precoder for multi-user MIMO systems, which significantly reduces the computational cost while resulting in no capacity loss, one method comprises obtaining an effective downlink (DL) channel matrix H for the DL channel after receiver processing at the user terminals; computing an uplink (UL) covariance matrix D by assuming there are as many user terminals as a number of rows in the effective DL channel matrix H; computing a filter matrix C based on the UL covariance matrix D; computing a feedforward filter matrix F based on the filter matrix C; computing an interference pre-cancellation matrix G, based on the feedforward filter matrix F and the filter matrix C, used in a transmitter at an interference pre-cancellation stage of the GDFE precoder; and processing user symbols by a decision feedback equalizing stage of the GDFE precoder to produce filtered vector symbols.03-10-2011
20110058598GENERALIZED DECISION FEEDBACK EQUALIZER PRECODER WITH INPUT COVARIANCE MATRIX CALCULATION FOR MULTI-USER MULTIPLE-INPUT MULTIPLE-OUTPUT WIRELESS TRANSMISSION SYSTEMS - To realize a GDFE precoder for multi-user MIMO systems, which significantly reduces the computational cost while resulting in no capacity loss, one method comprises computing an effective UL channel matrix H03-10-2011
20110013688APPARATUS AND METHOD FOR COMPENSATING FEEDBACK PATH DISTORTION - Provided are an apparatus and method for compensating a feedback path distortion in a digital broadcasting signal. The apparatus for improving a performance of a pre-equalizer in a transmitter of a digital broadcasting system having a feedback path for adaptively generating a filter coefficient of the pre-equalizer, includes a reference signal generator for generating a reference radio frequency (RF) signal, a feedback path estimator for estimating transmission band characteristic information for the feedback path based on the reference RF signal generated from the reference signal generator, and a feedback path compensator for compensating a demodulated signal transferred through the feedback path based on the estimated transmission band characteristic information from the feedback path estimator and generating a filter coefficient of the pre-equalizer.01-20-2011
20090296803BLOCK-BASED EQUALIZER AND METHOD THEREOF - A block-based equalizer used in a receiver, comprising a feed forward filter, a feed backward filter and a combiner. The feed forward filter generates one first data block for each round and each first data block has multiple first sub-blocks. The feed backward filter generates one second data block. Certain input symbols of the feed backward filter are suppressed during filtering. The combiner combines one second data block and one first sub-block.12-03-2009
20090268804Delayed decision feedback sequence estimator - Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.10-29-2009
20090268803Channel Estimation for High Doppler Mobile Environments - An apparatus and method of applying a fast algorithm to a pilot-based channel estimation process includes receiving, in a receiver, a signal comprising information bits transmitted in a wireless channel, executing a pilot-based channel estimation process running on a decision-directed turbo estimation procedure having a p structure for a vector of pilots and an upper bound N for a channel spread based on a feedback of detected information bits via OFDM, encoding the detected information bits, re-encoding the detected information bits at a decoder output, re-constructing and subtracting an ICI term from the received signal, modulating the detected information bits, estimating channel symbols in a per-carrier basis based on a diagonal matrix of a full matrix involved in the pilot-based channel estimation, and performing training of the wireless channel based on an entire vector of the channel symbols.10-29-2009
20090268802DECISION FEEDBACK EQUALIZER HAVING ADJUSTING DEVICE AND METHOD THEREOF - A decision feedback equalizer having a adjusting device and method thereof are described. The decision feedback equalizer having an adjusting device includes a feed-forward filter, a decision device, a feedback filter, the adjusting device, and a summation device. The feed-forward filter generates a forwarding signal (S10-29-2009
20120224621EQUALIZING RECEIVER - A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.09-06-2012
20130064281TECHNIQUES FOR SETTING FEEDBACK COEFFICIENTS OF A PAM-N DECISION FEEDBACK EQUALIZER - A decision feedback equalizer (DFE) for equalizing PAM-N signals comprises a coefficient setting unit for setting a first group of most significant feedback coefficients of the DFE to a predefined value selected from a group of predefined values; a coefficients computation unit coupled to the coefficient setting unit for computing values of feedback coefficients of a second group of feedback coefficients other than the first group of most significant feedback coefficients; a feedback (FB) unit for mitigating, using a complete group of feedback coefficients, effects of interference from data symbols that are adjacent in time to an input data symbol, wherein most significant feedback coefficients of the first group are set to an optimal value computed during an initialization of the DFE and feedback coefficients of the second group are computed by the coefficients computation unit.03-14-2013
20090232196APPARATUS AND METHOD FOR DECISION FEEDBACK EQUALIZATION - Disclosed is an apparatus including an odd data receiving unit that receives an input signal, an even data receiving unit that also receives the input signal, and a pattern filter. The odd data receiving unit samples a half-rate DFE equalized signal with an odd data timing clock to output data decision data. The odd data receiving unit also samples both the half-rate DFE equalized signal and a non-half-rate DFE equalized signal with an odd edge timing clock having the phase shifted by 90 degrees from the odd data timing clock to output resulting edge decision data. The even data receiving unit samples the half-rate DFE equalized signal with an even data timing clock having the phase shifted by 180 degrees from the odd data timing clock to output data decision data. The even data receiving unit also samples both the half-rate DFE equalized signal and the non-half-rate DFE equalized signal with an even edge timing clock having the phase shifted by 90 degrees from the even data timing clock to output resulting edge decision data. The pattern filter selects one of the edge decision data sampled at the odd edge timing and at the even edge timing in response to the value of a data pattern of three consecutive bits (110 or 001) obtained from the data decision data sampled at the odd and even data timings (FIG. 09-17-2009
20120236926FREQUENCY-DOMAIN ADAPTIVE FEEDBACK EQUALIZER - A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols.09-20-2012
20120269255Parallel Closed-Loop DFE Filter Architecture - A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.10-25-2012
20100238993AN INTEGRATED EQUALIZATION AND CDR ADAPTATION ENGINE WITH SINGLE ERROR MONITOR CIRCUIT - A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.09-23-2010
20120207204Clock Recovery Circuit for Receiver Using Decision Feedback Equalizer - In particular embodiments, a method includes receiving by a decision feedback equalizer (DFE) a first signal comprising transmitted data; adjusting by the DFE the first signal to an equalized signal comprising the transmitted data; detecting by a phase-error detector phase errors at a data rate of no more than one fourth of a data rate for the transmitted data; generating by the phase-error detector a phase-error level based on the detected phase errors; and recovering, by a clock-recovery circuit for the DFE and the phase-error detector, a clock signal associated with the transmitted data based on the phase error level.08-16-2012
20120099638Soft Cancellation Of Inter-Layer Interference Within A MIMO Codeword - A receiver for processing a received signal encoded with a codeword and mapped to two layers includes a plurality of equalizers for equalizing the received signal, a plurality of demodulators for demodulating a respective equalized signal, a decoder for decoding the demodulated signal by extracting soft bits from the demodulated signal, a modulator for modulating the decoded signal by generating soft symbols based on the extracted soft bits, a demapper for demapping the modulated signal to soft symbols corresponding to each of the two layers and a plurality of inter-layer interference cancellers for cancelling interference utilizing the demapped soft symbols wherein the demapped soft symbols are utilized also by the equalizers to reduce inter-symbol interference.04-26-2012
20100027611Adaptive equalization employing pattern recognition - In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fibre Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern.02-04-2010
20100020862INPUT CONTROL CIRCUIT FOR THE SUMMER OF A DECISION FEEDBACK EQUALIZER - This invention discloses a tap circuit in a summer of a decision feedback equalizer (DFE), the tap circuit comprises a differential pair of received signal lines, a current source having a magnitude being substantially proportional to a tap weight coupled between a first node and a ground, a plurality of NMOS transistors controllably coupled the current source to either one of the received signal lines, and DFE data signals and DEF logic sign signals being coupled only to the gates of the plurality of NMOS transistors, wherein tap circuit can operate at low supply voltage without losing speed.01-28-2010
20110286511DATA LATCH CIRCUIT AND METHOD OF A LOW POWER DECISION FEEDBACK EQUALIZATION (DFE) SYSTEM - Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.11-24-2011
20090168865LOWER PROCESSING RATE DECISION FEEDBACK EQUALIZER FOR HIGHER RATE CARRIER SIGNAL - Briefly, in accordance with one or more embodiments, parallel DFE processing may be utilized for single carrier systems that employ cyclic prefixes. The achieved parallelism allows working at contemporary clock rates that are significantly lower than the required sampling rate at high bandwidth systems such as 60 GHz transmissions.07-02-2009
20100091832PIPELINED DECISION-FEEDBACK UNIT IN A REDUCED-STATE VITERBI DETECTOR WITH LOCAL FEEDBACK - A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interfence-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.04-15-2010
20090154542High-speed serial data signal receiver circuitry - Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.06-18-2009
20100309970DVB-S2 DEMODULATOR - A method for demodulating a modulated signal, by: receiving a signal modulated in n-PSK or n-APSK comprising a succession of symbols organized in frames, each frame comprising a header followed by blocks of data symbols separated by blocks of pilot symbols, determining the phase of the headers and pilot blocks to predict the evolution of the signal phase, correcting the phase of the data symbols according to the evolution of the signal phase, and equalizing the data symbols corrected in phase using equalization coefficients evaluated thanks to estimated or known symbols of the signal, and pre-equalizing the header, pilot and data symbols, which is performed before determining the phase of the headers and pilot blocks, and using the estimated equalization coefficients to equalize the data symbols.12-09-2010
20100118931DECISION FEEDBACK EQUALIZER FOR PORTABLE ENVIRONMENTS - A method is provided. The method includes receiving a carrier signal and analyzing the received carrier signal to identify at least one of a static multipath delay and a dynamic multipath delay in the signal. The method also includes configuring an equalizer based upon the at least one of the static and dynamic multipath delays.05-13-2010
20100086019High-Speed Decoder for a Multi-Pair Gigabit Transceiver - A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder. This operation of storing the tentative samples in the registers before providing the tentative samples to the multiplexer facilitates high-speed operation by breaking up a critical path of computations into substantially balanced first and second portions, the first portion including computations in the decision-feedback equalizer and the multiple decision feedback equalizer, the second portion including computations in the decoder.04-08-2010
20090086808Equalization And Decision-Directed Loops With Trellis Demodulation In High Definition TV - Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.04-02-2009
20130077670IMPAIRMENT COVARIANCE AND COMBINING WEIGHT UPDATES DURING ITERATIVE TURBO INTERFERENCE CANCELLATION RECEPTION - In a receive node of a wireless network, an iterative multi-user multi-stage interference cancellation receiver is used. After each stage of interference cancellation, interference characteristics change. An adaptive strategy is used in which after each stage of interference cancellation, impairment covariance is parametrically updated and combining weights of the receiver are adapted to reflect the updated impairment covariance.03-28-2013
20100080281METHOD TO CALCULATE THE REAL DECISION FEEDBACK EQUALIZER COEFFICIENTS - A method used in a time domain equalizer is provided. The method comprising the steps of: providing a time domain equalizer comprising; and extracting a real part of an input or a derivative of the input to the time domain equalizer and using the only real part of the input in the time domain equalizer to derive an output of the time domain equalizer.04-01-2010
20090161749METHOD AND APPARATUS FOR IFDMA RECEIVER ARCHITECTURE - A method and receiver for processing a composite signal (06-25-2009
20090296804Method and System for Near Optimal Iterative Detection of the 2-Dimensional ISI Channel - A method and system for decoding data received from a channel experiencing two-dimensional inter-symbol interference, as well as systems implementing such a decoding method and system, are disclosed. The method includes an iterative multi-strip equalization method that receives a plurality of channel values associated with a plurality of locations in a plurality of rows of a matrix, computes initial probability values based upon those channel values, applies a BCJR algorithm to symbol probability values based upon bands of rows of the initial probability values, and resolves the results of applying the BCJR algorithm to arrive at a plurality of bands of rows of revised probability values, which are subsequently combined/substituted with one another. The process iteratively repeats until the revised probability values attain a sufficient degree of convergence. By utilizing data from overlapping bands to perform the BCJR algorithm, ISI in both dimensions is addressed.12-03-2009
20090296802METHOD AND APPARATUS TO PERFORM EQUALIZATION AND DECODING FOR A COMMUNICATION SYSTEM - A method and apparatus to perform equalization and decoding for a communication system are described12-03-2009
20090285277DECISION FEEDBACK EQUALIZING METHOD AND EQUALIZER - A decision feedback equalizer is provided for correcting ISI on a first postcursor without using received decision data of a preceding bit. The decision feedback equalizer includes an amplifying circuit that is to be supplied with received data, a duobinary signal decision device for determining an output signal from the amplifying circuit, the duobinary signal decision device including a flip-flop, a shift register for successively shifting a decision result held by the flip-flop, and a plurality of current control blocks that are to be supplied with respective output signals from the shift register, and feeding back output signals to an output terminal of the amplifier to control the potential thereof.11-19-2009
20090086807METHODS AND APPARATUS FOR DETERMINING THRESHOLD OF ONE OR MORE DFE TRANSITION LATCHES BASED ON INCOMING DATA EYE - Methods and apparatus are provided for determining the threshold position of one or mote DFE latches using an evaluation of the incoming data eye. A threshold position is determined for one or more transition latches employed by a decision-feedback equalizer by obtaining a plurality of samples of a data eye using a data eye monitor; obtaining a vertical eye opening metric from the data eye monitor; and determining the threshold position for the one or more transition latches based on the vertical eye opening metric. A decision-feedback equalizer is also disclosed that comprises at least one data latch having a data threshold; and at least one transition latching having a transition threshold, wherein the transition threshold and the data threshold ate unequal04-02-2009
20110200091Asymmetric Multi-Channel Adaptive Equalizer - An apparatus is disclosed to compensate for non-linear effects resulting from the transmitter, the receiver, and/or the communication channel in a communication system. A receiver of the communication system contains an image cancellation module that compensates for images generated during the modulation and/or demodulation process. The image cancellation module includes a fine carrier correction loop to correct for frequency offsets between the transmitter and receiver. The image cancellation module includes a coarse acquisition mode and a decision directed mode. The decision directed mode allows for a larger signal-to-noise ratio for the receiver when compared against the coarse acquisition mode.08-18-2011
20090103600 MOBILE RECEIVER EQUALIZER STRUCTURE FOR USE IN THE ATSC STANDARD - A receiving device is provided that comprises: a channel estimator adapted to receive an input; and an equalizer adapted to receive the input and generate an equalized output, wherein the equalized output is used by the channel estimator for at least one subsequent channel estimation.04-23-2009
20100061440DECISION FEEDBACK EQUALIZER HAVING CLOCK RECOVERY CIRCUIT AND METHOD FOR RECOVERING CLOCK - A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.03-11-2010
20080232455Maximum likelihood decoder for pulse and amplitude position modulation multi-source system - The present invention concerns a sphere decoder for maximum likelihood receiver intended to receive M-PPM-M′-PAM symbols at M modulation positions and at M′ amplitude levels from a plurality P of sources. The sphere decoder uses a Schnorr-Euchner type enumeration adapted to classify the points of a multidimensional PPM-PAM modulation.09-25-2008
20080304558HYBRID TIME-FREQUENCY DOMAIN EQUALIZATION OVER BROADBAND MULTI-INPUT MULTI-OUTPUT CHANNELS - A system and methodology for channel equalization are provided. According to one aspect, a receiver structure for a MIMO system is provided that employs frequency domain equalization (FDE) with noise prediction (FDE-NP). The FDE-NP structure may include a feedforward linear frequency domain equalizer and a group of time domain noise predictors (NPs), which may operate by predicting a distortion corresponding to a given linearly equalized data stream based on previous distortions of all linearly equalized data streams. According to another aspect, a receiver structure for a MIMO system is provided that employs FDE-NP with successive interference cancellation (FDE-NP-SIC), which can extend the functionality of FDE-NP by ordering all linearly equalized data streams according to their minimum mean square errors (MMSEs) and detecting those streams which have a low MMSE first, thereby allowing current decisions of lower-indexed streams to be considered along with previous decisions for all data streams for noise prediction. According to a third aspect, a method for analyzing the performance of a MIMO system with equalization is provided. Pursuant to the method, a general expression of MMSE may first be derived. The MMSE expression may then be related to an error bound by applying the modified Chernoff bounding methodology in a general MIMO system. The parameters in the result may then be varied for applicability to single-input single-output (SISO), multiple-input single-output (MISO), and single-input multiple-output (SIMO) systems with receiver equalization technology.12-11-2008
20080304559SYSTEM FOR AUTOMATIC BANDWIDTH CONTROL OF EQUALIZER ADAPTATION LOOPS - A method to reduce peak power consumption during adaptation for an IC with multiple serial link transceivers including the steps of (A) inactivating equalizer adaptation loops until a triggering event occurs, (B) when the triggering event occurs, determining whether the triggering event is a minor change or a major change, (C) when the triggering event is a minor change, spreading out activation of adaptation loops in time, and (D) when the triggering event is a major change, simultaneously activating all adaptation loops.12-11-2008
20130215955APPARATUS AND METHOD FOR DETECTING COMMUNICATIONS FROM MULTIPLE SOURCES - A method, apparatus, and computer program for detecting sequences of digitally modulated symbols transmitted by multiple sources are provided. A real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources is determined. The real-domain representation is processed to obtain a triangular matrix. In addition, at least one of the following is performed: (i) hard decision detection of a transmitted sequence and demapping of corresponding bits based on a reduced complexity search of a number of transmit sequences, and (ii) generation of bit soft-output values based on the reduced complexity search of the number of transmit sequences. The reduced complexity search is based on the triangular matrix.08-22-2013
20080240223Receiver-Based Adaptive Equalizer with Pre-Cursor Compensation - An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a wide range of communications channels. Interoperability and Bit Error Rate performance are optimized through compensation of pre-cursor inter-symbol interference, which is performed adaptively in the receiver as opposed to the transmitter.10-02-2008
20090304066Systems and Methods for Speculative Signal Equalization - Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.12-10-2009
20090129459DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.05-21-2009
20090252215SAMPLED CURRENT-INTEGRATING DECISION FEEDBACK EQUALIZER AND METHOD - A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.10-08-2009
20080240224STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.10-02-2008
20090097541Methods And Apparatus For Determining Receiver Filter Coefficients For A Plurality Of Phases - Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.04-16-2009
20110142120FLOATING-TAP DECISION FEEDBACK EQUALIZER FOR COMMUNICATION CHANNELS WITH SEVERE REFLECTION - An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.06-16-2011
20130121396DECISION FEEDBACK EQUALIZER HAVING PROGRAMMABLE TAPS - A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.05-16-2013
20080260017SELECTIVE SLICING EQUALIZER - An equalizer. The equalizer, either operated in a blind mode or a decision directed mode, comprises a feed-forward filter, a feedback filter, a decision device, a control circuit, and a multiplexer. The feed-forward filter receives an input signal. The feedback filter filters an equalized signal. The combiner combines the feed-forward filtered signal and the feedback filtered signal. The decision device maps the combined signal to one symbol of a symbol set. The control circuit receives the combined output and generates a slice control signal. The multiplexer selects the combined signal or the mapped signal as the equalized according to the slice control signal when operated in the blind mode.10-23-2008
20090252216MULTIDIMENSIONAL DECISION-DIRECTED TRAINED ADAPTIVE EQUALIZATION - An embodiment of the invention is a technique to equalize received samples. An equalizer to equalize a multidimensional signal transmitted over a communication channel and having a dimensionality of four or higher. The equalizer is adaptively decision directed trained.10-08-2009
20080285641 SLICER INPUT AND FEEDBACK FILTER CONTENTS FOR BLOCK CODED DIGITAL COMMUNICATIONS - Improved decision directed adaptation and decision feedback equalizers are provided in a block coded digital communication system. The performance of a receiver is significantly improved by allowing the decision feedback equalizer to perform time-tracking and residual frequency offset compensation during the data portion of a frame. This is accomplished by capitalizing on the inherent correlation among the chips of a code word in a block coded digital communication system to identify certain instances where more reliable symbol estimates can be derived from a sliced chip without introduction the delay inherent in decoding. As the more reliable symbol estimates are fed back into the chip slicer, the total efficiency of the decision feedback equalizer is improved and the more reliable symbol estimates can be used to replace older content in the feedback filter to further improve the accuracy of the modified slicer input and further decrease the effects of error propagation by the decision feedback equalizer.11-20-2008
20100158096EQUALIZATION APPARATUS AND METHOD OF COMPENSATING DISTORTED SIGNAL AND DATA RECEIVING APPARATUS - Provided are an equalization apparatus and method of compensating a distorted received signal. The equalization apparatus includes: a filter unit removing inter-symbol interference (ISI) from a multi-channel signal that is received; and a zero-offset controller identifying a zero offset of the multi-channel signal and determining operating coefficients of the filter unit by reflecting the identified zero offset. A response filter, which reduces loss and noise, can be used, and the structure of the response filter can be simplified. In addition, channel characteristics are estimated in real time at an initial stage of data transmission and reception. Thus, an equalizer optimized for channel interference characteristics can be provided.06-24-2010
20090316772Multidimensional Asymmetric Bang-Bang Control - In one embodiment, a system includes one or more digital feedback equalizers (DFEs) that include one or more residual intersymbol interference (ISI) detectors, one or more column balancers, and one or more weight selectors. The residual ISI detectors produce a first output signal indicating whether the residual ISI of a received input signal has a positive sign or a negative sign. The column balancers select one of the first output signals to produce a second output signal. The weight selectors access one of the weight values. The weight value corresponds to the column balancer, the residual ISI detector that, and the sign of the residual ISI, and has a magnitude that is substantially independent of the sign of the residual ISI. The weight selectors produce a third output signal based on the weight value and the sign of the residual ISI.12-24-2009
20090316771Sign-Based General Zero-Forcing Adaptive Equalizer Control - In one embodiment, a system includes one or more digital feedback equalizers (DFEs) that include one or more residual intersymbol interference (ISI) detectors, one or more column balancers, and one or more weight selectors. The residual ISI detectors produce a first output signal indicating whether the residual ISI of a received input signal has a positive sign or a negative sign. The column balancers select one of the first output signals to produce a second output signal. The weight selectors access one of the weight values. The weight value corresponds to the column balancer that produced the second output signal and the residual ISI detector that produced the first output signal, and has a magnitude that is substantially independent of the sign of the residual ISI. The weight selectors produce a third output signal based on the weight value and the sign of the residual ISI.12-24-2009
20100150221Continuous Time - Decision Feedback Equalizer - An apparatus comprises a summer suitable for subtracting a jfiltered feedback signal from an input; a symbol decision device suitable for receiving an output from the summer; a feedback filter suitable for filtering an output from the symbol decision device and for sending the filtered feedback signal to the summer, the feedback filter comprising an adjustable swing amplifier and an adjustable pole filter; and an adaptation algorithm suitable for simultaneously adapting both a pole setting and a swing setting based upon a least mean squared error criteria. The summer, the symbol decision device, and the feedback filter form a feedback circuit utilized to reconstruct an electrical signal distorted during transmission. 06-17-2010
20090161748MMSE-DFE EQUALIZATION WITH ANTENNA DIVERSITY FOR MOBILE DTV - A decision feedback equalizer has a feedback filter and K feed forward filter branches. Each of the K feed forward filter branches receives an input signal from a corresponding one of a plurality of channels associated with a corresponding one of a plurality of antennas, where K>1. Each of the K feed forward filter branches provides an output. An instantaneous SNR level Y06-25-2009
20100183065ITERATIVE DETECTION AND DECODING IN MULTIPLE ANTENNA COMMUNICATION SYSTEMS - One or more embodiments to iteratively detect and decode data transmitted in a wireless communication system, featuring a MIMO detector and a soft input soft-output error-correction-code decoder. More specifically, a method suitable for iterative detection and decoding schemes is proposed, which is able to output near optimal bit soft information processing efficiently given input bit soft information. First, a transmitting source is selected as a reference layer, wherein the associated symbol represents a reference transmit symbol. Subsequently, a set of candidate values are identified for the reference transmit symbol. For each candidate value a candidate transmit sequence is estimated through a novel spatial decision feedback equalization process based on both Euclidean distance metrics and the a-priori soft information provided by the SISO ECC decoder. The novel DFE technique uses a novel bit metric. Techniques are provided to identify a reduced size transmit symbol candidate set and generate from it near-optimal LLRs, also processing input a-priori LLRs in an iterative fashion.07-22-2010
20100177817SEGMENTED EQUALIZER - In one embodiment of the present invention, a segmented equalizer includes a plurality of feedforward equalizer segments, each feedforward equalizer segment responsive to delayed samples of an input signal {v07-15-2010
20130215954ANALOG SIGNAL CURRENT INTEGRATORS WITH TUNABLE PEAKING FUNCTION - Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.08-22-2013
20110058600MULTIPLE TUNER ATSC TERRESTRIAL DTV RECEIVER FOR INDOOR AND MOBILE USERS - A device is provided. the device comprises a maximum ratio combining (FD-MRC-DFE), a first device down stream to the FD-MRC-DFE; and a second device upstream to the maximum ratio combining (FD-MRC-DFE) having a second point directly connected to a first point within the first device. The method for producing the device is also provided.03-10-2011
20100208788SYSTEM AND METHOD FOR HIGH-SPEED DECODING AND ISI COMPENSATION IN A MULTI-PAIR TRANSCEIVER SYSTEM - A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.08-19-2010
20120140812Receiver Circuit Architectures - Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.06-07-2012
20100266007DUAL PDFE SYSTEM WITH FORWARD-BACKWARD VITERBI - The present invention provides a novel technique for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Methods and systems are described that can improve the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization (“pDFE”) architectures are described. Systems are described that include one or more enhanced Viterbi decoders together with novel methods of symbol correction to obtain better system performance. Systems and methods are described that utilize dual pDFEs and can use a blending algorithm to reduce errors in symbol decoding. Dual pDFEs are described that include forward and backward Viterbi decoders wherein the backward Viterbi decoded may operate on time reversed data blocks and with some degree of latency. Forward and backward Viterbi decoders can generate different decoded symbols from the same equalized data. A blending algorithm is described for weighting results based on reliability of the respective decoded symbols. A forward-backward blender can additionally increase performance of the second pDFE by blending long delayed trellis symbols from the first Viterbi decoder with symbols output by the second Viterbi decoder.10-21-2010
20120033726DECISION FEEDBACK EQUALIZER, RECEIVING CIRCUIT, AND DECISION FEEDBACK EQUALIZATION PROCESSING METHOD - A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.02-09-2012
20090323797Finite-Length Equalization Over Multi-Input Multi-Output Channels - A MIMO Decision Feedback Equalizer improves operation of a receiver by canceling the spatio-temporal interference effects caused by the MIMO channel memory with a set of FIR filters in both the feed-forward and the feedback MIMO filters. The coefficients of these FIR filters can be fashioned to provide a variety of controls by the designer.12-31-2009
20090110049Radio Receiver in a Wireless Communications System - Techniques are described for optimizing processing facilities of a receiver in a wireless communication environment, taking into consideration processing performance set against the computing resources and/or power consumption required to obtain the processing performance. An embodiment of a radio receiver is described that includes a channel equalization means arranged to receive digital samples of an incoming signal and to generate an equalized output, said channel equalization means including means for processing said digital samples in accordance with an equalizer algorithm utilizing a set of equalizer parameters. The receiver can include means for estimating at least one parameter of a channel over which the signal has been received, and means for selecting at least one of said equalizer parameters based on at least one of said estimated channel parameters. Related methods, algorithms, and computer program products are also described.04-30-2009
20100303144ARCHITECTURE FOR VERY HIGH-SPEED DECISION FEEDBACK SEQUENCE ESTIMATION - A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.12-02-2010
20090067486Method and apparatus for joint decoding and equalization - The present invention is related to joint trellis decoding and equalization using a decision feedback equalizer.03-12-2009
20090028234TAP INITIALIZATION OF EQUALIZER BASED ON ESTIMATED CHANNEL IMPULSE RESPONSE - A method of initializing tap coefficients of an equalizer may include estimating impulse response coefficients of a channel through which a received signal traveled based on a known portion of the received signal. The method may also include loading the impulse response coefficients into a channel filter and generating a reference signal. The reference signal may be passed through the channel filter to build a training signal. Tap coefficients of the equalizer may be adjusted based on the training signal from the channel filter and on a delayed version of the reference signal.01-29-2009
20100226424TAP/GROUP-REVIVABLE DECISION FEEDBACK EQUALIZING METHOD AND EQUALIZER USING THE SAME - A tap/group-revivable decision feedback equalizing method and equalizer using the same is disclosed. The equalizer includes a feed-forward filter and a feedback filter each with a plurality of taps divided in groups. The tap/group-revivable decision equalizing method includes training all the taps to generate their tap coefficients, and selecting all the taps of any of the groups with a tap coefficient greater than a predetermined value and selecting a number of taps of any of the groups without a tap coefficient greater than the predetermined value, but with a neighboring group with a tap coefficient greater than the predetermined value are selected, and having the selected taps utilized for equalization.09-09-2010
20100054324SYSTEM AND METHOD FOR LATENCY REDUCTION IN SPECULATIVE DECISION FEEDBACK EQUALIZERS - A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.03-04-2010
20110150071ADAPTIVE PADE FILTER AND TRANSCEIVER - According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.06-23-2011
20110103459SYSTEM AND METHOD FOR UN-INTERRUPTED OPERATION OF COMMUNICATIONS DURING INTERFERENCE - Methods and systems to substantially eliminate effects of EMI burst noise in an Ethernet system are provided herein. The method includes the step of computing and storing filter coefficients configured to adapt to a range of EMI frequencies. The method further comprises the step of receiving a signal and detecting EMI and frequency of the EMI in the received signal. The method further comprises selecting filter coefficients corresponding to the determined frequency of the detected EMI and adjusting a frequency response of one or more filters using the selected filter coefficients so as to substantially eliminate effects of the EMI in the received signal. The method further includes the step of sending filter coefficients to a link partner corresponding to the frequency of the detected EMI.05-05-2011
20090213923Method and apparatus for channel detection - The invention proposes a method for joint detection and channel decoding of binary data employing a trellis-based detector where the trellis describes RLL encoding, NRZI preceding, the influence of the channel, and PR equalization. In order to improve performance for the case of exchanging soft information with an outer soft-in soft-out channel decoder or ECC decoder under the presence of correlated noise, the trellis is extended to also comprise and model a Noise Prediction.08-27-2009
20090213922Method and Apparatus for Efficient Multi-Symbol Detection - Where two or more multi-valued digital data symbols are modulated so that they overlap after passing through a channel, forming a combined signal, a receiver receives the combined signal and forms detection statistics to attempt to recover the symbols. Where forming detection statistics does not completely separate the symbols, each statistic comprises a different mix of the symbols. A receiver determines the symbols which, when mixed in the same way, reproduce or explain the statistics most closely. For example, the receiver hypothesizes all but one of the symbols and subtracts the effect of the hypothesized symbols from the mixed statistics. The remainders are combined and quantized to the nearest value of the remaining symbol. For each hypothesis, the remaining symbol is determined. A metric is then computed for each symbol hypothesis including the so-determined remaining symbol, and the symbol set producing the best metric is chosen as the decoded symbols.08-27-2009
20110080939BASELINE WANDER COMPENSATION FOR PERPENDICULAR RECORDING - A tail estimate signal which includes noise associated with baseline wander is generated. The tail estimate signal is generated by processing an input signal using a detector to obtain one or more decisions. Using the one or more decisions, the tail estimate signal is generated. The tail estimate signal is removed from the input signal.04-07-2011
20120201289DECISION FEEDBACK EQUALIZER AND TRANSCEIVER - A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.08-09-2012
20110044384DECISION FEEDBACK EQUALIZER CIRCUIT - An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.02-24-2011
20100260253METHOD AND APPARATUS FOR IMPROVING COMMUNICATION SYSTEM PERFORMANCE IN TOMLINSON HARASHIMA PRECODING (THP) MODE WITH A ZERO EDGE FILTER - The invention relates to a method and apparatus of an improved Tomlinson Harashima Precoding (THP) communication system through special configuration of its feedback coefficients. Improvement, in terms of THP system robustness against analog-to-digital (ADC) sampling phase variation, is achieved either by deriving feedback coefficients of the Decision Feedback Equalizer at worst ADC sampling phase or by inserting a Zero Edge Filter (ZEF) at the receiver. The ZEF modifies the communication system such that the feedback filter coefficients derived in the Decision Feedback Equalizer (DFE) mode and later used in the THP mode is capable to compensate the zero at Nyquist Frequency due to a non-optimum sampling phase of the ADC. The THP communication system, modified and improved with the insertion of ZEF, is operable to switch from an adaptive Decision Feedback Equalizer (DFE) mode to a THP mode having an adaptive Linear Equalizer (LE) at the receiver. The modified THP communication system offers better performance in terms of signal-to-noise ratio (SNR) at the output of the receiver than traditional THP based communication systems when ADC sampling phase changes.10-14-2010
20100098149SYSTEMS AND METHODS FOR MULTICARRIER MODULATION USING MULTI-TAP FREQUENCY-DOMAIN EQUALIZER AND DECISION FEEDBACK - Through the use of feedback in determining frequency domain equalization, interference can be reduced. Specifically, the determined constellation point closest to the determined received point can be fed back to aid in determining one or more other closest constellation points.04-22-2010
20080298453NONLINEAR ADAPTIVE PHASE DOMAIN EQUALIZATION FOR MULTILEVEL PHASE CODED DEMODULATORS - A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter or receiver impairments, frequency selective channel response filtering, timing offset or carrier frequency offset. The invention uses phase domain signals (r, □ rather than the classical Cartesian quadrature components (I, Q) and employs a nonlinear adaptive equalizer on the phase domain signal. This results in significantly improved ISI performance which simplifies the design of a digital receiver.12-04-2008
20080205504DECISION FEEDBACK EQUALIZERS AND EQUALIZING METHODS THEREOF - Decision feedback equalizers and related equalizing method are provided. One proposed decision feedback equalizer includes: a feed-forward filter for filtering an incoming signal to generate a filtered signal; a feedback filter for generating a feedback signal according to a decision signal; an operating device, coupled to the feed-forward filter and the feedback filter, for generating an output signal according to the filtered signal and the feedback signal; a decision device, coupled to the operating device and the feedback filter, for generating the decision signal according to the output signal; and an updating device coupled to the feedback filter for constraining coefficients of predetermined taps of the feedback filter while updating the tap coefficients of the feedback filter; wherein each predetermined tap of the feedback filter corresponds to a tap of the feed-forward filter.08-28-2008
20100329326METHODS AND APPARATUS FOR DECISION-FEEDBACK EQUALIZATION WITH OVERSAMPLED PHASE DETECTOR - Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.12-30-2010
20120147945MIMO SIGNAL DETECTOR, A METHOD OF DETECTING MIMO SIGNALS AND A MIMO RECEIVER - A signal decoder, a method of detecting an RF signal at a MIMO receiver and a MIMO receiver are disclosed herein. In on embodiment, the signal decoder includes: (1) a tree pruner configured to reduce a number of nodes of an MLD tree to expand based on modulation properties of the transmitted radio signals and SE enumeration of at least a portion of the MLD tree and (2) a vector sorter configured to sort multiple rows of child nodes of the MLD tree in parallel.06-14-2012
20110026579 NOVEL EQUALIZER FOR SINGLE CARRIER TERRESTRIAL DTV RECEIVER - An equalizer is provided. The equalizer comprises a frequency domain a minimum-mean square-error (MMSE) decision feedback equalization (DFE) block having a backward filter co-efficient (BFC) feature adapted to operate in a single carrier environment.02-03-2011
20110096824MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING A SINGLE-STATE DECISION FEEDBACK EQUALIZER - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.04-28-2011
20110096825Fractional-Rate Decision Feedback Equalization Useful in a Data Transmission System - Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously-detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly.04-28-2011
20100195711Hybrid receiver with algorithmic combining and method - A hybrid receiver apparatus, a method, and a computer readable storage media encoded with a program are provided. The hybrid receiver apparatus a first receiver processor and a second receiver processor and a signal input by the hybrid receiver apparatus is processed by both the first receiver processor and the second receiver processor. The hybrid receiver apparatus includes a combiner unit combining data output from the first receiver processor with data output from the second receiver processor based on a weight values assigned to the data.08-05-2010
20120207203Analog Continuous-Time Phase Equalizer for Data Transmission - In particular embodiments, a method includes receiving as an input signal a phase-distorted signal or a transmitted-data signal, the phase-distorted signal having been distorted from a phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising transmitted data; generating a non-derivative version of the input signal by applying a delay operator in a continuous-time domain to the input signal; generating a derivative version of the input signal by applying a derivative operator in a continuous-time domain to the input signal; generating a first product signal by multiplying the non-derivative version of the input signal by a first coefficient, the first coefficient being a positive number; generating a second product signal by multiplying the derivative version of the input signal by a second coefficient, the second coefficient being a negative number; and generating an output signal by summing the first and second product signals.08-16-2012
20110051799EQUALIZATION APPARATUS - This invention provides an equalization apparatus for equalizing an input signal on a cable. The equalization apparatus comprises a cable equalizer for equalizing a cable attenuation effect of the input signal to output a first equalization signal; and a stub equalizer for equalizing a stub effect of the first equalization signal to output an outputting equalization signal.03-03-2011
20110188566POST-EQUALIZATION AMPLITUDE LATCH-BASED CHANNEL CHARACTERISTIC MEASUREMENT - A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.08-04-2011
20110188565COMMA ALIGNMENT WITH SCRAMBLED DATA - Computer-readable media, apparatus and other embodiments associated with performing comma alignment with scrambled data are described. One example method includes controlling an apparatus to generate a data stream that facilitates achieving and determining alignment in a device. The data stream includes sequences of N random portions of Y-bit characters followed by a Z-bit alignment character, N, Y and Z being integers. Another example method includes controlling an apparatus to receive and examine the data stream. The method also includes generating an alignment signal upon determining an alignment for recovered data in the device.08-04-2011
20090175328DECISION FEEDBACK EQUALIZER (DFE) CIRCUITS FOR USE IN A SEMICONDUCTOR MEMORY DEVICE AND INITIALIZING METHOD THEREOF - A DFE circuit for use in a semiconductor memory device and an initializing method thereof. In the method of initializing a DFE circuit used in a semiconductor memory device having a discontinuous data transmission, the DFE circuit may be used for changing a sampling reference level in response to a level of previous data and sampling transmission data. The method includes terminating a data channel having a transmission of the transmission data at a predefined termination level, and controlling a sampling start time point of the transmission data as a time point preceding a transmission time point of the transmission data by a predefined time. Further, an initialization may be performed of the previous data on the basis of initialization data obtained through a pre-sampling of the data channel at a sampling start time point of the transmission data, thereby obtaining an initialization of the DFE circuit and compensating for a feedback delay.07-09-2009
20080273586Maximum Likelihood Block Decision Feedback Estimation for CCK Demodulation Apparatus and Method - A system for demodulation of CCK symbols into data includes a post equalization register having values computed from feedback filter coefficients determined during a packet preamble, where the feedback filter coefficients are provided to a reduced complexity post equalization value generator which populates the post equalization register with an iteration variable i. During a demodulation interval, a pre-equalize register has values computed from the previous data, which are used to perform decision feedback equalization. A demodulator has a first subtractor which subtracts the contents of the corresponding pre-equalize register from a current symbol, and the output of this subtractor is coupled to a simple Fast Walsh Transform (FWT) with an iteration variable k. The output of the FWT is coupled to a second subtractor for subtracting a plurality of ICI corrections for all possible current symbols computed and stored in the post equalization registers from the post-FWT domain value of the current CCK symbol. The demodulator iteration variable k is used for performing the demodulation of a current symbol into current data by performing the subtraction of current symbol ICI in k iterations using the same hardware.11-06-2008
20090060021MULTI-TAP DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE ELIMINATING CRITICAL TIMING PATH FOR HIGHER-SPEED OPERATION - A decision feedback equalizer (DFE) and method include summer circuits to add a dynamic feedback signal representing a dynamic feedback tap to a received input and to speculate on a speculative tap. Data slicers are configured to receive outputs of the summer circuits and sample the outputs of the summer circuits. First multiplexers are included, each of which is configured to receive a first input from a corresponding data slicer. Second multiplexers are included, each of which is configured to receive an output of a plurality of the first multiplexers. The second multiplexers have an output fed back to a second input of the first multiplexers, and the second multiplexer output is employed to provide a select signal for a second multiplexer on a different section of the DFE and to drive the dynamic feedback signal to a summer circuit on a same section of the DFE.03-05-2009
20080310495DECISION FEEDBACK EQUALIZER USING SOFT DECISIONS - A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.12-18-2008
20100098147EQUALIZER AND METHOD FOR PERFORMING EQUALIZATION - An FFE/DFE equalizer is provided that uses unclocked FIR filters. At least one of the unclocked FIR filters has tunable delay cells that can be tuned to adjust their respective time delay time periods. Because the FIR filters of the FFE/DFE equalizer are unclocked, the complexity and die area associated with clocking circuits are avoided, thereby enabling costs to be reduced. Because the delay cells of at least one of the FIR filters are tunable to enable their respective time delay periods to be adjusted, very good equalizer performance is achieved without having to use clocked circuits. In addition, because clocked circuits are not used in the FIR filters, the need for clocking circuits to control the timing of clocked circuits is obviated, which leads to a reduction in the amount of power consumed by the FFE/DFE equalizer.04-22-2010
20100098148LINEAR FEEDBACK SHIFT CALCULATION APPARATUS, COMMUNICATION APPARATUS, MICROPROCESSOR, AND DATA OUTPUT METHOD IN A LINEAR FEEDBACK CALCULATION APPARATUS - A linear feedback shift calculation apparatus, into which input data is input, and which outputs output data, including: an L generation unit which generates q values of q04-22-2010
20100027610EQUALIZER AND EQUALIZATION METHOD - An equalizer generates an equalized sample from a plurality of received samples in which a forward equalizer filters a received sample to generate a FE output. A feedback equalizer filters the equalized sample to generate a FBE output. An integrator adds the FE and FBE outputs to generate the equalized sample. The feedback equalizer comprises first and a second sub-filters. The first sub-filter has a first bit-width capability to generate a first FBE output from the equalized sample. The second sub-filter has a second bit-width capability to generate a second FBE output from the equalized sample. The first bit-width is higher than the second bit-width, and the first and second FBE outputs jointly organize the FBE output.02-04-2010
20100177816TX BACK CHANNEL ADAPTATION ALGORITHM - Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g., a slicer) as the quantifier input signal to quantify the quantifier input signal to one of multiple digital values. The channel distorted signal may be further adjusted by summing the channel distorted signal with the output of a Decision Feedback Equalizer (DFE) filter to create a DFE corrected signal which then becomes the quantifier input signal. An error signal is determined by finding the difference between the scaled quantifier decision and the quantifier input signal. The pre/post cursor coefficient values that adjust the effects of the pre/post cursor taps of the FIR filter are updated as a function of the error signal and at least two quantifier decision values, and update coefficient values, may be sent over a communications back-channel to the FIR filter.07-15-2010
20110090947DECISION FEEDBACK EQUALIZERS AND OPERATING METHODS THEREOF - A method for updating a tap coefficient of a decision feedback equalizer is provided. The method includes sampling a first input signal received by a sampler of a decision feedback equalizer. It is determined if an amplitude of the first input signal falls within a range defined between a first predetermined voltage level and a second predetermined voltage level. If the amplitude of the first input signal falls outside the range, a tap coefficient is updated to generate an updated tap coefficient that is fed back to adjust an amplitude of a second input signal received at an input end of the decision feedback equalizer. If the amplitude of the first input signal falls within the range, the tap coefficient is free from being updated.04-21-2011
20110317754EQUALIZER EMPLOYING ADAPTIVE ALGORITHM FOR HIGH SPEED DATA TRANSMISSIONS AND EQUALIZATION METHOD THEREOF - Disclosed are an equalizer and an equalization method employing an adaptive algorithm for high speed data transmissions. The equalizer includes: a subtraction unit subtracting a feedback signal from an input signal to generate a subtraction signal; a timing signal generation unit generating a sampling timing signal; an equalization signal generation unit equalizing the subtraction signal according to the sampling timing signal to generate an equalization signal; and a feedback signal generation unit calculating a filter coefficient value by using the subtraction signal and the equalization signal, delaying the equalization signal, and weighting the delayed equalization signal according to the filter coefficient value to generate a feedback signal.12-29-2011
20120044984High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.02-23-2012
20120044983Channel Equalization Using Application Specific Digital Signal Processing In High-Speed Digital Transmission Systems - A method and circuit for performing channel equalisation in a high speed transmission system comprising a transmitter and receiver. An application specific digital signal processor, ASDSP, performs channel equalisation and compensation on digital data received from an analogue-to digital converter of the receiver. The ASDSP is operable to execute an application specific set of op-codes needed for performing channel equalisation and compensation. An ASDSP register is coupled between the ASDSP and a system CPU in a feedback loop for performing channel equalisation at the receiver. The ASDSP stores equalizer parameters and bit error rate measurements used by the ASDSP for performing channel equalisation and compensation. An ASDSP program storage memory, coupled to and accessible by the ASDSP, stores an ASDSP micro-sequence program for controlling the processing steps for channel equalisation and dataflow through the ASDSP.02-23-2012
20120002713MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.01-05-2012
20120057628SYSTEM AND METHOD FOR OFDM RECEPTION IN THE PRESENCE OF DOPPLER EFFECT BASED ON TIME DOMAIN WINDOWING - An OFDM receiver for processing an OFDM received signal to perform OFDM reception in presence of Doppler effects is provided. The receiver has at least two parallel processing chains, each processing chain has a time domain windowing for processing an OFDM block. The processing consisting of the multiplication, element by element of the OFDM block, by a set of predetermined coefficients.03-08-2012
20120057627ADAPTATION CIRCUITRY AND METHODS FOR DECISION FEEDBACK EQUALIZERS - Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.03-08-2012
20120057626ADAPTATION OF CROSSING LATCH THRESHOLD - An apparatus including a bang-bang clock data recovery module and a decision feedback equalizer. The decision feedback equalizer is coupled with the bang-bang clock data recovery module. The apparatus is configured to reduce an effect on a settling point of the bang-bang clock and data recovery module due to coupling between the bang-bang clock and data recovery module and the decision feedback equalizer.03-08-2012
20120155529METHOD AND APPARATUS FOR USING DFE IN A SYSTEM WITH NON-CONTINUOUS DATA - A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.06-21-2012
20120250753CROSSING ISI CANCELLATION - An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.10-04-2012
20120027073METHODS AND APPARATUS FOR ADAPTATION OF CONTINUOUS TIME-DECISION FEEDBACK EQUALIZERS WITH PROGRAMMABLE ADAPTATION PATTERNS - Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.02-02-2012
20120106619SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD AND PROGRAM - A signal processing apparatus includes a signal processing unit configured to carry out signal processing on a single-carrier signal and a multi-carrier signal by making use of a plurality of common filters shared by the single-carrier signal and the multi-carrier signal.05-03-2012
20090310667PHASE CONTROL BLOCK FOR MANAGING MULTIPLE CLOCK DOMAINS IN SYSTEMS WITH FREQUENCY OFFSETS - A circuit for performing clock recovery according to a received digital signal (12-17-2009
20120207202Adaptive Phase Equalizer - In particular embodiments, a method includes generating by a data detector a recovered data signal from a phase-equalized signal based on the transmitted data in the phase-equalized signal; comparing by a phase-distortion detector the phase-equalized signal and the recovered data signal with each other; based on the comparison, determining by the phase-distortion detector a phase-distortion level; generating by the phase-distortion detector a phase-distortion-level signal based on the phase-distortion level; generating by an integrator a phase-equalize-level signal based on the phase-distortion-level signal; and adjusting by a phase equalizer a transmitted-data signal based on the phase-equalize-level signal, the adjustment of the transmitted-data signal providing the phase-equalized signal or a phase pre-distorted signal configured to be distorted into the phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising the transmitted data.08-16-2012
20120300831METHODS FOR PERFORMING ADAPTIVE EQUALIZATION AND ASSOCIATED APPARATUS - A method for performing adaptive equalization includes: dynamically detecting current levels of a plurality of sets of pattern levels respectively corresponding to a plurality of data patterns, wherein each set of the sets of pattern levels includes a previous level, a current level, and a next level respectively corresponding to one of the plurality of data patterns; and dynamically calculating a plurality of data decision levels according to the current levels of the sets of pattern levels, for use of data decision, wherein each data decision level of at least one portion of the plurality of data decision levels is not equal to zero, and the data decision levels are dynamically adjusted in accordance with the current levels of the sets of pattern levels, in order to enhance a signal-to-noise ratio (SNR). An associated method for performing adaptive equalization is also provided. Associated apparatus are also provided.11-29-2012
20120155530DECOUPLING BANG-BANG CDR AND DFE - An apparatus including a bang-bang clock data recovery module and a decision feedback equalizer. A phase detector of the bang-bang clock and data recovery module may be configured to eliminate coupling between the bang-bang clock and data recovery module and the decision feedback equalizer based upon an error signal of the decision feedback equalizer and a predetermined coefficient.06-21-2012
20120134407ADAPTIVE EQUALIZATION WITH GROUP DELAY - Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights to produce a filtered signal, and adaptively updating each of the plurality of adjustable tap weights to a new value to reduce effects of inter-symbol interference, wherein each of the plurality of adjustable tap weights is adaptively updated to take into account a constraint relating to a measure of error in the filtered signal and a constraint relating to group delay associated with the filter. Each of the plurality of adjustable tap weights may be adaptively updated to drive group delay associated with the filter toward a target group delay.05-31-2012
20120170640EQUALIZATION DEVICE, EQUALIZATION METHOD, AND RECORDING MEDIUM - An equalization device (07-05-2012
20120170639DELAY COMPENSATION FOR FEEDBACK CONTROLLERS - A control system for using a predictive control with a control process having a time delay includes an adaptive feedback controller and a predictor. The predictor uses at least an adaptively updated control parameter from the adaptive feedback controller to predict the output of the control process during the time delay. The control system further includes a filter that dampens the rate of change of the adaptively updated control parameter provided to the predictor from the adaptive feedback controller to slow the adaptation of the predictor relative to the adaptation of the adaptive feedback controller.07-05-2012
20120314756Decision Feedback Equalizer - A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.12-13-2012
20120128056METHOD AND APPARATUS FOR JOINT EQUALIZATION AND DECODING OF MULTIDIMENSIONAL CODES TRANSMITTED OVER MULTIPLE SYMBOL DURATIONS - A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.05-24-2012
20120128055METHOD, APPARATUS, AND SYSTEM TO COMPENSATE INTER-SYMBOL INTERFERENCE - Described herein are a method, an apparatus, and a system to compensate inter-symbol interference (ISI) for a signal at a receiver. The apparatus comprises a first logic unit to generate decision feedback equalizer (DFE) coefficients for data samples of a data signal; a second logic unit to generate DFE coefficients for edge samples of the data signal, wherein the DFE coefficients for the edge samples of the data signal are based at least in part on the DFE coefficients for the data samples of the data signal; and a third logic unit to compensate the data and edge samples of the data signal for inter-symbol interference at the data and edge samples of the data signal, wherein the third logic unit to compensate for inter-symbol interference by using the DFE coefficients for the data and edge samples generated by the first and the second logic units respectively.05-24-2012
20090060022System and method for equalizing an incoming signal - An equalizer is provided, comprising: a feedback combiner to combine an input signal and a feedback signal to produce a first signal; a delay line to delay the first signal to produce a second signal; a feed-forward combiner to combine the second signal and a feed-forward signal to produce an output signal; an interim decision circuit to extract a sign bit from the first signal; N feedback scaling elements to generate N scaled feedback signals; M feed-forward scaling elements to generate M scaled feed forward signals; a feedback circuit to pass the N scaled feedback signals through feedback delay elements and feedback summing elements to generate the feedback signal in response to the sign bit; and a feed forward circuit to pass the M scaled feed forward signals through feed-forward delay elements and feed-forward summing elements to generate the feed-forward signal in response to the sign bit.03-05-2009
20120076196DECISION DIRECTED TIMING RECOVERY USING MULTI-PHASE DETECTION - A set of one or more samples is received. Using a first signal processor associated with a first phase offset, a first decision and a first error value are generated using the set of samples. Using a second signal processor associated with a second phase offset, a second decision and a second error value are generated using the set of samples. This includes interpolating the set of samples to obtain a set of interpolated samples at the second phase offset and generating the second decision and the second error value using the set of interpolated samples at the second phase offset. A selection associated with the first decision and the second decision is made based at least in part on the first error value and the second error value.03-29-2012
20120076195SCALED SIGNAL PROCESSING ELEMENTS FOR REDUCED FILTER TAP NOISE - An adaptive transversal filter having tap weights Wj which are products of corresponding tap coefficients C03-29-2012
20120314757CIRCUITS AND METHODS FOR DFE WITH REDUCED AREA AND POWER CONSUMPTION - A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.12-13-2012
20110103458ASYMMETRIC DECISION FEEDBACK EQUALIZATION SLICING IN HIGH SPEED TRANSCEIVERS - An asymmetric DFE receiver circuit. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.05-05-2011
20100272169COMPENSATING CARRIER FREQUENCY OFFSETS IN OFDM SYSTEMS - In an OFDM system a plurality of subcarriers interferes with a considered subcarrier in case of carrier frequency offsets. A method and a corresponding receiver topology are disclosed for reducing the interference caused by frequency offsets of the subcarriers, wherein in a decision feedback equalizer the resources for computing the interference of subcarriers are adaptively allocated, such that only the most interfering subcarriers are considered when subtracting the interfering symbols from considered subcarrier symbols.10-28-2010
20100008414High-Speed Signaling Systems And Methods With Adaptable, Continuous-Time Equalization - A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.01-14-2010
20110235696Non-Linear Analog Decision Feedback Equalizer - An equalizer that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol. When the previous received symbol is a binary one, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary one to compensate for the non-linear effects impressed onto the received symbol.09-29-2011
20090016423Equalizer and a Method for Filtering a Signal - An equalizer comprising memory for storing a set of filter tap coefficients for defining the filtering characteristics to be applied to an input signal; and means for updating the set of filter tap coefficients based on an error signal derived from a difference between a received signal and a filtered signal unless an error code associated with a received data packet indicates an error in the received data packet.01-15-2009
20090016422SYSTEM FOR AN ADAPTIVE FLOATING TAP DECISION FEEDBACK EQUALIZER - A method for adaptive selection of floating taps in a decision feedback equalizer including the steps of (A) determining values for a predefined metric for tap positions within a range covered by a decision feedback equalizer (DFE) and (B) setting one or more floating taps of the DFE to tap positions based upon the values of the predefined metric.01-15-2009
20120327995Pipelining and Sub-Rate Operation for Memory Links - A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip.12-27-2012
20120230385Narrowband ingress estimation and characterization using equalizer taps - Narrowband ingress estimation and characterization using equalizer taps. A equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) is implemented to process an input signal thereby generating an output signal. Analysis of the frequency response of the equalizer including the FFE and the DFE of the equalizer allows for the determination of whether or not narrowband ingress exists within the signal received by the equalizer. For example, analysis of the signal output from the equalizer provides for determination of the overall frequency response of the equalizer. In addition, analysis of the respective equalizer coefficients within one or both of the FFE and the DFE of the equalizer may be used to determine the overall frequency response of the equalizer. Narrowband ingress may be identified when the combination of the FFE (having a notch therein) and the DFE provides for an overall flat frequency response.09-13-2012
20120230384STORAGE DEVICE, ELECTRONIC DEVICE, AND FREQUENCY BAND COMPENSATION LEVEL ADJUSTING METHOD - According to one embodiment, a storage device includes a first equalizer, a second equalizer, and an adjuster. The first equalizer compensates for a predetermined frequency band of a first signal transferred by a host via a storage interface and outputs the compensated first signal as a second signal. The second equalizer equalizes the second signal by decision feedback compensation. The adjuster adjusts the level of the frequency band compensation of the first equalizer based on the state of the decision feedback compensation.09-13-2012
20120236925ADAPTATION OF DELAY LINE FEEDBACK EQUALIZER - An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.09-20-2012
20120327994METHOD FOR CHANNEL EQUALIZATION - A method of equalizing a signal received over transmission channel defined by BEM coefficients of a basis expansion model of its channel taps, comprising the step of approximately solving the relation (I) for x[n] by an iterative method, n being the index of time, y[n] being the received signal, x[n] being the equalized signal, B12-27-2012
20100232494FAST GENERALIZED DECISION FEEDBACK EQUALIZER PRECODER IMPLEMENTATION FOR MULTI-USER MULTIPLE-INPUT MULTIPLE-OUTPUT WIRELESS TRANSMISSION SYSTEMS - A technique is used to realize a generalized decision feedback equalizer (GDFE) Precoder for multi-user multiple-input multiple-output (MU-MIMO) systems, which significantly reduces the computational cost while resulting in no capacity loss. The technique is suitable for improving the performance of various MU-MIMO wireless systems including future 4G cellular networks. In one embodiment, a method for configuring a GDFE precoder in a base station of a MU-MIMO wireless system having k user terminals, each user terminal having associated therewith a feedforward filter. The method comprises computing a filter matrix C using one of a plurality of alternative formulas of the invention; and, based on the computation of the filter matrix C, computing a transmit filter matrix B for a transmit filter used to process a symbol vector obtained after a decision feedback equalizing stage of the GDFE precoder, a feedforward filter matrix F, and an interference pre-cancellation matrix G.09-16-2010
20120320964METHODS AND SYSTEMS FOR PROVIDING OPTIMUM DECISION FEEDBACK EQUALIZATION OF HIGH-SPEED SERIAL DATA LINKS - Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification.12-20-2012
20100202507High Performance Equalizer Having Reduced Complexity - An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L08-12-2010
20100202506CIRCUITS AND METHODS FOR DFE WITH REDUCED AREA AND POWER CONSUMPTION - A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.08-12-2010
20100027612TRANSVERSAL FILTER - A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units.02-04-2010
20120243599Pipelining and Sub-Rate Operation for Memory Links - A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip.09-27-2012
20080247453Current mode logic multi-tap feed-forward equalizer - A system and method are provided for feed-forward equalization (FFE) in a transmission system. The method accepts a serial stream of input digital data signals. For each input data signal, a temporal sequence of signals is generated. Each of the signals in the temporal sequence is selectively shaped. Shaping map include varying the degree of amplification, modifying the slew rate, or varying the time delay. The contributions of the selectively shaped signals in the temporal sequence are then selectively weighted, and a summed output signal is transmitted.10-09-2008
20130142245PATTERN DETECTOR FOR SERIALIZER-DESERIALIZER ADAPTATION - In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.06-06-2013
20110274154Compensated Phase Detector for Generating One or More Clock Signals Using DFE Detected Data in a Receiver - A method and apparatus generating one or more clock signals in a receiver employing decision-feedback equalization (DFE). A received signal is sampled by a data clock and a transition clock, generating a data sample signal and a transition sample signal, respectively. A DFE correction is performed DFE circuitry on the data sample signal to generate DFE detected data bits. The transition sample signal is sliced using a weighted threshold value to generate corrected transition data. One or more phase updates of the data clock and the transition clocks are in response to the DFE detected data bits and the corrected transition data. The weighted threshold is calculated from at least one prior-received DFE detected data bit. In one embodiment, the DFE correction may also be dependent on an effective delay (λ) of the DFE circuit in relation to the received signal baud-period, T.11-10-2011
20130114665Low Nonlinear Distortion Variable Gain Amplifier - A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.05-09-2013
20130094561TECHNIQUES FOR ADAPTIVELY ADJUSTING DECISION LEVELS OF A PAM-N DECISION FEEDBACK EQUALIZER - A PAM-N decision feedback equalizer (DFE) comprises a coefficient computation unit; a feedback unit that mitigates, using computed feedback coefficients, effects of interference from data symbols; an error-and-decision unit for at least computing a least error value respective to one of a plurality of decision levels, wherein the least error value indicates a difference of a pseudo equalized input PAM-N data symbol from an optimal position of the one of the plurality of decision levels, wherein the one of the plurality of decision levels corresponds to a modulation level used to modulate data in the input PAM-N data symbol; and a calibration unit for adaptively setting the plurality of decision levels based, in part, on the least error value, thereby enabling for compensating for gain changes resulted by a cable on which the input PAM-N data symbol is received and further compensating for embedded offsets of the error-and-decision unit.04-18-2013
20130101011DATA RECEIVER CIRCUIT AND METHOD OF ADAPTIVELY CONTROLLING EQUALIZATION COEFFICIENTS USING THE SAME - Provided are a data receiver circuit and a method of adaptively controlling an equalization coefficient using the same. The data receiver circuit includes n sampling receivers, n decision feedback equalizer (DFE) circuits, and a data recovery circuit. The n sampling receivers are configured to sample an input signal and output n respective sampling signals in response to n respective clock signals. The n DFE circuits are configured to equalize the n respective sampling signals in response to a DFE control signal and generate n respective pre-recovery signals in response to the n equalized sampling signals and n respective previous pre-recovery signals, the DFE control signal for changing an equalization ability of the n DFE circuits. The data recovery circuit is configured to select one of the n respective pre-recovery signals, and output the selected n pre-recovery signal as a recovered input signal.04-25-2013
20130101010METHOD AND APPARATUS FOR JOINT DECODING AND EQUALIZATION - The current application is directed to joint decoding and equalization using a decision feedback equalizer. An example method to which the current application and certain of the current claims are directed uses joint trellis decoding and decision feedback equalization to efficiently estimate non-contiguous symbols using non-contiguous equalizer outputs. The estimation process uses all new possibilities of symbol values, rather than old decision feedback symbol estimates.04-25-2013
20130128946METHOD OF OPTIMIZING FLOATING DFE RECEIVER TAPS - A method for determining floating tap positions in a DFE of a receiver is disclosed. The method include providing a group of floating taps for the DFE; obtaining a baseline eye opening value for the receiver when the group of floating taps is disabled; providing a plurality of floating tap distribution configurations, each specifying a distribution configuration for the group of floating taps within the DFE; obtaining a plurality of eye opening values for the receiver, each particular eye opening value corresponding to a particular floating tap distribution configuration when the group of floating taps are distributed within the DFE according to the particular floating tap distribution configuration; comparing each of the plurality of eye opening values against the baseline eye opening value; and identifying an optimal floating tap distribution configuration based on the comparison of each of the plurality of eye opening values against the baseline eye opening value.05-23-2013
20110222594Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.09-15-2011
20080198916Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch - Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.08-21-2008
20110243215EQUALIZER AND SIGNAL RECEIVER THEREOF - An equalizer includes a first sampler, a second sampler, and an equalization circuit. The first sampler is used for sampling an input data to generate an output data, and the second sampler is used for sampling the input data to generate an edge information. The equalization circuit is coupled to the first sampler and the second sampler, and includes an equalization unit and a control unit. The equalization unit performs an equalization operation on an original input data in order to generate the input data according to a plurality of tap coefficients. The control unit is coupled to the equalization unit, for adjusting the plurality of tap coefficients according to the output data and the edge information.10-06-2011
20130148712CONDITIONAL ADAPTATION OF LINEAR FILTERS IN A SYSTEM HAVING NONLINEARITY - Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.06-13-2013
20100316112COMMUNICATION SIGNAL RECEIVER AND SIGNAL PROCESSING METHOD THEREOF - A communication signal receiver includes an adder, a slicer, and an infinite impulse response (IIR) filter. The adder performs an addition on a first signal and a filtered signal to generate an output signal. The slicer performs a hard decision on the output signal to generate a detecting result. The IIR filter is coupled to the slicer and the adder for processing the output signal to generate the filtered signal. The communication signal receiver further includes a decoder. The decoder receives and decodes the output signal to generate a decoded output signal, wherein the decoder is a Viterbi decoder.12-16-2010
20130156087A DECISION FEEDBACK EQUALIZATION SCHEME WITH MINIMUM CORRECTION DELAY - A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.06-20-2013
20110310952METHOD AND APPARATUS FOR BLOCK-WISE DECISION-FEEDBACK EQUALIZATION FOR WIRELESS COMMUNICATION - Techniques for performing decision feedback equalization are described. A feed-forward filter response and a feedback filter response are derived based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an on-time sample. The reliability parameter is indicative of the reliability of the feedback used for equalization and may be frequency dependent or frequency invariant. Different feed-forward and feedback filter responses may be derived with different constraints on the feedback filter and different assumptions for the reliability parameter. Equalization is performed with the feed-forward and feedback filter responses. If equalization is performed for multiple iterations then, for each iteration, the reliability parameter may be updated, the feed-forward and feedback filter responses may be derived based on the updated reliability parameter, and equalization may be performed with the filter responses for the iteration.12-22-2011
20110310951COMPUTATIONALLY-EFFICIENT MIMO EQUALIZATION ALGORITHM FOR HIGH-SPEED, REAL-TIME, ADAPTIVE POLARIZATION MULTIPLEXED (POLMUX) OFDM TRANSMISSION WITH DIRECT DETECTION - A polarization-multiplexed (POLMUX) optical orthogonal frequency division multiplexing (OFDM) system with direct detection includes an adaptive dual POLMUX carrier OFDM transmitter; and a block symmetric (B-S) MIMO equalizer coupled to the adaptive dual POLMUX carrier OFDM transmitter through a standard single-mode-fiber (SSMF) feedback path.12-22-2011
20120027074Summer Block For A Decision Feedback Equalizer - Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount. The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.02-02-2012
20120082203SELECTABLE-TAP EQUALIZER - A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.04-05-2012
20130208782TIME DOMAIN ANALOG MULTIPLICATION TECHNIQUES FOR ADJUSTING TAP WEIGHTS OF FEED-FORWARD EQUALIZERS - Feed-forward equalizer (FFE) circuits and methods are provided which implement time domain analog multiplication for adjusting FFE tap weights. For example, a method includes inputting data signals to FFE taps of a current-integrating summer circuit, wherein the data signals are time-delayed versions of an analog input data signal. A capacitance is charged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each FFE tap during an integration period of the current-integrating summer circuit. The output currents from the FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to a given FFE tap during the integration period to enable the given FFE tap during a portion of the integration period in which the gating control signal overlaps the integration period so as to effectively multiply the data signal input to the given FFE tap with an FFE coefficient value corresponding to a period of overlap between the gating control signal and the integration period.08-15-2013

Patent applications in class Decision feedback equalizer