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Phase error or phase jitter

Subclass of:

375 - Pulse or digital communications

375224000 - TESTING

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20090028231APPARATUS FOR MEASURING IQ IMBALANCE - The present invention relates to an apparatus and a method for measuring an IQ imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.01-29-2009
20090122851METHOD AND DEVICE FOR DATA PROCESSING AND COMMUNICATION SYSTEM WITH DATA PROCESSING DEVICE - Signal processing and/or signal modulation includes tracking a phase parameter; determining a discontinuity; and compensating for the discontinuity.05-14-2009
20090122849TESTABILITY TECHNIQUE FOR PHASE INTERPOLATORS - A method and circuit for testing phase interpolators is provided. The method performs a sweep over a phase interpolator delay range and detects if the phase interpolators experience an unacceptably large non-linearity which leads to inaccurate clock timing. The testing circuit implementing this technique uses a phase detector to detect a fault, and in one embodiment, an additional phase interpolator is added as well.05-14-2009
20090041104Phase and Frequency Recovery Techniques - Phase and frequency recovery techniques comprising; a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, and receiver synchronization techniques (RST) enabling by one order more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of receivers oscillator.02-12-2009
20100074314Margin Test Methods And Circuits - Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.03-25-2010
20100046595SEMI-COHERENT TIMING PROPAGATION FOR GERAN MULTISLOT CONFIGURATIONS - A method for estimating timing in a wireless communication comprises the steps of receiving a plurality of symbol bursts corresponding to a plurality of time slots and selecting a subset of symbols from a first symbol burst of the plurality of symbol bursts. The subset comprises a first midamble symbol. The method further comprises the steps of calculating, for each symbol in the subset, a corresponding midamble estimation error, and determining the lowest calculated midamble estimation error to determine a timing for the first symbol burst. The method further comprises the steps of processing the first symbol burst utilizing the timing determined for the first symbol burst, and processing a second symbol burst of the plurality of symbol bursts utilizing the timing determined for the first symbol burst.02-25-2010
20100046594Method and device for decoding a signal - In a method and a device for decoding a signal, the signal is transmitted via at least one connecting line of a data transmission system, in a user of the data transmission system receiving the signal. It is provided to measure the interval of a change—provided compulsorily in a transmission protocol used in the data transmission system—of the signal from rising to falling or from falling to rising edge. A tendency for an asymmetrical delay of the signal can be ascertained from the measured interval. The sampling of the bits of the received signal can be improved as a function of the interval or of the asymmetrical delay, for example, by setting the sampling instant in variable fashion. Alternatively, the interval or the asymmetrical delay can be utilized for diagnostic purposes.02-25-2010
20100002757SYSTEM AND METHOD FOR IMPROVED FREQUENCY/PHASE ERROR TRACKING IN HIGH-SPEED HIGH-FREQUENCY COMMUNICATION - A single carrier modulation scheme suitable for use in high frequency communication systems is provided that achieves improved residual frequency error and phase noise estimation. At a transmitter, cyclically orthogonal constant amplitude pilot signals are inserted at the beginning (or end) of a plurality of SCBT blocks of a block coded data stream. At a receiver, a phase rotation of the received data stream is determined to remove a residual frequency error or to estimate the phase noise.01-07-2010
20130070829SAMPLING PHASE CALIBRATING METHOD, STORAGE SYSTEM UTILIZING THE SAMPLING PHASE CALIBRATING METHOD - A sampling phase calibrating method, comprising: transmitting a second command signal from a storage device controller, to read content in a storage device; transmitting a first command signal and a third data signal with a third sampling phase from the storage device controller to the storage device, according to the content; and determining if data transmitting from the storage device controller to the storage device has error, according to responding information that the storage device responds to the storage device controller corresponding to the first command signal and the third data signal, to determine if the third sampling phase is suitable; wherein the second command signal is transmitted via a second clock, the first command signal is transmitted via a first clock, where the second clock is slower than the first clock.03-21-2013
20130070830CHARACTERIZATION OF THE JITTER OF A CLOCK SIGNAL - A method for characterizing jitter of an internal clock signal of a circuit may include generating a series of samples of the internal clock signal by a reference clock signal, comparing the word formed by the N most recent samples of the series to an N-bit pattern, where N is an integer greater than, or equal to 2, and incrementing a first counter if the word complies with the pattern. The method may also include incrementing a second counter when the count of the first counter reaches a first threshold X1, and incrementing a third counter when the count of the first counter reaches a second threshold different from the first. The method may include calculating an average p and a standard deviation σ of a Gaussian density curve as a function of the counts reached in the second and third counters.03-21-2013
20130070828Systems and Methods For Demodulating a Signal - A high-sensitivity receiver may be made by using multiple demodulators to demodulate a given signal. For example, the receiver may use a first demodulator to demodulate an input signal into a first sequence of soft bits and a second demodulator to demodulate the same input signal into a second sequence of soft bits. The two sequences of soft bits may then be compared and combined to create a sequence of hard bits. For example, in some embodiments, a soft bit combiner may combine the two sequences of soft bits into a third sequence of soft bits, which may then be input into a decoder to produce the final decoded hard bits. The secondary demodulator may be less complex, less expensive, demand less power, and/or require fewer computational resources when operating, than the first demodulator.03-21-2013
20090268798WIRELESS COMMUNICATION UNIT AND METHOD FOR CHANNEL ESTIMATION - A method is provided for estimating at least one offset of a communication in a multicarrier communication system. The method comprises receiving a plurality of subcarriers wherein the plurality of subcarriers contain the subcarrier that is subject to the distortion; and generating a plurality of first channel estimates for a respective plurality of received subcarriers that are not subject to the distortion. The method further comprises processing a number of the plurality of first channel estimates for the respective plurality of received subcarriers that are not subject to the distortion to generate a second channel estimate for the subcarrier that is subject to the distortion; and estimating an offset associated with the subcarrier that is subject to the distortion.10-29-2009
20130064278Systems and Methods for Performing Phase Tracking Within an ADC-Based Tuner - Systems and methods for performing phase tracking scheme for an Analog to Digital converter based tuner. In many embodiments, a phase tracking scheme is used that includes a phase locked loop that corrects the phase of the output signals and an amplitude modulation compensator that modulates the amplitude of the output digital signals to compensate for phase noise based upon the received output digital signals.03-14-2013
20130163654ENCODER - An encoder (06-27-2013
20120236920DRX OPERATION WITH CRYSTAL OSCILLATOR - A method in a receiver includes receiving from a transmitter an instruction to check for messages from the transmitter at intervals having a specified time period. A frequency error of the receiver relative to the transmitter is estimated at the receiver, and an actual time period that does not exceed the specified time period is selected based on the estimated frequency error. The receiver is activated periodically according to the selected actual time period so as to reset the frequency error.09-20-2012
20130163655SYMBOL ERROR DETECTION FOR BLUETOOTH ENHANCED DATA RATE PACKETS - A symbol error detector can be configured to detect symbol errors of a Bluetooth enhanced data rate (EDR) packet without relying solely on a CRC error detection mechanism. After a phase of a current symbol is demodulated to determine a demodulated current symbol, the phase of the demodulated current symbol can be subtracted from the phase of the current symbol prior to demodulation to yield a phase error. The phase error can be compared against a phase error threshold to determine a potential unreliability of the demodulated current symbol. The phase error being greater than the phase error threshold can indicate that the demodulated current symbol may be unreliable. Accordingly, a symbol error notification can be generated to indicate that the demodulated current symbol may be unreliable.06-27-2013
20130163656COMMUNICATION DEVICE AND ORTHOGONAL-ERROR CORRECTION METHOD - By a simple computation, orthogonal errors from an orthogonal modulator and an orthogonal demodulator are separately corrected. Based on the amplitude of a demodulated signal, an orthogonal-error detection unit (06-27-2013
20100158092JITTER ADDITION APPARATUS AND TEST APPARATUS - Provided is a jitter injection apparatus that injects jitter into a signal, comprising: a plurality of jitter injecting sections that are provided in series in a transmission path that propagates the signal; an output section that selects the signal that is passed from a jitter injecting section at a first stage through a designated jitter injecting section, and outputs the selected signal; and a plurality of branch-path jitter injecting sections that (i) are provided in a plurality of branch paths that propagate the signal output by each jitter injecting section from the transmission path to the output section and (ii) are relays having frequency characteristics of attenuating a high-frequency band more than a low-frequency band06-24-2010
20110286510ELECTRONIC DEVICE FOR GENERATING A FRACTIONAL FREQUENCY - It is described an electronic device for generating a fractional synthesized frequency. The device comprises a multi-phase controlled oscillator configured to generate, from a control signal, a plurality of signals phase-shifted each other and comprises a phase detector configured to receive a selected signal from the plurality of phase-shifted signals, to receive a reference signal and to measure a difference between a phase of the selected signal and a phase of the reference signal. The electronic device further comprises control means for estimating, from the measured phase difference, a phase error affecting the generation of at least one of the plurality of phase-shifted signals, and for generating a corrected measure of the phase difference taking into account the estimated phase error, the corrected measure being used to provide the control signal.11-24-2011
20110292987METHOD FOR DECOMPOSING AND ANALYZING JITTER USING SPECTRAL ANALYSIS AND TIME-DOMAIN PROBABILITY DENSITY - A method for analyzing jitter using a test and measurement instrument includes obtaining a collection of time interval error (TIE) values corresponding to composite jitter of a waveform, optionally decomposing the composite jitter into jitter components that are correlated to the data pattern and components that are uncorrelated to the data pattern, and using a spectral approach to decompose the jitter components into jitter components that are recognizable as deterministic and jitter components that are unrecognizable as deterministic. Thereafter, the jitter components analyzed in the frequency domain are converted back to the time domain, and subtracted from the composite jitter, thereby isolating uncorrelated residual jitter. The uncorrelated residual jitter is decomposed into bounded uncorrelated jitter and random jitter, for example, by integrating a probability density (PDF) function of the residual jitter and analyzing the resulting cumulative distribution function (CDF) curve in Q-space.12-01-2011
20090296796METHOD AND APPARATUS FOR IMPROVED STORAGE AREA NETWORK LINK INTEGRITY TESTING - A method and apparatus that is configured to issue an echo extended link service with a payload of data patterns that are known in the art of fibre channel to produce jitter. The inventive apparatus is configured to use an echo extended link service to send data with a specified data pattern. Failing data patterns are compared against data patterns that are known in the art of fibre channel to create jitter and the results may be presented to the user.12-03-2009
20100266004DETECTING APPARATUS, CALCULATING APPARATUS, MEASUREMENT APPARATUS, DETECTING METHOD, CALCULATING METHOD, TRANSMISSION SYSTEM, PROGRAM, AND RECORDING MEDIUM - Provided is a detection apparatus that detects a phase alignment error between transmission signals transmitted on different channels, comprising a correlation calculating section that calculates a cross-spectrum between the transmission signals based on a result of a measurement of the transmission signals transmitted in the channels; a phase difference calculating section that calculates a phase difference spectrum between the transmission signals based on the cross-spectrum calculated by the correlation calculating section; and a detecting section that detects a difference between transmission times of the transmission signals transmitted on the different channels and a phase offset between the transmission signals, based on the phase difference spectrum calculated by the phase difference calculating section.10-21-2010
20100027603SYSTEM AND METHOD FOR AUTOMATIC RECOVERY AND COVARIANCE ADJUSTMENT IN LINEAR FILTERS - A communications device includes a time/frequency error measurement circuit that receives a communications signal and measures its timing and frequency errors. A Kalman filter receives the communications signal from the time/frequency error measurement circuit and processes the signal using a multi-level state error covariance matrix P for controlling the Kalman gain in the Kalman filter. An on-line monitoring circuit is operative with the Kalman filter for monitoring the actual state errors in time and frequency and controlling the state error covariance matrix P based on a measured error threshold.02-04-2010
20090207897MEASURING APPARATUS, TEST APPARATUS, RECORDING MEDIUM, PROGRAM AND ELECTRONIC DEVICE - There is provided a measuring apparatus for measuring a signal-to-noise ratio of a discrete waveform which is output from an AD converter in response to an input signal, where the signal-to-noise ratio indicates a ratio of a signal component of the input signal to noise generated by the AD converter. The measuring apparatus includes a spectrum compensating section that receives a spectrum of the discrete waveform output from the AD converter, and compensates the received spectrum in accordance with a non-symmetric sideband between an upper sideband and a lower sideband of the received spectrum, where the upper and lower sidebands are defined with respect to a fundamental frequency of the input signal, and a phase noise waveform calculating section that calculates a phase noise waveform of the discrete waveform based on the spectrum which has been compensated by the spectrum compensating section.08-20-2009
20120106611PHASE LOCKING LOOP - A phase-locking loop (PLL) for use with orthogonal frequency division multiplexed signals. In one embodiment, a wireless receiver includes a PLL is configured to reduce phase and frequency divergence between the wireless receiver and a transmitter of a packet received by the wireless receiver. The PLL includes a loop bandwidth controller. The loop bandwidth controller is configured to set a bandwidth of the PLL to a first value for reception of an initial symbol of the packet. The loop bandwidth controller is configured to reduce the bandwidth of the PLL over a number of symbols preceding an initial header of the packet.05-03-2012
20100111154ELECTRONIC DEVICE, INTEGRATED CIRCUIT AND METHOD THEREFOR - A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.05-06-2010
20110206106HIERARCHICAL FEEDBACK OF CHANNEL STATE INFORMATION FOR WIRELESS COMMUNICATION - Techniques for sending hierarchical feedback of channel state information are described. In one design, a user equipment (UE) determines channel gain information for multiple cells selectable to transmit data to the UE. The UE also determines intra-cell relative phase information for at least one cell among the multiple cells. The UE reports the channel gain information and the intra-cell relative phase information. The channel gain information may include multiple quantized channel vectors for each of the multiple cells. The intra-cell relative phase information may indicate phase errors in the quantized channel vectors for each of the at least one cell. The UE may also determine and report other information. The UE may receive data from one or more cells among the plurality of cells. Each cell may transmit data based on at least one transmit vector determined based on the channel gain information and the intra-cell relative phase information.08-25-2011
20100061435Jitter evaluation - A jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, is shown. A clock recovery circuit (03-11-2010
20090168860COMMUNICATION SYSTEM BETWEEN A FIRST AND A SECOND SYNCHRONOUS DEVICE THAT ARE UNCORRELATED IN TIME - A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.07-02-2009
20080273585Apparatus for Estimating Phase Error and Phase Error Correction System Using the Same - Provided are an apparatus for estimating a phase error and a phase error correcting system using the phase error estimating apparatus. The apparatus includes: a probability value estimating unit for estimating a negative log probability value for each transmission symbol by transforming a soft output information transferred from the outside to a log A posterior probability ratio (LAPPR) value; an APP value calculating unit for calculating a posterior probability (APP) value by applying a negative exponential function to the transmission symbol; an average value deciding unit for deciding an average value for each transmission symbol using the probability information entirely, partially, or selectively according to a probability information type; and a symbol phase estimating unit for estimating a phase of a symbol based on the decided average value.11-06-2008
20080310489COMMUNICATION SYSTEM, RECEIVER UNIT, AND ADAPTIVE EQUALIZER - A communication system in which a signal is transferred includes a transmitter that transmits a signal, a receiver that receives a signal transmitted thereto, and an adaptive equalizer that generates a compensated signal by compensating degradation of the signal to be received by the receiver. The adaptive equalizer includes a signal compensating section that generates the compensated signal by passing therethrough the signal to be received by the receiver, a jitter measuring section that measures jitter of the compensated signal output from the signal compensating section, and an adjusting section that adjusts a characteristic of the signal compensating section so as to reduce the jitter of the compensated signal which is measured by the jitter measuring section.12-18-2008
20090003423Frequency Offset Estimation Apparatus and Method in Wireless Communication System - The present invention relates to an apparatus and method for estimating a frequency offset in a wireless telecommunication system. The present invention does not estimate an initial frequency offset using a preamble which is the initial symbol of a frame upon estimation of the frequency offset in the wireless telecommunication system, but estimates a frequency offset using correlation of a cyclic prefix (CP) existing in each symbol, thereby eliminating a need to reproduce information about separate preamble signals and preamble signals, and easily estimating a frequency offset using only input signals.01-01-2009
20090122850 TEST CIRCUIT CAPABLE OF MASKING DATA AT READ OPERATION AND METHOD FOR CONTROLLING THE SAME - A test circuit capable of reducing the number of data I/O pins of a tester at a read operation includes a data masking control unit for masking a part of output data in response to an activation of one of an upper data masking signal to control a group of upper data pins and a lower data masking signal to control a group of lower data pins when a test mode signal is activated at a read operation.05-14-2009
20080317110RELIABLE MULTICARRIER COMMUNICATION IN THE PRESENCE OF TIMING PHASE ERROR - A method, system and apparatus for reliable multicarrier communication in the presence of timing phase error is disclosed. Phase noise due to a sampling-time phase mismatch between a transmitter device and a receiver device is measured in a signal. A Gaussian noise power level in the signal is determined, and a gain factor associated with the phase noise is calculated. The gain factor is applied to the Gaussian noise power level to calculate an equivalent noise power. In one aspect, the equivalent noise power is used to determine a signal-to-noise ratio. In another aspect, the signal is a multicarrier signal including a plurality of sub-carriers.12-25-2008
20090052511METHOD FOR SIGNAL JITTER DETECTIONS BASED ON TIME-FREQUENCY DOMAIN ANALYSIS - A jitter measuring method that helps the electronic system designer to reduce system jitter by tracing the jitter frequency variation and by detecting the transient jitter. The method includes below procedure: first, calculate the jitter of the signal to obtain signal jitter time trend waveform; then, decompose the jitter time trend waveform in the time-frequency domain to obtain the time varying frequency; after that, observe the decomposed results in time-frequency domain to trace out jitter frequency variation in time or to trace out transient jitter frequency and moment.02-26-2009
20090225822System and Methods for Receiving OFDM Symbols Having Timing and Frequency Offsets - Systems and methods for receiving an OFDM preamble without knowledge of channel characteristics are provided. An OFDM preamble signal with frequency shifted cyclic extensions is received. Taken together the cyclic extensions form a frequency shifted version of the OFDM preamble signal. Frequency offsets and timing offsets are estimated and corrected in an efficient manner using a simple concatenation approach in the time domain, followed by a summation of the OFDM preamble signal and the concatenation after a transformation of the OFDM preamble and the concatenation into the frequency domain. Phase errors in the frequency domain are estimated and corrected after FFT transformations of the received signals. A valid preamble is detected and additional parameters for receiving subsequently transmitted OFDM symbols in a channel are extracted from the OFDM preamble. The methods are computationally efficient and robust. Receiver implementations for performing the methods in a DVB receiver are disclosed.09-10-2009
20110222592MEASUREMENT APPARATUS, MEASUREMENT METHOD AND RECORDING MEDIUM - A measurement apparatus that measures at least one of phase error and gain error between I and Q of a quadrature modulator, comprising a supplying section that shifts a reference I signal corresponding to an I component in an IQ signal causing a tone signal and/or a reference Q signal corresponding to a Q component in the IQ signal to have a time difference therebetween, and supplies the resulting signals to the quadrature modulator; and a calculating section that calculates at least one of the phase error and the gain error, based on an I-signal frequency component corresponding to a tone signal in a modulated signal output from the quadrature modulator in response to the reference I signal being supplied thereto and a Q-signal frequency component corresponding to a tone signal in a modulated signal output from the quadrature modulator in response to the reference Q signal being supplied thereto.09-15-2011
20090245339APPARATUS AND METHOD FOR ANALYZING A SIGNAL UNDER TEST - A portion of a signal under test corresponding to a portion of interest in an eye pattern is easily identified. An eye pattern display area displays an eye pattern that is derived from sample data of a signal under test in a bitmap form and shows frequency information with colors or brightness. A user selects an arbitrary point on the eye pattern display area with a cross-hair shaped mouse cursor, by manipulating a mouse. Thereafter, a waveform passing through the selected point is discriminably displayed, for example, with highlighted display on the eye pattern. Further, the corresponding portion of a waveform in the waveform display area is distinguishably displayed, such as with a highlighted display.10-01-2009
20100150218JITTER GENERATION APPARATUS, DEVICE TEST SYSTEM USING THE SAME, AND JITTER GENERATION METHOD - A jitter generation apparatus for applying a phase modulation to a PLL is controlled by a control unit so as to output a signal with the desired jitter based on a parameters. When a switching unit is switched to a first state, the control unit controls first and second level control units so that the desired jitter in which an amplitude of a first modulation signal matches the parameter is added to an output signal from a voltage controlled oscillator unit, and passes through a quadrature modulator. When the switching unit is switched to the second state, the control unit controls the first and second level control units so that a quadrature modulation is applied to a local signal, which is input to the quadrature modulator without adding any jitter to an output signal from the voltage controlled oscillator unit, and a quadrature-modulated local signal is output.06-17-2010
20100158091FREQUENCY ERROR ESTIMATOR AND FREQUENCY ERROR ESTIMATING METHOD THEREOF - Provided is a frequency error estimating method of a communication system. The method includes receiving a frame, and calculating a frequency error from a SOF field of the received frame.06-24-2010
20100220778FREQUENCY CONVERTING SYSTEM - In a frequency converting system, an input signal x(t) is supplied to a signal branching section for dividing a predetermined frequency domain into M bands, extracting signal components of the respective divided bands. The respective signal components and local signals each including a frequency difference corresponding to a predetermined intermediate frequency with respect to a center frequency of each band are input to a frequency converting part. The signals of the respective divided bands are converted into signals of intermediate frequency bands each including the predetermined intermediate frequency as the center frequency, the conversion outputs are sampled by using a common clock signal, whereby the conversion outputs are converted into digital signals. Further, after being subjected to phase correction processing, the digital signals are subjected to frequency conversion and combination processing by a signal regeneration part.09-02-2010
20100080274JITTER MEASUREMENT APPARATUS, JITTER CALCULATOR, JITTER MEASUREMENT METHOD, PROGRAM, RECORDING MEDIUM, COMMUNICATION SYSTEM AND TEST APPARATUS - Provided is a jitter measurement apparatus that measures timing jitter of a signal under measurement having a prescribed repeating pattern, comprising a sampling section that coherently samples the signal under measurement within a prescribed measurement duration; a waveform reconfiguring section that rearranges ordinal ranks of data values sampled by the sampling section to generate a reconfigured waveform that is a reproduction of a waveform of the signal under measurement; an analytic signal generating section that converts the reconfigured waveform into a complex analytic signal; and a jitter measuring section that measures jitter of the signal under measurement based on the analytic signal.04-01-2010
20090274203Measuring Method and Device for Evaluating an OFDM-Multi-Antenna Transmitter - A method provides for evaluating the power performance of an OFDM multi-antenna transmitter, wherein a sum signal formed according to the WiMAX standard and transmitted from the multi-antenna transmitter, which represents a superposition of a preamble transmitted signal from a preamble transmit antenna of the multi-antenna transmitter and of at least one transmitted signal from a further transmit antenna of the multi-antenna transmitter, is transmitted via a transmission channel. A test receiver is phase-synchronized relative to the preamble transmit antenna on the basis of a preamble of the preamble transmitted signal, and a relative phase error between the transmitted signals is determined on the basis of a modulation method used for the transmission channel, the preamble and the error-vector magnitude (SEVM) calculated from the sum signal. A device for implementing the method is also provides.11-05-2009
20090074045Estimating frequency offset at a subscriber station receiver - A method and system of estimating frequency offset at a subscriber station is disclosed. The method includes the subscriber station receiving a composite signal, in which the composite signal includes multi-carrier signals transmitted from a plurality of base stations. The subscriber station selects a subset of the plurality of base stations. The subscriber station selects at least one pair of multi-carrier symbols of the composite signal, wherein each of the at least one pair of multi-carrier symbols include a plurality of pilot sub-carriers. The subscriber station selects a subset of the plurality of pilot sub-carriers of the at least one pair of multi-carrier symbols based on transmit pilot symbols of the pilot sub-carriers of the multi-carrier signals transmitted by the subset of the plurality of base stations. The frequency offset is estimated based on a conjugate product between received symbols across at least one pair of multi-carrier symbols of each of the pilot sub-carriers of the selected subset of the plurality of pilot sub-carriers.03-19-2009
20090147839QAM phase error detector - The present invention relates to a method for reducing cycle slips in a carrier recovery loop for a phase detector, the method comprising the steps of receiving an input signal consisting of samples, each received sample having an in-phase (I) and quadrature-phase (Q) component, providing the input signal to a phase error estimator adapted to determine a phase error estimate, providing the phase error estimate to a loop filter, and forming an output signal from the carrier recovery loop by subtracting an output from the loop filter from the input signal, wherein the phase error estimate is determined based on a combination of the amplitude and phase of the samples and a probability measure for a specifically transmitted symbol, thereby improving phase tracking performance of the carrier recovery loop.06-11-2009
20090161744METHOD FOR ESTIMATING AND MONITORING TIMING ERRORS IN PACKET DATA NETWORKS - A system and method is provided for estimating the T1 timing error and clock recovery errors by processing timing information from the associated pseudowire packet stream(s) from which the Ti is derived. The timing errors are presented as MTIE measurements which are used to present alarms for a Network Operation Control centre and are used to accurately alarm error conditions where the regenerated or derived T1 signal does not meet MTIE or clock accuracy errors. This alarm is intended to detect conditions of excessive packet jitter, wander or phase transients which may exist in the data network over which the pseudowire stream is transported. In another aspect, the errors are used to control the regeneration of the T1 clock information.06-25-2009
20130136165RECEPTION DEVICE - An FFT unit subjects a P-times oversampling output of an AD converter to Fourier transform into a frequency domain signal. A distortion estimation unit estimates a distortion characteristic from a difference between the frequency domain signal and a reference signal. A correction coefficient calculation unit calculates a correction coefficient of a distortion characteristic. A correction unit corrects the frequency domain signal by using the correction coefficient. An IFFT unit subjects the corrected frequency domain signal to inverse Fourier into a time domain signal having the same sampling speed as a symbol speed, and outputs a partial time series.05-30-2013
20110026573DATA SIGNAL GENERATING APPARATUS - It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization means 02-03-2011
20110032976Start-up Procedure Method and Timing Recovery for Receiver of Communication System - A method for starting up a receiver of a communication system includes training an interference canceller of the receiver, keeping the interference canceller in a tracking state after the interference canceller converges, and starting to train a timing recovery device of the receiver.02-10-2011
20090323793ESTIMATION AND CORRECTION OF INTEGRAL CARRIER FREQUENCY OFFSET - Systems, methods, and devices are described for estimating and correcting an integral carrier frequency offset. A wireless signal is received, the signal including a reference symbol. A first set of difference measurements between pairs of a series of subcarriers of the received wireless signal may be calculated. A second set of difference measurements between pairs of a series of subcarriers of the reference symbol may be calculated. The second set of difference measurements is searched using the first set of difference measurements. The first set of difference measurements is correlated with the second set of difference measurements to estimate an integral carrier frequency offset.12-31-2009
20120134404Symbol Synchronization for Communication - A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.05-31-2012
20120134403CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT - Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.05-31-2012
20100054318Timing Error Detector and Method Thereof - An effective data sequence based timing error detector (EDS-TED) for baseband transmission system using Tomlinson-Harashima Precoder is disclosed. The EDS-TED extracts timing error information embedded in the received signal to build up autocorrelation between the ESD signals and minimize the mean square error between the received and desired EDS so as to improve the performance of the TED in terms of Peak-to-Peak Jitter and TED gain. Thus the quality of the received signal increases and the error rate decreases.03-04-2010
20110176597CLOCK JITTER SUPPRESSION METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A value held in storage elements coupled to a clock buffer and variably set with a threshold voltage is read out in a state where an analyzing target circuit within an IC operates. An analyzing process specifies an impact of noise in a power supply or ground voltage of the clock buffer and a location where the impact is large, based on the threshold voltage and position information of the storage element from which the read out value has an inverted relationship to the set logic value and each storage element that is a read target. A constraint condition for placement of constituent elements of the IC and routing therein is created from results of the analyzing process, and a re-placement or re-routing process re-places or re-routes the constraint condition to reduce the noise.07-21-2011
20100135373CLOCK GENERATING DEVICE AND JITTER REDUCING METHOD IN THE CLOCK GENERATING DEVICE - A clock generating device includes: a DDS circuit that generates a periodic signal; and a comparator that compares an input signal and a reference signal and outputs a binary signal. The clock generating device includes a rate-of-change correcting unit that applies correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.06-03-2010
20090213918SEPARATING JITTER COMPONENTS IN A DATA STREAM - A method and corresponding device for measuring jitter in a data stream and separating the jitter into its various components is disclosed. The measurement device includes a sampling circuit operative to provide a sampled version of an input data stream in response to a sampling control signal; a comparison circuit operative to provide a signal representing the difference between the sampled input data and a reference pattern; an error counter circuit operative to maintain the number of times the sampled input data does not match the reference pattern or a bit selection value within a bit window; and a bit selector circuit operative to provide the bit selection value in response to the bit sampling window of the circuit.08-27-2009
20110249718METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMS - A system for dynamically correcting phase errors between data and a timing reference signal caused by a transient event during data communication between a transmitter and a receiver is described. During operation, the system stores one or more phase-offset values for the event in an offset table, wherein the constituent phase-offset values are associated with phase error caused by the event. Upon detecting a subsequent occurrence of the event, the system adjusts a phase relationship between the data and the timing reference signal based on the one or more phase-offset values.10-13-2011
20110134985Signal Processing System and Method Thereof - A signal processing system is provided. The system includes a calculating apparatus, for calculating a phase error of a received signal and generating a weight according to the phase error; a signal adjusting apparatus, coupled to the calculating apparatus, for generating a plurality of soft values according to the weight and the received signal; and a decoder, coupled to the signal adjusting apparatus, for decoding the soft values to generate data.06-09-2011
20110134984APPARATUS AND METHOD FOR OBTAINING PHASE CORRESPONDING TO OBJECT POSITION - The apparatus corrects multi-phase signals for detecting a position of an object and obtains a phase corresponding to the position of the object. The apparatus includes a correcting unit correcting the multi-phase signals with error coefficients, respectively, a phase calculating unit performing calculation for the corrected multi-phase signals to obtain the phase, a regression unit performing regression for the calculated phases to obtain reference phases, a Fourier transform unit respectively performing Fourier transform for the corrected multi-phase signals whose phases having been respectively changed into the reference phases, and an updating unit updating, using Fourier coefficients obtained by the Fourier transform unit, the error coefficients respectively corresponding to the Fourier coefficients. The updating unit updates the error coefficients if a regression error in the regression performed by the regression unit satisfies a predetermined condition.06-09-2011
20100158090CARRIER RECOVERING APPARATUS AND CARRIER RECOVERING METHOD - A carrier recovering apparatus, in which degradation of the demodulation performance caused when a pilot signal cannot be normally received is suppressed, includes a rotation calculator for multiplying a baseband signal and an oscillation signal and outputting a multiplied signal; a pilot signal extractor for extracting a pilot signal from the signal output from the rotation calculator; an error detection controller for outputting a phase error between the pilot signal and a reference signal as a value restricted within a given range; a loop filter for smoothing the phase error output from the error detection controller and outputting the smoothed phase error; and a variable frequency oscillator for generating a signal in accordance with the output of the loop filter and outputting the generated signal as the oscillation signal.06-24-2010
20100195706SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD - A signal processing circuit for compensating for an I/Q amplitude mismatch in which the amplitudes of I- and Q-components of output signals of a quadrature modulator are unequal to or for compensating for an I/Q phase mismatch in which the phase difference between the I- and the Q-components of output signals of the quadrature modulator deviates from 90 degrees. The signal processing circuit comprises an I/Q mismatch compensating part that corrects the amplitude or phase of an input signal based on the compensation amount for compensating for an I/Q amplitude mismatch or an I/Q phase mismatch and that inputs the corrected signal into a quadrature modulator; a test signal generating part that sequentially generates and inputs two sets of combined I- and Q-components of a test signal, which is an AC signal, to the I/O mismatch compensating part; a detector that determines an amplitude of the envelope of an output signal of the quadrature modulator; a filter that passes those ones of output signals of the detector which have frequencies equal to or lower than a cutoff frequency; and a control part that derives an amplitude or phase compensation amount of the I/Q mismatch compensating part such that the output values of the filter at the time of generating the two respective sets of test signals are equal to each other, the control part then inputting the derived amplitude or phase compensation amount into the I/Q mismatch compensating part.08-05-2010
20110051791Methods and Systems for Calibrating for Gain and Phase Imbalance and Local Oscillator Feed-Through - Methods and systems for calibrating a transmitter with I/Q imbalance and local oscillator feed-through include generating a test tone, frequency up-converting the test tone, monitoring one or more features of the up-converted test tone, and adjusting one or more features of the transmitter in response to the monitoring. The monitoring optionally includes monitoring a beating of the envelope of the up-converted test tone. In an embodiment, a first harmonic of the up-converted test tone is monitored for local oscillator feed-through (LOFT). Alternatively, baseband data inputs to the transmitter are disabled, and LOFT is measured by measuring power at the transmitter output. A second harmonic of the up-converted test tone is monitored for gain and phase imbalances. The adjusting optionally includes adjusting a gain imbalance, adjusting a phase imbalance, and/or adjusting a DC offset. The adjusting optionally includes an iterative refinement process.03-03-2011
20110188559REDUCING PHASE ERRORS ON A COMMUNICATION DEVICE - A communication device that is configured for reducing phase errors is described. The communication device includes a processor and instructions stored in memory. The communication device calculates a sum channel in the frequency domain, estimates one or more impulse responses and isolates an impulse response for one or more wireless communication devices. The communication device also calculates a phase error for each wireless communication device and reduces the phase error for each wireless communication device.08-04-2011
20090175325SYSTEM FOR MEASURING AN EYEWIDTH OF A DATA SIGNAL IN AN ASYNCHRONOUS SYSTEM - An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.07-09-2009
20090003424Ic Testing Methods and Apparatus - A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (01-01-2009
20080317109CHARACTERIZING NON-COMPENSABLE JITTER IN AN ELECTRONIC SIGNAL - One embodiment of the present invention processes a signal of interest through an optional reference channel, combines the resulting signal with white noise, and then processes the noisy signal through a reference receiver. Two metrics are calculated from the results of that processing: Non-Compensable Data-Dependent Jitter (NC-DDJ) and Enhanced Transmitter and Waveform Dispersion Penalty (Enhanced TWDP). Within the reference receiver, a variable delay module sweeps the eye opening defined by the noise-free samples of the signal of interest and determines the transition points (i.e., edges) of the eye opening. Those transition points are compared to the Unit Interval to yield NC-DDJ. Further, the signal-to-noise ratio (SNR) of the noisy samples of the signal of interest is compared to the SNR of an ideal receiver (i.e., matched filter) driven by an ideal transmitter via an ideal channel with additive white Gaussian noise n(t) to yield Enhanced TWDP.12-25-2008
20090161743INTEGRATED COMPACT EYE PATTERN ANALYZER FOR NEXT GENERATION NETWORKS - A portable hand-held battery powered eye pattern analyzer is provided that can analyze signal quality of a high speed digital communication network. The system is 10 times smaller in volume and 4 times lighter than the bench-top equivalent instruments. The system includes a housing containing a display, keypad, power supply, battery pack, and RF sampler board along with connections for electrical inputs, optical inputs, clock signal inputs, and clock recovery signal inputs. The sampler circuit board can support connections, such as a USB plug for attachment to a personal computer. The RF sampler board contains the following elements: (1) A dual sampler for two-channel electrical inputs. (2) An Optical-to-Electrical O/E conversion module. (3) A clock recovery unit (CRU) module to recover the clock from the electrical or optical pulse pattern signal. (4) A trigger circuit that accepts an input clock and uses that clock to trigger the sampling of the data signal. (5) A PRBS generator that could be used as stimulus for testing high speed devices, and (6) A controller such as an FPGA that processes the sampled signals and provides statistical analysis along with eye patterns to a display as controlled using the keyboard.06-25-2009
20120039378CONVERTER AND CONVERTER CONTROL METHOD - Techniques are generally described for a converter including a PLL and a pulse deleting circuit. The pulse deleting circuit is configured to delete a pulse from one of the inputs to the PLL when a filtered output in the PLL falls below a first reference level and an unlocked state of the PLL is detected in response to a phase lag of one of the first and second pulse inputs with respect to the other. The pulse deleting circuit may also be configured to delete one pulse of the other of the first and second pulse inputs when the filtered output exceeds a second reference level and the unlocked state of the PLL is detected in response to a phase lead of the one of the first and second pulse inputs with respect to the other.02-16-2012
20080267274Periodic Jitter (PJ) Measurement Methodology - Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.10-30-2008
20090190643CARRIER PHASE INDEPENDENT SYMBOL TIMING RECOVERY METHODS FOR VSB RECEIVERS - The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator. It uses both in-phase and quadrature-phase component of received VSB signal, is operated at twice of a symbol frequency F, and guarantees consistent symbol timing error signal resulting in the improvement of receiver's performance.07-30-2009
20090196334System and Method for In-Phase/Quadrature-Phase (I/Q) Mismatch Measurement and Compensation - A system for determining in-phase and quadrature-phase mismatch in a multiple-input, multiple-output (MIMO) communication architecture includes at least one transmitter coupled to at least one receiver and an in-phase (I) signal, quadrature-phase (Q) signal mismatch element configured to receive I and Q signal components over at least one communication channel, the I/Q signal mismatch element also configured to provide a signal representing gain imbalance, a signal representing quadrature error and a signal representing I/Q offset.08-06-2009
20120014427Methods and Apparatus for Determining a Phase Error in Signals - An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signals. The input signals have a common phase error. The phase error determination circuit receives the sampled signals from the samplers. The phase error determination circuit generates a representation of the common phase error of the input signals in response to sampled signals received in a set-up mode in which the samplers sample respective input signals having a common bit pattern. The periodic signal generators generate the periodic signals differing in phase from one another by defined phase differences in the set-up mode and subject the periodic signals to a common phase shift in a normal mode in response to the representation of the common phase error. The common phase shift matches the common phase error of the input signals.01-19-2012
20120300826TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.11-29-2012
20120300825SIGNAL GENERATOR, SIGNAL GENERATING SYSTEM, AND SIGNAL GENERATING METHOD - To provide a signal generator, a signal generating system, and a signal generating method capable of repeatedly generating an arbitrary waveform and making the phases of the head and tail of the generated waveform continuous with each other, without changing the frequency of the waveform. A signal generator (11-29-2012
20120155527Common mode noise reduction within differential signal - A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal06-21-2012
20110103451System for Independently Modifying Jitter and Noise Components in a Signal Measurement Device - A digitizing instrument is used for modifying pattern data and jitter and noise components of a communication signal. In a typical implementation, the midpoints of a rising edge slope and horizontal portion of the communication signal are determined and multiple digital data records are acquired at the midpoints. The data sample records are transformed to frequency components and the random jitter and noise, and periodic jitter and noise components are determined. A correlated pattern data and the jitter and noise components are matrix elements in a simulated signal channel having communication system elements. Each correlated pattern data and jitter and noise component may be modified for each of the communication system element. The selectively modified correlated pattern data and jitter and noise components are combined to produce a modified communication signal that is displayed as a numeric table, eye diagram or bit error rate presentation.05-05-2011
20100091828Digital Phase Feedback for Determining Phase Distortion - A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information.04-15-2010
20090110042Determining a bit error rate (BER) using interpolation and superposition - In one embodiment, the present invention includes a method for receiving a jitter profile and a step response of a channel coupled between a transmitter and a receiver and a bit pattern to be transmitted, transmitting the bit pattern along the channel from the transmitter to the receiver with the jitter profile and the step response, receiving the bit pattern at the receiver and converting the bit pattern to a data stream by interpolating the step response according to a jitter of a current bit to obtain a jittery step response, superposing the jittery step response onto the data stream, calculating the jitter at each transition bit of the bit pattern by determining a time difference between actual and ideal crossing points, incrementing a jitter distribution function with the jitter, and generating a timing curve for the channel using the jitter distribution function. Other embodiments are described and claimed.04-30-2009
20100246655JITTER MEASURING APPARATUS - It is an object of the invention to correctly display the waveform of a demodulation signal with a single apparatus. A jitter demodulator which demodulates a jitter component of a digital signal input from the outside, a jitter amount detector which detects the amplitude value of a demodulation signal output from the jitter demodulator, an interpolator which measures a period of the demodulation signal output from the jitter demodulator and interpolates the demodulation signal processing with a rate corresponding to the measured period, a display unit, and a display control section which displays on the display unit the value detected by the jitter amount detector and a waveform of the demodulation signal interpolated by the interpolator are provided in a single housing.09-30-2010
20120213266METHODS AND APPARATUSES OF CALIBRATING I/Q MISMATCH IN COMMUNICATION CIRCUIT - A method and apparatus of calibrating I/Q mismatch of a communication circuit is disclosed. The disclosure employs I/Q test signals respectively including different frequency components to calibrate the frequency-dependent I/Q mismatch existing in the communication system.08-23-2012
20120250750METHOD AND SYSTEM FOR RELIABLE CFO AND STO ESTIMATION IN THE PRESENCE OF TUNER INDUCED IMPAIRMENT - A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.10-04-2012
20080205502APPARATUS FOR MEASURING IQ IMBALANCE - The present general inventive concept relates to apparatuses and/or methods for measuring an IQ imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.08-28-2008
20120213265METHOD AND CIRCUIT OF CLOCK AND DATA RECOVERY WITH BUILT IN JITTER TOLERANCE TEST - A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.08-23-2012
20080298448METHOD AND APPARATUS FOR MEASURING SUBJECTIVE ASSESSMENT OF DIGITAL VIDEO IMPAIRMENT - A method and system for using key performance indicators of a transport channel to determine key quality indicators associated with information transported there through.12-04-2008
20120320960Method, Device and System for Clock Dejitter - The present invention discloses a clock dejitter method comprising: a data sending adapter module inputting data with a system clock and using a sending clock to send data; a clock dejitter module associating the system clock with the sending clock of the data sending adapter module using; and the clock dejitter module tracking variations in the system clock and a data enable signal reflecting data sending state by referring to the system clock, and dynamically generating the sending clock varying with the data sending state. The present invention also discloses a clock dejitter apparatus and a data transmission system. The present invention greatly improves the free scheduling processing ability of services and reduces the bit error rate of data transmission while increasing efficiency of large capacity data switch transmission by dynamically adjusting the sending clock.12-20-2012
20100232489FAST SERDES I/O CHARACTERIZATION - A system and method to perform automatic testing of a device using Design-for-Test functionality built-in a pair of serializer/deserializer (SERDES) of the device to perform I/O characterization with respect to clock jitter in a self-test mode. Performance of a SERDES operating with jitter injected clock signal is characterized by forming a self-test loop-back configuration with another SERDES operating with a clean clock signal where the clean clock signal and the jitter injected clock signal are supplied by a simplified tester.09-16-2010
20120087403COMMUNICATION APPARATUS FOR CONTINUOUS PHASE MODULATION SIGNAL - A communication apparatus for a continuous phase modulation signal. The communication apparatus includes a first processing unit configured to generate first information of the continuous phase modulation signal using first symbol data; a symbol converting unit configured to convert the first symbol data into second symbol data or convert the second symbol data into the first symbol data; a symbol storage unit configured to store the second symbol data; a second processing unit configured to second information of the continuous phase modulation signal using the second symbol data stored in the symbol storage unit; a third processing unit configured to generate third information of the continuous phase modulation signal using a modulo operation of an integer related to a modulation index; and an output unit configured to add an output from the third processing unit and an output from the first processing unit and generate the continuous phase modulation signal.04-12-2012
20120087402IN-SYSTEM METHOD FOR MEASUREMENT OF CLOCK RECOVERY AND OSCILLATOR DRIFT - Various embodiments relate to an in-system measurement of clock signals in a communications circuit. A circuit may include a central processing unit and at least one phase error counter (PEC) that uses a measurement clock to determine the accuracy of a target signal. In some embodiments, the PEC may include a counter that compares a clock signal produced by a reference oscillator with the signal of the measurement clock by generating an oscillator phase error based the measured difference during a target period. In some embodiments, the PEC may measure the performance of a clock recovery module by measuring a difference between a produced recovered clock signal and the measurement clock signal, which may be the clock recovery phase error between the two signals. The CPU may also use the measured phase errors to determine other values related to the target signal(s).04-12-2012
20130170531SELF-CORRECTING MULTIRATE FILTER - A system includes a polyphase multirate filter and a controller which, responsive to detecting a data stream: measures a current phase relationship between a current resampling filter input clock signal and a current multirate output clock signal; identifies, based on a mapping of the measured phase relationship within a pre-generated quantized mapping table, an initial polyphase filter coefficient index corresponding to the measured phase relationship; selects, based on the initial polyphase filter coefficient index identified, a corresponding polyphase filter component from within the multirate filter; configures the multirate filter to pass data from the data stream through the corresponding polyphase filter component to generate an initial output data sample; updates the initial polyphase filter coefficient index to a calculated next polyphase filter coefficient index value, in response to a request for generation of a next output data sample; and self-corrects the multirate filter responsive to a pre-identified error condition.07-04-2013
20080247451MEASUREMENT APPARATUS, MEASUREMENT METHOD, TEST APPARATUS, ELECTRONIC DEVICE, AND RECORDING MEDIUM - Provided is a measurement apparatus that measures jitter occurring in a data converter, including a measurement signal generating section that generates a measurement signal having a substantially constant period; a jitter injecting section that injects jitter of a deterministic signal having a predetermined jitter period into the measurement signal, and that inputs the resulting signal to the data converter; a jitter measuring section that measures a jitter string of a digital signal output by the data converter; and an extracting section that extracts data of the jitter string according to the jitter period of the jitter injected by the jitter injecting section.10-09-2008
20130142242BOUNDED UNCORRELATED SIGNAL IMPAIRMENT DECONVOLUTION FOR TOTAL SIGNAL IMPAIRMENT EXTRAPOLATION - Methods and systems are described for analyzing signal impairments using a test and measurement instrument. A method may include decomposing aggregate signal impairments into signal impairments that are correlated and uncorrelated to an acquired data pattern. The uncorrelated signal impairments may be further decomposed into periodic signal impairments (e.g., PJ) and non-periodic uncorrelated signal impairments. A PDF of the non-periodic uncorrelated signal impairments may be mathematically integrated, thereby producing an estimated cumulative distribution function (CDF) curve. Random signal impairments may be estimated as an unbound Gaussian distribution. The CDF curve of the non-periodic uncorrelated signal impairments and the unbound Gaussian distribution may be plotted in Q-space on a display device. Non-periodic bounded uncorrelated signal impairments (e.g., NP-BUJ) PDF may then be isolated. Bounded uncorrelated signal impairments PDF may then be synthesized. Complete uncorrelated signal impairments PDF may be synthesized. A synthesis of the decomposed components can be performed at a user-defined bit error rate to generate the total estimated jitter (e.g., TJ@BER or TN@BER).06-06-2013
20130142243TRANSMITTING DEVICE, TRANSMITTING METHOD, INTEGRATED CIRCUIT, AND PROGRAM - A transmitting device can suppress degradation of the video quality and determine a proper transmission rate, and include a transmitting unit that transmits a communication packet to a receiving device, a receiving unit that receives a feedback packet, which is a response signal corresponding to the communication packet, from the receiving device, a detecting unit that detects a change of a reception interval of the feedback packet, and a transmission rate determining unit that decreases a transmission rate at which the transmitting unit transmits the communication packet in the case where the change of the reception interval is detected, and increases the transmission rate on the basis of an amount of change of a travelling speed of at least either the transmitting device or the receiving device before and after the decrease in the transmission rate.06-06-2013
20130177061Fast Acquisition Of Frame Timing And Frequency - Modern digital signals include framing. A known sequence of transmission symbols (Unique Word (UW)) included in the transmitted signal may be used by a receiver for framing synchronization. A receiver configured to receive such a signal may be configured to detect the UW even when the signal is received with some frequency uncertainty (e.g. offset or error). A method is presented for fast acquisition of symbol and/or frame timing of a signal, including in the presence of frequency uncertainty. In some embodiments, the presented method may be used for determining a frequency offset of the received signal and a location of a unique word (UW) within a frame of the received signal, wherein said determining is based on a two-dimensional search map.07-11-2013
20130170532APPARATUS AND METHOD FOR PHASE NOISE SELF-TEST - An integrated circuit (IC) having a radio receiver configured to perform a jitter self-test is disclosed. In one embodiment, an IC includes a radio receiver and a pulse generator. The pulse generator is configured to generate a pulse train based on a first periodic signal received from the radio receiver. The radio receiver is configured to use the pulse train to determine an amount of phase noise generated by a local oscillator of the radio receiver. The pulse generator and the radio receiver are implemented on the same IC die.07-04-2013
20130094560COMMUNICATION APPARATUS AND COMMUNICATION METHOD - A communication apparatus including: a receiver to receive signals including reference signals at each of a plurality of different reception intervals; and a processor to estimate phase differences between the signals based on the reference signals, to determine a plurality of phase difference candidates for each of the reception intervals based on the phase differences, to select, from among a plurality of combinations of the phase difference candidates for the reception intervals, a combination of the phase difference candidates between the signals, and to estimate a frequency deviation of the signals based on the phase difference candidates included in the combination.04-18-2013
20130101006Clock Masking Scheme In A Mixed-Signal System - A method in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals where the digital clock signals and the analog clock signals are digitally controlled includes generating one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals; combining the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and applying the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals.04-25-2013
20130114660EXTRACTING PARAMETERS FROM A COMMUNICATIONS CHANNEL - A method for extracting a parameter of a communication channel from a channel estimate that characterises the communication channel in terms of a frequency response over time. The method includes generating a set of feature identifiers that characterise features of the channel, for example energy peaks or troughs and determining the parameter, for example time delay of a multipath signal or frequency offset of a multipath signal, dependent on the feature identifiers. Methods using the parameter are also described including methods to estimate the environment.05-09-2013
20110268169EQUALIZATION APPARATUS AND BROADCASTING RECEIVING APPARATUS - An equalization apparatus configured to receive a digitally modulated single carrier signal and perform multipath equalization in a frequency domain, including a frequency domain conversion unit which converts a received signal to a frequency domain signal, a channel estimation unit configured to estimate a channel response in a frequency domain from the received signal, an equalization weight calculation unit which calculates an equalization weight from the channel estimate value in the frequency domain, an equalization filter which receives the frequency domain signal from the frequency domain conversion unit and the equalization weight from the equalization weight calculation unit and performs equalization processing and a time domain conversion unit which converts the frequency domain signal from the equalization filter to a time domain signal, wherein the equalization weight calculation unit includes a power calculation unit, a power value correction unit, a complex conjugate generator and a divider.11-03-2011
20080198910Noise Estimation In Wireless Communication Systems - The invention relates to background noise estimation in wireless communication systems with power control. The total received interference is measured at a receiving unit. Thereafter, a predetermined noise signal is injected at the receiving unit and the total received interference is measured again, preferably when the power control of the system has responded to the noise injection. The background noise is calculated based on the injected predetermined noise signal and the interference measurements before and after the noise injection.08-21-2008
20110235694Apparatus and Method for Generating a Waveform Test Signal Having Crest Factor Emulation of Random Jitter - A signal generating device has a display and a central processing unit for setting parameters for a serial data pattern and parameters for deterministic and random jitter impairments, and a displacement crest factor emulation impairment to be applied to the serial data pattern. A waveform record file is generated using the serial data pattern parameters, the impairment parameters for the deterministic jitter and random jitter, and the displacement crest factor emulation impairment. The displacement crest factor emulation impairment is selectively positioned in the impaired serial data pattern. A waveform generation circuit receives the waveform record file and generates an impaired serial data pattern analog output signal based on the serial data pattern, deterministic and random jitter impairments, and the displacement crest factor emulation impairment with the displacement crest factor emulation impairment being selectively positioned in the impaired serial data pattern analog output signal.09-29-2011
20120275507Methods And Apparatus For Compensating For Propagation Delays In Coordinated Multi-Point Transmission - Systems and techniques for communication using coordinated multi-point transmission. In one embodiment, an apparatus comprises at least one processor and a memory storing a set of computer instructions, configured. The processor is configured to cause the apparatus to determine a linear phase variation between at least first and second transmissions from first and second transmission points based at least in part on a propagation delay difference between the first and second transmissions, and transmit the phase variation information for at least the first and the second transmissions. An apparatus configured to operate as a transmission point in a network receives linear phase variation information indicating phase variation experienced by at least one user equipment resulting from a propagation delay difference between at least the apparatus and a second apparatus operating as a second transmission point and manages transmission so as to control phase variation resulting from the propagation delay difference.11-01-2012
20100316105APPARATUS FOR MEASURING JITTER TRANSFER CHARACTERISTIC - An apparatus for rapidly measuring jitter transfer characteristics is provided. A modulation signal generator generates a modulation signal M including a plurality of sinusoidal components having known amplitudes m12-16-2010
20130195162SYNCHRONIZATION PROCESSING APPARATUS, SYNCHRONIZATION PROCESSING METHOD AND PROGRAM - A synchronization processing apparatus includes: a jitter amount calculating section that calculates a jitter amount on the basis of a synchronization packet including time information; and a frequency synchronization determining section that calculates an accumulation value of the jitter amounts, and determines whether frequency synchronization is present from the accumulation value.08-01-2013

Patent applications in class Phase error or phase jitter