Class / Patent application number | Description | Number of patent applications / Date published |
365239000 | Sequential | 7 |
20080267001 | Protocol Enhancement for PCI Express - In a method for enabling a root device to access a plurality of memory locations in an address space in an endpoint device, a first access is sent to the endpoint device by transmitting a first header and a first address. The header includes a continue bit that is set at a first state that indicates that the first access is accessing a selected first memory location that the address is being sent. A first memory location is accessed when the continue bit is in the first state. A second access, which accesses accessing a second memory location that is contiguous to an immediately previously accessed memory location, is sent to the endpoint device by transmitting a header that includes a continue bit set to a second state and not sending an address. The second memory location corresponds to the first address plus a predetermined address offset. | 10-30-2008 |
20090141582 | METHOD FOR RECORDING DATA USING NON-VOLATILE MEMORY AND ELECTRONIC APPARATUS THEREOF - A method for recording data using a non-volatile memory and an electronic apparatus thereof are provided. In the present method, a set of input data is provided. Then, a data structure of the input data is transformed into a bitmapping data structure. Afterwards, the input data is written sequentially into the non-volatile memory using at least one bit as a basic unit of modification. A total number of bits being modified is then calculated, so as to obtain information needed by the system. Therefore, a minimal memory space is used to record most information, so as to reduce the times for erasing the non-volatile memory and increase the life time of the non-volatile memory. | 06-04-2009 |
20090245013 | Sequential storage circuitry for an integrated circuit - Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry. More particularly, the output circuitry receives a second control signal derived from the first control signal, which causes the output circuitry to generate as said output data value an inverted version of the internal data value in the event that the input circuitry generated as the internal data value an inverted version of the input data value, and otherwise generates as the output data value the internal data value. Such a mechanism provides a simple and effective technique for annealing stress build-up within the storage structure, as for example may arise as a result of the NBTI phenomenon. The technique of the present invention can be also be used for other purposes, for example to improve security of the data held within such a sequential storage circuitry. | 10-01-2009 |
20110310692 | SEQUENTIAL-WRITE, RANDOM-READ MEMORY - In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array. | 12-22-2011 |
20140362657 | FLEXIBLE IDENTIFICATION TECHNIQUE - A shared-signaling multi-device memory system is capable of changing between addressing modes without the multi-device memory being required to undergo a power cycle. First and second registers of a memory device are set to both contain first address-identification information in response a first address-assignment command that is received a power cycle. The first register is set to contain second address-identification information in response a second address-assignment command that is received subsequently to the first address assignment command. Depending on the value of the second address-identification information, the memory device is configured in an individual-device-addressing mode or a parallel addressing mode without a power cycle. The first register can be reset to the first address-identification information contained in the second register in response to an address-restore command without a power cycle. A corresponding method is also disclosed. | 12-11-2014 |
365240000 | Using shift register | 2 |
20090154286 | N-BIT SHIFT REGISTER CONTROLLER - A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of âkâ bits. The controller only requires information regarding the value of the number âkâ and the pre-programmed stop code in order to control any number of bits in a shift chain. | 06-18-2009 |
20100290306 | CIRCUIT AND METHOD FOR SHIFTING ADDRESS - A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands. | 11-18-2010 |