Class / Patent application number | Description | Number of patent applications / Date published |
365230080 | Including particular address buffer or latch circuit arrangement | 52 |
20080198684 | Semiconductor memory integrated circuit - A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit. | 08-21-2008 |
20080205187 | DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT - A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller. | 08-28-2008 |
20080219082 | NONVOLATILE SEMICONDUCTOR MEMORY - Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte. | 09-11-2008 |
20080239864 | MEMORY ACCESS CIRCUIT - A memory access circuit is provided. The memory access circuit includes a latch circuit, a feedback reset circuit, and a gate latch circuit. The latch circuit receives a high level input signal and outputs a first signal. The feedback reset circuit generates a second signal and a reset signal according to the first signal. The gate latch circuit generates a pre-charge signal and an enable signal according to the first signal and the second signal. The memory is accessed according to the pre-charging signal and the enable signal. | 10-02-2008 |
20080247261 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in response to the latch of a normal command by the command latch circuit, and selects the mode latch circuit in response to the latch of an adjustment command. With this arrangement, the mode signal can be dynamically received without performing a mode register set. Therefore, when a sufficiently large latch margin of the mode latch circuit is secured, there is no risk that it becomes impossible to input the mode signal. | 10-09-2008 |
20080285373 | ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS - An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal. | 11-20-2008 |
20080285374 | Semiconductor memory device - A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode. | 11-20-2008 |
20090003121 | Column address control circuit capable of selectively enabling sense amplifier in response to column addresses - A column address control circuit comprises a control unit for outputting a control signal in response to a DDR mode signal and a first signal, and an address counting unit configured to receive a start column address and output a start column address in response to the control signal. The first signal is a burst read single write mode signal. The control signal is activated when the first signal is activated in a DDR mode. The control unit includes a first logic unit for performing an AND operation of the DDR mode signal and the first signal, and a second logic unit for performing an OR operation of an output signal of the first logic unit and a SDR mode signal. | 01-01-2009 |
20090003122 | Address synchronous circuit capable of reducing current consumption in dram - An address synchronous circuit comprises an address control signal generating unit for generating a control signal in response to operation mode signals of a semiconductor memory and an internal clock signal, and an address synchronous unit for controlling output of an address which is buffered in accordance with a clock enable signal, in response to the control signal. | 01-01-2009 |
20090010091 | ADDRESS COUNTER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND DATA PROCESSING SYSTEM - An address counter includes FIFO units and first to third command counters that controls the groups. In the FIFO units, latch circuits including input gates and output gates are connected in parallel. The first command counter conducts any one of the input gates in response to a first internal command; the second command counter conducts any one of the output gates in response to a second internal command; and the third command counter conducts any one of the output gates in response to a third internal command. Thereby, the same address signals can be outputted successively at a plurality of timings, and thus, a circuit scale of the address counter can be reduced. | 01-08-2009 |
20090027993 | Semiconductor memory device and data storage method - According to an aspect of the present invention, there is provided a semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, including: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information. | 01-29-2009 |
20090086564 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device. | 04-02-2009 |
20090109790 | Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit - An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed. | 04-30-2009 |
20090116330 | Semiconductor memory device using bus inversion scheme - A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block. | 05-07-2009 |
20090141581 | Semiconductor Memory Arrangement and System - A semiconductor memory arrangement includes a control device with a first port and a second port, the first and second port being adapted to receive command and address signals, a first buffer device being coupled to the first port, a second buffer device being coupled to the second port and a plurality of memory units at least including a first group of memory units and a second group of memory units. | 06-04-2009 |
20090154284 | SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR INTERCONNECTION IN A RING TOPOLOGY - A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device. | 06-18-2009 |
20090207683 | INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROLLING METHOD THEREOF - Disclosed is an input circuit of a semiconductor memory apparatus. The input circuit includes a first buffer and a second buffer. The first buffer has an input terminal connected with a first input pin for receiving a control signal used in a multi-control mode for controlling an entire memory area by dividing the entire memory area, and an output terminal having a first level according to a control mode signal. The second buffer has an input terminal connected with a second input pin for receiving one of plural signals used in a single control mode for controlling the entire memory area without dividing the entire memory area, and an output terminal having a second level according to the control mode signal. | 08-20-2009 |
20090231947 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING ADDRESS CONTROL CIRCUIT - A semiconductor IC in which a least significant bit of an external address signal is fixed to a signal level, the semiconductor integrated circuit includes an address control circuit configured to produce a carry signal, when a test mode signal is activated, in response to a column command signal and output an address signal, which is sequentially increased from an initial internal address signal, by latching the external address signal as the initial internal address signal and combining the latched initial internal address signal and the carry signal. | 09-17-2009 |
20090245012 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal. | 10-01-2009 |
20090268544 | MEMORY DEVICE AND METHOD HAVING PROGRAMMABLE ADDRESS CONFIGURATIONS - A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register. | 10-29-2009 |
20090290445 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER - A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits for sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed. | 11-26-2009 |
20090296513 | Semiconductor device and manufacturing method thereof - A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit. | 12-03-2009 |
20100039877 | EXTERNAL CLOCK TRACKING PIPELINED LATCH SCHEME - A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second command latch input, and a command latch output, the first command latch input to couple to the command decoder output, and the second command latch input to couple to a write command output of an internal clock control generator; and a command register including a first command register input and a second command register input, the first command register input to couple to the command latch output, and the second command register input to couple to an internal latch command output of the internal clock control generator. Additional apparatus, systems, and methods are disclosed. | 02-18-2010 |
20100118639 | SEMICONDUCTOR MEMORY APPARATUS - A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering an external data in accordance with the second external reference voltage. | 05-13-2010 |
20100157717 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND - The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode. | 06-24-2010 |
20100165780 | DYNAMIC RANDOM ACCESS MEMORY WITH SHADOW WRITES - Methods and apparatus are disclosed for reducing write-to-read turnaround times using shadow writes in memory controllers and in DRAM. Embodiments of controllers including shadow write control logic may, in response to receiving a write request, issue an external write column address strobe (CAS) to DRAM to latch a valid write CAS address, and assert a set of write data values to be stored in a set of DRAM locations corresponding to the write CAS address. After asserting the write CAS and prior to asserting the complete set of write data values, such memory controllers may, in response to receiving a read request, issue an external read CAS to DRAM to indicate a valid read CAS address. A set of read data values from a second set of DRAM locations corresponding to the read CAS address, are received with reduced turnaround time after asserting the complete set of write data values. | 07-01-2010 |
20100177587 | CIRCUIT AND METHOD FOR CONTROLLING DRAM COLUMN-COMMAND ADDRESS - The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address. | 07-15-2010 |
20100202242 | SEMICONDUCTOR MEMORY DEVICE USING BUS INVERSION SCHEME - A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block. | 08-12-2010 |
20100214865 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal. | 08-26-2010 |
20100246310 | Address converting circuit and semiconductor memory device using the same - A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group, a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group, and a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group. | 09-30-2010 |
20100278004 | ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS - An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal. | 11-04-2010 |
20110085406 | CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION FOR MEMORY MODULE - A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module. | 04-14-2011 |
20110228625 | WRITE COMMAND AND WRITE DATA TIMING CIRCUIT AND METHODS FOR TIMING THE SAME - Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory. | 09-22-2011 |
20110242928 | ADDRESS DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses. | 10-06-2011 |
20120008452 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND - The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode. | 01-12-2012 |
20120014204 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABLITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 01-19-2012 |
20120033523 | INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROLLING METHOD THEREOF - Disclosed is an input circuit of a semiconductor memory apparatus. The input circuit includes a first buffer and a second buffer. The first buffer has an input terminal connected with a first input pin for receiving a control signal used in a multi-control mode for controlling an entire memory area by dividing the entire memory area, and an output terminal having a first level according to a control mode signal. The second buffer has an input terminal connected with a second input pin for receiving one of plural signals used in a single control mode for controlling the entire memory area without dividing the entire memory area, and an output terminal having a second level according to the control mode signal. | 02-09-2012 |
20120147690 | MEMORY ACCESSING DEVICE - A memory accessing device includes a generator which generates K (K: an integer equal to or more than two) of address coefficients corresponding to a first mode whereas generates L (L: an integer more than K) of address coefficients corresponding to a second mode. A first converter converts each value of the address coefficients generated by the generator into a value of 1/M (M: an integer equal to or more than two). A creator creates address information based on the address coefficients generated by the generator corresponding to the first mode whereas creates address information based on address coefficients converted by the first converter corresponding to the second mode. An outputter outputs the address information created by the creator in order to access a memory provided with a plurality of addresses each of which has a bit width equivalent to any one of N bits and N/M bits. | 06-14-2012 |
20120147691 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal. | 06-14-2012 |
20130083619 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a first operation circuit configured to generate addition data by adding a column address and a page address and output a remainder obtained by dividing the addition data by a set value as seed data, a mask data output circuit configured to output mask data corresponding to the respective seed data, and a second operation circuit configured to generate random data by performing a logic operation on the mask data and program data corresponding to the column and page addresses. | 04-04-2013 |
20130286764 | CIRCUIT AND METHOD FOR ADDRESS TRANSITION DETECTION - A new address transition detection (ATD) circuit for use on an address bus having a plurality of address signal lines comprises a first circuit for each address signal line and a second circuit. The first circuit has a first input, a second input and an output. The first input is coupled to an address signal line. The second input is coupled to an ATD signal. The first circuit saves the current level of the first input in response to an ATD pulse on the ATD signal and generates a change signal at its output by comparing the current level and the saved level of the first input. The second circuit has an input and an output. The second circuit receives on its input the change signal from the first circuit. In response, the second circuit generates the ATD pulse on the ATD signal at its output. | 10-31-2013 |
20140003184 | REALIGNMENT OF COMMAND SLOTS AFTER CLOCK STOP EXIT | 01-02-2014 |
20140064014 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF OPERATING USING THE SAME - A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command. | 03-06-2014 |
20140071783 | MEMORY DEVICE WITH CLOCK GENERATION BASED ON SEGMENTED ADDRESS CHANGE DETECTION - A memory device comprises a memory array and associated control circuitry. The control circuitry comprises a clock generator configured to generate a clock signal for controlling timing of at least one of a read operation and a write operation directed to the memory array. The clock generator comprises a plurality of sets of address change detection circuits. The sets are configured to generate respective output signals as a function of respective subsets of address bits of an address signal identifying an address in the memory array. The clock generator further comprises logic circuitry coupled to the sets of address change detection circuits and configured to receive the respective output signals therefrom and to generate the clock signal as a function of said output signals. | 03-13-2014 |
20140219044 | MEMORY MODULE AND MEMORY SYSTEM COMPRISING SAME - A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal. | 08-07-2014 |
20140286119 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 09-25-2014 |
20140334242 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF OPERATING USING THE SAME - A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command. | 11-13-2014 |
20150009773 | VOLUME SELECT FOR AFFECTING A STATE OF A NON-SELECTED MEMORY VOLUME - Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can include selecting the targeted memory volume of the memory volumes and putting at least a portion of a non-selected memory volume of the memory volumes in a particular state based, at least in part, on a previous state of the non-selected memory volume and/or a portion of an address associated with the select command. | 01-08-2015 |
20150009774 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The semiconductor device includes an internal command generator and an internal address generator. The internal command generator generates first and second command latch signals from first and second internal clock signals in response to an external control signal and latches a command signal in response to the first and second command latch signals to generate a synthesized internal command signal. The internal address generator generates first and second address latch signals from the first and second internal clock signals in response to the external control signal and latches an address signal in response to the first and second address latch signals to generate a synthesized internal address signal. | 01-08-2015 |
20150098295 | APPARATUSES AND METHODS INCLUDING SELECTIVELY PROVIDING A SINGLE OR SEPARATE CHIP SELECT SIGNALS - Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a single-rank memory module by providing separate chip select signals to separately select a first memory device and a second memory device. A method may further include, subsequent to sensing that the initializing is completed, for example, providing a single chip select signal to simultaneously select the first memory device and the second memory device. | 04-09-2015 |
20160064057 | ADDRESS ALIGNER AND MEMORY DEVICE INCLUDING THE SAME - An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal. | 03-03-2016 |
20160148672 | SEMICONDUCTOR DEVICE HAVING A REDUCED FOOTPRINT OF WIRES CONNECTING A DLL CIRCUIT WITH AN INPUT/OUTPUT BUFFER - An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance. | 05-26-2016 |