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Plural blocks or banks

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365 - Static information storage and retrieval

365230010 - ADDRESSING

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Class / Patent application numberDescriptionNumber of patent applications / Date published
365230040 Alternate addressing (e.g., even/odd) 1
20130142002Semiconductor Memory Apparatus - A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.06-06-2013
Entries
DocumentTitleDate
20130044558MEMORY DEVICE AND METHOD - A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.02-21-2013
20090196116SEMICONDUCTOR MEMORY HAVING A BANK WITH SUB-BANKS - Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks.08-06-2009
20110194370Memory Having Asynchronous Read With Fast Read Output - A memory circuit is disclosed. The memory circuit includes memory cells and asynchronous read decode logic configured to decode a received address and to select particular ones of the memory cells for reading. The read decode logic may be comprised of static, combinational logic, and thus the decoding of the received address may be conducted without the use of a clock signal or a cycle of a clock signal. Accordingly, a read operation may be conducted responsive to receiving the read address, without waiting for a subsequent clock edge. Furthermore, read output logic may also be asynchronous, and thus may provide data read from the memory cells without having to wait for a clock edge. The read output logic may include push-pull driver circuits coupled to global bit lines. The push-pull driver circuits may drive their corresponding global bit lines based on the data read from corresponding memory cells.08-11-2011
20130033954Memory Buffers and Modules Supporting Dynamic Point-to-Point Connections - A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.02-07-2013
20130077426SEMICONDUCTOR STORAGE APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed.03-28-2013
20100097878USER SELECTABLE BANKS FOR DRAM - A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected.04-22-2010
20120182822SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated.07-19-2012
20120182821MEMORY SYSTEM COMPONENTS THAT SUPPORT ERROR DETECTION AND CORRECTION - A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. The memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.07-19-2012
20130070552NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a plurality of memory blocks, first block switches configured to correspond to the respective odd-numbered memory blocks of the plurality of memory blocks and couple the word lines of the odd-numbered memory blocks and first local lines, second block switches configured to correspond to the respective even-numbered memory blocks of the plurality of memory blocks and couple the word lines of the even-numbered memory blocks and second local lines, a local line switch unit configured to selectively couple the first local lines or the second local lines and global word lines, and a high voltage generator configured to supply operating voltages to the global word lines.03-21-2013
20090109788DATA MANAGEMENT METHOD AND MAPPING TABLE UPDATE METHOD IN NON-VOLATILE MEMORY DEVICE - A data management method of a non-volatile memory device includes writing data and representing a state of the data. The state includes one of multiple possible states. A state of the multiple possible states corresponding to a final operation is determined as a valid state of the data.04-30-2009
20090303825SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first plurality of banks arranged in a first direction to form a first group of banks; a second plurality of banks arranged in the first direction to form a second group of banks, the first group of banks and the second group of banks arranged in a second direction; a first local data line arranged in the second direction to cross a bank of the second plurality of banks and to transfer input/output data; a second local data line arranged in the second direction to transfer input/output data; a global data line disposed in the first direction that crosses the second direction; and a data exchanger disposed between the second plurality of banks and the global data line for configured to controlling data exchange between the first and second local data lines and the global data line.12-10-2009
20120224447SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ACTIVATION CIRCUIT FOR SELECTIVELY ACTIVATING CIRCUIT AREAS - A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.09-06-2012
20090231945ASSYMETRIC DATA PATH POSITION AND DELAYS TECHNIQUE ENABLING HIGH SPEED ACCESS IN INTEGRATED CIRCUIT MEMORY DEVICES - An asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices which is asymmetric in terms of the delay from the array to the I/O buffers based on the position relative within a known starting address of a pre-fetch field. In accordance with the technique of the present invention, the delay is not only asymmetric in terms of its physical length, but also in the number of pipeline stages and the clocks that control them and can also be asymmetric in terms of the column address required to access each section of the array and its designated pre-fetch field.09-17-2009
20090231944MULTI-BANK BLOCK ARCHITECTURE FOR INTEGRATED CIRCUIT MEMORY DEVICES HAVING NON-SHARED SENSE AMPLIFIER BANDS BETWEEN BANKS - A multi-bank block architecture for integrated circuit memory devices which effectively reduces the total length of the datapath for a given input/output (I/O) from the memory cells in the memory array to the actual device I/O pad. In accordance with the present, a memory block in a memory device is effectively divided into two or more banks, and between these banks an additional non-shared sense amplifier band is added as a sense amplifier cannot be shared across a bank boundary. Within this multi-bank block, separate data paths are provided for the banks with the column (Y-Select) lines being common.09-17-2009
20090046534Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus - A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information.02-19-2009
20110286295Methods of Arranging L-Shaped Cell Blocks In Semiconductor Devices - Semiconductor devices are provided including a plurality of L-shaped cell blocks each including a cell array and a plurality of decoders disposed in horizontal and vertical directions of the cell array. The plurality of L-shaped cell blocks is oriented in a diagonal direction intersecting the horizontal and vertical directions. Related methods are also provided herein.11-24-2011
20130163365SEMICONDUCTOR DEVICE HAVING HIGH-VOLTAGE TRANSISTOR - A semiconductor device includes a memory cell array having a plurality of memory cells respectively coupled to first and second bit lines, page buffers, and a bit line selection circuit including a plurality of selection circuit blocks configured to couple the first or second bit lines to the page buffers. A pair of the first and second bit lines is disposed in each of the plurality of selection circuits so that first bit lines of adjacent selection circuit blocks face each other, or second bit lines of adjacent selection circuit blocks face each other.06-27-2013
20110299354MEMORY ARRAY CIRCUIT INCORPORATING MULTIPLE ARRAY BLOCK SELECTION AND RELATED METHOD - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.12-08-2011
20110205828SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACCESS SPEEDS - A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.08-25-2011
20090196117SYSTEM AND METHOD FOR MEMORY ARRAY DECODING - A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory blocks. The memory system also includes a bit line decoder and Q×M switch modules. Each Q×M switch module selectively controls access to up to J of the M memory sub-blocks of the Q memory blocks. The Q word line decoders and the bit line decoder access less than M memory sub-blocks in at least two of the Q memory blocks during one of a read and write operation. M and Q are integers greater than 1, and J is an integer greater than or equal to 108-06-2009
20090154282SEMICONDUCTOR DEVICE - A semiconductor device comprises multiple memory cell blocks including multiple memory cells for storing a predetermined amount of data. Each of the memory cell blocks having three or more inputs and three or more outputs includes two readout address decoders as to the memory cells internally, stores truth table data for outputting a desired logical value as to predetermined address input, and is configured so as to operate as a logic circuit. Also, the memory cells include two readout word lines corresponding to the two readout address decoders, and in the case of the voltage of both of the two readout word lines being applied, the data held at this time is read out from readout data lines. Further, between the memory cell blocks is connected such that the three or more outputs from one memory cell block are input to three or more other memory cell blocks.06-18-2009
20080266999SEMICONDUCTOR MEMORY DEVICE AND SYSTEM PROVIDING SPARE MEMORY LOCATIONS - A semiconductor memory device having a plurality of memory locations is presented. The plurality of memory locations includes a plurality of primary memory locations and a plurality of spare memory locations. The device includes an address decoder configured to receive a memory location address and process the address to select one of the memory locations. The device further includes control logic configured to receive control signals and process the control signals to determine whether the selected one of the memory locations is one of the primary memory locations or one of the spare memory locations, and to provide access to the selected one of the memory locations via data lines.10-30-2008
20100054072DISTRIBUTED BLOCK RAM - Memory blocks, such as the embedded memory blocks in a reconfigurable device, are connected together using shared global busses and interface circuits. The interface circuits allow the memory blocks to be selectively connected together to form depth and width expanded memory blocks, and also allow the blocks to be used as standalone blocks. The interface circuits connect the memory array within a memory block to any desired memory input and output lines that are linked on the same shared global busses, to allow use of any convenient input and output lines to access the expanded memory block. A shared global address bus allows memory blocks to broadcast address information to each other, and allows unused address inputs to be re-used for broadcasting information such as block selection information or shared column information. Flexible and configurable depth and width-expanded memory blocks are thereby created.03-04-2010
20090290444SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data. Each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of a given address so as to function as a logic circuit. The number of inputs and the number of outputs of the memory cell block is three or more, and the memory cell blocks are connected to each other so that three or more outputs from one memory cell block are input to three or more other memory cell blocks.11-26-2009
20090103389Semiconductor memory device and method of providing product families of the same - Disclosed is a semiconductor memory device including a plurality of banks, a plurality of data input/output terminals, control signal terminals, address signal terminals, and at least one or a plurality of virtual chips, each of which has the banks grouped together, thereby being operable as one independent chip. Each of the data input/output terminals are allocated in dedicated manner to the one virtual chip or one of the plurality of virtual chips. The control signal terminals and the address signal terminals are shared among the one or the plurality of virtual chips.04-23-2009
20090103388HISTOGRAM GENERATION WITH BANKS FOR IMPROVED MEMORY ACCESS PERFORMANCE - Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.04-23-2009
20100103762Memory device and method - A memory device and method may include separating alternating read and write accesses to different banks of a memory device.04-29-2010
20100061177SEMICONDUCTOR MEMORY DEVICE AND WORD LINE DRIVING METHOD THEREOF - A semiconductor memory device having a plurality of cell blocks includes: a block decoding unit configured to decode an input address for selecting a corresponding cell block to generate a block selection signal; a block information address generating unit configured to perform a logic operation on the block selection signal and an assignment address for selecting a word line to be activated within the corresponding cell block to generate a block information address activated only when the corresponding cell block is selected; and a word line driving unit configured to select a word line in response to the block information address.03-11-2010
20090003118Word line block select circuit with repair address decision unit - A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control signal and an active command signal.01-01-2009
20090168587SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having multiple banks each including multiple memory blocks arranged in column and row directions. The memory blocks are divided into multiple memory block groups each sharing a corresponding column select signal. The memory blocks belonging to the respective memory block groups are arranged adjacently in the column direction. Multiple global input/output lines are separately connected to the memory block groups of the respective banks to transfer data of the memory blocks belonging to the respective memory block groups in a time division manner.07-02-2009
20080285371WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS - A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.11-20-2008
20080239862Semiconductor memory device - The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a bank control unit for selecting one of the first group and the second group in response to a bank address to transfer an address to the selected group.10-02-2008
20090180347SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a semiconductor memory device. The semiconductor memory device includes: a first memory block including a first memory cell; a second memory block including a second memory cell; and a column decoder circuit accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line, wherein the column decoder circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell and an address for reading the second memory cell.07-16-2009
20110188335Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.08-04-2011
20090052269Charge loss compensation methods and apparatus - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.02-26-2009
20090080280Electronic memory device - An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.03-26-2009
20090097348INTEGRATED CIRCUIT INCLUDING A MEMORY MODULE HAVING A PLURALITY OF MEMORY BANKS - An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i.04-16-2009
20090231943Multi-Bank Memory Device Method and Apparatus - In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a plurality of memory bank segments physically separated from each other and from the first set of memory banks. Each memory bank segment is arranged adjacent to, and occupies less area than, one of the memory banks of the first set.09-17-2009
20090207681SYSTEMS AND DEVICES INCLUDING LOCAL DATA LINES AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices, including a device having a fin field-effect transistor with a first terminal, a second terminal, and two gates. In some embodiments, the device includes a local data line connected to the first terminal, at least a portion of a capacitor plate connected to the second terminal, and a global data line connected to the local data line by the capacitor plate.08-20-2009
20090245009256 Meg dynamic random access memory - A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.10-01-2009
20090046533Multichip system and method of transferring data therein - Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data to the second memory chip in response to local transfer information provided from the host system. The first memory chip controls the host system not to access the first and second memory chips while conducting a local transfer operation. According to the invention, since the data is able to be directly transferred between the memory chips without the host system, it enhances the efficiency of the multichip system and improves a data transfer speed.02-19-2009
20090316512BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S - The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.12-24-2009
20100149900SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ACTIVATION CIRCUIT FOR SELECTIVELY ACTIVATING CIRCUIT AREAS - A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.06-17-2010
20130215702SEMICONDUCTOR MEMORY APPARATUS, BLOCK DECODER THEREFOR, AND DECODING METHOD THEREOF - A block decoder including a first selection unit configured to receive a block address signal and output a block select signal to any one of a plurality of blocks, and a second selection unit configured to receive a high voltage and control a potential level of the block select signal according to the block address signal.08-22-2013
20100208540INTEGRATED CIRCUIT WITH MULTIPORTED MEMORY SUPERCELL AND DATA PATH SWITCHING CIRCUITRY - An integrated circuit. The integrated circuit includes a plurality of memory requesters and a memory supercell. The memory supercell includes a plurality of memory banks each of which forms a respective range of separately addressable storage locations, wherein the memory supercell is organized into a plurality of bank groups. Each of the plurality of bank groups includes a subset of the plurality of memory banks and a corresponding dedicated access port. The integrated circuit further includes a switch coupled between the plurality of memory requesters and the memory supercell. The switch is configured, responsive to a memory request by a given one of the plurality of memory requesters, to connect a data path between the given memory requester and the dedicated access port of a particular one of the bank groups addressed by the memory request.08-19-2010
20100246308SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHODS THEREOF - A semiconductor storage device and control method are provided. The semiconductor storage device includes a storage unit including a plurality of storage elements specified by addresses and divided into a plurality of blocks each corresponding to a plurality of the addresses, a write address decoding circuit that decodes a write address specifying a block to write data, a write buffer provided in a write signal path to input write data including write address to the block specified by the write address and a write buffer control unit that disables a write buffer provided in the write signal path for inputting the write data to blocks other than a block including a write address decoded by the write address decoding circuit.09-30-2010
20120140586NONVOLATILE MEMORY DEVICE HAVING STACKED TRANSISTOR CONFIGURATION - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder that selects one of the memory blocks in response to an input address and generates a first control signal and a second control signal, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors that connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal, and a plurality of ground transistors that supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction.06-07-2012
20090040861Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus - A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating a word line in a bank of one of the memory devices based on the row activation command, wherein the bank address is used to select the memory device.02-12-2009
20090073797 SEMICONDUCTOR MEMORY DEVICE WITH CONTROL BLOCK SHARING ROW DECODERS - A semiconductor memory device comprises a plurality of banks including a plurality of mat rows, respectively, wherein the mat row includes a plurality of mats disposed in a same row, row decoder groups disposed between the banks and including row decoders that correspond to the mat rows, respectively, and common control blocks installed corresponding to a predetermined number of row decoders to simultaneously control the row decoders.03-19-2009
20090073796MEMORY ARRAY PERIPHERAL STRUCTURES AND USE - A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.03-19-2009
20090168588LOW CURRENT CONSUMPTION SEMICONDUCTOR MEMORY DEVICE HAVING INPUT/OUTPUT CONTROL CIRCUIT AND CONTROL METHOD THEREOF - A low-current consumption semiconductor memory device includes a plurality of cell blocks, in which each cell block includes a plurality of cell mats; a plurality of input/output line switches which transmit the plurality of cell blocks to input/output lines; and an input/output line control circuit which receives a block address indicating arbitrary blocks among the plurality of cell blocks and an active command to control a drive of an input/output line switch according to an input level of the block address.07-02-2009
20080291766Memory architecture having local column select lines - A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections of memory. Each section of memory having a plurality of memory cells arranged in rows and columns of memory and a plurality of sense amplifiers located in each of the plurality of regions. The sense amplifiers coupled to a respective column of memory. A plurality of column select lines are located in each of the plurality of regions with each column select line coupled to a group of column select switches associated with a section of memory to activate the respective column select switches.11-27-2008
20090109787NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.04-30-2009
20110242925REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES - The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.10-06-2011
20100188923SEMICONDUCTOR DEVICE - A semiconductor device 110 has a plurality of memory cell blocks provided with a plurality of memory cells storing a predetermined amount of data. Each memory cell block has four or more inputs and outputs, and is internally provided with a read address decoder to the memory cell and a sense amplifier for amplifying a voltage in outputting outside. Each memory cell block is structured so as to store a truth table data for outputting a desired logic value in response to a specified address input, thereby operating as a logic circuit. The memory cell has a read word line correspondingly to the read address decoder. In the case when a voltage is applied to the read word line, the data that is held at that time is read from a read data line. The memory cell blocks are connected to each other such that the four or more outputs from one memory cell block are inputted to other four or more memory cell blocks through the sense amplifier.07-29-2010
20090067276Storing Operational Information in an Array of Memory Cells - The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment includes storing data units of operational information in memory cells of at least one row of a first block of memory cells. The method also includes using a column scramble to shift the order of the data units. The method includes storing the data units in memory cells of at least one row of a second block of memory cells, wherein an order of the data units stored in the at least one row of the second block is different than an order of the data units stored in memory cells of the at least one row of the first block.03-12-2009
20090040860SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF SELECTIVELY PROVIDING DECODED ROW ADDRESS - A semiconductor memory apparatus includes a first bank block including a first bank group, a second bank block including a second bank group, and an address control unit that receives an address signal to selectively provide a decoded row address signal to the first bank block or the second bank block in response to a bank address signal.02-12-2009
20110085404Semiconductor memory device and information processing system including the same - The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.04-14-2011
20110242924SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.10-06-2011
20110211413SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal, a second bank selection driving control signal generation unit configured to generate a plurality of second bank selection driving control signals corresponding to the plurality of banks in response to one of a read command signal and a write command signal and in response to the address signal, and an internal voltage driver configured to selectively drive a plurality of internal voltage terminals corresponding to the plurality of banks in response to the plurality of first bank selection driving control signals and the plurality of second bank selection driving control signals.09-01-2011
20110085405SEMICONDUCTOR MEMORY DEVICE HAVING ADVANCED TAG BLOCK - A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.04-14-2011
20110085402BANK RE-ASSIGNMENT IN CHIP TO REDUCE IR DROP - A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the centre of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.04-14-2011
20110085403Semiconductor memory device and information processing system including the same - The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. A bit number of external unit data that is simultaneously input and output between an external device and the interface chip changes in the interface chip, and the interface chip changes chip selection information for comparison with the chip identification information, according to the bit number of the external unit data. As a result, the page configuration does not need to be changed, when the I/O configuration is changed.04-14-2011
20110075502BANK ACTIVE SIGNAL GENERATION CIRCUIT - The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode. The decoded signal generator also generates decoded signals from the first bank access signal, the second bank access signal, and a third bank access signal in response when the prefetch signal at a second mode. The active signal generator generates bank active signals in response to receiving the decoded signals, an active pulse and a precharge pulse.03-31-2011
20110149673Three State Word Line Driver ForA DRAM Memory Device - A memory bank includes an array of memory cells, word lines for accessing the memory cells, and word line drivers coupled to the word lines. When the memory bank is being accessed, the word line drivers are coupled to receive a first supply voltage, which is applied to the non-selected word lines of the memory bank. The first supply voltage turns off access transistors of the memory cells coupled to the non-selected word lines. When the memory bank is not being accessed, the word line drivers are coupled to receive a second supply voltage, which is applied to each of the word lines of the memory bank. The second supply voltage turns off the access transistors of the memory cells coupled of the word lines. The first and second supply voltages are selected such that the first supply voltage turns off the access transistors harder than the second supply voltage.06-23-2011
20090323454SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of easily checking whether banks are overlappingly activated. The semiconductor memory device includes a bank active signal generating unit and an overlap detecting unit. The bank active signal generating unit generates bank active signals for respective different banks in response to an active signal and bank addresses. The overlap detecting unit detects whether the bank active signals of the different banks are overlappingly enabled.12-31-2009
20080247260Semiconductor memory device for independently selecting mode of memory bank and method of controlling thereof - A semiconductor memory device in which a mode of a memory bank may be independently selected and a method of controlling the semiconductor memory device may be provided. The semiconductor memory device with a plurality of banks may include a plurality of bank groups that each may have at least one bank from among the plurality of banks, and a memory controller that may control a read/write operation to be performed on a bank belonging to a bank group from among the plurality of bank groups, in response to a control signal, where different modes or the same mode may be applied to the bank groups. Accordingly, different modes or the same mode may be applied to the banks so that the read/write operation may be performed on a bank having a mode that is advantageous to the type of data, thereby minimizing consumption of power and a time delay.10-09-2008
20090022005APPARATUS AND METHOD OF CONTROLLING BANK OF SEMICONDUCTOR MEMORY - An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption.01-22-2009
20080273414SEMICONDUCTOR DEVICE AND MEMORY CIRCUIT LAYOUT METHOD - A memory comprising a memory array, a sensor amplifier, and a column driver/decoder. The memory comprises a plurality of memory cells. The sensor amplifier is disposed on one side of the memory array for accessing the memory cells of the memory array. The column driver/decoder is disposed on the opposite side of the memory array for selecting the memory cells of the memory array.11-06-2008
20080198680SEMICONDUCTOR MEMORY DEVICE HAVING INPUT/OUTPUT SENSE AMPLIFICATION CIRCUIT WITH REDUCED JUNCTION LOADING AND CIRCUIT LAYOUT AREA - A semiconductor memory device includes an input/output sense amplifier that amplifies a read data and provides it to the external, when making a read operation. The semiconductor memory device includes a plurality of sense amplifiers that amplify data transferred from each bank and output them as amplified signals; a controller that judges the output states of the amplified signals in each sense amplifier to output driving signals corresponding to the output amplified signals; and a driver that drives an global input/output line with the driving signal, wherein the first and second sense amplifiers share the one driver, making it possible to reduce ‘tAA’ and get an advantage of a layout area.08-21-2008
20080205185Semiconductor memory device and its driving method - A semiconductor memory device includes a bit line sense amplifier block array, upper and lower unit memory cell arrays and a switching controller. The bit line sense amplifier block array senses and amplifies data of a unit memory cell array. The upper and the lower unit memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the unit memory cell array. The switching controller selectively connects one of the upper and lower unit memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower unit memory cell arrays are not selected but overdriven.08-28-2008
20110134715Method for accessing vertically stacked embedded non-flash re-writable non-volatile memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.06-09-2011
20090207682SEMICONDUCTOR MEMORY DEVICE - A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.08-20-2009
20110075503MAIN DECODING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column selection line of a first memory bank and a column selection line of a second memory bank in response to a bank selection signal.03-31-2011
20120147689THREE DIMENSIONAL NON-VOLATILE STORAGE WITH MULTI BLOCK ROW SELECTION - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.06-14-2012
20100080076COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.04-01-2010
20090296512Apparatus for writing to mutiple banks of a memory device - In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.12-03-2009
20110317507SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY - A semiconductor memory includes memory cells; word lines coupled to the memory cells; plate lines coupled to the memory cells; a selector that selects a first address signal in a first period and select a second address ,signal in a second period; a decode circuit that sequentially decodes the first and the second address signals selected by the selector, sequentially generates decode address signals based on the decoded first and second address signals, and sequentially activates the generated decode address signals; and a driver circuit that drives the word lines in accordance with the decode address signals activated based on the first address signal and drives the plate lines in accordance with the decode address signals activated based on the second address signal.12-29-2011
20120008451SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address.01-12-2012
20120008450FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT - A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b) at least one binary to one-hot address decode block and at least one one-hot address register block and (3) a memory array, at least one of the blocks having a timing selected to match at least some timing margins outside of the memory.01-12-2012
20120106287Memory Arrangement for Accessing Matrices - A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read access. The memory arrangement further includes a first macro bank comprising a first plurality of memory cells comprising a first subset of the memory elements and a second macro bank comprising a second plurality of memory cells comprising a second subset of the memory elements. The memory arrangement further includes an address resolution stage for addressing the memory cells in the respective macro banks. The memory cells are arranged so that the memory space is partitioned into a plurality of non-overlapping basic matrices, whereby each basic matrix is mapped to a given macro bank and wherein the memory cells are arranged logically so that the memory space is partitioned into a plurality of non-overlapping logic matrices of a given size, each logic matrix being of a size equal or larger than a basic matrix.05-03-2012
20120106286MEMORY CIRCUIT HAVING DECODING CIRCUITS AND METHOD OF OPERATING THE SAME - The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.05-03-2012
20080247259Configurable Memory Data Path - A data path in a memory device is configured by selecting a data path configuration configured to at least partially maintain data bit order between the memory device and a chip carrier. The memory data path is arranged based on the data path configuration for memory operations where maintaining data bit order between the memory device and the chip carrier is required.10-09-2008
20120155209SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is configured to have a first memory cell array having a plurality of blocks (cell arrays corresponded to one I/O bit), each block having a plurality of columns and being corresponding respectively to one of data terminals, wherein the blocks being arranged side by side in the column-wise direction, and a second memory cell array configured similarly to the first memory cell array, and is also configured to assign addresses while classifying the even-number-th memory blocks in the first memory cell array and the odd-number-th memory blocks in the second memory cell array into a first set, whereas the odd-number-th memory blocks in the first memory cell array and the even-number-th memory blocks in the second memory cell array into a second set, so as to output data from every other block in each memory cell array upon being accessed with a certain address.06-21-2012
20110103171SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: first and second memory banks located at a predetermined distance from each other; a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to corresponding memory cells in the first and second memory banks; and a column selection signal repeater inserted in the common column selection signal transmission line, and configured to transfer the column selection signal for controlling data access to the memory cell in the first memory bank. A transmission path of the column selection signal for controlling data access to the memory cell in the first memory bank is longer than that of the column selection signal for controlling data access to the memory cell in the second memory bank.05-05-2011
20120314523MULTI-PORT MEMORY DEVICES AND METHODS - Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.12-13-2012
20120127818SHARING ACCESS TO A MEMORY AMONG CLIENTS - In a memory device having a set of memory banks to store content data, at least two requests to perform respective memory operations in a first memory bank are received during a single clock cycle. One or more of the at least two requests is blocked from accessing the first memory bank, and in response: redundancy data associated with the first memory bank and different from content data stored therein is accessed, and, without accessing the first memory bank, at least a portion of the content data stored in the first memory bank is reconstructed based on the associated redundancy data. A first memory operation is performed using the content data stored in the first memory bank, and a second memory operation is performed using content data reconstructed i) without accessing the first memory bank and ii) based on the associated redundancy data.05-24-2012
20120163113MEMORY CONTROLLER AND MEMORY CONTROLLING METHOD - A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.06-28-2012
20120213028MEMORY CELL AND MEMORY ARRAY UTILIZING THE MEMORY CELL - A memory cell comprising a first switch device, a second switch device and a capacitor is disclosed. The first switch device has: a control terminal coupled to a select line, wherein the first switch device is controlled by the select line; a first terminal, coupled to a bit line parallel with the select line. The second switch device has: a first terminal, coupled to the second terminal of the first switch device; a control terminal, coupled to a word line orthogonal to the bit line and the select line, wherein the second switch device is controlled by the word line. The capacitor has a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line.08-23-2012
20090059710SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having banks includes an address input path selection circuit in each of the banks, the address input path selection circuit including a signal input unit configured to selectively activate a Y-address input enable signal in response to a bank-specific read/write signal, and a latch unit configured to latch the Y-address input enable signal. The address input path selection circuit reduces circuit area by reducing delay elements and prevents malfunction by operating only in a bank active state.03-05-2009
20090059709ADDRESS REPLACING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - An address replacing circuit includes a sub-bank region selecting unit that allows a first sub-bank region or a second sub-bank region to be selectively activated, in response to a row address and first and second bits of a column address in accordance with operation modes a first column region activating unit that generates a first column region activating address and a second column region activating address from the first bit of the column address, a second column region activating unit that generates a third column region activating address and a fourth column region activating address from the second bit of the column address, and a column region selecting unit that allows at least one of first to fourth column regions of the first sub-bank region and first to fourth column regions of the second sub-bank region to be selectively activated, in response to the first to fourth column region activating addresses.03-05-2009
20090059708SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING BANK SELECTION CONTROL BLOCK - A semiconductor integrated circuit according to one embodiment can include an up bank block that includes a first group of banks, a down bank block that includes a second group of banks, and a bank selection control block that provides up and down bank even-numbered global line control signals, up and down bank odd-numbered global line control signals, and up and down bank SDRAM write global line control signals in response to first and second group read control signals and a bank information signal in the up bank block and the down bank block. In this case, the bank selection control block may respond to a DDR signal and an SDR signal that are provided from an MRS (Mode Register Set).03-05-2009
20120176856MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVNG ACCESSES THEREOF - An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.07-12-2012
20120263005MEMORY APPARATUS AND SYSTEM WITH SHARED WORDLINE DECODER - A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.10-18-2012
20120327735BLOCK-ROW DECODERS, MEMORY BLOCK-ROW DECODERS, MEMORIES, METHODS FOR DESELECTING A DECODER OF A MEMORY AND METHODS OF SELECTING A BLOCK OF MEMORY - Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.12-27-2012
20110211414SEMICONDUCTOR MEMORY MODULE - A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit width of data. The data is transferred between the first circuit and the plurality of semiconductor memories.09-01-2011
20110235458ELECTRIC DEVICE - In one embodiment, an electric device includes a memory, first and second generators, a limit unit, and a reduction unit. The first generator generates the chip select signal representing an inactive mode or an active mode according to a potential of an enable terminal and a input potential The second generator generates an enable signal which is a first level, a second level or a level having the first value as a maximum value. The limit unit limits the potential of the terminal to a potential lower than the first potential during first and second periods, and does not prevent from the enable signal from being input to the terminal during other periods. The reduction unit reduces the level of the enable signal at a predetermined rate, and then inputs the reduced enable signal to the terminal.09-29-2011
20110158028BLOCK DECODER OF SEMICONDUCTOR MEMORY DEVICE - A block decoder of a semiconductor memory device includes a control signal generation circuit configured to output a control signal in response to a first address mixing signal, a second address mixing signal, and an enable period signal and a block selection signal generation circuit configured to generate a block selection signal for selecting a memory block in response to the control signal.06-30-2011
20120087200INTERNAL COLUMN ADDRESS GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second bank groups and an internal column address generating circuit. Each of the first and second bank groups includes at least one bank. The internal column address generating circuit converts a column address into a first internal column address and outputs the first internal column address through a first transmission line in response to a bank address if a read operation or a write operation is performed on a bank of the first bank group. Also, the internal column address generating circuit converts the column address into a second internal column address and outputs the second internal column address through a second transmission line in response to the bank address if a read operation or a write operation is performed on a bank of the second bank group.04-12-2012
20080253216Semiconductor package for forming a Double Die Package (DDP) - A semiconductor package for forming a Double Die Package (DDP) with a plurality of single chips includes: a buffer configured to buffer an external address to generate a row address which is defined only in a DDP mode; a column address control unit configured to replace the row address with a column address, which is defined only in the DDP mode, in a single chip mode; and a read operation control unit configured to output a bank read signal latched in an active bank in a read mode of the DDP, and to selectively activate a first address control signal and a second address control signal for activating a bank selected from the single chip or the DDP in response to the bank read signal.10-16-2008
20100091599SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks, wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal.04-15-2010
20080239861MEMORY AND OPERATION METHOD THEREOF - A memory and an operation method thereof are provided. The present invention divides memory banks of the memory into a plurality of memory groups, wherein each memory group has an independent driving power for providing an operating voltage to the corresponding memory bank in the memory group. The present invention specifies two tRRD times which are an inter-group interval and an intra-group interval. The intra-group interval is the minimum time interval between selecting one row of memory banks in a memory group to selecting another row in the memory banks of the same memory group and the inter-group interval is the minimum time interval between selecting one row of the memory banks in one memory group to selecting another row in a different memory group. Further, the inter-group interval is shorter than or equal to the intra-group interval.10-02-2008
20080225622SEMICONDUCTOR MEMORY DEVICE, OPERATIONAL PROCESSING DEVICE AND STORAGE SYSTEM - A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.09-18-2008
20130176807DRAM AND ACCESS AND OPERATING METHOD THEREOF - An access method for a DRAM is provided. A row address is partitioned into a first portion and a second portion. The first portion of the row address via an address bus and a first active command via a command bus are provided to the DRAM. The second portion of the row address via the address bus and a second active command via the command bus are provided to the DRAM after the first active command is provided. A column address via the address bus and an access command via the command bus are provided to the DRAM after the second active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address, and the access command is a read command or a write command.07-11-2013
20080219081SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes first and second data storing/processing sections that have memory areas in a bank and the first and second data storing/processing sections share a circuit block that inputs and outputs the data, and a signal line that transmits the data.09-11-2008
20130094319Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.04-18-2013
20130114365SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - Disclosed is a semiconductor memory device, including a plurality of internal voltage generation units configured to be enabled in response to each of a plurality of decoding signals and to generate an internal voltage, a controller configured to generate a plurality of control signals in response to a power up signal and a test mode signal, and a decoder configured to generate the plurality of decoding signals corresponding to at least one decoding source signal and to simultaneously activate some or all of the plurality of decoding signals in response to the control signals.05-09-2013
20110211415Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.09-01-2011
20120275257SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a first bit line section coupled to a first cell string, a second bit line section coupled to a second cell string, a page buffer coupled to the first bit line section and a switching circuit formed between the first bit line section and the second bit line section, wherein the switching circuit couples the first bit line section to second bit line section in response to a select signal.11-01-2012
20110310691Multi-Port Memory Using Single-Port Memory Cells - A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.12-22-2011
20120014202MEMORY DEVICE AND METHOD - A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period01-19-2012
20120020178MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.01-26-2012
20130201778SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON A ROW ADDRESS AND A BANK ADDRESS - A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.08-08-2013

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