Class / Patent application number | Description | Number of patent applications / Date published |
365230060 |
Particular decoder or driver circuit
| 197 |
365233100 |
Sync/clocking
| 177 |
365230030 |
Plural blocks or banks
| 164 |
365230080 |
Including particular address buffer or latch circuit arrangement
| 52 |
365230050 |
Multiple port access
| 30 |
365230020 |
Multiplexing
| 28 |
365239000 |
Sequential
| 7 |
365236000 |
Counting
| 6 |
365238500 |
Byte or page addressing | 4 |
20090190432 | DRAM with Page Access - A DRAM chip with a data I/O-interface of an access width equal to a page size. | 07-30-2009 |
20130142004 | DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS - Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. | 06-06-2013 |
20140160876 | ADDRESS BIT REMAPPING SCHEME TO REDUCE ACCESS GRANULARITY OF DRAM ACCESSES - One embodiment of the present invention sets forth a method for accessing non-contiguous locations within a DRAM memory page by sending a first column address command to a first DRAM device using a first subset of pins and sending a second column address command to a second DRAM device using a second subset of repurposed pins. One advantage of the disclosed technique is that it requires minimal additional pins, space, and power consumption. Further, sending multiple column address commands allows for increased granularity of DRAM accesses and therefore more efficient use of pins. Thus, the disclosed technique provides a better approach for accessing non-contiguous locations within a DRAM memory page. | 06-12-2014 |
20140254300 | DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS - Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. | 09-11-2014 |
365231000 |
Using selective matrix | 3 |
20090052271 | SEMICONDUCTOR MEMORY DEVICE - An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address. | 02-26-2009 |
20150071021 | ACCESSING INDEPENDENTLY ADDRESSABLE MEMORY CHIPS - A method of accessing rows and columns stored in a memory system that include memory chips that can be individually addressed and accessed is described. In order to leverage this capability, prior to performing a row-write request on the memory system, a computer system may transform the rows and the columns in a matrix. In particular, in response to receiving a row-write request to write to a row N in the matrix, the computer system rotates the row right by N elements, and writes the row in parallel to address N of the memory chips in the memory system. Similarly, in response to receiving a column-write request to write to column M in the matrix, the computer system rotates the column right by M elements, and writes the column in parallel to the memory chips in the memory system. | 03-12-2015 |
20150103613 | MEMORY DEVICES AND METHODS OF OPERATING THE SAME - The present disclosure includes memory devices and methods of operating the same. One such device includes an array of groups of memory cells, a group selector configured to select a particular group of memory cells from within the array, and a cell selector configured to select a particular memory cell from within the selected particular group of memory cells. | 04-16-2015 |
365230090 |
Combined random and sequential addressing | 2 |
20090251986 | FIFO PEEK ACCESS - Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal. | 10-08-2009 |
20160055897 | SEMICONDUCTOR DEVICE, MEMORY ACCESS CONTROL METHOD, AND SEMICONDUCTOR DEVICE SYSTEM - In a semiconductor device in accordance with one embodiment, a memory access control unit counts the number of addresses accessed by burst access to each address included in an address set of an external memory that is going to be accessed. When the number of addresses is larger than a reference value, the memory access control unit performs burst access to the address, and when the number of addresses is smaller than the reference value, the memory access control unit performs random access to the address. | 02-25-2016 |
Entries |
Document | Title | Date |
20080304350 | SIGNAL PROCESSING CIRCUIT - A signal processing circuit includes a signal processing section which generates first address data and second address data in accordance with data processing, reads data stored in an external memory based on the first address data and the second address data for performing a predetermined processing, and outputs processed data along with the first address data and the second address data, an address conversion section which, receiving the first address data and the second address data input thereto, holds at least 1 bit of the first address and outputs third address data, and also adds the at least 1 bit of the held first address data to the second address and outputs fourth address data, and a data interface which performs a writing operation or a reading operation of the data processed by the signal processing section with respect to the external memory on the basis of a time when the address conversion section outputs the third address data and the forth address data. | 12-11-2008 |
20090003117 | SEMICONDUCTOR MEMORY DEVICE - A circuit can control a bit rate of information output from a multi-purpose register (MPR) of a semiconductor memory device in a test mode, thereby reducing current consumption for outputting information in a multi-purpose register (MPR). The semiconductor memory device includes a multi-purpose register configured separately to store a plurality of information, and to control a bit rate of the stored information in a test mode, each of the information having multiple bits, and a connection selector configured selectively to connect an output terminal of the multi-purpose register to one of a number of global lines according to an operation mode. | 01-01-2009 |
20090016143 | WORD LINE ACTIVATION IN MEMORY DEVICES - Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control bus. By identifying the address space to which a word line belongs, its appropriate configuration control bus may be selected and the control signals from the selected bus used to select the appropriate potentials for driving the word lines. | 01-15-2009 |
20090034355 | INTEGRATED CIRCUIT INCLUDING MEMORY CELLS WITH TUNNEL FET AS SELECTION TRANSISTOR - An integrated circuit having an array of memory cells is disclosed. One embodiment provides selection transistors for selecting one of a plurality of memory cells. The selection transistor is a tunnel field effect transistor in order to reduce a leakage current when the transistor is in its non-conducting state. Furthermore an operation method and a method for production are described. | 02-05-2009 |
20090052267 | METHOD OF SIMPLE CHIP SELECT FOR MEMORY SUBSYSTEMS - Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID. | 02-26-2009 |
20090147614 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal. | 06-11-2009 |
20090207680 | Method for the allocation of addresses in the memory cells of a rechargeable energy accumulator - A method for placing addresses in the memory cells of a rechargeable energy storage device for use in a motor vehicle, each of which memory cells includes at least one sensor device and an individualizing device for storing an address. In order to optimize the placing of addresses in the memory cells of a rechargeable storage device, the functionality of the memory cells is checked using the sensor device in the vehicle, an individual address is assigned to each operable memory cell, and the individual address is used to individualize the sensor values made available from the sensor device. | 08-20-2009 |
20090213679 | POWER DEPENDENT MEMORY ACCESS - An apparatus and method of accessing a memory by determining available power, and accessing a number of bits of the memory in parallel, wherein the number of bits accessed in parallel is based at least in part on the available power. | 08-27-2009 |
20090213680 | METHOD AND APPARATUS FOR MONITORING MEMORY ADDRESSES - Disclosed herein is a method and apparatus for monitoring a memory address transmitted along an address path and converted into a row or column address of memory. The method includes: generating a path decision signal for deciding whether to connect the address path to a data terminal of the memory according to a memory command; and when the address path is connected to the data terminal of the memory in response to the path decision signal, transmitting a memory address, corresponding to the memory command, to the data terminal of the memory so that the memory address is monitored through the data terminal of the memory. | 08-27-2009 |
20090231942 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING AND OPERATING THE SAME - A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor. | 09-17-2009 |
20100220542 | Integrated circuit memory access mechanisms - A memory cell | 09-02-2010 |
20110128809 | Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. | 06-02-2011 |
20130021866 | Semiconductor Devices Compatible with Mono-Rank and Multi-Ranks - A provided memory device is compatible with a mono-rank or multi-ranks. A plurality of memory layers are stacked in the memory device. The memory device receives an address signal and chip select signals in response to a chip identification signal and a mode signal used to determine a mono-rank or multi-ranks. The plurality of memory layers operate as the mono-rank accessed by the address signal, or operate as the multi-ranks accessed by the chip select signals. | 01-24-2013 |
20140133259 | MEMORY SYSTEM COMPONENTS THAT SUPPORT ERROR DETECTION AND CORRECTION - The disclosed embodiments relate to components of a memory system that support error detection and correction by means of storage and retrieval of error correcting codes. In specific embodiments, this memory system includes a memory device, which further contains a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. Moreover, the memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row. | 05-15-2014 |
20140140162 | MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION INFORMATION - A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device. | 05-22-2014 |
20140177375 | Memory Device with Internal Combination Logic - Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic. | 06-26-2014 |
20140241097 | LOADING TRIM ADDRESS AND TRIM DATA PAIRS - Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and the trim data of each trim address and trim data pair in the trim register array. The trim address of a particular trim address and trim data pair corresponds to a storage location of a trim settings array containing trim settings used in performing operations on an array of memory cells. The trim data of the particular trim address and trim data pair corresponds to data to modify a value of the storage location of the trim settings array corresponding to the trim address of the particular trim address and trim data pair. | 08-28-2014 |
20140286118 | SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE - A method for accessing a semiconductor device having a memory array, includes receiving a chip select signal, receiving a command signal and an address signal, receiving a verification signal, calculating an error signal based on the address signal, the command signal, and the verification signal, generating an internal chip select signal based on the received chip select signal if the error signal indicates no error, and generating an external alert signal if the error signal indicates an error. | 09-25-2014 |
20140313844 | FLEXIBLE INPUT/OUTPUT TRANSCEIVER - An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input. The feedback circuit can provide a feedback control signal that is coupled to a pre-driver circuit. The pre-driver circuit can modify a data signal in response to the feedback control signal and the data signal. A driver circuit is coupled to the pre-driver circuit and can provide a driver output signal responsive to the modified data signal. A receiver can be coupled to the driver to receive the driver output signal. The receiver includes a level shifting circuit that shifts the received signal to a voltage level determined by a selected signaling interface. | 10-23-2014 |
20140347948 | APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK - Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units. | 11-27-2014 |
20150049568 | MEMORY ACCESS CONTROL IN A MEMORY DEVICE - A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed. | 02-19-2015 |
20150063052 | INDEPENDENTLY ADDRESSABLE MEMORY ARRAY ADDRESS SPACES - Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space. | 03-05-2015 |
20150092509 | SEMICONDUCTOR APPARATUS AND CHIP ID GENERATION METHOD THEREOF - Provided is a semiconductor apparatus including a plurality of memory chips which are sequentially stacked. Each of the memory chips includes: a temperature sensor configured to sense the temperature of the memory chip; and a chip ID output unit configured to generate a chip ID for the memory chip based on an output of the temperature sensor. | 04-02-2015 |
20150098292 | METHODS AND SYSTEMS FOR ADDRESSING MEMORY WITH VARIABLE DENSITY - Embodiments relate to systems and methods for simplified addressing of a memory device whose total memory capacity is extendible by an additional memory capacity or a factor to a total extended memory capacity, the method comprising dividing the additional memory capacity into a set of binary memory fractions of the total memory capacity such that a sum of all binary memory fractions equals the additional memory capacity, and addressing each one of the binary memory fractions by a binary based addressing scheme. | 04-09-2015 |
20150098293 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal. | 04-09-2015 |
20160105168 | CHIP AND CHIP CONTROL METHOD - Provided is a chip in which operation state information on a main logic unit operating in response to an enable signal is acquired, and determining whether a toggling condition of the main logic unit is satisfied based on the operation state information. | 04-14-2016 |