Class / Patent application number | Description | Number of patent applications / Date published |
365225700 | Having fuse element | 79 |
20080212387 | INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses. | 09-04-2008 |
20080212388 | INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses. | 09-04-2008 |
20080225620 | Semiconductor memory device - In a semiconductor memory device, a repair circuit includes mode fuses to select one of plural repair modes corresponding to plural kinds of defects, respectively. The semiconductor memory device can repair a defective memory cell having operational margin defect without using redundancy memory cells. | 09-18-2008 |
20080266994 | LEVEL DETECT CIRCUIT - A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit. | 10-30-2008 |
20080273411 | FUSE OF A SEMICONDUCTOR MEMORY DEVICE AND REPAIR PROCESS FOR THE SAME - Disclosed herein is a fuse of a semiconductor memory device and a repair process for the same. The fuse includes a lower conductive film of a multilayer interconnection formed on a lower structure of a semiconductor substrate, an upper conductive film of the multilayer interconnection spaced apart upward from the lower conductive film to define a predetermined vertical space therebetween, and a contact electrode, which vertically connects the upper and lower conductive films to each other and forms a fuse body. The lower conductive film includes a form not coinciding with that of the upper conductive film. With such a configuration, the device can achieve a stable minimization in the length of the fuse and the distance between adjacent fuses in consideration of a laser beam irradiation region for the high integration of the semiconductor memory device. In this way, the device performs the repair process of cutting the contact electrode and/or upper conductive film using a laser beam. | 11-06-2008 |
20080304347 | ONE TIME PROGRAMMABLE ELEMENT SYSTEM IN AN INTEGRATED CIRCUIT - A system with a repairable memory array having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array circuits having circuitry that may adjust one or more operating parameters such as operating current, operating voltage, resistance, capacitance, timing characteristics and an operating mode. A set of one time programmable elements can be used to selectively store information for modifying operating parameters and replacing the defective memory cells with redundant memory cells. | 12-11-2008 |
20080304348 | Current-mode memory cell - Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors. | 12-11-2008 |
20090059704 | CALIBRATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - A calibration circuit is capable of correcting an error of a calibration operation by adjusting a calibration code generated thereby. The calibration circuit of a semiconductor memory device includes a code generator, a calibration resistor unit, and a variable resistor unit. The code generator is configured to generate a calibration code for determining a termination resistance in response to a voltage of a first node and a reference voltage. The calibration resistor unit, which has internal resistors turned on/off in response to the calibration code, is connected to the first node. The variable resistor unit is connected in parallel with the calibration resistor unit and has a resistance that varies with a setting value. | 03-05-2009 |
20090116327 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 05-07-2009 |
20090122632 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 05-14-2009 |
20090141577 | ANTI-FUSE REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DRAM HAVING THE SAME - In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled. | 06-04-2009 |
20090141578 | FUSE BOX AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A fuse box of a semiconductor memory device which comprises a plurality of fuse units commonly connected to a power line, each of the fuse units comprising a first fuse connected with the power line; and a plurality of second fuses connected with the first fuse in parallel. If the second fuses are determined to be cut off, the first fuse is cut off instead of the second fuses. | 06-04-2009 |
20090147609 | TECHNIQUES FOR CONFIGURING MEMORY SYSTEMS USING ACCURATE OPERATING PARAMETERS - Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, or voltage and timing parameters. The memory device may be incorporated into a memory module that is incorporated into a system. Once the memory module is incorporated into a system, the programmable elements may be accessed such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for each memory device in the system. | 06-11-2009 |
20090161470 | CIRCUIT FOR DYNAMIC READOUT OF FUSED DATA IN IMAGE SENSORS - A circuit for reading fused data, an image sensing apparatus, a method of reading fused data and a method of manufacturing a circuit for reading fused data. The circuit includes a fuse and a capacitive component configured to provide a data input signal to a data input node of a one bit data storage unit and a signal delay component configured to provide a delayed signal to a clock input terminal of the one bit data storage unit. The method of operating the circuit includes applying a signal to the fuse and to the signal delay element, delaying the signal in the delay element, providing a delayed signal from the delay element to a clock input of a one bit storage element, and providing the signal from the fuse and the capacitive component to a data input of the one bit storage element. | 06-25-2009 |
20090168580 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal. | 07-02-2009 |
20090168581 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor memory device includes a fuse repair unit including a plurality of fuses each programmed with at least one repair address, configured to receive a fuse reset signal and to output a plurality of fuse state signals each corresponding to a connection state of one of the fuses, a fuse monitoring unit configured to receive a monitoring enable signal and to output a plurality of fuse state monitoring signals each corresponding to a corresponding one of the fuse state signals, each of the fuse state signals corresponding to one of a plurality of addresses, and an output unit configured to receive an output control signal and to output the fuse state monitoring signals to an output pad. | 07-02-2009 |
20090175111 | CIRCUIT HAVING GATE OXIDE PROTECTION FOR LOW VOLTAGE FUSE READS AND HIGH VOLTAGE FUSE PROGRAMMING - A circuit for reading and programming a fuse. The electronic circuit includes a data fuse coupled to a data node and a reference fuse coupled to a reference node. A programming circuit is coupled to the data node, wherein the programming circuit is configured to, when activated, cause the data fuse to be programmed. A sensing circuit is configured to draw current from the data node and the reference node in order to develop a voltage differential between the data node and the reference node during a read operation. A read circuit is configured to, when activated, enable the sensing circuit to develop the voltage differential during the read operation. A protection circuit is configured to form a voltage divider within the sensing circuit during programming of the fuse. | 07-09-2009 |
20090238022 | SEMICONDUCTOR DEVICE AND CONTROLLING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a setting circuit which sets a first setting value; a control circuit which receives a predetermined control signal and the first setting value so as to output a second setting value; and an output circuit which outputs a predetermined level in response to the first setting value or the second setting value, wherein the second setting value is changed from the first setting value based on the predetermined control signal. | 09-24-2009 |
20090245005 | RECOVERY OF EXISTING SRAM CAPACITY FROM FUSED-OUT BLOCKS - A system, device, and method are disclosed. In one embodiment the system includes an interconnect within an integrated circuit. The system also includes a first fuse-disabled design block within the integrated circuit that has an internal static random access memory (SRAM). The first fuse-disabled design block is coupled to the interconnect. The system also includes a memory controller that is coupled to the interconnect. The memory controller is capable of selecting the internal SRAM and allocating the internal SRAM for storage accessible by one or more devices external to the first fuse-disabled integrated peripheral. | 10-01-2009 |
20090245006 | Semiconductor memory device - The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded. | 10-01-2009 |
20090257300 | FUSE INFORMATION CONTROL DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME, AND CONTROL METHOD THEREOF - A fuse information control device having a delay circuit to delay an active signal, includes a fuse circuit that outputs fuse information in response to a fuse information control signal, and a fuse information control signal generating unit that generates the fuse information control signal in response to one of the active signal and internal delay signals of the delay circuit. | 10-15-2009 |
20090296511 | MICROPROCESSOR WITH PROGRAM-ACCESSIBLE RE-WRITABLE NON-VOLATILE STATE EMBODIED IN BLOWABLE FUSES OF THE MICROPROCESSOR - A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times. | 12-03-2009 |
20090323450 | NON-VOLATILE PROGRAMMABLE MEMORY CELL AND MEMORY ARRAY - A non-volatile one time programmable memory cell couples in series a two terminal fuse and a three terminal antifuse. The non-volatile one time programmable memory cell includes a memory cell write enable node and a memory cell output node. The non-volatile one time programmable memory cell includes fuse having a first node and a second node, and an antifuse having a trigger node, a first node, and a second node. The trigger node is coupled to the memory cell write enable node. The first node of the antifuse and the second node of the fuse are coupled to the memory cell output node. First and second voltages appearing at the memory cell output node are indicative of first and second binary states of the memory cell. A plurality of such memory cells can be included in a non-volatile programmable memory array. A non-volatile programmable memory cell capable of re-programming is also described. | 12-31-2009 |
20100014373 | REGULATING ELECTRICAL FUSE PROGRAMMING CURRENT - An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of reference fuses; and a voltage comparator coupled to a gate terminal of the reference programming FET so as to adjust the gate voltage of the reference programming FET to equalize a first voltage across the first current path with a second voltage across the second current path. The gate voltage of the reference programming FET is an output of the current control generator, coupled to corresponding gates of one or more selected programming devices of an eFUSE array such that the selected programming devices source the desired eFUSE programming current to a selected eFUSE to be programmed. | 01-21-2010 |
20100014374 | FUSE ELEMENT READING CIRCUIT - A fuse element reading circuit including a first fuse element having a resistance which differs in accordance with whether the first fuse element is in a blown state or an unblown state, a reference voltage output circuit unit that outputs a reference voltage that differs in accordance with a normal mode or a test mode, and a voltage comparison circuit unit that compares a read voltage corresponding to the resistance of the first fuse element with the reference voltage output from the reference voltage output circuit unit. | 01-21-2010 |
20100067319 | Implementing Precise Resistance Measurement for 2D Array Efuse Bit Cell Using Differential Sense Amplifier, Balanced Bitlines, and Programmable Reference Resistor - A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse. | 03-18-2010 |
20100118636 | Methods and Systems Involving Electrically Reprogrammable Fuses - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 05-13-2010 |
20100124139 | SEMICONDUCTOR DEVICE INCLUDING AN ANTI-FUSE ELEMENT - A semiconductor device includes a first high potential power supply, a second low potential power supply, a third power supply having a potential higher than the first, a fourth power supply having a potential more negative than the second, and an anti-fuse element having a node at each end, one of which is connected to the fourth power supply. A driver transistor has a source connected to the third power supply, a gate connected to a control node and a drain connected to one end of the anti-fuse element. A decoding circuit includes a load transistor connected between the third power supply and the control node and at least one selection transistor connected between the second power supply and the control node. A decision circuit is connected to the first and second power supplies. The decision circuit decides the resistance value of the anti-fuse element. The anti-fuse element is rendered electrically conductive in response to activation of the driver transistor as selected by the decoding circuit. The decision circuit decides whether or not the anti-fuse element has been rendered electrically conductive. | 05-20-2010 |
20100135096 | ANTIFUSE CIRCUIT WITH WELL BIAS TRANSISTOR - An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate and a bias voltage terminal. The bias transistor has a second gate terminal and is operable to couple the bias voltage terminal to the substrate responsive to an assertion of a bias enable signal at the second gate terminal. | 06-03-2010 |
20100149898 | Antifuses and program circuits having the same - Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed. | 06-17-2010 |
20100165774 | SMALL-SIZED FUSE BOX AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - Disclosed are a fuse box and a semiconductor integrated circuit having the same. The semiconductor integrated circuit includes a plurality of banks, column control blocks, and column fuse blocks. The plurality of banks including a plurality of mat rows and mat columns. The banks are arranged in row and column directions and disposed away from each other. The column control blocks are disposed in a space between the banks which are extended to the column direction. The column fuse blocks are disposed adjacent to the column control blocks and have a plurality of fuse boxes. The fuse boxes include fuse sets arranged in two rows. The fuse boxes are disposed to correspond to the one mat column. Each fuse box has an interconnection fuse and address fuses which are arranged with a constant interval and are the same type. | 07-01-2010 |
20100165775 | SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSES WITH LESS POWER CONSUMPTION AND INTERCONNECTION ARRANGEMENT - In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area. | 07-01-2010 |
20100226193 | SEMICONDUCTOR MEMORY DEVICE - A unit memory circuit includes a fuse element capable of electrically programming data. A sense amplifier circuit is connected to the fuse element. The sense amplifier circuit senses data of the fuse element. Either of a first interconnect and a second interconnect is selectively formed by changing an interconnect formation mask. The first interconnect is short-circuiting the fuse element and the second interconnect is cutting off a current path when data is read from the fuse element. | 09-09-2010 |
20100232248 | Implementing eFuse Resistance Determination Before Initiating eFuse Blow - A method and an eFuse programming circuit for implementing resistance determination of an eFuse before initiating eFuse blow, and a design structure on which the subject circuit resides are provided. An eFuse on a chip is used to set current flow through a known resistor and measure the eFuse resistance. An applied voltage to program selected eFuses on the chip is selected responsive to an identified eFuse voltage value. | 09-16-2010 |
20100271897 | Anti-fuse memory cell and semiconductor memory device - An anti-fuse memory cell includes: a first transistor connected with a word line and configured to output a second voltage based on a first voltage supplied to the word line in a write mode; a second transistor connected with a bit line, and configured to output a third voltage supplied to the bit line when the second voltage is supplied to a gate of the second transistor in the write mode; and an anti-fuse element connected to a ground line, and having an insulator film. The insulator film is set to a conductive state with the third voltage supplied from the second transistor. | 10-28-2010 |
20100290302 | FUSE CIRCUIT AND DRIVING METHOD THEREOF - A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node. | 11-18-2010 |
20100290303 | Semiconductor device - A semiconductor device includes a first terminal, a second terminal, and a fuse link that connects between the first terminal and the second terminal. The first terminal and the fuse link have a polysilicon layer doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer. The second terminal has a polysilicon layer not doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer, in at least a part of an end side connected to the fuse link. | 11-18-2010 |
20100302890 | Electrical Fuse, Semiconductor Device Having the Same, and Method of Programming and Reading the Electrical Fuse - Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the first anode to the cathode, and a second fuse link couples the second anode to the cathode. | 12-02-2010 |
20100329061 | ELECTRICAL FUSE CIRCUIT FOR SECURITY APPLICATIONS - A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation. | 12-30-2010 |
20110002186 | SECURE ELECTRICALLY PROGRAMMABLE FUSE AND METHOD OF OPERATING THE SAME - An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element. | 01-06-2011 |
20110002187 | LATCH TYPE FUSE CIRCUIT AND OPERATING METHOD THEREOF - A latch type fuse circuit includes a non-volatile memory, a PMOS transistor, and an output circuit. The non-volatile memory cell stores a logic bit. A voltage level of a source of the PMOS transistor determines the latch type fuse operating in the data program status or the data read status. In the data program status, a gate of the PMOS transistor receives a first signal including an address and the logic bit for determining the logic bit written in the non-volatile memory cell. The output circuit includes two NMOS transistors and an inverter. In the data read status, the output circuit can latch the logic bit. | 01-06-2011 |
20110002188 | Apparatus for Nonvolatile Multi-Programmable Electronic Fuse System - Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system. | 01-06-2011 |
20110007595 | ELECTRONIC EQUIPMENT SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT CONTROLLER - An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory. | 01-13-2011 |
20110019494 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element. | 01-27-2011 |
20110075500 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween. | 03-31-2011 |
20110103170 | NOVEL FUSE PROGRAMMING SCHEMES FOR ROBUST YIELD - An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession. | 05-05-2011 |
20110158025 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit. | 06-30-2011 |
20110158026 | FUSE CIRCUIT AND CONTROL METHOD THEREOF - A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage. | 06-30-2011 |
20110176380 | PAIRED PROGRAMMABLE FUSES - A plurality of fuses are arranged in pairs and configured such that each pair of fuses represents a data bit when one fuse of the pair is blown; represents an un-programmed bit when no fuse of the pair is blown; and represents a zero-ized bit when both fuses of the pair are blown. A fuse programming system programs the fuses of the pairs such that each pair represents a bit, comprising blowing a first fuse of a pair to represent a “1” bit, blowing a second fuse of a pair to represent a “0” bit, and blowing both fuses of a pair to represent a zero-ized pair, whereby if neither fuse of a pair is blown represents a null, un-programmed bit. | 07-21-2011 |
20110176381 | MEMORY HAVING A DISABLING CIRCUIT AND METHOD FOR DISABLING THE MEMORY - A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix. | 07-21-2011 |
20110235452 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information. | 09-29-2011 |
20110235453 | FUSE CIRCUIT AND REPAIR CONTROL CIRCUIT USING THE SAME - A fuse circuit includes a fuse driving unit, a separation/connection unit, a voltage equalization unit, and a latching unit. The fuse driving unit is configured to drive an output terminal in response to a fuse reset signal, depending on data programmed in a fuse. The separation/connection unit is disposed between the fuse and the output terminal and configured to separate or connect the fuse from or to the output terminal in response to a control signal. The voltage equalization unit is configured to equalize both ends of the fuse to the same voltage in response to the control signal. The latching unit is configured to latch and output the output terminal driven by the fuse driving unit. | 09-29-2011 |
20110267915 | ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE - Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer. | 11-03-2011 |
20110273949 | ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME - A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse. | 11-10-2011 |
20110273950 | Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit - A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates | 11-10-2011 |
20110292752 | SEMICONDUCTOR MEMORY DEVICE HAVING FUSE ELEMENTS PROGRAMMED BY IRRADIATION WITH LASER BEAM - A relief-address control unit of a semiconductor memory device includes a fuse storage unit and a relief circuit. The fuse storage unit includes a plurality of fuse elements that are made nonconductive by irradiation with a laser beam, and a protective film with an opening directly above the fuse elements to facilitate the laser beam to pass through. The relief circuit specifies a relieved address based on a nonconductive state of the fuse elements. The opening is in a unified form along a long-side direction of the fuse storage unit. Further, the relief circuit is arranged adjacent to a short-side end of the fuse storage unit. | 12-01-2011 |
20120008448 | ANTI-FUSE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal. | 01-12-2012 |
20120014200 | Multi-Time Programmable Memory - Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products. | 01-19-2012 |
20120020177 | ELECTRICAL FUSE MEMORY - Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row. | 01-26-2012 |
20120026822 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament. | 02-02-2012 |
20120057423 | ELECTRICAL FUSE MEMORY ARRAYS - Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column. | 03-08-2012 |
20120092947 | FUSE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit. | 04-19-2012 |
20130033951 | STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A FUSEBAY - Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended. | 02-07-2013 |
20130058182 | Method and Apparatus for Programming an Anti-Fuse Element in a High-Voltage Integrated Circuit - A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates | 03-07-2013 |
20130100756 | ELECTRICAL FUSE MEMORY ARRAYS - A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resisivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses. | 04-25-2013 |
20130155799 | ELECTRICAL FUSE MEMORY - A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on. | 06-20-2013 |
20130176805 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 07-11-2013 |
20140071779 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes a program gate line and a word line gate line that are stretched in parallel to each other, and a metal line formed over the program gate line and the word line gate line to cover the program gate line and the word line gate line, the metal line connected to the program gate line through a plurality of contact plugs disposed at a given distance. | 03-13-2014 |
20140071780 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line. | 03-13-2014 |
20140098623 | APPARATUSES AND METHODS FOR SENSING FUSE STATES - Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse. | 04-10-2014 |
20140126318 | INTEGRATED CIRCUIT INCLUDING E-FUSE ARRAY CIRCUIT - An integrated circuit includes a high voltage generator generating a high voltage, a negative voltage generator generating a negative voltage, a divided voltage generator generating a divided voltage by dividing the power source voltage and supplying it to a read voltage terminal, a first power gate supplying the high voltage or the divided voltage to a program voltage terminal, a second power gate supplying the negative voltage or the ground voltage to a deactivation voltage terminal, a third power gate supplying the ground voltage or the divided voltage to an activation voltage terminal, and an e-fuse array circuit operating using voltage of the program voltage terminal as a program voltage, voltage of the divided voltage terminal as a read voltage, voltage of the activation voltage terminal as an activation voltage, and voltage of the deactivation voltage terminal as a deactivation voltage. | 05-08-2014 |
20140140160 | Semiconductor Device - A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element | 05-22-2014 |
20140177373 | SYSTEM INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 06-26-2014 |
20140269135 | CIRCUIT AND SYSTEM FOR CONCURRENTLY PROGRAMMING MULTIPLE BITS OF OTP MEMORY DEVICES - Circuits and systems for concurrently programming a plurality of OTP cells in an OTP memory are disclosed. Each OTP cell can have an electrical fuse element coupled a program selector having a control terminal. The control terminals of a plurality of OTP cells can be coupled to a plurality of local wordlines, and a plurality of the local wordlines can be coupled to at least one global wordline. A plurality of banks of bitlines can have each bitline coupled to a plurality of the OTP cells via the control terminal of the program selector. A plurality of bank selects can enable turning on the wordlines or bitlines in a bank. A plurality of the OTP cells can be configured to be programmable concurrently into a different logic state by applying voltages to at least one selected global wordline and at least one selected bitline to a plurality of the selected OTP cells in a plurality of banks, if a plurality of banks are enabled. | 09-18-2014 |
20140313842 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line. | 10-23-2014 |
20150055427 | MULTI-CORE MICROPROCESSOR CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM - An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores. | 02-26-2015 |
20150055428 | MICROPROCESSOR MECHANISM FOR DECOMPRESSION OF CACHE CORRECTION DATA - An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory. | 02-26-2015 |
20150055429 | APPARATUS AND METHOD FOR COMPRESSION AND DECOMPRESSION OF MICROPROCESSOR CONFIGURATION DATA - An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core. | 02-26-2015 |
20150364161 | ELECTRONIC DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - An electronic device includes a power-up signal generation circuit block suitable for generating a power-up signal during a power-up section of a source voltage, a delay circuit block suitable for generating a plurality of delay signals by sequentially delaying the power-up signal, and a plurality of internal circuit blocks sequentially initialized in response to a corresponding one of the power-up signal and the delay signals. | 12-17-2015 |