Entries |
Document | Title | Date |
20080205182 | Method of operating a memory cell, memory cell and memory unit - A method of operating a memory cell, a memory cell and a memory unit are described. For example, a memory cell comprises a capacitance and an access circuit in association with said capacitance and having an access circuit terminal. The memory cell further includes a voltage control unit to adjust a potential at said access circuit terminal in a retention state such that a retention time of the memory cell is increased. A method of operating a memory cell includes, for example, adjusting a potential at an access circuit terminal of the memory cell to increase a retention time. | 08-28-2008 |
20080205183 | SELF-REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage. | 08-28-2008 |
20080212386 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND REFRESH CONTROL METHOD - A semiconductor memory device comprises: a memory cell array in which memory cells are divided into banks; cache memories each for storing data of a word line selected by a row address; a setting register for setting a data holding capacity so that a holding area where data is held during a self refresh period and a non-holding area where data is not held during the self refresh period are commonly included in each bank; a refresh controller for outputting a row address to be refreshed at predetermined intervals during the self refresh period and for performing a refresh operation for a selected word line corresponding to the row address in an activated bank; and a bank controller for activating all banks when the selected word line is included in the holding area and inactivating all banks when the selected word Line is included in the non-holding area. | 09-04-2008 |
20080219075 | Control of inputs to a memory device - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 09-11-2008 |
20080225619 | SEMICONDUCTOR MEMORY, MEMORY CONTROLLER, SYSTEM, AND OPERATING METHOD OF SEMICONDUCTOR MEMORY - When a main block address held in a memory refresh address counter coincides with an access block address corresponding to an access request, its counter value is transferred to a sub refresh address counter. Thereafter, a sub refresh address counter operates with priority over a main refresh address counter until its counter value reaches a final value. Consequently, an access operation and a refresh operation can be simultaneously executed without interfering with each other. As a result, it is possible to execute the refresh operation with a minimum increase in circuit scale and without any deterioration in access efficiency. | 09-18-2008 |
20080239851 | Flash Memory with Data Refresh Triggered by Controlled Scrub Data Reads - The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less than all of a block in response to a read command from a host or memory controller. The small portion is selected for the scrub read because of its greater vulnerability than other portions of the block to being disturbed as a result of the commanded partial block data read. This then determines, as the result of reading a small amount of data, whether at least some of the data in the block was disturbed by the command data read to a degree that makes it desirable to refresh the data of the block. | 10-02-2008 |
20080239852 | Test feature to improve DRAM charge retention yield - In some embodiments, a design for test feature to improve DRAM charge retention yield is presented. In this regard, an apparatus is introduced comprising a first integrated circuit die, and a second integrated circuit die stacked together in a package, wherein the second integrated circuit die comprises a dynamic random access memory (DRAM) and circuitry to increase a refresh rate provided by a self refresh timer by a predetermined percentage. Other embodiments are also disclosed and claimed. | 10-02-2008 |
20080239853 | Semiconductor memory device - A semiconductor memory device includes a command decoder, a refresh address counter, an address delivery unit, and an address output selector. The command decoder decodes a command signal to generate a refresh signal. The refresh address counter generates a refresh address in response to the refresh signal. The address delivery unit delivers one of the refresh address and an address from outside of the semiconductor memory device to a memory core area. The address output selector outputs the refresh address to the outside of the semiconductor memory device. | 10-02-2008 |
20080239854 | SEMICONDUCTOR MEMORY, SYSTEM, AND OPERATING METHOD OF SEMICONDUCTOR MEMORY - Partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input and is output as a partial set signal. A refresh request signal is output periodically corresponding to a memory block for which a refresh operation is enabled. The partial set signal is masked so as to enable a refresh operation for all of the memory blocks during a period in which the partial refresh information is changed by the external input. Thus, it is possible to prevent disabling of a refresh operation in response to a refresh request even when timing of changing the partial refresh information and timing of occurrence of the refresh request signal overlap. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented. | 10-02-2008 |
20080239855 | Semiconductor memory device performing self refresh operation - The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command and therefore it is possible to implement a simple circuit for the self refresh. A semiconductor memory device includes a self refresh enable signal generator for outputting an activated self refresh enable signal when positive and negative external clock signals are in phase and a de-activated self refresh enable signal when the positive and negative external clock signals are out of phase and a self refresh block for performing a self refresh operation in response to the activated self refresh enable signal. | 10-02-2008 |
20080247256 | REFRESH SIGNAL GENERATOR OF SEMICONDUCTOR MEMORY DEVICE - A refresh signal generator generates an internal refresh signal to conduct a refresh with an interval controlled based on PVT fluctuations. The refresh signal generator includes a temperature sensing unit for sensing an internal temperature and activating a corresponding signal of a plurality of temperature sensing signals in response to a temperature sense driving signal, a power supply selecting unit for driving a driving voltage supply terminal to one of different voltage levels according to the plurality of temperature sensing signals, and an internal refresh signal generating unit for receiving a driving voltage from the power supply selecting unit and producing internal refresh signals at a constant interval. | 10-09-2008 |
20080253212 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks. The refresh word line counter generates a common word line address that is common to the at least two memory blocks. The arbitration circuit generates at least one first word line address based on the at least two block addresses and the common word line address and arbitrate so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed. | 10-16-2008 |
20080253213 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME - A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized. | 10-16-2008 |
20080259708 | MEMORY CONTROLLER - A memory controller for controlling data access to a memory comprises a refresh controller. A read count memory part included in the refresh controller counts the number of read operations on each page of the memory and stores the read count therein. If the read count for any page exceeds a predetermined number, the refresh controller rewrites data stored in this page into the memory. | 10-23-2008 |
20080259709 | Column redundancy circuit - A column redundancy circuit is disclosed. The column redundancy circuit includes a first control signal generator configured to receive a refresh flag signal having an enable width larger than that of a refresh signal and a control signal and generate a pull-up control signal, a second control signal generator configured to receive the refresh flag signal and an address signal and generate a pull-down control signal, and a column repair fuse circuit configured to receive the pull-up control signal and the pull-down control signal and generate a redundant cell access signal. | 10-23-2008 |
20080273409 | Junction field effect dynamic random access memory cell and applications therefor - A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell. | 11-06-2008 |
20080273410 | Tungsten digitlines - Methods, devices, and systems for using and forming tungsten digitlines have been described. The tungsten digitlines formed according to embodiments of the present disclosure can be formed with a tungsten (W) monolayer on a tungsten nitride (WN | 11-06-2008 |
20080279028 | FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY - A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline. | 11-13-2008 |
20080285370 | Semiconductor memory and system - An access control unit performs an access operation and a refresh operation of a memory block in response to an access request and a refresh request. The access control unit operates respective memory blocks in a single-cell mode or a twin-cell mode according to cell mode information in a mode setting unit. A refresh control unit disables the refresh operation of the memory block the nonperformance of which is set in the mode setting unit. By operating only the memory block requiring high reliability in the twin-cell mode and selectively disabling the refresh operation of the memory block, a semiconductor memory can be operated optimally according to a specification of a system, enabling a reduction in power consumption. | 11-20-2008 |
20080291765 | Methods, circuits, and systems to select memory regions - Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location. | 11-27-2008 |
20080298152 | POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed. | 12-04-2008 |
20080298153 | Semiconductor memory device - The present invention provides a semiconductor memory device with an open bit line structure in which sense amplifiers are arranged in a zigzag pattern and a plurality of banks, each having a plurality of mats, are provided. The semiconductor memory device includes: a refresh counter that counts the number of refresh commands and generates word line addresses; pre-decoders, each of which is provided for a corresponding bank, and which pre-decodes the word line address and outputs a pre-decode signal for selecting a mat row; bit arrangement changing circuits each of which changes the arrangement of bits of the pre-decode signal when a refresh signal indicating a refresh operation is input; and X decoders each of which outputs signals for driving a mat row and a word line according to the pre-decode signal and the word line address. | 12-04-2008 |
20080298154 | Semiconductor memory device - A semiconductor memory device includes: a plurality of banks each of which includes a plurality of mats each having normal word lines and redundant word lines; a first refresh generating circuit that generates a first refresh start signal for performing a first refresh operation in response to input of a refresh command; and a second refresh generating circuit that generates a second refresh start signal for performing a second refresh operation in response to a refresh operation end signal indicating that the first refresh operation ends. | 12-04-2008 |
20080316848 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREFOR - This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies and storing therein logic data; bit lines and word lines connected to the memory cells; sense amplifiers connected to the bit lines; a refresh controller instructing a refresh operation for restoring deteriorated storage states of the memory cells; and a refresh interval timer setting a refresh interval between one refresh operation and a next refresh operation to a first interval in a data read mode or a data write mode, and setting the refresh interval to a second interval longer than the first interval in a data retention mode, the data read mode being a mode in which the data stored in the selected memory cell is read to an outside of the device, the data write mode being a mode in which data from the outside is written to the selected memory cell. | 12-25-2008 |
20080316849 | MEMORY DRIVING METHOD AND SEMICONDUCTOR STORAGE DEVICE - This disclosure concerns a method of driving a memory including memory cells, bit lines, and word lines, each memory cell having a source, a drain, and a floating body, the method comprising performing a refresh operation for recovering deterioration of first logical data of the memory cells and deterioration of second logical data of the memory cells, wherein in the refresh operation, the number of the carriers injected into the floating body is larger than the number of the carriers discharged from the floating body when a potential at the floating body is larger than a critical value, and the number of the carriers injected into the floating body is smaller than the number of the carriers discharged from the floating body when the potential at the floating body is smaller than the critical value. | 12-25-2008 |
20090016134 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory comprising memory cells; word lines connected to gates of the cells; n bit lines connected to the memory cells; sense amplifiers connected to the bit lines; refresh cells provided to correspond to the word lines, respectively, and provided to correspond to k bit lines, where k is a natural number smaller than n, one of the refresh cells storing therein refresh data indicating whether to perform a refresh operation on k memory cells out of the plural memory cells connected to a corresponding word line out of the plural word lines and connected to the k bit lines, respectively; a refresh sense amplifier reading the refresh data; and a refresh selection part provided to correspond to the refresh sense amplifier, and selecting whether to perform the refresh operation on the k memory cells according to the refresh data read by the refresh sense amplifier. | 01-15-2009 |
20090016135 | OSCILLATING DEVICE, METHOD OF ADJUSTING THE SAME AND MEMORY - An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference number, is provided. | 01-15-2009 |
20090016136 | OSCILLATION DEVICE, METHOD OF OSCILLATION, AND MEMORY DEVICE - An oscillation device includes a first setting unit that outputs an oscillation period designation signal, a calculating unit that performs an arithmetic operation on the oscillation period designation signal, and an oscillating unit that generates an oscillation signal having a period based on the oscillation period designation signal subjected to the arithmetic operation. | 01-15-2009 |
20090022003 | MEMORY CELL STRUCTURES, MEMORY ARRAYS, MEMORY DEVICES, MEMORY CONTROLLERS, AND MEMORY SYSTEMS, AND METHODS OF MANUFACTURING AND OPERATING THE SAME - Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation. | 01-22-2009 |
20090027989 | System and Method to Reduce Dynamic Ram Power Consumption via the use of Valid Data Indicators - A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation is directed to the associated memory, the refresh operation is suppressed if the memory does not contain valid data. Significant power savings may be realized by suppressing refresh operations directed to invalid data. | 01-29-2009 |
20090040856 | SEMICONDUCTOR MEMORY DEVICE CHANGING REFRESH INTERVAL DEPENDING ON TEMPERATURE - A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit. | 02-12-2009 |
20090046531 | CIRCUIT AND METHOD FOR CONTROLLING REFRESH PERIODS IN SEMICONDUCTOR MEMORY DEVICES - An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device. | 02-19-2009 |
20090073793 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME - A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized. | 03-19-2009 |
20090073794 | Method for Hiding a Refresh in a Pseudo-Static Memory - A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-array | 03-19-2009 |
20090080278 | CIRCUIT AND METHOD FOR REDUCING POWER IN A MEMORY DEVICE DURING STANDBY MODES - A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device. | 03-26-2009 |
20090086560 | MEMORY DEVICE WITH SELF REFRESH CYCLE CONTROL FUNCTION - Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent upon a temperature variation, a comparing unit for comparing the first voltage with the second voltage to provide a comparison result signal, and a self refresh signal generating unit for receiving a self refresh entry signal and generating a self refresh signal of temperature compensated cycle under the control of the comparison result signal. | 04-02-2009 |
20090091997 | SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR MOUNTING ON PORTABLE TERMINAL - A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register. | 04-09-2009 |
20090103383 | DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION - A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application. | 04-23-2009 |
20090103384 | APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS - A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array. | 04-23-2009 |
20090109781 | DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE - An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential. | 04-30-2009 |
20090109782 | TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT - A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The timer is configured to generate a time-out signal, which is affected by one of the temperature-dependent voltage. The clock-driven recorder has a clock input terminal in response to the clock signal and time-out signal. | 04-30-2009 |
20090109783 | Refresh controlling circuit - A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal and a second address signal with a pulse signal, a bank active control unit configured to output a bank active signal in response to the mask information signal of the bank, and a decoding unit configured to output a row address decoding signal in response to the bank active signal, the mask information signal of the segment, and a third address signal. | 04-30-2009 |
20090109784 | Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same - An access area is set within an address space of a dynamic random access memory by arranging two or more complete columns of blocks, in which blocks of memory cells are arranged within an entirety of a specified range of row addresses, along a direction of column addresses. Each of the blocks includes memory cells positioned at a same row address and a specified number of consecutive column addresses. The total number of blocks arranged in the access area is just capable of storing the number of words of the data to be stored. The two or more complete columns of blocks are successively accessed by successively accessing the blocks arranged in each of the columns of blocks. Thereby, a refresh operation of the dynamic random access memory is made unnecessary. | 04-30-2009 |
20090116326 | Semiconductor memory device capable of performing per-bank refresh - A semiconductor memory device is provided that can support a per-bank refresh as well as an all-bank refresh and a self refresh. The semiconductor memory device includes an address counting unit for counting a bank address signal of a specific bank and row address signals of the specific bank in response to a control signal including refresh mode information when a per-bank refresh command is lo received, and for counting row address signals in response to the control signal when an all-bank refresh command or a self refresh command is received. | 05-07-2009 |
20090122631 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF-REFRESH - A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time. | 05-14-2009 |
20090141575 | Method and Apparatus for Idle Cycle Refresh Request in Dram - Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions. | 06-04-2009 |
20090141576 | METHOD OF REFRESHING DATA IN A STORAGE LOCATION - An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate. | 06-04-2009 |
20090147606 | MEMORY REFRESH METHOD AND APPARATUS - An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation. | 06-11-2009 |
20090147607 | RANDOM ACCESS MEMORY AND DATA REFRESHING METHOD THEREOF - A random access memory and a data refreshing method thereof are provided. The random access memory includes a memory array having a plurality of word lines; a control logic unit which is used for outputting a refreshment indicating signal, a thermal sensor which is used for outputting a temperature indicating signal; a refresh counter which is used for outputting a row address counting signal; and a row address decoder which is used for performing a decoding operation on the row address counting signal in response to the refreshment indicating signal and the temperature indicating signal, and simultaneously enabling the plurality of word lines of the memory array based on a result of the decoding operation. | 06-11-2009 |
20090147608 | POWER MANAGEMENT CONTROL AND CONTROLLING MEMORY REFRESH OPERATIONS - A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation. | 06-11-2009 |
20090154276 | Auto-refresh controlling apparatus - An auto-refresh control apparatus is provided which includes a counter unit for outputting counter signals in response to an external auto-refresh command signal, and a refresh command signal generating unit for generating internal auto-refresh command signals in response to the counter signals when a test mode signal is activated. | 06-18-2009 |
20090154277 | METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RELATED MEMORY - The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period. | 06-18-2009 |
20090154278 | MEMORY DEVICE WITH SELF-REFRESH OPERATIONS - An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh. | 06-18-2009 |
20090154279 | REFRESH PERIOD SIGNAL GENERATOR WITH DIGITAL TEMPERATURE INFORMATION GENERATION FUNCTION - A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by using a first period signal and a second period signal, a refresh period signal generating part configured to output a refresh period signal by selecting one signal having a shorter period between the first period signal and the second period signal, and an operation timing control part operating the temperature information generating part and the refresh period signal generating part at a predetermined timing. | 06-18-2009 |
20090161466 | EXTENDING FLASH MEMORY DATA RETENSION VIA REWRITE REFRESH - Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate. | 06-25-2009 |
20090161467 | MEMORY DEVICE AND REFRESH METHOD THEREOF - A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to the memory rows. When a row refresh strobe (RRS) signal is received, it is determined whether to refresh one of the memory rows according to a plurality of parameters including a value of a row to refresh counter, a value of a refresh deadline counter and/or a queue. When it is decided to start a refresh operation, one of the memory rows is selected according to the tag flag and the status, and the status of the selected memory row is updated after the selected memory row is refreshed. | 06-25-2009 |
20090161468 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND MEMORY ACCESS CONTROL METHOD - A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal. | 06-25-2009 |
20090161469 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM - The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that includes a circuit having a similar configuration to the first buffer circuit, that outputs a second output signal on receipt of the first input signal, and that outputs the second output signal based on a check signal; a third buffer circuit that outputs a third output signal based on the check signal; a determination circuit that receives the second output signal and the third output signal and activates a detection signal, in response to the detection that the second output signal is behind the third output signal; and a fourth buffer circuit that operates during the activation of the detection signal and outputs the third output signal to the output terminal, on receipt of the first input signal. | 06-25-2009 |
20090180344 | Self-refresh period measurement circuit of semiconductor device - A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a delay means for delaying the received oscillation signal by a unit self-refresh period to output a first delayed oscillation signal, and delaying the received oscillation signal to output a third delayed oscillation signal, a first period measurement start signal generator for generating a first period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a first refresh period output unit for generating a first refresh period output signal that is enabled for a period from a time that the first period measurement start signal is enabled to a time that the first delayed oscillation signal is enabled for the first time. | 07-16-2009 |
20090201757 | SEMICONDUCTOR DEVICE - Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh. | 08-13-2009 |
20090238020 | INTEGRATED CIRCUIT INCLUDING MEMORY REFRESHED BASED ON TEMPERATURE - An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature. | 09-24-2009 |
20090238021 | Semiconductor memory device and operation method therefor - Disclosed herein is a semiconductor memory device, including: a memory array section wherein a memory array which requires a refresh operation is formed; an interface section configured to carry out an interfacing process between an external apparatus and the memory array section; and a refresh control block for controlling the refresh operation; the interface section configured to include a plurality of interface modules individually corresponding to a plurality of memory types and selectively applied to the interfacing process between the external apparatus and the memory array section; the refresh control block having a function of issuing a refresh command within a refresh cycle and another function of preventing, if, upon issuance of the refresh command, an access command and the refresh command to the memory array are estimated to collide with each other, the collision. | 09-24-2009 |
20090245004 | SEMICONDUCTOR DEVICE INCLUDING MULTI-CHIP - In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding. | 10-01-2009 |
20090251982 | Low Energy Memory Component - The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for amplifying a voltage difference between two bit lines coupled to the sense amplifier. As a result, the heat produced by the self-refresh operation is only a fraction of the heat produced by the conventional self-refresh powered by the substantially invariant power supply voltage. | 10-08-2009 |
20090257299 | SOFTWARE REFRESHED MEMORY DEVICE AND METHOD - A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation. For example, the processor can determine whether each individual memory cell needs to be refreshed, thereby advantageously avoiding performing unnecessary refresh operations on memory cells that do not need to be refreshed. | 10-15-2009 |
20090268539 | Chip, Multi-Chip System in a Method for Performing a Refresh of a Memory Array - A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh of the memory array only once per i of the received refresh trigger signals where i is a number greater than 1. | 10-29-2009 |
20090279373 | AUTO-REFRESH OPERATION CONTROL CIRCUIT FOR REDUCING CURRENT CONSUMPTION OF SEMICONDUCTOR MEMORY APPARATUS - An auto-refresh operation control circuit for a semiconductor memory apparatus is activated according to a bank active signal for executing a refresh operation and terminates the refresh operation by receiving a precharge signal. The auto-refresh operation control circuit is configured to prevent an over-driving operation during an auto-refresh operation and to delay the enablement of the precharge signal. The auto-refresh operation control circuit also delays the enablement of the precharge signal during the auto-refresh operation more than a delay of the precharge signal during a self-refresh operation. | 11-12-2009 |
20090296509 | VOLTAGE REGULATOR CIRCUIT FOR A MEMORY CIRCUIT - A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor. | 12-03-2009 |
20090296510 | Semiconductor memory device having refresh circuit and word line activating method therefor - A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block. | 12-03-2009 |
20090303824 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS - A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time. | 12-10-2009 |
20090316511 | Method and Apparatus for Selectively Disabling Termination Circuitry - In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry re-enables the termination circuitry prior to the electronic device performing a relatively high frequency operation after completion of the low frequency operation, the high frequency operation causing substantial signal reflections at the I/O signals. The electronic device is a memory device in one embodiment. This way, the termination circuitry may be disabled during at least a portion of a refresh operation performed by the memory device and re-enabled prior to the memory device resuming normal operation (i.e., reads and writes) after completion of the refresh operation. | 12-24-2009 |
20090323449 | CIRCUIT AND METHOD FOR CONTROLLING SELF-REFRESH CYCLE - The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature. | 12-31-2009 |
20100008173 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal. | 01-14-2010 |
20100014371 | CIRCUIT AND METHOD FOR CONTROLLING A CLOCK SYNCHRONIZING CIRCUIT FOR LOW POWER REFRESH OPERATION - A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete. | 01-21-2010 |
20100014372 | Semiconductor Device, an Electronic Device and a Method for Operating the Same - A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state. | 01-21-2010 |
20100027363 | REFRESH CONTROLLER AND REFRESH CONTROLLING METHOD FOR EMBEDDED DRAM - The present invention provides a refresh controller for embedded DRAM, configured to receive an external access signal and generate refresh enabling signal REFN, refresh address signal CRA and confliction signal, said embedded DRAM comprising a plurality of memory groups, said controller comprising: a status controlling module that generates refresh enabling signal REFN and last refresh signal last_ccr according to the refresh interval and clock cycles; a refresh searching module that searches in said plurality of memory bank groups for at least one memory bank group that is to be refreshed in the refresh interval, and generates refresh address signal CRA according to the external access signal and the searched memory bank group; a scoreboard module that records the status of each of said plurality of memory bank groups according to said refresh address signal CRA and external access signal; and a confliction detecting module that generates confliction signal according to said external access signal, last refresh signal last_ccr and the status of each of said memory banks. A corresponding refresh controlling method is also provided in the present invention. | 02-04-2010 |
20100027364 | MULTI-PORT MEMORY DEVICE HAVING SELF-REFRESH MODE - The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal. | 02-04-2010 |
20100034041 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE - Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state. | 02-11-2010 |
20100054070 | METHOD AND SYSTEM FOR CONTROLLING REFRESH TO AVOID MEMORY CELL DATA LOSSES - A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier. | 03-04-2010 |
20100061173 | AUTO-REFRESH CONTROL CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE USING THE SAME - An auto-refresh control circuit includes a control signal generating section configured to simultaneously or individually enable first and second control signals in response to an information combination signal having refresh information and operation mode information and first and second chip selection signals, and an auto-refresh signal generating section configured to generate first and second auto-refresh signals in response to a plurality of command signals and the first and second control signals. | 03-11-2010 |
20100074042 | SEMICONDUCTOR MEMORY DEVICE - A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines. | 03-25-2010 |
20100080075 | Memory Device Refresh Method and Apparatus - In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks. | 04-01-2010 |
20100097874 | METHOD AND APPARATUS FOR PERFORMING REFRESHES - A method of operating a system including a memory device. The method includes, upon receiving a request for an internal hidden refresh for the memory device, latching external command, address, and data information for the memory device. The method further includes placing the memory device in a standby state and during the standby state, performing the internal hidden refresh. The method further includes, after performing the internal hidden refresh, placing the memory device in a state corresponding to the latched external command, address, and data information for the memory device. | 04-22-2010 |
20100110816 | TECHNIQUES FOR BLOCK REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for block refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for block refreshing a semiconductor memory device. The method may comprise arranging a plurality of memory cells in one or more arrays of rows and columns. Each of the plurality of memory cells may comprise a first region coupled to a source line, a second region, a first body region disposed between the first region and the second region, wherein the body region may be electrically floating and charged to a first predetermined voltage potential, and a first gate coupled to a word line, wherein the first gate may be spaced apart from, and capacitively coupled to, the first body region. The method may also comprise applying voltage potentials to the plurality of memory cells to refresh a plurality of data states stored in the plurality of memory cells. | 05-06-2010 |
20100110817 | Semiconductor device and refreshing method - A semiconductor device comprising a word line wired on a memory bank, a memory cell storing data provided in correspondence with the word line and a sense amplifier provided in correspondence with the word line, refreshing the memory cell corresponding to the word line selected by a row address that has been generated, including refresh counter | 05-06-2010 |
20100110818 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation. | 05-06-2010 |
20100124138 | Semiconductor memory device having variable-mode refresh operation - A semiconductor memory device includes a bit line sense amplifier, a bit line pair that includes a bit line and a complementary bit line, the bit line and the complementary bit line of the bit line pair each being coupled to the bit line sense amplifier, a memory cell array having a plurality of memory banks, the memory banks including word lines and a plurality of memory cells, and a word line activation control unit that performs a control to access data corresponding to an externally same address in at least two memory cells by simultaneously activating a predetermined number of word lines from among the word lines sharing the bit line sense amplifier, and the word line activation control unit operates in response to a determination mode allowing signal that is set in accordance with a used memory density. | 05-20-2010 |
20100128547 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD OF MEMORY SYSTEM - There are provided a semiconductor memory device and others having a preferable operation efficiency and eliminating complicated control when refreshing a memory array divided into a plurality of banks. The semiconductor memory device includes a memory array ( | 05-27-2010 |
20100128548 | SEMICONDUCTOR DEVICE AND METHOD OF REFRESHING THE SAME - A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines. | 05-27-2010 |
20100142304 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF-REFRESH - A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time. | 06-10-2010 |
20100157711 | Self-Refresh Based Power Saving Circuit and Method - A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the adjustable impedance circuit in response to the impedance control signal. In addition, the self-refresh adjustable impedance driver circuit provides a memory interface signal based on the memory self-refresh information. | 06-24-2010 |
20100157712 | REFRESH CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A refresh circuit of a semiconductor memory apparatus includes a bank active signal generator configured to selectively enable a plurality of bank active signals in response to a piled signal and disable the plurality of bank active signals in response to a plurality of precharge pulses when a refresh signal is enabled; a precharge pulse generator configured to generate a plurality of preliminary precharge pulses in response to the plurality of bank active signals; a delaying unit configured to generate a plurality of preliminary delay precharge pulses by delaying the plurality of preliminary precharge pulses; and a selecting unit configured to selectively output the plurality of preliminary precharge pulses or the plurality of preliminary delay precharge pulses as the plurality of precharge pulses in response to the piled signal. | 06-24-2010 |
20100157713 | Semiconductor device with refresh control circuit - In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state. | 06-24-2010 |
20100157714 | APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS - A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array. | 06-24-2010 |
20100165773 | SEMICONDUCTOR MEMORY DEVICE FOR SELF REFRESH AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle. | 07-01-2010 |
20100172200 | MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM - Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks. | 07-08-2010 |
20100177583 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY CONTROLLER, AND REFRESH CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device performs a refresh operation in response to an externally supplied signal during the power-down mode. A memory system has a plurality of the semiconductor devices and a memory controller. The memory controller outputs a control signal during the power-down mode, and the plurality of semiconductor devices perform a refresh operation in response to the control signal during the power-down mode. | 07-15-2010 |
20100182862 | Semiconductor memory device and method of controlling auto-refresh - Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected. | 07-22-2010 |
20100182863 | SEMICONDUCTOR MEMORY DEVICE - A conventional semiconductor memory device may be in need of a special refresh sequence if it is desired to reduce the current consumption in connection with a refresh operation. With this in view, there is disclosed a semiconductor memory device | 07-22-2010 |
20100182864 | SEMICONDUCTOR MEMORY DEVICE REQUIRING REFRESH OPERATION - To provide a plurality of memory banks, each of which is divided into a plurality of segments; a bank address register that designates a memory bank that becomes a refresh target; a segment address register that designates a segment that becomes a refresh target; and a refresh control circuit that prohibits a refresh operation of the memory bank or the segment not designated by at least one of the bank address register and the segment address register. This semiconductor device is capable of designating whether to perform a refresh operation not only in a memory bank unit but also in a segment unit within the memory bank, and thus it achieves a further reduction of the power consumption. | 07-22-2010 |
20100188914 | SELF REFRESH OPERATION OF SEMICONDUCTOR MEMORY DEVICE - A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires. | 07-29-2010 |
20100188915 | SELF REFRESH OPERATION OF SEMICONDUCTOR MEMORY DEVICE - A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires. | 07-29-2010 |
20100195429 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided between a refresh request circuit and a command decoder, and includes a refresh synchronous circuit for deactivating a refresh request if an external access request is output from the command decoder. The semiconductor memory device further includes a clock phase adjusting unit that generates a delay to a clock, where the delay is same or longer than the time taken from when the external access request is issued until when a critical path is passed, and the delay is also shorter than one cycle. Then a flip-flop retrieves the request from the command decoder at the clock timing from the clock phase adjusting unit to supply it to the memory cell array. | 08-05-2010 |
20100202232 | REFRESHING METHOD - A refreshing method suitable for a memory device is provided which includes the following steps. A sleep mode is set and the memory device cannot be read and programmed in the sleep mode. A first and a second memory cell arrays are sequentially auto-refreshed, and the steps for auto-refreshing each of the first and the second memory cell arrays individually include: during an equalization period, switching the potential of a sense line pair, a first bit line pair and a second bit line pair to a reference voltage wherein the sense line pair is not coupled to the second bit line pair, and during a refreshing period, adjusting the potential of the first and the second bit line pairs according to a refresh sequence of the first and the second memory cell arrays, thereby coupling the sense line pair to one of the first and the second bit line pairs. | 08-12-2010 |
20100202233 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor storage device includes a timing allocation unit that sets refresh timing to preferentially perform a refresh operation for maintaining data and data access timing to preferentially perform a data access operation for reading or writing the data in accordance with a clock signal with respect to each memory bank including a plurality of memory cells, and a waiting unit that waits start of the data access operation until the data access timing is started in a case where a request for the data access operation is made during the refresh timing and waits start of the refresh operation until the refresh timing is started in a case where a request for the refresh operation is made during the data access timing. | 08-12-2010 |
20100232246 | REFRESH CONTROL CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY APPARATUS - A refresh control circuit of a semiconductor memory apparatus includes: a variable oscillator configured to generate a room-temperature oscillation signal and a limit-temperature oscillation signal in response to a temperature state signal; a cycle selector configured to selectively output the room temperature oscillation signal and the limit-temperature oscillation signal as a variable oscillation signal in response to the temperature state signal; a refresh signal generator configured to generate a refresh signal in response to the variable oscillation signal and a fixed oscillation signal; and a temperature state detector configured to generate the temperature state signal by detecting current temperature in response to the room-temperature oscillation signal and the fixed oscillation signal. | 09-16-2010 |
20100232247 | DATA STORAGE APPARATUS AND CONTROL METHOD OF DATA STORAGE APPARATUS - In a data storage apparatus having data storage means, if it is judged that a condition of transitioning the data storage apparatus into a power saving state is established, it is controlled so that states of signals to be output by operation control means of controlling an operation of the data storage means to plural signal lines are fixed to a specific signal state, and supply of a reference voltage by reference voltage supply means to the plural signal lines is stopped. | 09-16-2010 |
20100238750 | CONTROL OF INPUTS TO A MEMORY DEVICE - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 09-23-2010 |
20100246304 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD - A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by a predetermined number of times corresponding to the number of word lines to be refreshed in response to the refresh instruction; a bank address counter that holds a bank address for selecting a memory bank to be refreshed, counts up the bank address every time the refresh command signal is output, and performs a carry-over action when count-up operations equivalent to the number of the memory banks are performed; and a row address counter that holds a row address for selecting a word line to be refreshed, and counts up the row address in response to the carry-over action. | 09-30-2010 |
20100254208 | SEMICONDUCTOR MEMORY DEVICE, REFRESH CONTROL METHOD THEREOF, AND TEST METHOD THEREOF - The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system. | 10-07-2010 |
20100260003 | SEMICONDUCTOR MEMORY APPARATUS AND REFRESH CONTROL METHOD OF THE SAME - A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal. | 10-14-2010 |
20100265784 | ADDRESS CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - An address control circuit for a semiconductor memory apparatus so as to make a refresh operation test possible by designating a refresh address is presented. The circuit includes a buffer block, a decoder, and a latch block. The buffer block receives coding information coded testing address information in accordance to a test signal. The decoder generates a test refresh address by decoding the coding information. The latch block latches the test refresh address depending on the test signal. | 10-21-2010 |
20100271895 | SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities - An SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities includes a memory cell array comprised of a plurality of single-port memory cells with dual-port capability, a first and a second port access units connected to the memory cell array in order to access the memory cells, and an access arbiter connected to the first and the second port access units in order to arbitrate a first port access request, a second port access request and a hidden refresh request. | 10-28-2010 |
20100271896 | MEMORY MALFUNCTION PREDICTION SYSTEM AND METHOD - A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells. | 10-28-2010 |
20100296356 | CIRCUIT FOR GENERATING REFRESH PERIOD SIGNAL AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - Circuits for generating refresh period signals and semiconductor integrated circuits using the same are presented. The refresh period signal generation circuit can include an oscillator, a pulse generation unit, and a signal controller. The oscillator is configured to generate an oscillation signal in response to a refresh duration correction signal. The pulse generation unit is configured to generate a refresh period signal in response to the oscillation signal. The signal controller configured to generate the refresh duration correction signal, which corrects an active time of a refresh duration signal, in response to the oscillation signal. | 11-25-2010 |
20100302889 | SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a plurality of memory cells, a refresh request generator circuit for generating a refresh request signal to refresh the plurality of memory cells based on a number of clock cycles elapsed in a clock signal, a clock cycle detector circuit for detecting the clock cycle of the clock signal, and a refresh controller circuit for controlling a number of memory cells to refresh from among the plurality of memory cells, in accordance with the detected clock cycle. | 12-02-2010 |
20100329060 | COUNTER CONTROL SIGNAL GENERATOR AND REFRESH CIRCUIT - A counter control signal generator comprises a first pulse signal generator configured to generate a first pulse signal including a pulse generated when a self-refresh period is terminated, a second pulse signal generator configured to generate a second pulse signal including a pulse generated in sync with a cyclic signal generated during a refresh period, and a signal generator configured to generate a counter control signal counting an address of a memory cell, corresponding to a memory cell on which a refresh operation is conducted, in response to the first and second pulse signals. | 12-30-2010 |
20110002185 | Semiconductor device with control circuit controlling controlled circuit to the same potential - A device includes a first circuit, a second circuit, and a control circuit controlling the first and the second circuits. The control circuit controls a plurality of output signals of the second circuit so as to have the same potential when the control circuit activates the first circuit and inactivates the second circuit. | 01-06-2011 |
20110007592 | Semiconductor storage device and refresh control method thereof - In a large capacity semiconductor storage device having a multi-bank configuration, it is desired to reduce a peak current of one refresh operation, to avoid an interference between adjacent banks, and to prevent a data breaking of a memory cell caused by a lack of a data hold time. A semiconductor storage device includes: a memory cell array part including a plurality of banks; a refresh control circuit configured to output a refresh timing control signal periodically; and an access control circuit configured to perform a refresh operation on a group of banks which are not adjacent to one another in accordance with a preset combination of banks which are simultaneously activated and a preset activating order when the refresh timing control signal is supplied. | 01-13-2011 |
20110007593 | Semiconductor memory device and access method - A semiconductor memory device includes a memory comprising a plurality of banks; an input section configured to input an address of a bank address, a row address and a column address; and a command generating circuit configured to issue one of a read command, a write command, and a refresh command based on to an input signal. A control section selects a selection bank from the plurality of banks based on the bank address when the read command or the write command is issued from the command generating circuit, performs a read operation or a write operation on the selection bank based on the row address and the column address, and performs a refresh operation on the selection bank when the refresh command is issued immediately after the read command or the write command. | 01-13-2011 |
20110007594 | MULTI-CHANNEL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF REFRESHING THE SAME - A multi-channel semiconductor memory device and a method of refreshing the same. In the multi-channel semiconductor memory device and method, a common refresh controller is prepared to detect refresh operation states of a plurality of sub-memory circuits (e.g. ICs) and to adjust refresh operation times of multiple sub-memory ICs so that two or more sub-memory ICs do not simultaneously perform a refresh operation, thereby reducing the peak current. | 01-13-2011 |
20110026351 | METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RELATED MEMORY - The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period. | 02-03-2011 |
20110026352 | METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RELATED MEMORY - The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period. | 02-03-2011 |
20110026353 | DATA REFRESH FOR NON-VOLATILE STORAGE - Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element. | 02-03-2011 |
20110058437 | Clock generating circuit, semiconductor device including the same, and data processing system - A clock generating circuit includes a delay line that generates an internal clock signal, a phase-controlling unit that adjusts a phase of the internal clock signal by controlling the delay line, and a mode switching circuit that switches an operation mode of the phase-controlling unit. The phase-controlling unit has a first operation mode in which a phase of the internal clock signal is changed in synchronization with a sampling clock signal and a second operation mode in which the phase of the internal clock signal is fixed. The mode switching circuit shifts the phase-controlling unit to the first operation mode in response to a trigger signal, such as a refresh signal, and, shifts the phase-controlling unit to the second operation mode in a state where the internal clock signal attains a predetermined phase. | 03-10-2011 |
20110058438 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD OF MEMORY SYSTEM - There are provided a semiconductor memory device and others having a preferable operation efficiency and eliminating complicated control when refreshing a memory array divided into a plurality of banks. The semiconductor memory device includes a memory array ( | 03-10-2011 |
20110069572 | ROW ADDRESS CODE SELECTION BASED ON LOCATIONS OF SUBSTANDARD MEMORY CELLS - A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together. | 03-24-2011 |
20110069573 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a plurality of bank sets and an address controller. Each bank set includes a plurality of banks Each bank includes a plurality of memory mats and sense amplifier arrays corresponding to row addresses. The plurality of bank sets is arranged in both sides of arrays of power electrode pads to be used for operations of the sense amplifier arrays. The plurality of bank sets commonly shears the arrays of power electrode pads. The address controller generates different row addresses that are supplied to different ones of the plurality of bank sets. The different row addresses designate different memory mats in the different ones of the plurality of bank sets, so as to designate different arrays of the power electrode pads for the different ones of the plurality of bank sets for refresh operation in accordance with an external refresh command. | 03-24-2011 |
20110085398 | Multiple Cycle Memory Write Completion - A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. | 04-14-2011 |
20110103169 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS - A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time. | 05-05-2011 |
20110110175 | MEMORY REFRESH SYSTEM AND OPERATING METHOD THEREOF - A memory refresh system includes a comparative detection circuit, a logic circuit, and a timing circuit. The comparative detection circuit detects a voltage of the storage capacitor of a memory cell of the memory and generates a corresponding digital code by comparing the voltage with a reference voltage. Each memory cell has a corresponding digital code. The combination of the digital codes of the memory cells forms a first state. After a specific period of time, the voltages of the storage capacitors of the memory cells are once detected by the comparative detection circuit, and corresponding digital codes are generated and combined to form a second state. The logic circuit compares the first state and the second state to determining whether or not to change the refresh period of a refresh period detecting process. The timing circuit changes the refresh period according to the determination result of the logic circuit. | 05-12-2011 |
20110116335 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block. | 05-19-2011 |
20110134714 | SEMICONDUCTOR MEMORY DEVICE CHANGING REFRESH INTERVAL DEPENDING ON TEMPERATURE - A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit. | 06-09-2011 |
20110141836 | TECHNIQUES FOR REDUCING IMPACT OF ARRAY DISTURBS IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing impact of array disturbs in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for reducing impact of array disturbs in a semiconductor memory device by increasing the refresh rate to the semiconductor memory device based at least in part on a frequency of active operations. The method may comprise receiving a first refresh command including a first subarray address to perform a first refresh operation to a first logical subarray of memory cells associated with the first subarray address. The method may also comprise receiving a second refresh command including a second subarray address to perform a second refresh operation to a second logical subarray of memory cells associated with the second subarray address, wherein the second refresh command is received after a time period from the reception of the first refresh command. The method may further comprise performing a number of concurrent refresh operations during the time period. | 06-16-2011 |
20110158024 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals. | 06-30-2011 |
20110170367 | DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION - A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application. | 07-14-2011 |
20110194369 | VARIABLE MEMORY REFRESH DEVICES AND METHODS - Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate. | 08-11-2011 |
20110205826 | Storage control device, storage device and storage device system - Disclosed herein is a storage control device that includes a temperature sensor, temperature information selection section, refresh command reception section and trigger issuance frequency setting section. | 08-25-2011 |
20110242923 | SEMICONDUCTOR MEMORY DEVICE INCLUDING CLOCK CONTROL CIRCUIT AND METHOD FOR OPERATING THE SAME - A clock control circuit includes a first clock buffer configured to toggle a first clock signal when a self-refresh exit command signal is inputted during a self-refresh operation; and a second clock buffer configured to toggle a second clock signal when the self-refresh operation is finished, the second clock being provided to internal circuits. | 10-06-2011 |
20110273947 | TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array. Applying a plurality of voltage potentials to the memory cells may further include applying a third voltage potential to a respective word line of the array, wherein the word line may be spaced apart from and capacitively to a body region of the memory cell that may be electrically floating and disposed between the first region and the second region. Applying a plurality of voltage potentials to the memory cells may further include applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the array. | 11-10-2011 |
20110273948 | SEMICONDUCTOR DEVICE AND METHOD OF REFRESHING THE SAME - A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines. | 11-10-2011 |
20110299352 | Semiconductor device including memory cells that require refresh operation - A semiconductor device includes a first circuit that generates a self refresh signal in a predetermined cycle asynchronous with a cycle set externally, a second circuit that generates a refresh address in response to the self refresh signal and updates the refresh address and outputs the refresh address, a third circuit that retains a relief address, a fourth circuit that counts number of generation of the self refresh signal and activates an interrupt signal when a count of the number of generation reaches a predetermined count, a fifth circuit that specifies the refresh address when the interrupt signal is in an inactive state and specifies the relief address when the interrupt signal is in an active state, and a sixth circuit that performs a refresh operation on memory cells specified by the selected refresh address or the relief address. The second circuit temporarily stops updating the refresh address in response to activation of the interrupt signal. | 12-08-2011 |
20110299353 | POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed. | 12-08-2011 |
20120014199 | Semiconductor device that performs refresh operation - To include a refresh control circuit that generates a refresh execution signal in response to a refresh command supplied from outside, and a refresh address counter that performs a counting operation in response to activation of the refresh execution signal. The refresh control circuit generates the refresh execution signal 2 | 01-19-2012 |
20120026820 | INTEGRATED CIRCUITS FOR PROVIDING CLOCK PERIODS AND OPERATING METHODS THEREOF - An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor. | 02-02-2012 |
20120026821 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bank groups including at least two banks, respectively, and a plurality of address counters corresponding to the plurality of bank groups in a one-to-one manner. A refresh operation of a selected bank group is performed in response to a bank group refresh command. | 02-02-2012 |
20120033519 | TEMPERATURE ALERT AND LOW RATE REFRESH FOR A NON-VOLATILE MEMORY - A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory. | 02-09-2012 |
20120075947 | Semiconductor Memory Devices Having Self-Refresh Capability - A semiconductor memory device is provided. The semiconductor memory device includes at least one memory bank including a plurality of memory cells and a self-refresh controller configured to generate a refresh address and to output a row address for a page to be refreshed based on the refresh address. The semiconductor memory device drives the at least one memory bank based on the row address and selectively refreshes pages in the at least one memory bank in response to the row address. | 03-29-2012 |
20120106283 | Row Address Control Circuit Semiconductor Memory Device Including The Same And Method Of Controlling Row Address - A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided. | 05-03-2012 |
20120127817 | SEMICONDUCTOR DEVICE HAVING RESET FUNCTION - A semiconductor device comprises a memory cell array, a row control circuit for controlling an access to the memory cell array, and a refresh control circuit for instructing the row control circuit to refresh the memory cell array. After temporarily transiting to a reset state due to an activation of a reset signal, the refresh control circuit instructs to refresh the memory cell array in response to a transition to an initial state due to a de-activation of the reset signal. | 05-24-2012 |
20120155205 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor memory apparatus includes a buffer control unit configured to deactivate a buffer control signal in response to an auto-refresh start pulse, and activate the buffer control signal in response to an auto-refresh end pulse, a command buffer configured to buffer an external command and output an internal command when the buffer control signal is activated, an address buffer configured to buffer an external address and output an internal address when the buffer control signal is activated, and a clock buffer configured to buffer an external clock and output an internal clock when the buffer control signal is activated. | 06-21-2012 |
20120155206 | SEMICONDUCTOR DEVICE PERIODICALLY UPDATING DELAY LOCKED LOOP CIRCUIT - Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal. | 06-21-2012 |
20120163111 | REFRESH CONTROL CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal having refresh mode information, a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to an active signal enabled in an active mode, and a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array. | 06-28-2012 |
20120170396 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature; a start signal generator configured to receive a refresh command and generate a start signal according to the low-temperature signal; and an address counter configured to count refresh addresses in response to the start signal. | 07-05-2012 |
20120176853 | REFRESH CONTROL CIRCUIT, MEMORY APPARATUS AND REFRESH CONTROL METHOD USING THE SAME - A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time. | 07-12-2012 |
20120195149 | CIRCUITS AND METHODS FOR PROVIDING REFRESH ADDRESSES AND ALTERNATE REFRESH ADDRESSES TO BE REFRESHED - Circuits and refresh address circuits for providing a refresh address, and methods for refreshing memory cells. An example method includes refreshing a first plurality of memory cells and interrupting the refreshing of the first plurality of memory cells. A second plurality of memory cells is refreshed, at least one of the second plurality of memory cells the same as one of the first plurality of memory cells. Refreshing of the first plurality of memory cells is resumed following the refreshing of the second plurality of memory cells. An example refresh address circuit includes a refresh address counter configured to provide addresses to be refreshed and a refresh address interrupt circuit configured to interrupt the provision of addresses. An alternate refresh address circuit is configured to provide an alternate address and the refresh address counter resumes providing the addresses responsive to completing the refreshing of the alternate address. | 08-02-2012 |
20120195150 | REFRESH CIRCUIT - A refresh circuit includes an enable pulse generator configured to generate a first enable pulse and a second enable pulse, a first address latch configured to latch the first row address in synchronization with the first enable pulse and generate a first latch address, and a second address latch configured to latch a second row address in synchronization with the second enable pulse and generate second and third latch addresses. | 08-02-2012 |
20120218848 | SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING OPERATION OF DELAY-LOCKED LOOP CIRCUIT - A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks. | 08-30-2012 |
20120224444 | METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES - An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device. | 09-06-2012 |
20120236671 | REFRESHING DATA OF MEMORY CELLS WITH ELECTRICALLY FLOATING BODY TRANSISTORS - A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle. | 09-20-2012 |
20120263003 | DEVICE PERFORMING REFRESH OPERATIONS OF MEMORY AREAS - Disclosed herein is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level. | 10-18-2012 |
20120263004 | SEMICONDUCTOR DEVICE WITH REFRESH CONTROL CIRCUIT - In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state. | 10-18-2012 |
20120287742 | CIRCUIT AND METHOD FOR OUTPUTTING REFRESH EXECUTION SIGNAL IN MEMORY DEVICE - A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode comprises a first frequency dividing unit, a first selection circuit, a second frequency dividing unit, and a second selection circuit. The first frequency dividing unit receives an auto-refresh signal from outside the memory device and generates a plurality of first divided signals. The first selection circuit generates a selection signal selected from the auto-refresh signal and the first divided signals. The second frequency dividing unit divides the frequency of the selection signal and generates a plurality of second divided signals. The second selection circuit generates the refresh execution signal from the selection signal and the second divided signals. | 11-15-2012 |
20120300568 | Method of Refreshing a Memory Device, Refresh Address Generator and Memory Device - A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging. | 11-29-2012 |
20120300569 | MEMORY SYSTEM AND REFRESH CONTROL METHOD THEREOF - A memory system and a refresh control method thereof are provided. The memory system includes a semiconductor memory device including a plurality of memory cells and a memory controller configured to generate a special command for searching for refresh information stored in the semiconductor memory device and to control a refresh operation of the semiconductor memory device. The semiconductor memory device is configured to output the refresh information to the memory controller in response to the special command generated by the memory controller. | 11-29-2012 |
20120300570 | ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY - An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device. | 11-29-2012 |
20120307581 | SEMICONDUCTOR DEVICE ON WHICH WAFER-LEVEL BURN-IN TEST IS PERFORMED AND MANUFACTURING METHOD THEREOF - Disclosed herein is a device that includes a clock generation circuit that generates an internal clock signal during a normal operation and stops generation of the internal clock signal during a wafer-level burn-in test, a clock tree line that transmits the internal clock signal, and a selector that supplies a dummy clock signal, which is different from the internal clock signal, to the clock tree line during the wafer-level burn-in test. | 12-06-2012 |
20120307582 | SEMICONDUCTOR DEVICE PERFORMING SELF REFRESH OPERATION - When refresh activation signals (REFACT | 12-06-2012 |
20120307583 | SEMICONDUCTOR DEVICE FOR PERFORMING A REFRESH OPERATION - A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines. | 12-06-2012 |
20130003481 | HIDDEN REFRESH METHOD AND OPERATING METHOD FOR PSEUDO SRAM - In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation. | 01-03-2013 |
20130003482 | SELF-REFRESH CONTROL CIRCUIT AND MEMORY INCLUDING THE SAME - An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device. | 01-03-2013 |
20130010562 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF-REFRESH - A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. Entry into and an exit from the self-refresh mode is detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time. | 01-10-2013 |
20130028037 | INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE - Disclosed herein is a semiconductor device having first and second operation modes. In the first operation mode, the semiconductor device deactivates a DLL circuit during a self-refresh mode. In the second operation mode, the semiconductor device intermittently activates the DLL circuit to generate an internal clock signal. | 01-31-2013 |
20130028038 | INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE - Disclosed herein is a semiconductor device having self-refresh modes in which a refresh operation of storage data is periodically performed asynchronously with an external clock signal. The semiconductor device performs the refresh operation on n memory cells in response to an auto-refresh command. The semiconductor device periodically performs the refresh operation on m memory cells included in the memory cell array during the self-refresh mode, where m is smaller than n. | 01-31-2013 |
20130033950 | APPARATUS AND METHOD FOR REFRESHING DRAM - A refresh method for DRAM is provided, in which a memory cell array is arranged to have multiple storing pages. Each storing page has a counter value. The method includes detecting out a portion of the storing pages being no longer used, indicated as a “no-use portion”, and another portion of the storing pages being still in use, indicated as “in-use portion”. Then, only the in-use portion of the storing pages is performed with a refreshing operation. | 02-07-2013 |
20130044557 | MEMORY CONTROL METHOD OF MEMORY DEVICE AND MEMORY CONTROL SYSTEM THEREOF - One exemplary memory control method of a memory device includes: assigning an indicator to each physical row partition in the memory device for indicating if the corresponding physical row partition is to be refreshed; and controlling a partial refresh operation of the memory device according to the indicator of each physical row partition. Each physical row partition is a portion of the memory device. Another exemplary memory control system of a memory device, comprising: a checking unit configured for setting at least one indicator to indicate if part of the memory device is to be refreshed by a partial refresh operation; and a refresh control unit configured for controlling the memory device to perform the partial refresh operation according to the at least one indicator. | 02-21-2013 |
20130077425 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array, a second region coupled to a respective source line of the array, a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region, and a third region coupled to a respective carrier injection line of the array, wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other. | 03-28-2013 |
20130094316 | MEMORY SYSTEM - A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other. | 04-18-2013 |
20130094317 | REFRESH CONTROL CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS - A refresh control circuit of a semiconductor apparatus includes: a first bank refresh counter configured to increase or decrease a logic value of a first refresh address signal when a first bank address signal is enabled during a refresh operation, a second bank refresh counter configured to increase or decrease a logic value of a second refresh address signal when a second bank address signal is enabled during the refresh operation, a bank selection unit configured to generate first and second bank select signals in response to the first and second bank address signals during the refresh operation, and a row selection unit configured to generate first and second row select signals in response to the first and second refresh address signals and the first and second bank select signals. | 04-18-2013 |
20130100755 | SEMICONDUCTOR MEMORY DEVICE IMPLEMENTING COMPREHENSIVE PARTIAL ARRAY SELF REFRESH SCHEME - A semiconductor memory device performing a comprehensive partial self refresh (CPSR) scheme, in which a CPSR operation of not performing a self refresh operation on the segments included in each bank is disclosed. The semiconductor memory device includes a mask information register configured to generate mask information by storing information indicating a bank and a segment on which the self refresh operation is not performed; and a mask operation circuit configured to not perform the self refresh operation on the segments of each of the banks in response to the mask information. The semiconductor memory device efficiently performs a refresh operation according to user convenience and supports lower power consumption. | 04-25-2013 |
20130114364 | SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION - Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal. | 05-09-2013 |
20130128682 | MEMORY SYSTEM WITH DYNAMIC REFRESHING - An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic. | 05-23-2013 |
20130176804 | METHOD AND APPARATUS FOR REDUCING CURRENT CONSUMPTION BY MEMORY REFRESH OPERATION CONTROL - A method and apparatus for reducing current consumption by employing a memory refresh operation is provided. The method employs a refresh operation in an apparatus including a memory in which a partial refresh operation is performed. The method includes classifying data loaded in the memory into first data and second data, dividing the memory into a first area and a second area when an attempt to access the first data is not detected during a preset time, separately arranging the first data and the second data in the first area and the second area, respectively, performing a refresh operation in the second area at a preset time in order to retain data, and loading the first data into the memory when the attempt to access the first data is detected. | 07-11-2013 |
20130182522 | MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND APPARATUS INCLUDING THE SAME - A method of operating a memory device includes masking at least one bank among a plurality of banks in response to a mode register writing command; and performing a refresh operation on a plurality of rows in one of unmasked banks in response to a first per-bank refresh command. | 07-18-2013 |
20130201777 | REFRESH CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address. | 08-08-2013 |
20130215700 | SEMICONDUCTOR MEMORY DEVICE CHANGING REFRESH INTERVAL DEPENDING ON TEMPERATURE - A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit. | 08-22-2013 |
20130250711 | MEMORY AND METHOD OF REFRESHING A MEMORY - A memory includes a determination circuit, a plurality of refresh counters, and a plurality of banks. The determination circuit receives a refresh command. The plurality of refresh counters are coupled to the determination circuit. Each refresh counter of the plurality of refresh counters corresponds to one bank of the plurality of banks. The determination circuit detects whether a first bank of the plurality of banks is enabled or a number counted by a first refresh counter of the plurality of refresh counters corresponding to the first bank is equal to a predetermined value. Then, the determination circuit optionally refreshes one bank of the plurality of banks according to a detection result. Thus, the memory still refreshes an idle bank according to a refresh command even if the plurality of banks are not all idle. | 09-26-2013 |
20130279283 | MEMORY DEVICES AND MEMORY CONTROLLERS - A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals. | 10-24-2013 |
20130279284 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR REFRESHING MEMORY CELLS - A semiconductor memory device is provided. The semiconductor memory device includes a memory block including a plurality of memory cells; a default refresh controller configured to receive a refresh command from a host, to generate a default refresh signal, and to control the memory cells to be refreshed; and a weak cell refresh controller configured to receive the default refresh signal, to generate a weak cell refresh signal, and to control a weak cell among the memory cells to be refreshed. The weak cell may be refreshed at least one more time during a refresh period during which all of the memory cells are refreshed by the default refresh controller. The semiconductor memory device performs at least one more refresh on a weak cell having a data retention time shorter than a refresh period apart from a normal default refresh, thereby preventing data loss. | 10-24-2013 |
20130301371 | DYNAMIC RANDOM ACCESS MEMORY WITH MULTIPLE THERMAL SENSORS DISPOSED THEREIN AND CONTROL METHOD THEREOF - A dynamic random access memory (DRAM) with multiple thermal sensors disposed therein and a control method for the DRAM. A DRAM in accordance with an exemplary embodiment of the invention provides multi-zone temperature detection. The DRAM comprises a plurality of banks, a plurality of thermal sensors and a control unit. The thermal sensors are disposed between the banks. The control unit controls the thermal sensors to obtain sensed temperatures, and sets a self-refresh cycle for all of the banks based on the highest one of the sensed temperatures. | 11-14-2013 |
20130308405 | SEMICONDUCTOR MEMORY DEVICE CONTROLLING REFRESH CYCLE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable. | 11-21-2013 |
20130308406 | SEMICONDUCTOR DEVICE, METHOD FOR OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal. | 11-21-2013 |
20130315019 | REFRESH CIRCUITS - A refresh circuit includes a period signal generation circuit configured to drive a control node according to a level of the control node, discharge first and second currents from the control node in response to the first temperature signal, and generate a period signal, a division signal generator configured to divide the period signal to generate a first division signal and a second division signal, and a selector configured to select one of the first and second division signals in response to a second temperature signal and for outputting the selected division signal as a refresh signal. | 11-28-2013 |
20130336079 | MEMORY DEVICE, OPERATION METHOD THEREOF AND MEMORY SYSTEM HAVING THE SAME - A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L. | 12-19-2013 |
20130343142 | DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR - A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. | 12-26-2013 |
20140003178 | SEMICONDUCTOR MEMORY DEVICE | 01-02-2014 |
20140016421 | SEMICONDUCTOR MEMORY DEVICE STORING REFRESH PERIOD INFORMATION AND OPERATING METHOD THEREOF - A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band. | 01-16-2014 |
20140016422 | SEMICONDUCTOR MEMORY DEVICE THAT CONTROLS REFRESH PERIOD, MEMORY SYSTEM AND OPERATING METHOD THEREOF - A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate. | 01-16-2014 |
20140016423 | Reducing Memory Refresh Exit Time - Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal. | 01-16-2014 |
20140016424 | METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES - An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device. | 01-16-2014 |
20140022858 | METHOD OF CONTROLLING A REFRESH OPERATION OF PSRAM AND RELATED DEVICE - A plurality of refresh requests are generated at a predetermined period shorter than the longest time during which a PSRAM is able to retain a data without being refreshed. For two consecutive first and second refresh requests, the second refresh request is ignored if the interval between the first and the second refresh requests is not larger than a predetermined duration. The first refresh request is delayed if the first refresh request conflicts with an external command of the PSRAM. | 01-23-2014 |
20140029367 | REFRESH ADDRESS GENERATOR, VOLATILE MEMORY DEVICE INCLUDING THE SAME AND METHOD OF REFRESHING THE VOLATILE MEMORY DEVICE - A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal. | 01-30-2014 |
20140064008 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit. | 03-06-2014 |
20140064009 | MEMORY DEVICE - A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated. | 03-06-2014 |
20140071778 | MEMORY DEVICE REFRESH - According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger. | 03-13-2014 |
20140078845 | CELL ARRAY, MEMORY, AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines. | 03-20-2014 |
20140078846 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PERFORMING REFRESH OPERATION WITHOUT AUTO REFRESH COMMAND - A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation. | 03-20-2014 |
20140078847 | MEMORY REFRESH METHODS, MEMORY SECTION CONTROL CIRCUITS, AND APPARATUSES - Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section an and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage. | 03-20-2014 |
20140078848 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE - In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened. | 03-20-2014 |
20140078849 | CONTROL OF INPUTS TO A MEMORY DEVICE - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 03-20-2014 |
20140085999 | SEMICONDUCTOR MEMORY DEVICE HAVING ADJUSTABLE REFRESH PERIOD, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME - A semiconductor memory device comprises a cell array comprising a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells. | 03-27-2014 |
20140092698 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device may comprise monitoring error handling information corresponding to an address of a semiconductor memory device, setting a refresh period for the address considering the error handling information and requesting a refresh request for the address. | 04-03-2014 |
20140092699 | INTERMEDIATE CIRCUIT AND METHOD FOR DRAM - An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a Command Output Enable signal CON, a Data Read Enable signal DRN and a Refresh Enable signal REFN based on the second clock, wherein a ration of duration the signal CON is in a first state to duration in a second state equals to CLK | 04-03-2014 |
20140112086 | REFRESH METHOD, REFRESH ADDRESS GENERATOR, VOLATILE MEMORY DEVICE INCLUDING THE SAME - A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device. | 04-24-2014 |
20140112087 | POWER MANAGEMENT CONTROL AND CONTROLLING MEMORY REFRESH OPERATIONS - A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by logically ORing, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation. | 04-24-2014 |
20140133255 | SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM - A semiconductor device comprises a first memory cell array, a register storing information of whether or not one of the word lines in an active state exists in a unit area and storing address information, and a control circuit controlling a refresh operation for a refresh word line based on the information in the register when receiving a refresh request. When the one of the word lines in an active state does not exist, memory cells connected to the refresh word line are refreshed. When the one of the word lines in an active state exists, the one of the word lines in an active state is set into an inactive state temporarily and the memory cells connected to the refresh word line are refreshed after precharging bit lines of the memory cells. | 05-15-2014 |
20140153350 | METHODS AND APPARATUSES FOR REFRESHING MEMORY - Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method further includes refreshing the memory at a first refresh rate after receiving the self refresh command. The method further includes refreshing the memory at a second refresh rate in response to a determination that each memory cell of the memory has been refreshed at the first refresh rate. The first refresh rate is greater than a second refresh rate. | 06-05-2014 |
20140169114 | VOLATILE MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND RELATED METHODS - A volatile memory device includes a memory cell array including a plurality of pages and a refresh control circuit. The refresh control circuit may adjust a refresh interval according to a refresh information signal and refreshes the plurality of pages according to the adjusted refresh interval while refreshing weak pages of the plurality of pages at least twice during a refresh period. Each of the weak pages may include at least a weak cell whose data retention time is shorter than a data retention time of normal cells, and the refresh information signal is based on a number of the weak pages. A memory controller and may generate auto refresh commands for volatile memory device(s) based on refresh information reflecting a number of weak pages of the volatile memory device(s). Systems and methods are also disclosed. | 06-19-2014 |
20140177370 | METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT - Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh. | 06-26-2014 |
20140177371 | SUSPEND SDRAM REFRESH CYCLES DURING NORMAL DDR OPERATION - An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus. | 06-26-2014 |
20140177372 | SEMICONDUCTOR DEVICE THAT PERFORMS REFRESH OPERATION - A method for refreshing memory cells in a DRAM includes receiving a refresh command, receiving a refresh mode specifying signal in synchronization with the refresh command, refreshing a first quantity of memory cells when the refresh mode specifying signal has a first value, and refreshing a second quantity of memory cells, at least double the first quantity, when the refresh mode specifying signal has a second value. | 06-26-2014 |
20140185403 | REFRESH METHOD FOR SWITCHING BETWEEN DIFFERENT REFRESH TYPES BASED ON AT LEAST ONE PARAMETER OF VOLATILE MEMORY AND RELATED MEMORY CONTROLLER - A refresh method of a volatile memory includes at least the following steps: detecting at least one parameter of the volatile memory; selecting a target refresh type from a plurality of candidate refresh types according to the at least one parameter; and performing a refresh operation upon the volatile memory according to the target refresh type. In one embodiment, the candidate refresh types include at least a first candidate refresh type and a second candidate refresh type, each refresh command complying with the first candidate refresh type is arranged to refresh a first number of banks of the volatile memory, and each refresh command complying with the second candidate refresh type is arranged to refresh a second number of banks of the volatile memory. | 07-03-2014 |
20140192605 | MEMORY REFRESH MANAGEMENT - Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed. | 07-10-2014 |
20140192606 | STACKED MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING THE SAME - A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank. In one arrangement, the controller controls the refresh operation to be selectively performed for a first rank in each of the memory chips during the non-overlapping time periods independently from a refresh operation performed for a second rank in each memory chip. Delay circuits or other logic may be included to ensure that the refresh operations do not overlap. | 07-10-2014 |
20140198597 | DYNAMIC RANDOM ACCESS MEMORY FOR COMMUNICATIONS SYSTEMS - An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit. | 07-17-2014 |
20140211583 | INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE - A method for operating a dynamic random access memory device includes providing a clock signal to a clock terminal of the dynamic random access memory device, selecting one of a first operating mode and a second operating mode of the dynamic random access memory device, the first operating mode, when selected, corresponding to the DRAM periodically refreshing a first number of word lines, and the second operating mode, when selected, corresponding to the DRAM periodically refreshing a second number of word lines different from the first number, and providing a self-refresh command to a command terminal of the dynamic random access memory device. | 07-31-2014 |
20140219042 | MEMORY DEVICE AND METHOD OF REFRESHING IN A MEMORY DEVICE - In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed. | 08-07-2014 |
20140241093 | DEVICES, SYSTEMS AND METHODS WITH IMPROVED REFRESH ADDRESS GENERATION - A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation. | 08-28-2014 |
20140241094 | MEMORY DEVICE REFRESH COMMANDS ON THE FLY - On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly. | 08-28-2014 |
20140247680 | POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change between refresh operations of the memory device. Other embodiments including additional apparatus, systems, and methods are described. | 09-04-2014 |
20140254298 | VARIABLE DYNAMIC MEMORY REFRESH - A system and method are provided for refreshing a dynamic memory. A first region of a memory is refreshed at a first refresh rate and a second region of the memory is refreshed at a second refresh rate that is different than the first refresh rate. A memory controller is configured to refresh the first region of a memory at the first refresh rate and refresh the second region of the memory at the second refresh rate. | 09-11-2014 |
20140269134 | MEMORY DEVICE AND METHOD OF CONTROLLING REFRESH OPERATION IN MEMORY DEVICE - A method of controlling a refresh operation for a memory device is disclosed. The method includes storing a first row address corresponding to a first row of a memory cell array, storing one or more second row addresses corresponding to one or more second rows of the memory cell array, the one or more second row addresses corresponding to the first row address, sequentially generating row addresses as a refresh row address during a first refresh interval, for each generated row address, when a generated row address identical to one of the one or more second row addresses is detected, stopping the generation of row addresses and sequentially outputting the one second row address and the first row address as the refresh row address, restarting the generation of the row addresses as the refresh row address after outputting the one second row address and the first row address. | 09-18-2014 |
20140293725 | MEMORY WITH REFRESH LOGIC TO ACCOMODATE LOW-RETENTION STORAGE ROWS - An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate. | 10-02-2014 |
20140301152 | REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES - Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source. | 10-09-2014 |
20140321226 | DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR - A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. | 10-30-2014 |
20140340976 | INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE - A method for controlling termination impedance of a data terminal in a dynamic random access memory device includes receiving a mode register set command to set an operation mode to a first mode, setting the operation mode in a mode register to the first mode, receiving a self-refresh entry command, entering self-refresh mode, activating a first input buffer connected to a termination impedance control terminal, and receiving an impedance control signal at the first buffer, wherein the termination impedance of the data terminal is set to a first impedance value if the termination impedance control signal has a first level and the termination impedance of the data terminal is set to a second impedance value if the termination impedance control signal has a second level. | 11-20-2014 |
20140355370 | SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR PACKAGE - A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification. | 12-04-2014 |
20140376321 | SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM - To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation. | 12-25-2014 |
20150016203 | DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION - A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank. | 01-15-2015 |
20150016204 | INSERTION-OVERRIDE COUNTER TO SUPPORT MULTIPLE MEMORY REFRESH RATES - A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations. | 01-15-2015 |
20150023121 | MEMORY REFRESH METHODS, MEMORY SECTION CONTROL CIRCUITS, AND APPARATUSES - Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage. | 01-22-2015 |
20150029804 | APPARATUSES AND METHODS FOR ADJUSTING DEACTIVATION VOLTAGES - Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage. | 01-29-2015 |
20150036445 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups. | 02-05-2015 |
20150043293 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks; a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; and a refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation N times on the selected bank, N being a positive integer. | 02-12-2015 |
20150043294 | MEMORY DEVICE, MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory device comprises a cell array having a plurality of word lines, an address counting unit suitable for generating a counting address that is changed whenever one or more of the plurality of word lines are refreshed, and a control unit suitable for selecting a word line corresponding to the counting address among the plurality of word lines and refreshing the selected word line within a first period in response to a refresh command during a first operation mode, within a second period that is longer than the first period during a second operation mode, and within a third period that is shorter than the second period in a high frequency section after the second operation mode begins. | 02-12-2015 |
20150043295 | METHOD OF REFRESHING VOLATILE MEMORY DEVICE - A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period. | 02-12-2015 |
20150049566 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory including a first cell block comprising a plurality of first word line groups, and one or more first redundancy word line groups each corresponding to one hit signal of a plurality of hit signals; a second cell block comprising a plurality of second word line groups, and one or more second redundancy word line groups each corresponding to one hit signal of the plurality of hit signals; and a control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a redundancy word line, wherein the first input address is first inputted in a target refresh section. | 02-19-2015 |
20150049567 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a first cell block comprising a plurality of first word lines and one or more first redundancy word lines for replacing at least one of the plurality of first word lines; a second cell block comprising a plurality of second word lines and one or more second redundancy word lines for replacing at least one of the plurality of second word lines; and a control unit suitable for sequentially receiving one or more input addresses, during a target refresh section, selecting one of the first cell block and the second cell block and a word line included in the selected cell block in response to a first input address, and activating one or more adjacent word lines adjacent to the selected word line, which is selected based on the first input address, when the selected word line is adjacent to the redundancy word line, wherein the adjacent word lines comprise the redundancy word line. | 02-19-2015 |
20150063049 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array including a normal memory cell array and a redundancy memory cell array, a normal refresh counter suitable for generating a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode and a redundancy refresh counter suitable for generating a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period. | 03-05-2015 |
20150063050 | SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION - Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal. | 03-05-2015 |
20150078112 | METHOD FOR AUTO-REFRESHING MEMORY CELLS IN SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE USING THE METHOD - An exemplary embodiment of the present disclosure illustrates a method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a same index and L remained sectors with different indices. Two word lines of the two particular sectors with the same index in the memory bank and (M−1) word lines of the L remained sectors respectively in the other (M−1) memory banks are selected in one cycle. Then, memory cells of the selected word lines are refreshed. | 03-19-2015 |
20150085594 | METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL - Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information. | 03-26-2015 |
20150085595 | Protocol For Refresh Between A Memory Controller And A Memory Device - The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller. | 03-26-2015 |
20150092508 | DIRECTED PER BANK REFRESH COMMAND - A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition. | 04-02-2015 |
20150098288 | ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR MEMORY AND OPERATION METHOD OF THE SAME - An electronic device includes a semiconductor memory. The semiconductor memory includes a cell array including first to N | 04-09-2015 |
20150098289 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation. | 04-09-2015 |
20150103610 | PROTOCOL FOR MEMORY POWER-MODE CONTROL - In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command. | 04-16-2015 |
20150109871 | ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE - Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row. | 04-23-2015 |
20150109872 | DEVICE PERFORMING REFRESH OPERATIONS OF MEMORY AREAS - Disclosed heroin is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level. | 04-23-2015 |
20150117131 | MEMORY DEVICES - A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed. | 04-30-2015 |
20150124544 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A semiconductor system includes a controller and a semiconductor device. The controller outputs offset signals whose level combination is controlled according to temperature code signals including information on an internal temperature. The semiconductor device generates the temperature code signals according to a level combination of the offset signals. Further, the semiconductor device controls a refresh cycle time determined by the level combination of the offset signals. | 05-07-2015 |
20150124545 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal. | 05-07-2015 |
20150131395 | Method for triggering a delay-locked loop (DLL) update operation or an impedance calibration operation in a dynamic random access memory device - A method for triggering an adjustment operation in a dynamic random access memory device, the method including receiving a refresh command, generating an execute signal, counting the execute signal to provide a count value, refreshing a memory array based on the count value and triggering the adjustment operation when the count value reaches a predetermined value. | 05-14-2015 |
20150146494 | PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY - Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2 | 05-28-2015 |
20150302913 | VOLATILE MEMORY DEVICE, MEMORY MODULE INCLUDING THE SAME, AND METHOD OF OPERATING MEMORY MODULE - A memory module includes an emergency power; a volatile memory device including a plurality of memory blocks; a nonvolatile memory device; and a module control block suitable for controlling data of the volatile memory device to be backed up to the nonvolatile memory device by using the emergency power when a power failure occurs, wherein data of the memory blocks are sequentially backed up to the nonvolatile memory device, and a refresh operation prohibited for a memory block of which back up is completed. | 10-22-2015 |
20150318035 | PRIORITY ADJUSTMENT OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) TRANSACTIONS PRIOR TO ISSUING A PER-BANK REFRESH FOR REDUCING DRAM UNAVAILABILITY - Priority adjustment of dynamic random access memory (DRAM) transactions prior to issuing a per-bank refresh for reducing DRAM unavailability is disclosed. In one aspect, DRAM is refreshed on a per-bank basis. If a queued memory transaction corresponds to a memory bank that will soon be refreshed, the transaction may be delayed if a refresh of the corresponding memory bank begins prior to execution of the transaction. To avoid delaying execution of the transaction while waiting for the corresponding memory bank to be refreshed, a priority of the memory transactions may be adjusted based on a memory bank refresh schedule. The priority of the transaction corresponding to the memory bank to be refreshed may be increased, and the priority of other memory transactions may be decreased, if such an adjustment would avoid or reduce delaying execution due to unavailability of the corresponding memory bank. | 11-05-2015 |
20150325284 | SEMICONDUCTOR APPARATUS CAPABLE OF PREVENTING REFRESH ERROR AND MEMORY SYSTEM USING THE SAME - A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal. | 11-12-2015 |
20150325291 | REFRESH OF A MEMORY AREA OF A NON-VOLATILE MEMORY UNIT - A method for performing a refresh of a first memory area of a non-volatile memory unit includes overwriting at least one additional memory area of the non-volatile memory unit with a memory content from the first memory area, adding a reference to the at least one additional memory area to a memory address area corresponding to the memory content and removing a reference to the first memory area from the memory address area corresponding to the memory content, overwriting the first memory area with the memory content from the at least one additional memory area, and subsequently replacing the reference in the memory address area with the reference to the first memory area. | 11-12-2015 |
20150340079 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include an active control portion configured to generate a preliminary bank active signal and a single bank refresh signal in response to a command, a refresh control signal, and a bank active signal. The semiconductor memory apparatus may also include a signal combination portion configured to enable the bank active signal when either the preliminary bank active signal or the single bank refresh signal is enabled. | 11-26-2015 |
20150340080 | Refreshing Dynamic Memory - A method of refreshing dynamic memory includes associating, for each refreshable memory element of a dynamic random access memory device, an indicator with the refreshable memory element. The method also includes detecting a predetermined data value being written to a memory location associated with a first refreshable memory element, and setting the indicator associated with the first refreshable memory element to a first value. The method further includes refreshing only the refreshable memory elements of the dynamic random access memory device whose associated indicators have values different from the first value, wherein refreshing does not comprise refreshing the first refreshable memory element. | 11-26-2015 |
20150348608 | MEMORY DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage. | 12-03-2015 |
20150348611 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, the first power control signal having an enablement period that may be controlled in response to a temperature signal having a cycle time. The cycle time may be controlled according to a mode signal and an internal temperature. The sense amplifier circuit may generate a first power signal driven to have a first drive voltage in response to the first power control signal. In addition, the sense amplifier circuit may sense and amplify a level of a bit line using the first power signal as a power supply voltage. | 12-03-2015 |
20150364182 | SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGURABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM - A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs. | 12-17-2015 |
20150371700 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes an oscillating signal generation section suitable for generating an oscillation signal oscillating with a period, which is defined by a predetermined temperature-period function, a period control section suitable for controlling the period of the oscillation signal according to a combination of two or more predetermined temperature-period functions, which are different from one another, in response to a refresh characteristic information, and a memory cell array suitable for performing a refresh operation in response to the oscillation signal. | 12-24-2015 |
20150380072 | DYNAMICALLY APPLYING REFRESH OVERCHARGE VOLTAGE TO EXTEND REFRESH CYCLE TIME - A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a memory device needs to be refreshed, and determine that the refresh cycle time is too short for a state of the portion of the memory device. The memory device typically has an associated refresh cycle time or time between refreshes based on the device and system architecture. The control engine can generate one or more control signals to cause the system to apply an overcharge refresh to overcharge the portion of the memory device with a refresh operation to extend the refresh cycle time for the portion of the memory device. | 12-31-2015 |
20160005456 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled. | 01-07-2016 |
20160005457 | DIRECTED PER BANK REFRESH COMMAND - A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition. | 01-07-2016 |
20160027491 | REFRESH CIRCUIT - A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. The refresh circuit may be configured to perform a second refresh operation for a partial number of memory banks among the plurality of memory banks. The second refresh operation may be performed for the partial number of memory banks that have completed the first refresh operation. The second refresh operation may be performed within the first time period. | 01-28-2016 |
20160027492 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF PERFORMING A REFRESH FOR SEMICONDUCTOR MEMORY DEVICE AND REFRESH COUNTER IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address. | 01-28-2016 |
20160027498 | REDUCED REFRESH POWER - N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced. | 01-28-2016 |
20160035398 | MEMORY DEVICES - A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed | 02-04-2016 |
20160035407 | DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR - A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. | 02-04-2016 |
20160035410 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines. | 02-04-2016 |
20160042782 | SEMICONDUCTOR STORAGE DEVICE AND SYSTEM PROVIDED WITH SAME - [Problem] To regenerate the charge of a memory cell having reduced information retention characteristics using a target row refresh operation. [Solution] A semiconductor storage device is provided with a memory cell array ( | 02-11-2016 |
20160055899 | FAST EXIT FROM DRAM SELF-REFRESH - Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller. | 02-25-2016 |
20160055901 | INDUCED THERMAL GRADIENTS - A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die. | 02-25-2016 |
20160064062 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH OPERATING METHOD - A semiconductor memory device includes a plurality of normal memory mats, one or more of which includes a redundancy word line, a dummy memory mat suitable for performing an operation with an edge memory mat as a pair during an active operation, wherein the edge memory mat is one among the plurality of normal memory mats disposed at an edge, and a refresh control section suitable for controlling refresh operations for the plurality of normal memory mats and the dummy memory mat, and restricting activation of the redundancy word line during a refresh operation for the edge memory mat. | 03-03-2016 |
20160071570 | REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor apparatus may include a plurality of slices electrically coupled through through electrodes. Any one slice of the plurality of slices may be configured to generate a refresh cycle signal in response to a refresh command, and transmit the refresh cycle signal to the other slices through the through electrodes. The other slices may be configured to perform refresh operations in synchronization with the refresh cycle signal. | 03-10-2016 |
20160071579 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - According to one embodiment, a semiconductor memory device includes a source voltage adjustment circuit and a word line voltage adjustment circuit, which are configured to respectively supply a source voltage supply end and a word line switchingly with voltage-adjusted voltages, in response to a mode switching signal for switching between a retention state mode and an active state mode, wherein the source voltage supply end is connected to sources of MOS transistors forming a flip-flop of a memory cell, and the word line is connected to gates of access transistors. | 03-10-2016 |
20160078918 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed to when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation. | 03-17-2016 |
20160078921 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 03-17-2016 |
20160086650 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device includes: a command generator suitable for generating an internal active command signal corresponding to an active command signal, wherein, when an active section of the active command signal lasts for a predetermined time or longer, the internal active command signal is additionally activated; an address storage suitable for storing an address signal based on an activation number of the internal active command signal; and a refresh operation driver suitable for performing a refresh operation on a word line corresponding to the stored address signal. | 03-24-2016 |
20160086651 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation. | 03-24-2016 |
20160086655 | Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle - Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state. | 03-24-2016 |
20160099042 | Devices, Systems and Methods of Setting Machines - A self-refresh device, adopted in a memory array including a plurality of memory cells, includes a first word-line selecting module, which is enabled according to a first main-word-line signal, and a self-refresh controller. The first word-line selecting module includes a first selecting device, which selects a first word line according to a first word-line driving signal, and a second selecting device, which selects a second word line according to a second word-line driving signal. The self-refresh controller generates the first word-line driving signal, the second word-line driving signal, and the first main word-line signal to select one of the memory cells corresponding to the selected one of the first word line and the second word line for self-refreshing. When the first word line switches to the second word line, the self-refresh controller maintains the first main word-line signal at the same logic level. | 04-07-2016 |
20160099043 | MEMORY CIRCUIT AND REFRESH METHOD THEREOF - A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality of memory blocks. The memory controller outputs an access instruction and an access address to address the word lines for accessing the memory array, or the memory controller outputs a refresh instruction and a refresh address to address the word lines for refreshing the memory array, wherein the memory controller performs a refresh operation on each of the memory blocks corresponding to each of the word lines at predetermined intervals. The memory controller counts the number of times the access instructions have been output and determines whether that number equals a predetermined value or not. According to the determination result, the memory controller selects an address adjacent to the access address as the refresh address for the next refresh operation. | 04-07-2016 |
20160111140 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device includes a 1st controller suitable for generating refresh control signals for controlling two or more types of refresh operations according to an external refresh signal; and a 2nd controller suitable for controlling a plurality of word lines according to the refresh control signals such that the two or more types of refresh operations are alternately performed a predetermined number of times during a unit refresh period corresponding to the external refresh signal. | 04-21-2016 |
20160125931 | SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS A REFRESH OPERATION - A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change. | 05-05-2016 |
20160141016 | CONTROLLED MULTI-STEP DE-ALIGNMENT OF CLOCKS - An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals. | 05-19-2016 |
20160141017 | CONTROLLED DYNAMIC DE-ALIGNMENT OF CLOCKS - A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that drive the first and second functional units respectively. The second clock-signal generates its second clock-signal based on the first clock-signal. The clock-retardation unit dynamically causes the second clock-signal to have a target time-domain offset relative to the first clock-signal. | 05-19-2016 |
20160148668 | CELL ARRAY, MEMORY, AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines. | 05-26-2016 |
20160163372 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD THEREOF - A semiconductor memory device includes a memory bank including a plurality of word lines, and a refresh operation control unit suitable for performing a first refresh operation for a first adjacent word line group of a target word line of the plurality of word lines, and performing a second refresh operation for a second adjacent word line group of the target word line after the first refresh operation, in response to a smart refresh command. | 06-09-2016 |
20160163377 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING SAME - A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line. | 06-09-2016 |
20160180919 | MULTI-CHANNEL SELF REFRESH DEVICE | 06-23-2016 |
20160180920 | REFRESH REQUEST QUEUING CIRCUITRY | 06-23-2016 |
20160180921 | SEMICONDUCTOR MEMORY DEVICE CONTROLLING REFRESH CYCLE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE | 06-23-2016 |
20160196863 | METHOD OF OPERATING MEMORY DEVICE AND METHOD OF OPERATING MEMORY SYSTEM INCLUDING THE SAME | 07-07-2016 |
20160203853 | SEMICONDUCTOR APPARATUS CAPABLE OF PREVENTING REFRESH ERROR AND MEMORY SYSTEM USING THE SAME | 07-14-2016 |
20160203854 | SEMICONDUCTOR PACKAGE WITH POP STRUCTURE AND REFRESH CONTROL METHOD THEREOF | 07-14-2016 |
20180025770 | SEMICONDUCTOR DEVICE | 01-25-2018 |
20180025771 | DIRECTED PER BANK REFRESH COMMAND | 01-25-2018 |
20180025772 | SEMICONDUCTOR DEVICES HAVING A REFRESH OPERATION | 01-25-2018 |
20190147939 | METHOD OF OPERATING MEMORY DEVICE AND MEMORY DEVICE PERFORMING THE SAME | 05-16-2019 |