Class / Patent application number | Description | Number of patent applications / Date published |
365210100 | Reference or dummy element | 47 |
20080205181 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line. | 08-28-2008 |
20080247250 | Semiconductor memory device with two-stage input buffer - A semiconductor memory device includes: a pre-amplifying unit configured to amplify a difference between an input signal and a reference signal to output a pre-output signal; a delaying unit configured to delay the input signal to output a delayed input signal; and a main amplifying unit configured to receive the pre-output signal and the delayed input signal as differential inputs to output an output signal. | 10-09-2008 |
20080253211 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory cell is implemented in which the area of a row selection circuit is reduced and the effects of exposure, etching, and so on performed during manufacture are eliminated. The semiconductor memory device is provided with word line selection circuits connected with a row address signal line to select some desired word line according to an address input and dummy word line potential fixation circuits connected to word lines for dummy memory cells. As in the case of the word line selection circuits, the dummy word line potential fixation circuits each include a NAND gate NANDR(i) (i=−1, 0, m+1, or m+2) and an inverter INVR(i) (i=−1, 0, m+1, or m+2). The inputs of the dummy word line potential fixation circuits are connected with a row address signal line such that the word lines for the dummy memory cells are maintained in a non-selected state at all times. These make it possible to make the circuits which selectively drive all the word lines identical with each other in configuration, reduce the area of the row selection circuit, and eliminate the effects of exposure, etching, and so on during manufacture. | 10-16-2008 |
20080279027 | Thermally Stable Reference Voltage Generator for Mram - A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the reference is degraded by thermal instability. This can help reduce a data error rate. Detecting such degradation can prove to be more effective than trying to design in enough margins for the lifetime of the device. The reference cell can be less susceptible to degradation than other cells by using different shape of cells and different write currents. Where each reference cell is used by many memory cells, the reference cell tends to be used more often than any particular memory cell and so can be more susceptible to degradation. Another way of ensuring against longer term degradation of the reference is periodically rewriting the reference cell. | 11-13-2008 |
20080316847 | SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor are respectively coupled to a pre-charge voltage via first switches. First terminals of the storage memory device and the reference memory device are respectively coupled to the first terminals of the storage capacitor and the reference capacitor. The storage discharge switch and the reference discharge switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The arbitrator is coupled to the first terminals of the storage memory device and the reference memory device and provides an output as a read result of the storage memory device. | 12-25-2008 |
20090027987 | Memory Device and Testing - An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed. | 01-29-2009 |
20090129189 | METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE - A memory device comprising at least a plurality of memory cells and a memory control unit to read and write user data to said memory cells is provided. The memory device comprises further a monitoring unit for retrieving a plurality of data concerning the memory device and a comparing unit. The comparing unit receives an output signal of the monitoring unit and is configured to compare the plurality of retrieved data with a plurality of reference values. | 05-21-2009 |
20090141574 | Memory accessing circuit and method - The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2 | 06-04-2009 |
20090175108 | Integrated Circuit, Cell Arrangement, Method for Manufacturing an Integrated Circuit and for Reading a Memory Cell Status, Memory Module - An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first memory cell status and the second memory cell status. | 07-09-2009 |
20090175109 | CURRENT-MODE SENSE AMPLIFIER AND SENSE AMPLIFYING METHOD - A current-mode sense amplifier comprises a first current mirror, a second current mirror and an amplifying circuit. The first current mirror outputs a cell current to a memory cell and duplicates the cell current to generate a mirrored cell current. The second current mirror outputs a reference current to the reference cell and duplicates the reference current to generate a mirrored reference current. The amplifying circuit comprises a first switch, second switch, third switch and fourth switch. The first switch has first and second terminals for respectively receiving the mirrored cell and reference currents. The second and third switches have first terminals respectively coupled to the first and second terminals of the first switch, and control terminals respectively coupled to the second and first terminals of the first switch. The fourth switch is connected to second terminals of the second and third switches. | 07-09-2009 |
20090219776 | NON-VOLATILE MEMORY DEVICE WITH PLURAL REFERENCE CELLS, AND METHOD OF SETTING THE REFERENCE CELLS - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 09-03-2009 |
20100061171 | Semiconductor Memory Device and Method of Operating the Same - A semiconductor memory device includes a plurality of word lines, a plurality of pairs of bit lines and complementary bit lines, and a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a bit line and a complementary bit line cross each other. A voltage control unit controls a power voltage to obtain a controlled voltage appliable to the memory cells in response to a control signal that controls an operation of the memory cells. At least one dummy cell is disposed between the voltage control unit and the memory cells and is configured to reduce the controlled voltage to a predetermined level. | 03-11-2010 |
20100118633 | SEMICONDUCTOR MEMORY DEVICE HAVING DUMMY SENSE AMPLIFIERS AND METHODS OF UTILIZING THE SAME - A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells. | 05-13-2010 |
20100202231 | THERMALLY STABLE REFERENCE VOLTAGE GENERATOR FOR MRAM - A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the reference is degraded by thermal instability. This can help reduce a data error rate. Detecting such degradation can prove to be more effective than trying to design in enough margins for the lifetime of the device. The reference cell can be less susceptible to degradation than other cells by using different shape of cells and different write currents. Where each reference cell is used by many memory cells, the reference cell tends to be used more often than any particular memory cell and so can be more susceptible to degradation. Another way of ensuring against longer term degradation of the reference is periodically rewriting the reference cell. | 08-12-2010 |
20100214861 | Semiconductor memory cell array and semiconductor memory device having the same - A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage | 08-26-2010 |
20100254207 | Non-Volatile Memory Device with Plural Reference Cells, and Method of Setting the Reference Cells - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 10-07-2010 |
20100265783 | Self-Timed Integrating Differential Current - A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. Integration continues until a desired voltage or time is reached, resulting in a sufficiently reliable output. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion. | 10-21-2010 |
20100277999 | FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A fuse circuit includes a fuse unit configured to drive an output terminal via a current path including a fuse in response to a fuse enable signal; and a comparison unit configured to be activated in response to an activation signal for comparing a reference voltage having a predetermined level with a voltage level of the output terminal to generate a fuse state signal. | 11-04-2010 |
20100315895 | SEMICONDUCTOR DEVICE - A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR | 12-16-2010 |
20110026348 | Semiconductor device having hierarchically structured bit lines and system including the same - A semiconductor device includes a global bit line, a dummy global bit line that is shorter than the global bit line, a sense amplifier that amplifies a potential difference between the global bit line and the dummy global bit line, a plurality of memory blocks each including a hierarchy switch and a local bit line that is connected to the global bit line via the hierarchy switch, a dummy memory block that includes a dummy hierarchy switch and a dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch, and a control circuit that activates any one of hierarchy switches and the dummy hierarchy switch. With this configuration, it is possible to obtain the same memory capacity between a memory mat located at an edge and the other memory mat. | 02-03-2011 |
20110134713 | Methods circuits devices and systems for operating an array of non-volatile memory cells - Disclosed are methods, circuits, devices and systems for operating one or more non-volatile memory (NVM) cells within an array of NVM cells. According to embodiments, there may be provided a nonvolatile memory (NVM) device comprising an array of NVM data cells including one or more border/periphery data cells and one or more non-periphery cells. Array control circuitry may be adapted to gauge a state of the one or more periphery data cells differently than non-periphery data cells. | 06-09-2011 |
20110149669 | Sense Amplifier and Data Sensing Method Thereof - A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node. | 06-23-2011 |
20110211410 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having an open bit line structure includes a normal memory cell block, a reference memory cell block, and a sense amplifier. The normal memory cell block includes a plurality of normal memory cells and a driving bit line connected to the normal memory cells. The reference memory cell block includes a reference bit line connected to a reference cell capacitor. The sense amplifier is configured to sense and amplify voltage levels of the driving bit line and the reference bit line. | 09-01-2011 |
20110242921 | Systems And Methods Of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 10-06-2011 |
20120033518 | CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 02-09-2012 |
20130003479 | SEMICONDUCTOR MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage | 01-03-2013 |
20130058180 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A system includes a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit. The first circuit includes an interface unit that performs communication with the second circuit, a plurality of sense amplifiers including a first sense amplifier, each of the plurality of sense amplifiers performing communication with the interface unit, a first global bit line, a dummy global bit line, a plurality of first memory blocks, each of the first memory blocks including a first hierarchy switch that is connected to the first global bit line, a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line connected to the dummy global bit line, and a control circuit that controls the first hierarchy switches and the dummy hierarchy switch. | 03-07-2013 |
20130148453 | Current-mode Sense Amplifier for high-speed sensing - A sense amplifier circuit according to some implementations includes a differential input stage to receive mirrored input currents and a transistor switch whose state is controlled by a signal applied to its gate. The sense amplifier circuit includes a pair of cross-coupled NMOS transistors and a pair of cross-coupled PMOS transistors to which the mirrored input currents are coupled and whose drain nodes are shorted when the transistor switch is in a conductive state. The sense amplifier is arranged to generate a digital output signal indicative of which of the input currents is larger. | 06-13-2013 |
20130301370 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A device includes first memory blocks each including a first local bit line, first memory cells connected to the first local bit line and a first hierarchy switch connected between a first global bit line and the first local bit line, a dummy global bit line connected to the second node of a first sense amplifier, a dummy block including a dummy local bit line, dummy memory cells connected to the dummy local bit line and a dummy hierarchy switch connected between the dummy global bit line and the dummy local bit line, and a control circuit supplied with address information and configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first hierarchy switch of one of the first memory blocks designated by the address information. | 11-14-2013 |
20130336078 | SEMICONDUCTOR DEVICE, METHOD OF RETRIEVING DATA, AND MICROCOMPUTER - A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process. | 12-19-2013 |
20140029366 | MEMORY DEVICE WITH SEPARATELY CONTROLLED SENSE AMPLIFIERS - A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals. | 01-30-2014 |
20140293723 | MEMORY WITH AN ASSIST DETERMINATION CONTROLLER AND ASSOCIATED METHODS - A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value. | 10-02-2014 |
20140293724 | SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 10-02-2014 |
20140321225 | SENSE AMPLIFIER WITH DUAL GATE PRECHARGE AND DECODE TRANSISTORS - The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T | 10-30-2014 |
20150036444 | SENSOR AMPLIFIER, MEMORY DEVICE COMPRISING SAME, AND RELATED METHOD OF OPERATION - A sense amplifier comprises a sense amplifying unit configured to be connected to a bitline and a complimentary bitline of a memory device, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complimentary sensing bitline based on the sensed voltage change. It further comprises a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal, a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal, a first offset cancellation switch configured to connect the bitline with the sensing bitline in response to an offset cancellation signal, and a second offset cancellation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the offset cancellation signal. | 02-05-2015 |
20150063048 | Sample-and-Hold Current Sense Amplifier and Related Method - A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier. | 03-05-2015 |
365210110 | Compensate signal | 4 |
20080212385 | Output driver - According to one embodiment a semiconductor device is provided. The device includes a first compensator to generate a first compensated signal and a first limiter to control operation of the first compensator. Furthermore, a second compensator to generate a second compensated signal and a second limiter to control operation of the second compensator is provided. An output device is adapted to receive the first compensated signal and the second compensated signal to drive an output. | 09-04-2008 |
20080247251 | MEMORY DEVICE THAT TAKES LEAKAGE CURRENTS INTO ACCOUNT IN ACTIVATING THE READ AMPLIFIERS - A memory device is proved that includes memory cells situated at the intersection of lines and columns, and a dummy path including a first dummy column having two bit lines to which there are connected dummy memory cells, and a circuit adapted to select at least one of the dummy memory cells to discharge one of the dummy bit lines. The dummy path also includes at least one second dummy column adapted to generate a dummy leakage current (representing a leakage current of a column of the memory device selected in read mode), and a circuit adapted to copy the dummy leakage current to the one dummy bit line, so that the discharge of the one dummy bit line also depends on the dummy leakage current. | 10-09-2008 |
20090190426 | CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS - The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided. | 07-30-2009 |
20100232245 | ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION - Data is read from a memory matrix ( | 09-16-2010 |
365210120 | Voltage setting | 5 |
20080219073 | Semiconductor memory device and method for driving the same - A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory device includes a bit line sense amplifier for performing an amplification operation using a normal driving voltage or an overdriving voltage to sense and amplify data applied to bit lines, a normal driving voltage compensator configured to drive a normal driving voltage terminal according to a voltage level of the normal driving voltage terminal and target normal driving voltage levels, and a discharge enable signal generator configured to generate a discharge enable signal by adjusting an activation period of the discharge enable signal according to the overdriving voltage. | 09-11-2008 |
20090168578 | Dummy cell for memory circuits - A memory cell array includes reference cells each associated with a plurality of data cells of the array. | 07-02-2009 |
20090231939 | Circuit and Method for a Vdd Level Memory Sense Amplifier - A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed. | 09-17-2009 |
20090273999 | SENSE AMPLIFIER AND DATA SENSING METHOD THEREOF - A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage. | 11-05-2009 |
20090296508 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation. | 12-03-2009 |
365210130 | Common bit line | 1 |
20130343141 | SEMICONDUCTOR MEMORY DEVICE AND ERASURE VERIFICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a plurality of memory blocks each including a bit line to which a plurality of memory cells are connected, and a dummy bit line to which a plurality of dummy cells are connected; a reference cell; and a sense amplifier including a first input terminal to which selected memory cell of the plurality of memory cells is to be electrically connected via the bit line, and a second input terminal to which the reference cell is to be electrically connected, the dummy bit line of one memory block of the plurality of memory blocks different from another memory block of the plurality of memory blocks including the selected memory cell being to be electrically connected to the second input terminal of the sense amplifier. | 12-26-2013 |
365210140 | Plural elements per reference cell | 1 |
20090147605 | NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT - In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC. | 06-11-2009 |