Class / Patent application number | Description | Number of patent applications / Date published |
365205000 | Flip-flop used for sensing | 86 |
20080198676 | SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH A CHANGEABLE SUBSTRATE POTENTIAL - A semiconductor memory device and method with a changeable substrate potential. One embodiment provides for operating a semiconductor memory device having at least one read or write/sense amplifier. The method includes changing the substrate potential of the read or write/sense amplifier. | 08-21-2008 |
20080205176 | MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL - A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations. | 08-28-2008 |
20080205177 | LAYOUT STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE HAVING IOSA - Embodiments of the invention provide a layout for a semiconductor memory device that splits each memory bank into two blocks. Embodiments of the invention dispose input/output sense amplifiers between the two memory blocks to achieve relatively short global input/output lines to all areas of the memory bank. Shorter global input/output lines have less loading and therefore enable higher-speed data transfer rates. Some embodiments of the invention include column selection line repeaters between the two memory blocks. The column selection line repeaters reduce loading in the column selection lines, and increase column selection speed. Embodiments of the invention include both input/output sense amplifiers and column selection line repeaters disposed between the two memory blocks to increase data transfer rates on the global input/output lines and also increase column selection speed. | 08-28-2008 |
20080205178 | DRAM writing ahead of sensing scheme - This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated. | 08-28-2008 |
20080212384 | SENSE AMP CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A differential input circuit receives differential input signals at a pair of differential input terminals and produces a pair of first differential output signals. A sensing circuit senses at least one of the pair of first differential output signals reaching a certain voltage and provides an activation signal. A latch-type amplifier provides a pair of second differential output signals when activated in accordance with the activation signal. A cutoff circuit establishes connection between the differential input circuit and the latch-type amplifier and breaks connection between the differential input circuit and the latch-type amplifier in accordance with the activation signal. | 09-04-2008 |
20080219072 | Method and apparatus for a dynamic semiconductor memory with compact sense amplifier circuit - A high-density dynamic memory device with compact sense amplifier circuit is described. The memory device achieves high density through the use of a compact sense amplifier circuit that employs a single transistor to sense stored dynamic data. Functionality of the device is enabled by an architecture and method of operation that support a compact sense amplifier circuit. Enabling techniques include sequential sensing of memory columns, a two-pass write operation, a two-step refresh operation, a reference scheme that uses reference data stored in regular memory cells, and the application of digital signal processing to determine sensed data and cancel crosstalk noise. | 09-11-2008 |
20080232183 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a word line, a source line, a row decoder, and a source line driver circuit. The memory cell array includes a memory cell unit having a plurality of memory cells connected in series. The word line is connected to control gates of the memory cells. The source line is electrically connected to sources of the memory cells positioned on one end sides of the memory cell unit. The row decoder selects the word line. The source line driver circuit is arranged in the row decoder and applies a first voltage to the source line. | 09-25-2008 |
20080239849 | Semiconductor memory device with reduced sense amplification time and operation method thereof - A semiconductor memory device is capable of swiftly sensing data loaded on local I/O lines and transferring the sensed data to a global I/O line, thereby reducing an operating time of a sense amplifier by increasing the sensing and amplifying speed. The semiconductor memory device includes a sense amplifying unit, a precharging unit, a charge sharing unit, and a driving unit. The sense amplifying unit amplifies data applied to a first data line in response to an I/O strobe signal. The precharging unit precharges an output unit of the sense amplifying unit in response to a precharge signal. The charge sharing unit performs a charge sharing operation between the first data line and the output unit before a sense amplifying operation of the sense amplifying unit. The driving unit drives a second data line in response to an output signal of the sense amplifying unit. | 10-02-2008 |
20080247249 | Circuit and method for a sense amplifier - A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided. | 10-09-2008 |
20080279024 | PROGRAMMABLE BOOSTING AND CHARGE NEUTRALIZATION - A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a circuit path between the input node and the output node. Each of the capacitance stages includes a capacitor, and a control transistor having a gate capacitance in series with the capacitor, wherein the gate capacitance is configured to be added to the capacitance of the capacitor between the input node and the output node. | 11-13-2008 |
20080291764 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: word lines; global bit lines intersecting therewith; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each of which includes memory cells each having a vertical transistor structure connected to the local bit lines at a lower portion and each being formed at an intersection of the word line and the local bit line, and is arranged corresponding to each section of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line. | 11-27-2008 |
20090003108 | SENSE AMPLIFIER METHOD AND ARRANGEMENT - In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed. | 01-01-2009 |
20090027985 | SEMICONDUCTOR STORAGE DEVICE - The semiconductor storage device according to the present invention comprises a switch provided to a bit line between a memory cells and a sense amplifier and capable of continuously varying a degree of conduction; and a switch control circuit for varying the degree of conduction of the switch in accordance with an access request signal. The semiconductor storage device of the present invention enables operation in which the degree of conduction between the sense amplifier and a memory cell is increased, and an ON state is achieved during a time in which the sense amplifier amplifies the holding voltage of the memory cell and feeds the amplified holding voltage to the bit line. The access time can thereby be reduced. | 01-29-2009 |
20090040855 | METHOD AND SYSTEM FOR PROVIDING A SENSE AMPLIFIER AND DRIVE CIRCUIT FOR SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disablies at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation. | 02-12-2009 |
20090046528 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated. | 02-19-2009 |
20090059701 | Core voltage discharger and semiconductor memory device with the same - A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information. | 03-05-2009 |
20090059702 | Sense amplifier for semiconductor memory device - A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made. | 03-05-2009 |
20090086559 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the second gate electrode by applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other, and a state of the memory cell is covered to an stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation. | 04-02-2009 |
20090091995 | SENSE AMPLIFIER CIRCUIT HAVING CURRENT MIRROR ARCHITECTURE - A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit. | 04-09-2009 |
20090097347 | SENSE-AMPLIFIER CIRCUIT FOR A MEMORY DEVICE WITH AN OPEN BIT LINE ARCHITECTURE - A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current. | 04-16-2009 |
20090103382 | Gated Diode Sense Amplifiers - A sense amplifier for use in sensing a signal in an integrated circuit comprises an amplifier portion and an output portion. The amplifier portion comprises a gated diode having a gate terminal. The output portion comprises an output transistor in signal communication with the gate terminal of the gated diode and having a source terminal. A variable source voltage acts on the source terminal of the output transistor when the sense amplifier is in operation. The variable source voltage is temporarily altered when the sense amplifier is actively sensing the signal in the integrated circuit. | 04-23-2009 |
20090109776 | Sense amplifier driving circult and semiconductor device having the same - The semiconductor memory device blocks a power supply voltage, which is supplied to the sense amplifier, in a write operation, or pull-down drives first and second local I/O lines LIO and LIOB lest they reach the level of ground voltage Vss. Driving time of a write driver of the semiconductor memory device is reduced, and current consumption is reduced. A sense amplifier driving circuit of a semiconductor memory device includes a transfer unit for transferring first and second control signals in response to an enable signal which is activated in a write operation, and a power supply unit for supplying first and second power supply voltages to a sense amplifier in response to the first and second control signals. | 04-30-2009 |
20090109777 | Sense amplifier power supply circuit - A sense amplifier power supply circuit includes an overdriving unit configured to apply a first voltage to a sense amplifier in response to a first enable signal, a sense amplifier driving unit configured to apply a second voltage to the sense amplifier in response to a second enable signal, and a switching unit configured to selectively apply the first voltage or the second voltage to the sense amplifier in response to the first enable signal and the second enable signal. | 04-30-2009 |
20090109778 | LOW-POWER SENSE AMPLIFIER - In one embodiment, a sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell is provided. The sense amplifier includes: a first pair of switches including a first switch coupled to a node on the bit line and a second switch coupled to a node on the complementary bit line; a signal detector having a first input terminal coupled to the first switch and a second input terminal coupled to the second switch, the signal detector configured to sense voltages on the bit line and the complementary bit line through the first pair of switches during a read operation; a second pair of switches, wherein a first switch in the second pair couples between the node on the bit line and ground and is responsive to a data signal to be written to the memory cell and a second switch couples between the node on the complementary bit line and ground and is responsive to a complementary data signal to be written to the memory cell, wherein if either the data signal or the complementary data signal is true, a corresponding bit line is grounded so as to force the binary state of memory cell into an appropriate value during a write operation; and wherein the first pair of switches are controlled such that they turn on during a read operation while the signal detector determines the binary state of the memory cell, the first pair of switches being off during the write operation whereby a capacitance presented to the bit line and the complementary bit line by the sense amplifier is lower during the write operation than during the read operation. | 04-30-2009 |
20090109779 | Sense amplifier controlling circuit and controlling method - A sense amplifier controlling circuit for controlling a sense amplifier in a semiconductor memory, which amplifies differential electric potential of a pair of bit lines to which memory cells are connected by sequentially operating a CMOS flip-flop and a preamplifier performing an amplification operation different from each other, controls the sense amplifier, and activate the preamplifier at an early operation stage of the CMOS flip-flop and the preamplifier independently of activation of the CMOS flip-flop during the amplification operation of the CMOS flip-flop. | 04-30-2009 |
20090147604 | SENSE AMPLIFIER AND DRIVING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SENSE AMPLIFIER - The semiconductor memory device includes a bank having a cell array and a sense amplifier. A back bias voltage generating unit supplies a back bias voltage to the cell array of the bank. A negative drive voltage generating unit generates negative driving voltages including a normal pull-up voltage, an overdrive voltage, a normal pull-down voltage, and a negative voltage and supplies the negative driving voltages to the sense amplifier of the bank. A switching unit opens a connection between the back bias voltage generating unit and the negative drive voltage generating unit when in active mode and shares the back bias voltage between the back bias voltage generating unit and the negative drive voltage generating unit when in a refresh mode, in response to an external command. | 06-11-2009 |
20090154275 | SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF - A semiconductor device includes a sense amplifier, a drive circuit that operatively supplies a predetermined potential to the sense amplifier, and disconnection transistors that are provided between the sense amplifier and the drive circuit. According to the present invention, the disconnection transistors can disconnect the sense amplifier from the drive circuit. Therefore, when the sense amplifier is disconnected from the drive circuit during at least a part of a period from when the word line is activated till when the sense amplifier is activated, outflow and inflow of charge from and into the bit line can be stopped immediately. | 06-18-2009 |
20090201755 | MAINTENANCE OF AMPLIFIED SIGNALS USING HIGH-VOLTAGE-THRESHOLD TRANSISTORS - Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated. | 08-13-2009 |
20090201756 | Method and Circuit for Implementing Enhanced Efuse Sense Circuit - A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline. | 08-13-2009 |
20090207679 | Systems and Methods for Data Transfers Between Memory Cells - Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic. | 08-20-2009 |
20090213675 | SEMICONDUCTOR MEMORY DEVICE - A memory includes memory cells, wherein in a first cycle of writing first logic data, sense amplifiers apply a first potential to bit lines, drivers apply a second potential to a selected word line and a third potential to a selected source line, and the second and third potentials with reference to the first potential have the same polarities as polarities of the carriers, and in a second cycle of writing second logic data, the sense amplifiers apply a fourth potential to a selected bit line, the drivers apply a fifth potential to the selected word line and a sixth potential to the selected source line and, the sixth potential is nearer to the first potential than the second and third potentials, the fifth potential with reference to the sixth potential has the same polarity as polarities of the carriers, and the fourth potential with reference to the sixth potential has a polarity opposite to the polarities of the carriers. | 08-27-2009 |
20090251981 | MEMORY WITH A FAST STABLE SENSING AMPLIFIER - A memory includes a memory cell, a sensing amplifier, four N-type MOS transistors, a reference circuit, and a comparator. The sensing amplifier is used for sensing digital data stored in the memory cell of the memory and generating an output signal corresponding to the digital data when the memory cell is read. The sensing amplifier includes a current source, a voltage generator, an auxiliary transistor, and an operational amplifier. The auxiliary transistor is coupled in parallel to the current source so as to provide an additional current to the sensing amplifier initially. Thus, the sensing amplifier can output a stable signal in a short time so as to improve the performance of the memory. | 10-08-2009 |
20090273998 | BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF - A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved. | 11-05-2009 |
20090279370 | MEMORY CIRCUIT AND METHOD OF SENSING A MEMORY ELEMENT - The memory circuit comprises at least one memory element (T | 11-12-2009 |
20090296506 | SENSE AMPLIFIER AND DATA SENSING METHOD THEREOF - A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node. | 12-03-2009 |
20090303823 | SENSE AMP CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A differential input circuit receives differential input signals at a pair of differential input terminals and produces a pair of first differential output signals. A sensing circuit senses at least one of the pair of first differential output signals reaching a certain voltage and provides an activation signal. A latch-type amplifier provides a pair of second differential output signals when activated in accordance with the activation signal. A cutoff circuit establishes connection between the differential input circuit and the latch-type amplifier and breaks connection between the differential input circuit and the latch-type amplifier in accordance with the activation signal. | 12-10-2009 |
20100034039 | Semiconductor integrated circuit - A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation. | 02-11-2010 |
20100034040 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a plurality of memory cells connected to one word line; a plurality of sense amplifier circuits that are connected to the memory cells and divided into an N number of groups; and N number of data inversion processing circuits that respectively receive data read out from the N number of groups of sense amplifier circuits, in which after a sense amplifier circuit of a first group terminates operation, a sense amplifier circuit of a second group different from the first group operates, and each of the data inversion processing circuits performs data inversion processing based on the data read out from each of the groups of sense amplifier circuits, and outputs the data to an output terminal of each of the data inversion processing circuits. | 02-11-2010 |
20100054065 | Sense amplifier circuit and semiconductor memory device - A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell. | 03-04-2010 |
20100097873 | LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME - A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line. | 04-22-2010 |
20100110814 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE OPERATION METHOD - Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit ( | 05-06-2010 |
20100128545 | Sense amplifier and semiconductor memory device using it - A sense amplifier having a pre-amplifier and a main-amplifier is disclosed. The pre-amplifier is connected to paired data line, senses and amplifies data on the paired data line using voltage mode and outputting a pair of differential signal. The main-amplifier is connected to the paired data line, senses and amplifies data on the paired data line using current mode and generating a first amplified signal, senses and amplifies the first amplified signal using voltage mode in response to the pair of differential signal, and outputting an amplified data. | 05-27-2010 |
20100128546 | Embedded Memory Databus Architecture - A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs. | 05-27-2010 |
20100157707 | Sense Amplifier with Redundancy - A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount. | 06-24-2010 |
20100157708 | NOISE TOLERANT SENSE CIRCUIT - A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation. | 06-24-2010 |
20100195427 | 1-TRANSISTOR TYPE DRAM CELL, DRAM DEVICE AND DRAM COMPRISING THEREOF AND DRIVING METHOD THEREOF AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor device, and more precisely to an 1-transisotr type DRAM cell implemented using bulk silicon, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof. The driving method of an 1-transistor type DRAM comprises: a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process allowing a write current to be flowed from the bit line to a floating body by rasing the bit line to the second constant voltage level and raising the sensing line to the half second constant voltage level, while maintaining the bias of the word line at the second constant voltage level. | 08-05-2010 |
20100246302 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device storing a resistance difference as information, a long time is taken so as to charge and/or discharge a selected cell by an equalizer circuit, which results in a difficulty of a high speed operation. A selection circuit puts, in a selected state, at least three bit lines which includes a selected bit line connected to a selected memory cell together with unselected bit lines adjacent to the selected bit line on both sides of the selected bit line. The selected and the unselected bit lines are coupled to sense amplifiers through an equalizer circuit. The equalizer circuit puts both the selected and the unselected bit lines into charging states and thereafter puts only the selected bit line into a discharging state to perform a sensing operation. On the other hand, the unselected bit lines are continuously kept at the charging states during the sensing operation. This makes it possible to perform the sensing operation at a high speed with a rare malfunction. | 09-30-2010 |
20100296355 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The semiconductor device also includes a driver circuit having a latch circuit connected to an output of the multiplexer, and an output driver circuit connected to the latch circuit and operating under the second frequency. The voltage of a power supply of the sense amplifiers is the same as the voltage of a power supply of the output driver circuit. The power supply of the sense amplifiers and the power supply of the output driver circuit are connected to respective different power supply lines. | 11-25-2010 |
20110013471 | CURRENT MODE DATA SENSING AND PROPAGATION USING VOLTAGE AMPLIFIER - A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method may include providing a current output signal from a voltage-to-current converter in response to the voltage-to-current converter receiving the output signal. The output signal may be used to drive a current sense amplifier. | 01-20-2011 |
20110051543 | SENSE AMPLIFIER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is configured to be activated in response to a second and a fourth activation signals. The first and third activation signals and the second and fourth activation signals are provided through separate signal sources from each other. | 03-03-2011 |
20110075499 | SEMICONDUCTOR MEMORY DEVICE COMPRISING SENSING CIRCUITS WITH ADJACENT COLUMN SELECTORS - A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other. | 03-31-2011 |
20110080796 | INTEGRATED CIRCUIT - An integrated circuit is disclosed. One embodiment provides a sense amplifier; a first bit line; a second bit line. A first switch is configured to connect/disconnect the first bit line to/from the sense amplifier. A second switch is configured to connect/disconnect the second bit line to/from the sense amplifier independently from the first switch. | 04-07-2011 |
20110080797 | SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIERS - A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation. | 04-07-2011 |
20110103166 | LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE - A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier. | 05-05-2011 |
20110199847 | SENSE AMPLIFIER WITH LOW SENSING MARGIN AND HIGH DEVICE VARIATION TOLERANCE - In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P | 08-18-2011 |
20110199848 | TECHNIQUES FOR CONTROLLING A SEMICONDUCTOR MEMORY DEVICE - Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying the plurality of voltage potentials to the plurality of memory cells may include applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor, applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor, and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell may be located between the first memory cell and the second memory cell in the row of the array. | 08-18-2011 |
20110222361 | NANO-SENSE AMPLIFIER - A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. | 09-15-2011 |
20110249524 | Programmable Tracking Circuit for Tracking Semiconductor Memory Read Current - One example memory device includes a memory array, a sense amplifier, and a tracking circuit. The memory array is formed of a plurality of memory cells. The sense amplifier is for accessing the memory array. The tracking circuit is for tracking memory read current of the memory array. The tracking circuit comprises one or more columns of tracking cells. Each column is coupled to a corresponding bit line to provide a drive current on the bit line for triggering a memory read operation by the sense amplifier. At least one of the columns comprises two tracking cells connected in series to each other. | 10-13-2011 |
20120106282 | PATTERN LAYOUT IN SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below. | 05-03-2012 |
20120127816 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line. | 05-24-2012 |
20120134225 | SENSE AMPLIFIER LATCH WITH INTEGRATED TEST DATA MULTIPLEXER - A sense amplifier latch may be provided to controllably latch the output of a sense amplifier. The latch may open in response to assertion of a latch enable signal to receive data, and close in response to deassertion of the latch enable signal to capture and store the received data. Additionally, a multiplexer may be provided to select from among multiple sources of test data, such as scan data and bypass data. The multiplexer may produce a test data input to the sense amplifier latch that encodes a data value and a control value that causes the data value to be selected. Depending on the state of the test data input, the sense amplifier latch may output either a value received from the sense amplifier or a value encoded in the test data input. | 05-31-2012 |
20120213025 | SEMICONDUCTOR MEMORY DEVICE FOR MINIMIZING MISMATCH OF SENSE AMPLIFIER - A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized. | 08-23-2012 |
20120230140 | MAINTENANCE OF AMPLIFIED SIGNALS USING HIGH-VOLTAGE-THRESHOLD TRANSISTORS - Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated. | 09-13-2012 |
20120243357 | NONVOLATILE SEMICONDUCTOR STORAGE - According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels. | 09-27-2012 |
20120243358 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate including a device region which is isolated by a device isolation film, a first conductive layer provided on the device region via a gate insulation film, an inter-gate insulation film provided on the first conductive layer and including an opening on the first conductive layer, a second conductive layer disposed over the device region and the device isolation film via the inter-gate insulation film, a third conductive layer provided on the first conductive layer, isolated from the second conductive layer by a peripheral trench, and connected to the first conductive layer via the opening of the inter-gate insulation film, and source/drain diffusion layers provided, spaced apart, in the device region in a manner to sandwich the first conductive layer. | 09-27-2012 |
20120269019 | SEMICONDUCTOR DEVICE HAVING CONTROL BITLINE TO PREVENT FLOATING BODY EFFECT - A vertical semiconductor device is provided. The semiconductor device includes a cell array including a control bit line connected to cells and electrically isolated from a bit line, and a floating body control circuit for applying a floating control voltage to the control bit line in a predetermined period. | 10-25-2012 |
20120281490 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A technology is capable of improving a process margin in forming a bit line and reducing bit line resistance to improve characteristic of the semiconductor device by forming a cell bit line in a double layer structure are provided. The semiconductor device includes a buried gate buried within a cell region of a semiconductor substrate, a first bit line formed over the semiconductor substrate, a second bit line formed over the first bit line and coupled to the first bit line. The first bit line is formed in the same layer as a peripheral gate of a peripheral circuit region and the second bit line is formed in the same layer as a metal line of the peripheral circuit region. | 11-08-2012 |
20120320696 | SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER - In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. | 12-20-2012 |
20120327733 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and second control circuits. The local bus and the dummy local bus are precharged to a first potential before a read operation. In the read operation, the first control circuit outputs the selection signal to a selected switch to electrically connect a selected bit line pair and the local bus, while the second control circuit supplies a second potential lower than the first potential to the dummy local bus. The first control circuit stops outputting the selection signal when a potential of the dummy local bus is decreased to a predetermined set potential that is between the first and second potentials. | 12-27-2012 |
20130121098 | Serial Memory with Fast Read with Look-Ahead - A serial memory may have memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory block which are accessed in parallel before an entire address has been received through the serial interface. The controller is further configured to stream out one of the plurality of most significant bits upon full reception of the memory address while retrieving the remaining bits from memory using the entire address and stream out the remaining bits after the most significant bits have been streamed out. | 05-16-2013 |
20130258794 | MEMORY DEVICE HAVING CONTROL CIRCUITRY FOR SENSE AMPLIFIER REACTION TIME TRACKING - A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to the memory array. The sensing circuitry comprises a plurality of output sense amplifiers configured to sense stored data associated with respective columns of the memory array, and sense amplifier control circuitry configured to generate a sense amplifier control signal for application to control inputs of respective ones of the output sense amplifiers. The sense amplifier control circuitry comprises reaction time tracking circuitry including at least one dummy sense amplifier configured to track reaction time of one or more of the output sense amplifiers, with the sense amplifier control signal being generated at least in part responsive to an output signal of the dummy sense amplifier. | 10-03-2013 |
20130286760 | SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER - In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. | 10-31-2013 |
20130315018 | SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 11-28-2013 |
20140003176 | Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced layout Area and Power Consumption | 01-02-2014 |
20140050040 | BIT LINE SENSE AMPLIFIER AND LAYOUT METHOD THEREFOR - A bit line sense amplifier and a layout method therefor which can reduce coupling capacitance. The bit line sense amplifier is disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block and configured to include first and third switching elements substantially symmetrically formed in a first direction so that the drain terminals of the first and third switching elements face each other, second and fourth switching elements substantially symmetrically formed in the first direction so that the drain terminals of the second and fourth switching elements face each other, a first line configured to electrically couple the gate terminal of the first switching element and the drain terminal of the second switching element, and a second line configured to electrically couple the gate terminal of the third switching element and the drain terminal of the fourth switching element. | 02-20-2014 |
20140064004 | SEMICONDUCTOR DEVICE INCLUDING BURIED GATE, MODULE AND SYSTEM, AND METHOD FOR MANUFACTURING - An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device. | 03-06-2014 |
20140085997 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line. | 03-27-2014 |
20140126314 | Memory Architecture With Local And Global Control Circuitry - A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier. | 05-08-2014 |
20140140159 | SHORT ASYNCHRONOUS GLITCH - A circuit receives a parameter signal at a set or reset input, a clock signal at a clock input and a constant digital value at a data input. A synchronous signal is output from the circuit: wherein when the parameter signal is in a first state, then the output synchronous signal has the digital value; wherein when the parameter signal transitions to a second state, then the output synchronous signal transitions to an inverse of the digital value at substantially the same time; and wherein when the parameter signal transitions back to the first state, then the output synchronous signal transitions to the digital value on a next clock edge. | 05-22-2014 |
20140233336 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period. | 08-21-2014 |
20140269129 | METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL - A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided. | 09-18-2014 |
20140286116 | NOISE TOLERANT SENSE CIRCUIT - A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation. | 09-25-2014 |
20140286117 | SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER - In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. | 09-25-2014 |
20150348602 | SENSE AMPLIFIER CIRCUIT - A sense amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistive device, a second resistive device, a fifth transistor and a sixth transistor. A gate of the first transistor is coupled to a drain of the fourth transistor. A drain of the first transistor is coupled to a gate of the fourth transistor. A gate of the second transistor is coupled to a drain of the third transistor. A drain of the second transistor is coupled to a gate of the third transistor. The first resistive device is coupled to a first data line and at least the drain of the first transistor or third transistor. The second resistive device is coupled to a second data line and at least the drain of the second transistor or the fourth transistor. The sources of the third and fourth transistor are coupled together. | 12-03-2015 |
20150381199 | COMPARATORS FOR DELTA-SIGMA MODULATORS - Methods, systems and devices are disclosed, such as an electronic device that includes a plurality of data locations and a delta-sigma modulator. In some embodiments, the delta-sigma modulator includes a preamplifier coupled to the data locations and a latch coupled to the preamplifier. | 12-31-2015 |
20160125919 | APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation. | 05-05-2016 |