Class / Patent application number | Description | Number of patent applications / Date published |
365202000 | Complementing/balancing | 8 |
20090080274 | MEMORY CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE - A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data. | 03-26-2009 |
20100322025 | DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB-ARRAYS - A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other. | 12-23-2010 |
20110267912 | DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB ARRAYS - A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other. | 11-03-2011 |
20120250439 | Degradation Equalization for a Memory - In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one or a binary zero. In some implementations, the inversion may be controlled for the memory as a whole via a global indication. In other implementations, data may be inverted on a row-by-row or column-by-column basis. In other embodiments, the global indication may be changed at each boot of a device including the integrated circuit. | 10-04-2012 |
20140029365 | PRECHARGE OPERATIONS AND CIRCUITRY THERE FOR - Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of example precharge operations. By driving the digit lines to ground, charge accumulating in bodies of vertical access devices may be discharged to the digit lines in some examples. To drive the digit lines to ground, a dynamic reference may be used where the reference is ground during one portion of the precharge operation and another value, which may be between two supply voltages (e.g. V | 01-30-2014 |
20140146627 | SECONDARY BIT LINE EQUALIZER - Systems, methods, and other embodiments associated with bit line equalization are described. Systems and methods described herein provide secondary bit line equalization for embedded memory systems to reduce equalization time and improve memory performance. The reduction in equalization time is accomplished by adding a secondary equalizer in addition to a standard primary equalizer for a column of memory cells. | 05-29-2014 |
20140293720 | DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB-ARRAYS - A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other. | 10-02-2014 |
20150124543 | SEMICONDUCTOR DEVICES - Semiconductor devices are provided. The semiconductor device includes a first pre-charge element and a second pre-charge element. The first pre-charge element receives a first pre-charge signal to pre-charge a first bit line to have a first pre-charge voltage signal. The second pre-charge element receives a second pre-charge signal to pre-charge a second bit line to have a second pre-charge voltage signal. The second pre-charge signal is enabled earlier than the first pre-charge signal in the event that a data stored in a memory cell of a first cell block is loaded on the first bit line. | 05-07-2015 |