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Subclass of:

365 - Static information storage and retrieval

365189011 - READ/WRITE CIRCUIT

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DocumentTitleDate
20130044554DRAM REPAIR ARCHITECTURE FOR WIDE I/O DRAM BASED 2.5D/3D SYSTEM CHIPS - A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The control logic further comprises a wide input/output controller, a built-in-repair analyzer (BIRA), and a repair controller. A method utilizing the repair architecture provides for repairing failed columns and rows of a memory device.02-21-2013
20090201752Semiconductor memory device - There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines whether the address is a defective address. The row main decoder, the row predecoder, and the repair determining circuit all have a shape in which a column direction is set to be a longitudinal direction. The row predecoder and the repair determining circuit are arranged adjacent to each other in the column direction, and are arranged in parallel with the row main decoder.08-13-2009
20110205820Semiconductor device - The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.08-25-2011
20090196113Fuse circuit and semiconductor memory device including the same - The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing mode, such that the first signal increases when the first program unit is programmed. The second program unit is programmed in the program mode in response to the program signal and outputs a second signal in the sensing mode, such that the second signal decreases when the second program unit is programmed. The sensing circuit generates a sensing output signal in response to the first and second signals, such that the sensing output signal indicates whether or not the program units are programmed.08-06-2009
20090196112Block decoding circuits of semiconductor memory devices and methods of operating the same - A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.08-06-2009
20080259701Redundancy architecture for an integrated circuit memory - An integrated circuit memory 10-23-2008
20130028035MEMORY DEVICE - A memory device has: a plurality of memory cell blocks, the memory cell block including a plurality of memory cells, a redundancy memory cell, and a selector switching a defective memory cell among the plurality of memory cells to the redundancy memory cell; and a control circuit outputting control signals of the selectors of the plurality of memory cell blocks, based on defect information indicating whether or not each of the plurality of memory cell blocks has a defective memory cell and on specification information for specifying the defective memory cell in the memory cell block having the defective memory cell, wherein the control circuit has: a plurality of flip-flops provided in correspondence with respective bit lines of the control signals of the selectors of the plurality of memory cell blocks and for shifting the specification information serially.01-31-2013
20090122624SEMICONDUCTOR MEMORY DEVICE - A word line activation circuit having a temporary memory circuit for storing word line inactivation information for inactivating a word line of a defective memory cell, and an inactivation address sensing circuit for determining whether or not a redundant memory cell is to be used in accordance with the word line inactivation information and an address specification signal is provided for each of word lines. When the inactivation address sensing circuit determines that the redundant memory cell is to be used, a redundant word line is activated by a redundant word line activation circuit.05-14-2009
20100157703Embedded Memory Repair - A memory repair circuit for repairing one or more failures in an embedded memory includes at least one fuse register and state machine circuitry coupled to the fuse register. The state machine circuitry implements a first state machine operative: (i) to receive status information regarding the one or more failures in the embedded memory; (ii) to determine whether the memory is repairable based on the status information; (iii) when the memory is deemed repairable, to store an address corresponding to a failed memory cell of the memory; (iv) to burn the address corresponding to the failed memory cell into the fuse register using a voltage source supplied to the memory repair circuit; and (v) to verify that the address corresponding to the failed memory cell was burned into the fuse register. The state machine circuitry further implements a second state machine operative: (i) to download information stored in the at least one fuse register into at least one repair register associated with the embedded memory; and (ii) when an address is received in the circuit corresponding to a failed memory instance in the embedded memory, to reroute access to the failed memory instance to the at least one repair register.06-24-2010
20100074039SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes a memory cell array, a data input/output terminal, a data input/output circuit, and a test circuit. The data input/output circuit is provided between the memory cell array and the data input/output terminal. The data input/output circuit includes a main amplifier that amplifies data written into selected memory cells in the memory cell array during data write operation and that amplifies data read from the selected memory cells during read operation, and a memory element provided accompanying the main amplifier in order to repair a defective memory cell in the memory cell array. The test circuit starts up in test mode, writes data into the memory element through the data input/output terminal, and read data from the memory element into the data input/output terminal regardless of access address information to the memory cell.03-25-2010
20100074038Memory Dies for Flexible Use and Method for Configuring Memory Dies - A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.03-25-2010
20130135951SYSTEMS AND METHODS FOR TESTING AND ASSEMBLING MEMORY MODULES - Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises, for each memory device of a plurality of memory devices, based on testing performed on the memory device, determining whether the memory device has any defective memory locations, and if so, identifying the one or more defective memory locations, and generating data that identifies the one or more defective memory locations on the memory device; and assembling a memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises, for each memory device of the memory module having one or more defective memory locations, storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module.05-30-2013
20130039138METHODS FOR PROVIDING REDUNDANCY AND APPARATUSES - Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a memory determined to indicate a defective memory cell and an address of a redundant area of the memory, only after the data has been loaded into a buffer. The direction of the mapping is determined by the operation (e.g., programming or reading).02-14-2013
20130077419DATA GENERATION APPARATUS - An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information and the defective information. The second storage has storage regions in a number larger than the first number. The input unit inputs data to the second storage by the first number at a time. The shift number determining unit determines a shift number. The output unit outputs the data stored in the storage regions which is after a head storage region by the shift number, as the data is to be supplied to the data line having no defect sector based upon the defective information, and outputs information that differs from the data to the defective data line.03-28-2013
20130077420SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD - A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.03-28-2013
20100014367MEMORY REPAIR CIRCUIT AND REPAIRABLE PSEUDO-DUAL PORT STATIC RANDOM ACCESS MEMORY - The present invention relates to a memory repair circuit and a repairable pseudo-dual port static random access memory (pseudo-dual port SRAM). The memory repair circuit uses fewer redundant column blocks and stores a few failed block addresses to reduce the required complexity of decoding the redundant column blocks. Thus, the present invention can reduce a layout area required by redundant memory cells.01-21-2010
20130083612MEMORY DEVICE INCLUDING REPAIR CIRCUIT AND REPAIR METHOD THEREOF - A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array. The repair circuit also includes a row address comparison unit configured to compare the row address of the defective cell with a row address of a first access cell received from the outside, and to output a first row match signal when the defective cell's row address matches the row address of the first access cell, and a column address comparison unit configured to compare the column address of the defective cell with a column address of the first access cell received from the outside, and to output a first column address replacement signal if the column address of the defective cell is the same as the column address of the first access cell.04-04-2013
20100110810SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - A semiconductor memory device includes a memory cell array including primary word lines and one or more redundant word lines, a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant intervals, and a refresh-target selecting circuit configured to successively select all the primary word lines and all the one or more redundant word lines one by one in response to the respective pulses of the refresh timing signal, wherein a refresh operation is performed with respect to the word lines that are successively selected by the refresh-target selecting circuit.05-06-2010
20100110808Semiconductor memory device and control method thereof - A semiconductor memory device according to the present invention includes: a memory cell array having a normal memory cell and a redundant memory cell that is used to replace the normal memory cell when it is defective; a word driver selecting a predetermined word line within the memory cell array based on a row address supplied in synchronism with an active command, and canceling selection of the word line in response to a precharge command; and a signal control circuit resetting a repair address generated when the row address indicates the normal memory cell that is defective, without resetting a predecode signal generated by predecoding the row address, in response to issuance of the precharge command.05-06-2010
20120263001SYSTEMS, MEMORIES, AND METHODS FOR REFRESHING MEMORY ARRAYS - Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.10-18-2012
20100091593SEMICONDUCTOR MEMORY DEVICE INCLUDING SIGNAL CONTROLLER CONNECTED BETWEEN MEMORY BLOCKS - A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.04-15-2010
20100329053SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY AREA - Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect.12-30-2010
20120182817REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.07-19-2012
20120182816SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes: a row redundancy circuit and a column redundancy circuit for replacing defective sub word lines and defective bit lines included in a memory cell array, respectively; first and second electrical fuse circuits that store the addresses of the defective sub word lines and the defective bit lines, respectively; and a fuse select circuit that selects, in a first operation mode, either one of the first and second electrical fuse circuits based on an address signal supplied when a determination signal is activated, and selects, in a second operation mode, the other of the first and second electrical fuse circuits based on the address signal supplied when the determination signal is activated. According to the present invention, it is possible to flexibly switch between replacement using redundant word lines and replacement using redundant bit lines.07-19-2012
20130070548SEMICONDUCTOR MEMORY DEVICE CORRECTING FUSE DATA AND METHOD OF OPERATING THE SAME - A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.03-21-2013
20130070545SEMICONDUCTOR INTEGRATED CIRCUIT - The built-in self-test (BIST) circuit includes an address generating circuit. The BIST circuit includes a data generating circuit. The BIST circuit includes a chip enable signal generating circuit. The BIST circuit includes a control signal generating circuit. The memory block circuit includes the multiple memories. The memory block circuit includes an address converting circuit that generates, based on the address signal, an address input signal corresponding to the address of the memory to be tested out of the multiple memories, and generates a memory selection signal for selecting the memory to be tested from the multiple memories. The memory block circuit includes a memory output selecting circuit that selects and outputs data from the memory to be tested out of the multiple memories, based on the memory selection signal.03-21-2013
20130070547MEMORY SYSTEM WITH A LAYER COMPRISING A DEDICATED REDUNDANCY AREA - Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.03-21-2013
20130070546NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural blocks arranged in a first direction, each block containing plural memory cells operative to store data; a row decoder including a faulty block information holder circuit operative to store faulty block information indicative that the block is a faulty block; and a faulty block detector circuit operative to, when each of block groups includes at least one of the plural blocks, subject one of the block groups to a first detection step of simultaneously and intensively referring to pieces of faulty block information respectively corresponding to the plural blocks in one of the block groups simultaneously to detect whether the block group contains a faulty block.03-21-2013
20090129181SYSTEM AND METHOD FOR IMPLEMENTING ROW REDUNDANCY WITH REDUCED ACCESS TIME AND REDUCED DEVICE AREA - A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.05-21-2009
20090303816SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING REDUNDANCY THEREOF - A semiconductor memory apparatus includes a memory cell array. A redundancy controller that determines whether to activate a redundancy enable signal on the basis of a refresh signal and outputs the redundancy enable signal. A comparator outputs a redundancy selection signal in response to the redundancy enable signal and an address signal. A decoder activates an area corresponding to the redundancy selection signal in the memory cell array.12-10-2009
20090303815Apparatus for redundancy reconfiguration of faculty memories - A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUX12-10-2009
20090303814INTEGRATED CIRCUIT THAT STORES DEFECTIVE MEMORY CELL ADDRESSES - An integrated circuit including an array of memory cells, a circuit, volatile storage, and non-volatile storage. The circuit is configured to detect defective memory cells in the array of memory cells and provide addresses of the defective memory cells. The volatile storage is configured to store the addresses, where each entry in the volatile storage includes one of the addresses and a volatile storage master bit. The non-volatile storage is configured to store the addresses, where each entry in the non-volatile storage includes one of the addresses and a non-volatile storage master bit.12-10-2009
20090303813INTEGRATED CIRCUIT THAT STORES FIRST AND SECOND DEFECTIVE MEMORY CELL ADDRESSES - An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circuit detects second defective memory cells via the sense first addresses and stores second addresses of the second defective memory cells in the volatile storage and in the non-volatile storage.12-10-2009
20090091994SYSTEM AND METHOD FOR INITIATING A BAD BLOCK DISABLE PROCESS IN A NON-VOLATILE MEMORY - A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid command, a process for disabling access to the defective portions of the array of non-volatile memory is initiated in addition to executing the initial valid command. One implementation provides receiving a memory command and determining whether an indicator has been set. In response to the indicator not being set, access to defective regions of the array of non-volatile memory is disabled in addition to executing the memory command. The indicator is also set to prevent the disabling process from being performed in response to receipt of subsequent memory commands.04-09-2009
20090091993SEMICONDUCTOR STORAGE DEVICE AND MEMORY CELL TEST METHOD - A semiconductor storage device includes: a memory section including memory cell groups; a redundancy circuit which stops to access the memory section when the redundancy circuit section is activated, and to activate one of the redundancy memory cell groups corresponding to an address signal when the redundancy circuit section is activated; a redundancy decoder which accesses one of the redundancy memory cell groups corresponding to an input selection signal; and a decoder which accesses one of the memory cell groups corresponding to an input address signal, and stops to access the memory cell groups in response to a selection signal. In a normal mode, an access to the redundancy memory section is permitted. In a redundancy circuit inactivation mode, an access to the redundancy memory section is prohibited. Memory tests of a storage device under various conditions can be performed in a short time.04-09-2009
20130058176DETERMINING FUSEBAY STORAGE ELEMENT USAGE - Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included.03-07-2013
20110013469Redundancy circuits and semiconductor memory devices - A redundancy circuit includes at least one fuse set circuit and a fuse control circuit. The at least one fuse set circuit includes a plurality of fuse cells, each of the plurality of fuse cells having a first transistor and a second transistor having same sizes. The first transistor has a first contact resistance and the second transistor has a second contact resistance different from the first contact resistance. Each of the plurality of fuse cells stores a fuse address indicating a defective cell in a repair operation and outputs a repair address corresponding to the stored fuse address. The fuse control circuit, connected to the plurality of fuse cells, controls the plurality of fuse cells in response to a program signal and a precharge signal such that the corresponding fuse address is stored in each of the fuse cells.01-20-2011
20130064026TECHNOLOGY OF MEMORY REPAIR AFTER STACKING OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked.03-14-2013
20130163355MEMORY DEVICE - A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.06-27-2013
20090046523SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A semiconductor memory device comprising a regular cell array that includes a regular memory cell to which one of a first power supply voltage and a second power supply voltage is supplied and to which a third power supply voltage is supplied, a redundant cell array that includes a redundant memory cell to which one of the first power supply voltage and the second power supply voltage is supplied and to which the third power supply voltage is supplied, and a power supply control circuit that controls supply of the first power supply voltage and the second power supply voltage to the regular cell array and the redundant cell array, wherein a difference between the second power supply voltage and the third power supply voltage is smaller than a difference between the first power supply voltage and the third power supply voltage.02-19-2009
20090010085SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND REDUNDANCY METHOD THEREOF - A semiconductor integrated circuit device includes a first fuse circuit, a second fuse circuit, and a control signal generating circuit which sends a first control signal and executes program such that the resistance value of the first fuse circuit becomes greater than the resistance value of the second fuse circuit, and sends a second control signal and executes reprogram such that the resistance value of the second fuse circuit becomes greater than the resistance value of the first fuse circuit.01-08-2009
20100085825STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.04-08-2010
20120236668MEMORY MODULE WITH DISCRETE HEATING ELEMENT - A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.09-20-2012
20130163356SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of memory cells, a plurality of receivers, each of the plurality of receivers being provided for a corresponding one of a plurality of units set by dividing the plurality of memory cells in a unit, and each of the plurality of receivers receiving a test result of the corresponding one of the plurality of units, and a controller that reads out a plurality of test results from the plurality of receivers.06-27-2013
20120120749JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.05-17-2012
20100142299ANTI-FUSE REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DRAM HAVING THE SAME - In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.06-10-2010
20120099389MEMORY CIRCUITS, SYSTEMS, AND MODULES FOR PERFORMING DRAM REFRESH OPERATIONS AND METHODS OF OPERATING THE SAME - A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.04-26-2012
20090027980SEMICONDUCTOR MEMORY - Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect.01-29-2009
20110292747SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device which performs a repair method of replacing a repair target word line and one adjacent word line at the same time by a repair operation through an efficient decoding operation for selecting a repair target address, a test operation of enabling only a word line corresponding to a cell coupled to a bit line or a bit line bar is stably performed.12-01-2011
20100271891Accessing Memory Cells in a Memory Circuit - Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters.10-28-2010
20110194367SYSTEMS, MEMORIES, AND METHODS FOR REFRESHING MEMORY ARRAYS - Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to the digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.08-11-2011
20090154269MANAGING REDUNDANT MEMORY IN A VOLTAGE ISLAND - An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. Each of the one or more voltage islands comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions. The redundancy initialization component is configured to initialize each memory using redundancy and associated repair register with repair data. The redundancy initialization component is configured to initialize a memory using redundancy and associated repair register with repair data independent of, or in conjunction with, the initialization of other memories using redundancy and associated repair registers.06-18-2009
20090147598Integrated circuits and methods to compensate for defective memory in multiple layers of memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells.06-11-2009
20090147599Column/Row Redundancy Architecture Using Latches Programmed From A Look Up Table - A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.06-11-2009
20100124132REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells.05-20-2010
20090147600APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY - An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.06-11-2009
20100124133REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES - Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block.05-20-2010
20120033515SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.02-09-2012
20100080074SEMICONDUCTOR MEMORY DEVICE - Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant memory cell array, and the number of correcting defects is judged. Then, based on the result of the judgment, it is determined the judgment of a defective memory cell is continued or the judgment is finished to write data to a main memory cell. By providing the redundant memory cell array that stores the number of correcting defects, a state of correcting defects can be observed fast in such a manner.04-01-2010
20100080073SEMICONDUCTOR MEMORY - A semiconductor memory includes: a plurality of regular memory cells; a first redundant memory cell; a second redundant memory cell; a first redundancy program circuit, first defect position information indicating a position of a first defective regular memory cell being programmed into the first redundancy program circuit; a second redundancy program circuit, second defect position information indicating a position of a second defective regular memory cell being programmed into the second redundancy program circuit; a redundancy switch circuit which couples signal lines to the regular memory cell, the first redundant memory cell, and the second redundant memory cell; and a redundancy signal switch circuit which replaces the first defect position information and the second defect position information with each other when the second defective regular memory cell is located between the first defective regular memory cell and the first redundant memory cell.04-01-2010
20090080273SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY MEMORY BLOCK AND CELL ARRAY STRUCTURE THEREOF - A semiconductor memory device having a redundancy memory block and a cell array structure thereof, the semiconductor memory device having a plurality of sub-mats constituting a memory cell array, wherein each of the plurality of sub-mats includes a plurality of normal memory blocks of which each includes a plurality of normal memory cells and that are disposed adjacent one another; and at least one redundancy memory block having the same structure as the plurality of normal memory blocks, being disposed adjacent at least one of the plurality of normal memory blocks and having a plurality of redundancy memory cells for a row and column repair, thereby enhancing a redundancy efficiency.03-26-2009
20090201754SEMICONDUCTOR DEVICE HAVING TRANSMISSION CONTROL CIRCUIT - A semiconductor device has a transmission control circuit comprising a signal transmission circuit, an output control circuit, a replica circuit and a detection circuit. The single transmission circuit receives a predetermined signal in synchronization with a first control signal, and transmits and outputs the signal through a signal bus in synchronization with a second control signal. The output control circuit supplies the second control signal and controls an output timing thereof. The replica circuit transmits and outputs a replica signal (having level shifted in response to the input timing of the predetermined signal) through a replica signal bus having the same transmission characteristics as the signal bus. The detection circuit detects shifting of the replica signal and supplies a feedback signal to the output control circuit whose output timing is controlled in accordance with the shifting timing of the replica signal based on the feedback signal.08-13-2009
20090201753Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address - There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.08-13-2009
20090285043Block Repair Scheme - Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with a section associated with a block failure to distributed redundant rows.11-19-2009
20110199845REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF - A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.08-18-2011
20110170365ROW ADDRESSING - Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2̂n number of normal rows and mapping the row address to a redundant row address by subtracting a value from the row address.07-14-2011
20090103379INTEGRATED CIRCUIT MEMORY HAVING DYNAMICALLY ADJUSTABLE READ MARGIN AND METHOD THEREFOR - A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.04-23-2009
20090168571DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF - Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.07-02-2009
20100284234MEMORY CONTROL METHOD AND MEMORY CONTROL DEVICE - A memory control method that carries out first-in first-out access control for a memory having a plurality of storage areas, including: selecting, as write positions, an address of a storage area in a storage block having at least one or more storage areas and an address of a storage area in any one of a plurality of redundant blocks that are made redundant with respect to the storage block and have at least one or more storage areas when the write positions are selected to write data to the memory; and selecting, as read positions, an address of a storage area of the storage block and an address selected by the selecting of the write position from among the addresses of a plurality of the redundant blocks when the read positions are selected to read data written by the writing of the data to the memory.11-11-2010
20100110809SEMICONDUCTOR MEMORY DEVICE AND SYSTEM WITH REDUNDANT ELEMENT - A semiconductor memory device includes a memory cell array, a redundant element, an address specifying circuit configured to select one of a plurality of addresses as a redundancy address in response to a switchover signal, a decoder circuit configured to select the redundant element in response to an externally applied address that matches the redundancy address selected by the address specifying circuit, and a test mode setting circuit configured to change the switchover signal in response to an externally applied input, thereby to cause the redundancy address assigned to the redundant element to be switched between different ones of the plurality of addresses.05-06-2010
20120294100METHOD AND APPARATUS FOR MEMORY POWER AND/OR AREA REDUCTION - A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V11-22-2012
20100061168FUSES FOR MEMORY REPAIR - Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired. Others of the fuses identify how the repair is accomplished.03-11-2010
20100290297Semiconductor Memory Device - A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.11-18-2010
20090003098Method for Hiding Defective Memory Cells and Semiconductor Memories - A method for hiding defective memory cells in a semiconductor memory having a plurality of memory cells coupled with word lines for controlling is suggested. In the method, at least one word line is determined, where one control signal selects the at least one defective memory cell. For hiding the at least one defective memory cell, a signal inverted with regard to the selection signal is applied to the at least one determined word line during addressing of the plurality of memory cells.01-01-2009
20110205819REDUNDANCY DATA STORAGE CIRCUIT, REDUNDANCY DATA CONTROL METHOD AND REPAIR DETERMINATION CIRCUIT OF SEMICONDUCTOR MEMORY - A redundancy data storage circuit of a semiconductor memory includes a memory cell array; a write driver configured to write redundancy data in the memory cell array in response to a test signal; and a sense amplifier configured to detect and output the redundancy data written in the memory cell array in response to a read signal.08-25-2011
20090147601Non-volatile memory structure - A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number.06-11-2009
20090168570REDUNDANCY CIRCUIT USING COLUMN ADDRESSES - A redundancy circuit includes an address redundancy circuit block that compares column address information of a defective memory cell and an external input column address and outputs a redundancy column activation signal, and an input/output (IO) redundancy circuit block that, in response to IO fuse information, which is information about a sub-block where a column line of the defective memory cell is arranged, and the redundancy column activation signal, controls whether or not to activate a global IO line connected to an IO pad of the sub-block.07-02-2009
20090168572SEMICONDUCTOR MEMORY - In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is arranged.07-02-2009
20080291760Sub-array architecture memory devices and related systems and methods - Memory devices, systems and methods implementing an architecture for partitioning a memory area of normally used memory cells and redundant memory cells are disclosed. A memory area is partitioned into a plurality of substantially equally sized sub-arrays of normally used memory cells and redundant memory cells. The groups of memory cells in a first portion of the sub-arrays are each selectable by a first quantity of select signals and a second portion of the sub-arrays are each selectable by a second quantity of select signals. One of the plurality of sub-arrays partially includes all of the groups of the redundant memory cells selectable by respective redundant select signals.11-27-2008
20080304342SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRUIT - A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.12-11-2008
20080310242SYSTEMS FOR PROGRAMMABLE CHIP ENABLE AND CHIP ADDRESS IN SEMICONDUCTOR MEMORY - Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.12-18-2008
20110007589Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells.01-13-2011
20110007588Defective Bit Scheme for Multi-Layer Integrated Memory Device - Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.01-13-2011
20110267909FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing mode, such that the first signal increases when the first program unit is programmed. The second program unit is programmed in the program mode in response to the program signal and outputs a second signal in the sensing mode, such that the second signal decreases when the second program unit is programmed. The sensing circuit generates a sensing output signal in response to the first and second signals, such that the sensing output signal indicates whether or not the program units are programmed.11-03-2011
20100135092CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS - A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.06-03-2010
20090190422Electronic fuses - The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data received from said fusebox; a data communication path linking said fusebox controller with said fusebox; wherein said data stored in said fusebox is compacted data and said at least one fusebox controller comprises a data expander for expanding said compacted data received from said fusebox via said data communication path prior to repairing any faulty elements in said circuitry.07-30-2009
20090190423SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A semiconductor memory is provided which performs redundancy on a memory cell by a given bit unit, the semiconductor memory includes: a comparator circuit that compares an input address and a redundancy address; a judgment circuit that judges whether to perform the redundancy based on a compared result, wherein the judgment circuit outputs a plurality of redundancy judgment signals that indicates whether to perform redundancy for each portion obtained by dividing the given bit unit by n which is an integer equal to or greater than two.07-30-2009
20110267908REPAIR CIRCUIT AND REPAIR METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A repair circuit of a semiconductor memory apparatus includes a repair address detection circuit that determines the occurrence of a failure in a memory block based on a plurality of test data signals outputted from the memory block, and stores an address corresponding to the memory block determined to have failed as a repair address, and an anti-fuse circuit that receives the repair address from the repair address detection circuit and electrically programs the repair address to store a programmed address.11-03-2011
20090168569Method and device for redundancy replacement in semiconductor devices using a multiplexer - A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row.07-02-2009
20110188332Semiconductor memory device having regular area and spare area - Memory arrays ARY08-04-2011
20090161457Semiconductor storage device having redundancy area - A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell in the normal area; a normal area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the normal area; and a redundancy area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the redundancy area in parallel with the CBR refresh operation of the memory cell in the normal area.06-25-2009
20090161458CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS - A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.06-25-2009
20090129182Memory module with failed memory cell repair function and method thereof - A memory module with failed memory cell repair function and method thereof are provided. The memory module comprises a programming interface, a mode register, a control signal generator, a fuse unit, a main memory array and a redundant memory array, wherein the programming interface is defined by selecting pins from a standard interface of the memory module. The programming interface is used to input a plurality of programming commands and a plurality of programming data. When the failed memory cells have occurred within the main memory array, the mode register will enter into a programming mode according to the programming commands, and the control signal generator will program the fuse unit, such that the redundant memory cells of the redundant memory array will be used to replace the failed memory cells. Thus, the fuse unit can be programmed directly through the standard interface, and the repairing period and the cost will be reduced efficiently.05-21-2009
20120069691BLOCK REPAIR SCHEME - Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with a section associated with a block failure to distributed redundant rows.03-22-2012
20120069690SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD - A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit.03-22-2012
20120069689BUILT-IN SELF REPAIR FOR MEMORY - A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are compared. A repair method using either the redundant row block or the redundant column block is selected. The memory is repaired by replacing a row block having at least one faulty bit with the redundant row block or replacing a column block having at least one faulty bit with the redundant column block.03-22-2012
20120069688IMPLEMENTING SINGLE BIT REDUNDANCY FOR DYNAMIC SRAM CIRCUIT WITH ANY BIT DECODE - A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input.03-22-2012
20130215695SELF-REPAIRING MEMORY - A memory array has a plurality of rows. Each row of the plurality of rows includes a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the memory word associated the each first bit has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. Each second bit of a plurality of second bits is associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows. A state of the each second bit indicates whether the redundancy word associated with the each second bit has had an error.08-22-2013
20110141835CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS - A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.06-16-2011
20090185438SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CIRCUIT FOR REPAIRING DEFECTIVE UNIT CELL, AND METHOD FOR REPAIRING DEFECTIVE UNIT CELL - A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input.07-23-2009
20080316844SELECTION METHOD OF BIT LINE REDUNDANCY REPAIR AND APPARATUS PERFORMING THE SAME - A selection method of bit line redundancy repair includes the steps of providing a plurality of logical addresses of memory blocks in the normal cell array, generating a plurality of extra fuse signals, generating a code based on states of the extra fuse signals, the code matching a defective type of the memory blocks, and selecting a plurality of redundancy blocks in the redundancy cell array to replace the memory blocks according to the code. The apparatus includes a redundancy repair enable circuit for generating a redundancy enable signal based on logical addresses of the memory blocks, a controlling fuse circuit for sending a code matching a defective type of the memory blocks, and a redundancy decoder circuit for receiving the redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks.12-25-2008
20090213671CIRCUIT AND METHOD FOR CONTROLLING REDUNDANCY IN SEMICONDUCTOR MEMORY APPARATUS - Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy control block. The peripheral circuit redundancy control block buffers and latches an external command to generate an internal command. The peripheral circuit redundancy control block also buffers and latches an external address to generate a global address by comparing the external address with a predetermined output signal of a fuse circuit. The memory bank redundancy control block receives the global address corresponding to the internal command to selectively activate a redundancy word line or a main word line, such that the fuse circuit is provided in the peripheral circuit redundancy control block.08-27-2009
20090219772Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.09-03-2009
20090251978INTEGRATION OF LBIST INTO ARRAY BISR FLOW - A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.10-08-2009
20120195144SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory cell array is correct or incorrect; and an analysis circuit that supplies, in a first operation mode, the electrical fuse circuit with an address signal supplied when the determination signal is activated, and supplies, in a second operation mode, the electrical fuse circuit with an address signal supplied when a data mask signal supplied from outside is activated irrespective of the determination signal.08-02-2012
20090257296Programmable memory repair scheme - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.10-15-2009
20100149894Semiconductor memory device that can relief defective address - To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.06-17-2010
20120195145SEMICONDUCTOR MEMORY FOR DISCONNECTING A BIT LINE FROM A SENSE AMPLIFIER IN A STANDBY PERIOD AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY - Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on.08-02-2012
20100157704Semiconductor memory device that can relief defective address - Plural nonvolatile address storing circuits hold address data. A serial transfer circuit sequentially transfers the address data stored in each of the nonvolatile address storing circuits. A serial reception circuit sequentially receives the address data transferred by the serial transfer circuit. An address latch circuit holds the address data received by the serial reception circuit. An address comparison circuit compares each of the address data stored in the address latch circuit with an input address, and determines whether each address data coincides with the input address.06-24-2010
20100002530Memory Address Repair Without Enable Fuses - A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.01-07-2010
20090116318SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit.05-07-2009
20080298144Semiconductor Memory Device Capable of Confirming a Failed Address and a Method Therefor - A semiconductor memory device includes an address buffer, a row decoder, a column decoder, a fuse circuit, a memory cell array including regular and redundant memory cells, a regulator, a regular sense amplifier, a redundant sense amplifier, a selection circuit, an input/output buffer, and a test control circuit for a test mode. The test control circuit controls the regular and redundant sense amplifiers so as to output the signal upon accessing a regular memory cell different in level from that output upon accessing a redundant memory cell, whereby a failed address can be electrically confirmed with ease.12-04-2008
20090316505Soft Error Robust Static Random Access Memory Cell Storage Configuration - A Static Random Access Memory (SRAM) cell storage configuration is provided with an improved robustness to radiation induced soft errors. The SRAM cell storage configuration comprises the following elements. First and second storage nodes are configured to store complementary voltages. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error.12-24-2009
20110058434SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a plurality of memory devices each comprising a memory cell array which includes a plurality of memory cells to store data, a spare part which includes a redundant cell to avoid a memory cell judged to be defective in the plurality of memory cells and conduct redundancy repair on data, and a switching circuit to avoid the defective memory cell and conduct switching to the redundant cell; and a repair code decoding circuit comprising a storage circuit which stores a repair code, a decoder which outputs a repair decoded signal obtained by decoding the repair code, wherein the switching circuit respectively in the memory devices avoids a memory cell corresponding to the repair decoded signal and conducts switching to the redundant cell of the memory devices in accordance with the repair decoded signal.03-10-2011
20090116319Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.05-07-2009
20090116317Block repair apparatus and method thereof - A block repair apparatus includes a plurality of cell blocks, a block repair fuse, a block isolation control unit, and a block repair selector. The block repair fuse outputs a repair signal of the plurality of cell blocks. The block isolation control unit outputs a control signal for activating the plurality of cell blocks or electrically isolating a defective cell block of the plurality of cell blocks, in response to the block repair signal. The block repair selector outputs a block repair selection signal for replacing the defective cell block with another cell block in response to a cell block address signal.05-07-2009
20090073788Repairing Advanced-Memory Buffer (AMB) with Redundant Memory Buffer for Repairing DRAM on a Fully-Buffered Memory-Module - A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.03-19-2009
20090257297MULTI-CHIP SEMICONDUCTOR DEVICE PROVIDING ENHANCED REDUNDANCY CAPABILITIES - A semiconductor device including a plurality of semiconductor chips is provided. A semiconductor device includes a storing unit in which redundancy information portions are stored, and a comparing unit comparing a current address to the redundancy information portions and enabling or disabling operation of a semiconductor device based on the comparison result.10-15-2009
20090109773SEMICONDUCTOR DEVICE AND REFRESH METHOD - In order to successively perform refresh operations, a semiconductor device has a plurality of regions performing a repair independently from each other, even when the repair is carried out in the region by a replacement with a repair memory block included in a plate included in each region. Specifically, the successive refresh operations are performed by alternately activating word lines in the respective regions so as to ensure a sufficiently long precharge period.04-30-2009
20080285365Memory device for repairing a neighborhood of rows in a memory array using a patch table - A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N−1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N−1, N, and N+1 to a table stored in the memory device.11-20-2008
20080273405Multi-bit programming device and method of multi-bit programming - A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.11-06-2008
20110122716DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF - Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.05-26-2011
20100322024SEMICONDUCTOR MEMORY, SYSTEM, OPERATING METHOD OF SEMICONDUCTOR MEMORY, AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY - A plurality of memory blocks includes real memory cells and redundancy memory cells, are accessed independently during a normal operation mode, and are accessed simultaneously during a test mode in order for common data to be written to the plurality of memory blocks. A block control unit selects the plurality of memory blocks irrespective of a block address signal in order to execute a compression test. During the test mode, a redundancy access unit simultaneously accesses the redundancy memory cells of the plurality of memory blocks when a forced redundancy signal supplied to a block address terminal indicates first level. Therefore, the redundancy memory cells of the plurality of memory blocks may simultaneously access and test without providing any special terminal. As a result, before a defect is relieved, an operation test of the redundancy memory cells may efficiently execute, which may shorten the test time.12-23-2010
20100322023SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE TEST METHOD - A semiconductor device includes a first memory including a first memory cell and a first redundant memory cell; a first test circuit configured to test the first memory and output first defect information indicating a defective portion included in the first memory cell; a first storage part; and a first control circuit configured to, based on unmodified information stored in the first storage part, and the first defect information, determine modified information to be stored in the first storage part, wherein the first memory identifies the defective portion based on the modified information of the first storage part and replaces the first memory cell including the defective portion with the first redundant memory cell.12-23-2010
20110242917SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit configured to generate a line choice address signal by combining the first address signal and the repair address signal according to a determination as to whether the repair address signal is to be used; and a cell line decoding unit configured to select one of a normal cell region and a redundancy cell region according to the determination, and select one of a plurality of local cell lines provided in the selected cell region in response to the line choice address signal.10-06-2011
20090067270STRUCTURE FOR IMPROVED MEMORY COLUMN REDUNDANCY SCHEME - A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.03-12-2009
20090067269MEMORY COLUMN REDUNDANCY SCHEME - A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.03-12-2009
20110026338REDUNDANCY CIRCUIT OF SEMICONDUCTOR MEMORY - A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information signal and a second mat grouping information signal and enable an enable signal when at least one of the plurality of enable fuses is cut and a mat grouping information signal corresponding to the cut fuse is inputted; a fail address setting control block configured to select the first mat grouping information signal or the second mat grouping information signal depending upon whether an enable fuse corresponding to the first mat grouping information signal is cut or not, and generate fail setting addresses; and a comparison section configured to compare the fail setting addresses with real addresses and generate a redundancy address.02-03-2011
20110019491REDUNDANCY SYSTEM FOR NON-VOLATILE MEMORY - A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.01-27-2011
20110019490SEMICONDUCTOR MEMORY - A semiconductor storage device includes a memory cell array that stores data and includes a plurality of memory cells two dimensionally arrayed on row and column lines extending along row and column directions, at least one of the memory cells assigned to a redundant memory cell having a lager area size than the other memory cells, the plurality of memory cells and at least one of the redundant memory cells arrayed on at least one of the row lines.01-27-2011
20100142298MEMORY COMPILER REDUNDANCY - An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit. Means are provided in the memory instances for comparing incoming memory addresses to address bits for defective memory subunits stored in each memory-instance register.06-10-2010
20100220538Integrated circuit memory power supply - An integrated circuit memory 09-02-2010
20110085396REPAIR FUSE DEVICE - A repair fuse device is provided. The repair fuse device remarkably reduces the number of the enable fuse cuttings by making initial states of all repair fuse sets to a repair state, cutting an address fuse corresponding to a defective cell, and cutting an enable fuse corresponding to a defective redundancy cell.04-14-2011
20110176377SEMICONDUCTOR MEMORY DEVICE - A driver circuit having a redundant control function to store address data of a defective memory cell is provided to compensate a defect of a memory cell array. In other words, address data of a defective memory cell is stored not by using part of the memory cell array, but by using a non-volatile memory, which is provided in a memory controller, to store address data of a defective memory cell. The memory controller storing the address data of a defective memory cell contributes an increase in process speed, because it is not necessary to access the memory cell array in order to obtain the address data of the defective memory cell.07-21-2011
20090016129DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD - A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.01-15-2009
20100054061Semiconductor memory device having bit test circuit with ignore function - A semiconductor memory device including a bit test circuit with an ignore function is provided. The semiconductor memory device includes a memory cell array and a bit test circuit. The memory cell array includes a plurality of memory cells. The bit test circuit is configured to perform a parallel bit test to determine defective memory cells based on bits received from the plurality of memory cells, a tester signal for each of the plurality of memory cells, and a mode register set signal for each of the plurality of memory cells. The bit test circuit is also configured to output a non-defective pass signal for at least one of the plurality of memory cells based on at least one of the at least one bit received from the at least one memory cell, the tester signal for the at least one memory cell and the mode register set signal for the at least one memory cell.03-04-2010
20120243355SEMICONDUCTOR APPARATUS - Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input data from an external device to the memory block chip or transmit output data from the memory block chip to an external device and process the input data or the output data by selectively enabling a clock phase control unit and a signal processing unit according to the specifications.09-27-2012
20100135091Semiconductor memory devices having redundancy arrays - A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.06-03-2010
20090213672LOGIC EMBEDDED MEMORY HAVING REGISTERS COMMONLY USED BY MACROS - A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.08-27-2009
20090290440Row Addressing - Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed.11-26-2009
20110149664WORD LINE BLOCK/SELECT CIRCUIT WITH REPAIR ADDRESS DECISION UNIT - A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control signal and an active command signal.06-23-2011
20090021999SEMICONDUCTOR DEVICE - Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter.01-22-2009
20090185439ARCHITECTURE OF HIGHLY INTEGRATED SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; and a second column control circuit region corresponding to a third memory bank and disposed adjacent to the first column control circuit region.07-23-2009
20120170394COLUMN ADDRESS CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF GENERATING COLUMN ADDRESSES - The column address circuit of a semiconductor memory device according to an aspect of the present disclosure includes a column address generation circuit configured to generate an internal dummy clock in response to a data output enable signal, generate an internal clock in response to a read enable signal, generate first count addresses in response to the internal dummy clock, and generate normal count addresses in response to the internal clock after the generation of the first count addresses, where the read enable signal is activated later than the data output enable signal, and a column address output circuit configured to store the first count addresses and the normal addresses and to generate column addresses by synchronizing the first count addresses and the normal addresses with output clocks, respectively.07-05-2012
20080279020SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.11-13-2008
20110164463Structure and Method for Decoding Read Data-Bus With Column-Steering Redundancy - A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redundancy. A master redundancy signal is triggered when column steering redundancy is requested. A plurality of sense amplifiers, wherein, each sense amplifier in the plurality of sense amplifiers is coupled to at least one memory cell in an array of memory cells. A second decoder receives the input address and selectively activates a first set of sense amplifiers of the plurality of sense amplifiers and selectively activates a second set of sense amplifiers in the plurality of amplifier only when the master redundancy signal is activated.07-07-2011
20100284233SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or more repair word lines arranged in each of the cell arrays, and a plurality of repair information storages configured to store bank information and row addresses of the array word lines to be replaced with the repair word lines.11-11-2010
20100329052Word line defect detecting device and method thereof - Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line.12-30-2010
20110096615MEMORY DEVICES HAVING REDUNDANT ARRAYS FOR REPAIR - Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data transmission. The memory device also includes one or more multiplexers/demultiplexers, wherein each of the multiplexers/demultiplexers is electrically coupled to one or more, but not all, of the global I/O lines. The memory device further includes a plurality of local I/O lines, each configured to provide a data path between one of the multiplexers/demultiplexers and one or more, but less than the first number, of the columns in the sub-array. This configuration allows local I/O line repairability with fewer redundant elements, and shorter physical local I/O lines, which translate to improved speed and die size reduction.04-28-2011
20100097871REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.04-22-2010
20100165766Semiconductor Memory Device - A semiconductor memory device includes a fuse set configured to form a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells and to output a redundancy address corresponding to a programming state of the plurality of fuses where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells, and at least one current controlling unit configured to control a driving current flowing through the current path according to at least one detection signal.07-01-2010
20100165765PROTECTION REGISTER FOR A NON-VOLATILE MEMORY - A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory cells. The memory further includes a protection register comprising storage elements configured to store configuration data of the memory device. The storage elements of the protection register are redundant memory cells not being used to replace defective memory cells.07-01-2010
20100165764MEMORY DEVICE WITH REDUCED CURRENT LEAKAGE - The memory device (for example, a DRAM) includes a matrix of memory cells arranged in a plurality of rows and columns (for example, organized in pairs), which include redundancy rows and columns for replacing defective rows and columns. Each one of a plurality of bit lines is connected to the cells of a corresponding column, and each one of a plurality of word lines is connected to the cells of a corresponding row. A bit line driver is used for biasing the bit lines and a word line driver is used for biasing the word lines. Each one of a plurality of selectors is arranged along a potential conduction path between the bit line driver and the word line driver through a set of corresponding word lines and bit lines. A selection driver is used for setting each selector to a first resistance (for example, closed) if the corresponding rows and columns are non-defective or to a second resistance higher than the first resistance (for example, open) if at least one of the corresponding rows and columns is defective.07-01-2010
20100195425SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND MEMORY REPAIR METHOD - A semiconductor device includes a BIST circuit configured to detect a defective bit in a DRAM connected to the semiconductor device, and retrieve an address of the detected defective bit, a non-volatile eFuse macro configured to retain the address of the defective bit in the DRAM, the defective bit being detected by the BIST circuit, and a repair register configured to store data for the address of the defective bit. The semiconductor device also includes an address controller configured to, based on the address retained in the eFuse macro, perform control to use the repair register during writing or reading of data to or from the address of the defective bit.08-05-2010
20100195424SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device 08-05-2010
20110149665CIRCUIT FOR CONTROLLING REDUNDANCY IN SEMICONDUCTOR MEMORY APPARATUS - Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy control block. The peripheral circuit redundancy control block buffers and latches an external command to generate an internal command. The peripheral circuit redundancy control block also buffers and latches an external address to generate a global address by comparing the external address with a predetermined output signal of a fuse circuit. The memory bank redundancy control block receives the global address corresponding to the internal command to selectively activate a redundancy word line or a main word line, such that the fuse circuit is provided in the peripheral circuit redundancy control block.06-23-2011
20090175104Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.07-09-2009
20110216614SEMICONDUCTOR DEVICE ENABLING REFRESHING OF REDUNDANT MEMORY CELL INSTEAD OF DEFECTIVE MEMORY CELL - A semiconductor device includes memory blocks MB09-08-2011
20110051538METHODS AND MEMORY DEVICES FOR REPAIRING MEMORY CELLS - Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.03-03-2011
20080273406ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED NUMBER OF REDUNDANT ELEMENTS - A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.11-06-2008
20080205171Redundant cross point switching system and method - A redundant cross point switching is achieved by mapping a redundant column/row of point cells and enabling at least one of the switching devices which is associated with each column/row to define an alternate path around the defective point cell which replicates the function of the switching location of the defective point cell.08-28-2008
20120307578SEMICONDUCTOR DEVICE HAVING REDUNDANT SELECT LINE TO REPLACE REGULAR SELECT LINE - Disclosed herein is a semiconductor device that includes a plurality of normal memory cells, a plurality of first normal lines each coupled to corresponding one or ones of the normal memory cells, a plurality of redundant memory cells, and first and second redundant lines each coupled to corresponding one or ones of the redundant memory cells. The first redundant line is configured to replace selected one or ones of the normal lines and the second line is configure to replace any one of the selected one or ones of the normal lines and remaining one or ones of the normal lines.12-06-2012
20120039140FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.02-16-2012
20120147685SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device including an open bit line core architecture includes a plurality of array areas, wherein each of the array areas includes two redundant array blocks, a plurality of real array blocks, and a power supply capacity control unit. The two redundant array blocks contain only redundant word lines and located in edge portions at both ends of the array area, and the plurality of real array blocks contain only real word lines and arranged between the two redundant array blocks by interposing a sense amplifier in alternating fashion. The power supply capacity control unit is configured to increase power supply capacity for a first array area when word line redundancy switching is performed in the first array area to replace any one of the real word lines with a corresponding one of the redundant word lines.06-14-2012
20120155202DEFECTIVE MEMORY CELL ADDRESS STORAGE CIRCUIT AND REDUNDANCY CONTROL CIRCUIT INCLUDING THE SAME - A fail address storage circuit includes a fail address storage unit configured to store a fail address and a discrimination information storage unit configured to store information indicating whether a value stored in the fail address storage unit is a row address or column address.06-21-2012
20110063933Semiconductor device, relief-address-information writing device, and relief-address-information writing method - To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming circuit that writes into any one of fuse sets the relief address information generated by the relief-address generating circuit. With this configuration, repetition of a programming operation by the total number of the fuse sets at the maximum completes a series of write processing on relief address information. Therefore, it is possible to reduce the time required for a series of write processing on relief address information.03-17-2011
20120176851METHODS AND MEMORY DEVICES FOR REPAIRING MEMORY CELLS - Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.07-12-2012
20110158012SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CIRCUIT FOR REPAIRING DEFECTIVE UNIT CELL - A semiconductor memory device includes a first bank including a plurality of cell matrices a second bank including a plurality of cell matrices and a shared-fuse set, which is shared by the first and second banks, configured to output a defect indication signal when the first bank or the second bank is enabled and a defective cell matrix is included in the enabled bank.06-30-2011
20110090751SYSTEMS AND METHODS FOR EFFICIENTLY REPAIRING DYNAMIC RANDOM-ACCESS MEMORY HAVING MARGINALLY FAILING CELLS - A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.04-21-2011
20120008441SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit configured to control a normal memory cell or a redundancy memory cell corresponding to the external address to be accessed in response to the repair control signal and an internal active signal, and an activation interval detection unit configured to generate an interval detection signal by detecting a time interval between an activation timing of the repair control signal and an activation timing of the internal active signal in a test operation mode.01-12-2012
20120057419SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes an address controller for storing fail column addresses and sequentially outputting the fail column addresses while a first control signal is activated and a control logic for performing control so that data indicating a program pass is inputted to each of main page buffers associated with the respective fail column addresses outputted from the address controller while the first control signal is activated.03-08-2012
20120026816DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE - During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.02-02-2012
20120026815Semiconductor device and method of testing the same - A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit.02-02-2012
20100172197Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.07-08-2010
20110032781MEMORY DEVICE AND MEMORY CONTROL METHOD - The embodiments of the present invention disclose a memory device having a fast and shared redundancy decision scheme and a memory control method. The memory device includes an address receiver, a command receiver, a command controller, a row address generator, a column address generator and a shared redundancy decision circuit.02-10-2011
20120314520Memory Architecture With Redundant Resources - A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses.12-13-2012
20120120748TEST APPARATUS AND REPAIR ANALYSIS METHOD - A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each block; a row fail counter that, for each row address in a group including a plurality of the blocks in the memory under test, counts the fail cells indicated by the address fail data; and a column fail counter that counts the fails cells for each column address.05-17-2012
20120250437SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM - Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.10-04-2012
20100290298FUSE CIRCUIT AND REDUNDANCY CIRCUIT - A fuse circuit or a redundancy circuit is capable of detecting a fuse with a crack. The fuse circuit includes a fuse block configured to drive an output node through a current path including a fuse in response to a fuse enable signal, and a voltage detection block configured to detect a voltage level of the output node based on a critical voltage adjusted according to a test mode signal, thereby generating a fuse condition signal.11-18-2010
20100290296SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 211-18-2010
20100254205Integrated circuit - Provided is an integrated circuit including: multiple memory cells; a redundant memory having a function of repairing a defective cell included in the multiple memory cells by placing a corresponding fuse among multiple fuses into a first state; a fuse data conversion circuit that generates first information of a first defective cell based on position information of the fuse placed into the first state corresponding to the first defective cell having been repaired; a repair data generation circuit that generates, upon detection of a second defective cell as a result of a test for the multiple memory cells, repair information for repairing the second defective cell according to the first information and second information of the second defective cell; and a fuse state change circuit that places a predetermined fuse among the multiple fuses into the first state according to the repair information generated by the repair data generation circuit.10-07-2010
20100246299SEMICONDUCTOR STORAGE DEVICE AND REDUNDANCY METHOD - A semiconductor storage device includes a normal area that contains a plurality of memory cells and a redundancy area that contains a plurality of memory cells. The semiconductor storage device further includes a delaying unit that changes, between a first mode in which both the normal area and the redundancy area are used and a second mode in which only the normal area is used without use of the redundancy area, a timing for issuing a cell-array control signal for selecting a memory cell from among the memory cells used in a corresponding mode.09-30-2010
20100246297INTEGRATED CIRCUIT HAVING AN EMBEDDED MEMORY AND METHOD FOR TESTING THE MEMORY - A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.09-30-2010
20100246298INTEGRATED CIRCUIT MEMORY HAVING ASSISTED ACCESS AND METHOD THEREFOR - A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation.09-30-2010
20120127813DEVICE AND METHOD FOR STORING ERROR INFORMATION OF MEMORY - A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column address of one defective cell. Each of the child memories stores a column address of a defective cell, having a row address identical to a row address stored in the corresponding parent memory, or a row address of a defective cell, having a column address identical to a column address stored in the corresponding parent memory. Herein, each of the parent memories stores information about information about whether a row repair must be performed to repair a defective cell stored in the parent memory and information about whether a column repair must be performed to repair a defective cell stored in the parent memory.05-24-2012
20120163105SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has a great number of logic circuits and fuse blocks with its space-saving design. In the semiconductor storage device, a plurality of fuse blocks is arranged in a line or row in the vicinity of a gate array. Each fuse block includes a plurality of fuse pieces arranged in a juxtaposed manner and exposed to the exterior through a fuse window. A power-supply wire and a ground wire extend along the juxtaposed direction of the fuse pieces. Spacing in the vicinity of the gate array is used for arrangement of the fuse blocks.06-28-2012
20120213021SEMICONDUCTOR DEVICE HAVING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE - Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.08-23-2012
20090059696Multi-port memory device - There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a fuse set having a physical position information of a fail column; and a switching part for selectively connecting outputs of the normal bus connection part and the redundant bus connection part to the global data buses, which corresponds to the fail column, in response to the physical position information of the fail column. The column redundancy scheme can be applied to semiconductor memory devices having such a structure that a lot of column selection lines are enabled with respect to one column address and can also be applied to a case when a fail column address is not present. Therefore, the redundancy efficiency can be improved and an increase of the chip area can be prevented.03-05-2009
20090059695SEMICONDUCTOR MEMORY DEVICE AND BLOCK MANAGEMENT METHOD OF THE SAME - A semiconductor memory device includes adjacent planes and a control module. The adjacent planes include a reserve field and a data field having multiple blocks. The blocks of each of the reserve and data fields are successively arranged over the adjacent planes to form a multi-plane operation group. The control module is configured to control the adjacent planes to conduct a first operation or a second operation in accordance with whether the reserve field includes free blocks corresponding to a unit of the multi-plane operation group. The first operation includes replacing blocks of the data field with free blocks of the reserve field in the unit of the multi-plane operation group. The second operation includes replacing one block of the data field with one free block of the reserve field.03-05-2009
20120075944Semiconductor device and manufacturing method thereof - A plurality of memory cells are tested in order. Each time a defective memory cell is detected by the test, error pattern information is updated based on a relative arrangement relationship between a plurality of defective memory cells, and error address information is updated based on the addresses of at least part of the plurality of defective memory cells. According to the present invention, it is possible to significantly reduce the storage capacity of the analysis memory. This allows the implementation of the analysis memory itself in the semiconductor device, in which case external testers need not include the analysis memory.03-29-2012
20120075943Method and Apparatus for Memory Repair With Redundant Columns - A first redundant column is used to repair multiple defects in an array of memory cells. The defects include at least a first defect and a second defect in different main columns of a plurality of main columns in the array. However, all of the multiple defects repaired by the first redundant column are not required to be in different main columns. The array is arranged into a plurality of rows accessed by row addresses and the plurality of main columns accessed by column addresses.03-29-2012
20120257467MEMORY REPAIR ANALYSIS APPARATUS, MEMORY REPAIR ANALYSIS METHOD, AND TEST APPARATUS - A memory repair analysis apparatus that performs a repair analysis on a memory under test, comprising a row-oriented fail number storage section that stores the number of fail cells in each row; a column-oriented fail number storage section that stores the number of fail cells in each column; a row-weighting storage section that, for each row, stores the total number of fail cells in each column containing a fail cell included in the row; a column-weighting storage section that, for each column, stores the total number of fail cells in each row containing a fail cell included in the column; and a determining section that determines which of spare row regions and spare column regions are to replace the fail cells.10-11-2012
20120314519WORD LINE DRIVING SIGNAL CONTROL CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME, AND WORD LINE DRIVING METHOD - A word line driving signal control circuit of a semiconductor memory apparatus provided with a sub-redundancy cell array includes a fuse unit configured to generate a redundancy enable signal in response to a bank active signal and an address signal, and a repair determination unit configured to activate one of a normal word line driving signal, a redundancy word line driving signal, and a sub-redundancy word line driving signal in response to the bank active signal and the redundancy enable signal.12-13-2012
20120257468SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a transmission line configured to transmit a fuse enable signal for performance of a repair operation; a first repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a first repair enable signal for performing a repair operation for a first bank; and a second repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a second repair enable signal for performing a repair operation for a second bank.10-11-2012
20120081983METHOD OF PROGRAMMING, ERASING AND REPAIRING A MEMORY DEVICE - A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.04-05-2012
20120230136SELECTABLE REPAIR PASS MASKING - The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method comprises performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further comprises storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.09-13-2012
20110122717REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES - Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.05-26-2011
20110122715REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.05-26-2011
20080304341REDUNDANCY CIRCUIT - A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a defective cell by using a laser beam radiating method, a second fuse set that is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a defective cell exists, and the address signal, and to output a second redundancy signal, the second redundancy signal being used to repair the defective cell by using an electrical fusing method, a first memory cell array that is controlled by the first redundancy signal, and a second memory cell array that is controlled by the second redundancy signal.12-11-2008
20080298146MEMORY REDUNDANCE CIRCUIT TECHNIQUES - In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can includeselectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.12-04-2008
20080298145ANTIFUSE REPLACEMENT DETERMINATION CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY DEVICE - An antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge at the node self-discharge via the antifuse element after the charging of the node is completed; a comparison and determination circuit for comparing the voltage at the node of the antifuse element with a plurality of reference voltages when a predetermined time has elapsed after the completion of the charging of the node; and a determination part for deter g, based on a determination result with respect to the comparison using the plurality of reference voltages in the comparison and determination circuit, whether or not replacement of the bad memory cell has been performed normally by using the antifuse element.12-04-2008
20120269018MEMORY SYSTEM HAVING MEMORY AND MEMORY CONTROLLER AND OPERATION METHOD THEREOF - An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory.10-25-2012
20110235447LOW POWER MEMORY ARRAY COLUMN REDUNDANCY MECHANISM - A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value to the one or more unused columns of the memory array, and provide write data to the plurality of data columns during each write operation of the plurality of columns.09-29-2011
20120275247SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR REPAIRING THE SAME - A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses.11-01-2012
20100232241Redundancy architecture for an integrated circuit memory - An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group09-16-2010
20100232240Columnar replacement of defective memory cells - Circuits and methods to compensate for defective memory in BEOL third dimensional memory technology are described. An integrated circuit is configured to perform columnar replacement of defective BEOL multi-layered memory. For example, the integrated circuit can include a primary BEOL memory array having a plurality of BEOL memory cells being configured to change resistivity, a secondary BEOL memory array having another plurality of BEOL memory cells being configured to change resistivity, and a FEOL restoration module associated with the primary BEOL memory array and the secondary BEOL memory array, the FEOL restoration module being configured to locate a BEOL memory cell within the secondary BEOL memory array to replace a defective BEOL memory cell within the primary BEOL memory array. The FEOL portion can be fabricated on a substrate and the BEOL portion can be fabricated above and in contact with the FEOL portion to form the integrated circuit.09-16-2010
20110267910SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING COLUMN REDUNDANCY FUSE BLOCK - A semiconductor integrated circuit includes a column redundancy fuse block having a fuse set array having a plurality of fuse sets including a plurality of column address fuses, and a fuse blowing information block configured to output a fuse blowing determination signal of a corresponding column based on a cutting state of the column address fuses, wherein the column redundancy fuse is disposed in the edge area, wherein the fuse blowing determination signal is inputted to a column control block through upper portion of a memory cell array of a corresponding bank.11-03-2011
20110280091MEMORY REPAIR SYSTEMS AND METHODS FOR A MEMORY HAVING REDUNDANT MEMORY - Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory.11-17-2011
20120287737REPAIRING CIRCUIT FOR MEMORY CIRCUIT AND METHOD THEREOF AND MEMORY CIRCUIT USING THE SAME - A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit.11-15-2012
20100177579SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS - In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.07-15-2010
20100202228NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.08-12-2010
20130010557MEMORY REPAIR SYSTEMS AND METHODS FOR A MEMORY HAVING REDUNDANT MEMORY - Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory.01-10-2013
20110158013FUSE SET OF SEMICONDUCTOR MEMORY AND REPAIR DETERMINATION CIRCUIT USING THE SAME - A fuse set of a semiconductor memory includes a first fuse array and a second fuse array each configured to designate a column redundancy address; and a unit fuse circuit configured to select one of the first fuse array and the second fuse array based on a row address.06-30-2011
20130021860MECHANISMS FOR BUILT-IN SELF REPAIR OF MEMORY DEVICES USING FAILED BIT MAPS AND OBVIOUS REPAIRS - Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. At the same time, the compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.01-24-2013
20130021859MECHANISMS FOR BUILT-IN SELF REPAIR OF MEMORY DEVICES USING FAILED BIT MAPS AND OBVIOUS REPAIRS - Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. By performing obvious repair during collection of the FBM data, testing and date storage resources can be saved. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. The compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.01-24-2013
20130021861MECHANISMS FOR BUILT-IN SELF TEST AND REPAIR FOR MEMORY DEVICES - Mechanisms for self-testing and self-repairing memories are efficient in testing and repairing failed memory cells. The self-test-repair mechanisms are based on self-test results of failed bit map (FBM) data of the entire memories and enable early determination of non-repairable memories to prevent and limit wasting time and resources on non-repairable memories. The self-test-repair mechanisms also involve identifying candidates for column and row repairs and allow repeated repair cycles until either the memories are deemed irreparable or are fully repaired.01-24-2013
20120243354Repairing Soft Failures in Memory Cells in SRAM Arrays - An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell.09-27-2012
20100091594SEMICONDUCTOR MEMORY FOR DISCONNECTING A BIT LINE FROM SENSE AMPLIFIER IN A STANDBY PERIOD AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY - Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on.04-15-2010
20080225614METHOD AND SYSTEM FOR REDUCING VOLATILE MEMORY DRAM POWER BUDGET - A portable device (09-18-2008
20080225613MEMORY ROW AND COLUMN REDUNDANCY - In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.09-18-2008
20130141995METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE - One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell.06-06-2013
20130094314SRAM POWER REDUCTION THROUGH SELECTIVE PROGRAMMING - A method of programming a memory array having plural subarrays is disclosed. (FIG. 04-18-2013
20130128679REDUNDANCY SYSTEM FOR NON-VOLATILE MEMORY - A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.05-23-2013
20130141996METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE - One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.06-06-2013
20130148451MEMORY DEVICE INCLUDING REDUNDANT MEMORY CELL BLOCK - A clock signal is supplied to a first repair flag flip-flop, a second repair flag flip-flop, a first repair data flip-flop group, and a second repair data flip-flop group to serially transfer a second repair flag and a first repair flag stored in a non-volatile memory to the second repair flag flip-flop and the first repair flag flip-flop. Subsequently, repair data stored in the non-volatile memory is serially output to the first repair data flip-flop group, and repair data of the first repair data flip-flop group and the second repair data flip-flop group is serially transferred.06-13-2013
20100290299SEMICONDUCTOR CHIP AND METHOD OF REPAIR DESIGN OF THE SAME - A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.11-18-2010
20100302887SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected to the memory cell and the spare memory cell, a data holding circuit connected to the decoder, and a battery which supplies electric power to the data holding circuit. The spare memory cell operates in accordance with an output from the data holding circuit.12-02-2010
20120275249REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF - A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.11-01-2012
20120275248SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a memory block configured to have a normal cell array and a redundancy cell array; a column address buffer configured to compare a plurality of input column addresses with a fail column address signal-stored in a fuse array, and generate a column enable signal or a fail column enable signal; a column decoder configured to decode the column enable signal, and output a column selection signal to the normal cell array; and a column redundancy controller configured to generate a redundancy control signal in response to the fail column enable signal, generate a redundancy enable signal so as to reuse a redundancy bit line which has been substituted before according to the generated redundancy control signal, and output the generated redundancy enable signal to the redundancy cell array.11-01-2012
20130155794REPAIRABLE MULTI-LAYER MEMORY CHIP STACK AND METHOD THEREOF - A repairable multi-layer memory chip stack is provided. Each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.06-20-2013
20130182517FAIL ADDRESS STORAGE CIRCUIT, REDUNDANCY CONTROL CIRCUIT, METHOD FOR STORING FAIL ADDRESS AND METHOD FOR CONTROLLING REDUNDANCY - A redundancy control circuit includes: a fail address storage unit configured to store a fail address; a shared storage unit configured to store data as to whether a value stored in the fail address storage unit corresponds to both of a first address and a second address; an address comparator configured to compare a value stored in the fail address storage unit with a first input address and a second input address, respectively; and a redundancy controller configured to control a redundancy operation in response to a value stored in the shared storage unit and comparison results of the address comparator.07-18-2013
20120020175METHOD AND SYSTEM FOR PROCESSING A REPAIR ADDRESS IN A SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a memory device having a first plane and a second plane and a repair address latch unit configured to latch a plurality of repair addresses outputted from the memory device. The apparatus also includes an address comparison unit configured to compare the plurality of repair addresses stored in the repair address latch unit and a first plane address and a second plane address which are sequentially inputted. A repair processing unit is configured to selectively activate corresponding memory cell groups of the first plane and the second plane in conformity with the comparison result of the address comparison unit under the control of a first plane signal, a second plane signal and a start pulse signal.01-26-2012
20080316845MEMORY ROW ARCHITECTURE HAVING MEMORY ROW REDUNDANCY REPAIR FUNCTION - The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module.12-25-2008

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