Class / Patent application number | Description | Number of patent applications / Date published |
365195000 | Inhibit | 12 |
20080247246 | METHODS AND APPARATUS FOR READ/WRITE CONTROL AND BIT SELECTION WITH FALSE READ SUPPRESSION IN AN SRAM - Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit comprises one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can comprise, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state. | 10-09-2008 |
20080259700 | BUS CONTROL APPARATUS AND BUS CONTROL METHOD - A bus control apparatus includes a plurality of blocks configured to output a write command for writing data into memory via a bus, and a bus connection control unit provided in correspondence with each of the blocks. The bus connection control unit monitors signals between the bus and the block, and upon detecting a read command signal for reading data in a cause register of the block, blocks connection of a signal line between the block and the bus and outputs a dummy read command signal for the memory. The bus connection control unit releases blockage when a response signal for the dummy read command signal is received. | 10-23-2008 |
20090251977 | DEVICE HAVING MALFUNCTION PREVENTING CIRCUIT - A fixing device fixes a toner image on a recording medium. The fixing device includes a heat source that converts electric power into heat and a fixing member that gives the heat generated by the heat source to the recording medium on which the toner image is formed. The fixing device includes a safety circuit that forcibly interrupts voltage supplied from a power supply to the heat source if the temperature in the device detected by a temperature detection sensor exceeds reference temperature. The fixing device has a malfunction preventing circuit that stops the operation of the safety circuit in order to prevent the voltage supplied to the heat source from being forcibly interrupted when the voltage of the power supply supplied to the heat source is unstable. | 10-08-2009 |
20090323444 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines. | 12-31-2009 |
20100149893 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 06-17-2010 |
20100265781 | DATA RETENTION KILL FUNCTION - Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided. | 10-21-2010 |
20110194366 | Nonvolatile Data Storage Devices, Program Methods Thereof, and Memory Systems Including the Same - Provided are methods of programming a nonvolatile data storage device including memory blocks sharing a block word line. The methods may include selecting the memory blocks, and the selected memory blocks may include a first memory block that is to be programmed and a second memory block that is to be program-inhibited. The methods may also include applying a program voltage to a selected word line of the first memory block. The methods may further include applying a bipolar prohibition voltage to word lines of the second memory block. | 08-11-2011 |
20120008440 | DATA RETENTION KILL FUNCTION - Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided. | 01-12-2012 |
20120044778 | Semiconductor Device, Method for Inspecting the Same, and Method for Driving the Same - A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited. | 02-23-2012 |
20130094313 | COLLISION PREVENTION IN A DUAL PORT MEMORY - A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row. | 04-18-2013 |
20140003172 | MEMORY WITH WORD LINE ACCESS CONTROL | 01-02-2014 |
365196000 | Sense/inhibit | 1 |
20090010084 | APPARATUS FOR CONTROLLING ACTIVATION OF SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for controlling an activation of semiconductor integrated circuit includes: an active control unit configured to generate active control signal for determining activation of banks; and a plurality of active signal generating units configured to input the active control signal commonly, and generate active signals for activating the banks to according to the active control signal. According to this structure, it is possible to reduce current consumption to a minimum in a refresh mode, to easily arrange signal lines, and thus to effectively use extra space. | 01-08-2009 |