Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


Delay

Subclass of:

365 - Static information storage and retrieval

365189011 - READ/WRITE CIRCUIT

365191000 - Signals

Patent class list (only not empty are listed)

Deeper subclasses:

Entries
DocumentTitleDate
20110176376LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME - A synchronous memory array includes: a command receiver, for receiving a command signal; an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and a decoder, coupled to the command receiver and the address receiver, for decoding the command signal to selectively generate a receiver enable signal for turning on the address receiver.07-21-2011
20130044553INTEGRATED CIRCUIT, SYSTEM INCLUDING THE SAME, AND OPERATION METHOD OF THE SYSTEM - A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.02-21-2013
20080298143MEMORY DEVICE WITH DELAY TRACKING FOR IMPROVED TIMING MARGIN - A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, based on the internal clock signal, to ensure reliable writing of data to the memory cells.12-04-2008
20090244995Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor - A receive circuit (10-01-2009
20130028034INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE - Disclosed herein is a semiconductor device having a self-refresh mode in which a refresh operation of the storage data is performed. The semiconductor device activates an input buffer circuit that receives an impedance control command to control an impedance of the data terminal even in the self-refresh mode so that the semiconductor device can change an impedance of the data terminal during the self-refresh mode.01-31-2013
20130077418DLL CIRCUIT, FREQUENCY-MULTIPLICATION CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a DLL circuit including a delay chain, a plurality of phase comparators, and a controller. The plurality of phase comparators receive the reference clocks individually and receive respectively the clocks from the delay elements in mutually different stages, among the delay elements of the plurality of stages. The controller simultaneously receives comparison results of the plurality of phase comparators, determines the number of stages that generate the clock of which a phase is synchronized with a phase of the reference clock from among the delay elements of the plurality of stages, and selects the number of output stages from among the delay elements of the plurality of stages based on the determined number of stages so that a delay clock having a demanded delay amount with respect to the reference clock is output.03-28-2013
20100074037CONTROL VOLTAGE TRACKING CIRCUITS, METHODS FOR RECORDING A CONTROL VOLTAGE FOR A CLOCK SYNCHRONIZATION CIRCUIT AND METHODS FOR SETTING A VOLTAGE CONTROLLED DELAY - Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the synchronization circuit until a phase dependent control voltage stabilizes. The stable phase dependent control voltage is substituted for the initial control voltage. Following stabilization of the phase dependent control voltage, a phase detector of the clock synchronization circuit is activated. A recovery control voltage is provided by the clock synchronization controller to the voltage controlled delay during recovery of the clock synchronization from a power-saving mode until the phase dependent control voltage stabilizes.03-25-2010
20130039137SEMICONDUCTOR MEMORY DEVICE - A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control circuit that generates the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier, the longer the sense amplifier control circuit sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier, the later the sense amplifier is activated.02-14-2013
20130039136SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.02-14-2013
20130033947CLOCK GENERATOR - Disclosed herein is a clock generator that comprises a master or first oscillator having an output terminal which provides a master clock signal and at least one slave or second oscillator having an output terminal which provides a slave clock signal, the master and slave oscillators comprising respective time delay stages and latches, the slave oscillator also comprising logic gates connected to the outputs of the latches and configured to logically combine said outputs to generate a slave clock signal having a different phase with respect to a master clock signal.02-07-2013
20120206984METHOD AND APPARATUS FOR PERFORMING REFRESH OPERATIONS IN HIGH-DENSITY MEMORIES - A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.08-16-2012
20100103753DATA DETECTING APPARATUS AND METHODS THEREOF - A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.04-29-2010
20100110806SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks, each configured to receive a bank operation control signal and perform predetermined operations in response to the received bank operation control signal, a plurality of bank control blocks, each configured to receive a bank sequential signal and generate the plurality of bank operation control signals in response to enable periods of the received bank sequential signal, and a bank sequential signal generating block configured to generate the plurality of bank sequential signals each having a multiplicity of enable periods that are sequential in response to a command signal.05-06-2010
20100110807Bitline Leakage Detection in Memories - An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.05-06-2010
20100027357Memory System Having Distributed Read Access Delays - A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay.02-04-2010
20090190419CIRCUIT AND METHOD FOR CONTROLLING SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY APPARATUS - A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal.07-30-2009
20100329051METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS - A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.12-30-2010
20100329049SEMICONDUCTOR MEMORY DEVICE HAVING A LATENCY CONTROLLER - A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.12-30-2010
20130051166APPARATUSES AND METHODS FOR COMPENSATING FOR POWER SUPPLY SENSITIVITIES OF A CIRCUIT IN A CLOCK PATH - Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.02-28-2013
20100135089METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS - A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.06-03-2010
20100135090APPARATUS AND METHOD FOR TRIMMING STATIC DELAY OF A SYNCHRONIZING CIRCUIT - A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.06-03-2010
20090129179VARIABLE DELAY CIRCUIT, MEMORY CONTROL CIRCUIT, DELAY AMOUNT SETTING APPARATUS, DELAY AMOUNT SETTING METHOD AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH DELAY AMOUNT SETTING PROGRAM IS RECORDED - A variable delay circuit being able to change a delay amount from when a signal is inputted to when the signal is outputted has a first delay section delaying the signal by a first delay amount, a second delay section delaying the signal by a second delay amount greater than the first delay amount, and a delay amount selector selecting a signal route where the delay amount is a sum of the first delay amount and the second delay amount when the delay amount exceeds a maximum delay amount delayable by the first delay amount section. The delay amount from when a signal is inputted to when the signal is outputted can be set in a wide range, while suppressing the circuit scale.05-21-2009
20090303812PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS - A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.12-10-2009
20090303811ROW ADDRESS DECODER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight lo main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.12-10-2009
20090303810Semiconductor memory device - Disclosed is a semiconductor memory device. The semiconductor memory device includes a signal generating unit for generating first and second enable signals in response to a power-up signal, a first sub-word line signal driving unit for driving a first sub-word line signal in response to the first enable signal, a first voltage supplying unit for supplying a first voltage to a pair of bit lines in response to the first enable signal, a second sub-word line signal driving unit for driving a second sub-word line signal in response to the second enable signal, and a second voltage supplying unit for supplying a second voltage to a pair of bit lines in response to the second enable signal.12-10-2009
20120218844MEMORY CONTROLLER, SYSTEM INCLUDING THE CONTROLLER, AND MEMORY DELAY AMOUNT CONTROL METHOD - A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.08-30-2012
20090040848SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device to/from which a data signal is input/output in synchronism with a clock, including: an input signal delaying circuit for delaying an input signal to output the delayed input signal; a delayed clock generation circuit for delaying an input clock by different amounts of delay time to thereby generate a plurality of delayed clocks; a plurality of delayed input signal holding circuits for holding the delayed input signal on the plurality of delayed clocks, respectively; an input signal latch timing determination circuit for outputting a determination signal indicating a timing at which to latch the delayed input signal, based on a plurality of held signals held by the delayed input signal holding circuits; and a held signal selector circuit for integrating the plurality of held signals into a single signal.02-12-2009
20090040847OUTPUT ENABLE SIGNAL GENERATING CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.02-12-2009
20110013468SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SAME - A memory cell is provided at an intersection of a word line and a bit line. A sense amplifier circuit senses and amplifies a signal on the bit line. Replica circuits include a replica cell configured to retain certain data fixedly. A signal detection circuit detects an output signal that rises up at the latest timing among output signals output from the plurality of replica circuits respectively and outputs a detection signal. A delay circuit delays the detection signal. The sense amplifier circuit is activated based on the delayed signal.01-20-2011
20090268533Sensing delay circuit and semiconductor memrory device using the same - A sensing delay circuit includes a logic element which responds to a test mode signal to transfer a start signal, a delay unit which is configured of a plurality of inverters having MOS transistors with controlled threshold voltage, and receives external voltage as bulk voltage and delays an output signal from the logic element by a predetermined period, and a buffer which responds to an output signal from the delay unit to buffer the output signal from the logic element and output it.10-29-2009
20090238017DIGITAL DLL CIRCUIT - A digital delay locked loop circuit generates a delay value to delay the timing of taking in read-data by a memory interface when data is read from a memory. The digital delay locked loop circuit includes a selector that selects either one of a clock signal and a data strobe signal as a signal to output; a delay line that induces delay on the signal output from the selector when the signal passes through the delay line; and a phase-comparing/delay-value determining unit that compares a phase of the clock signal and a phase of the signal output from the delay line, and that determines a delay value that defines an amount of delay to be induced on the data strobe signal when passing through the delay line.09-24-2009
20090238016CIRCUITS TO DELAY SIGNALS FROM A MEMORY DEVICE - Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other embodiments are described.09-24-2009
20090238015Appartus and method for controlling refresh with current dispersion effect in semiconductor device - A refresh control apparatus is provided which is capable of dispersing a peak current at an all-bank refresh mode and reducing the characteristic difference between the banks. The refresh control apparatus includes an internal refresh counter for outputting row address signals to select word lines when a refresh command is inputted from an external circuit, a row decoder for outputting row decoding signals to select all banks in response bank active signals and the row address signals, an enable signal control unit for sequentially outputting at a time interval sense amplifier enable signals in response to the bank active signals and the refresh command, and a sense amplifier for sequentially refreshing all of the banks at a time interval in response to the sense amplifier enable signals.09-24-2009
20090238014LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME - A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.09-24-2009
20090231937Address Multiplexing in Pseudo-Dual Port Memory - A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.09-17-2009
20090010083CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER - A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.01-08-2009
20130163354SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a command delay section configured to delay a command signal applied through a command input pad by a parity delay amount in synchronization with an operating clock and output a parity command signal in a parity operation mode, wherein the command delay section is further configured to be controlled in response to an error determination signal, a command decoder configured to decode the parity command signal and transfer a resultant signal to a plurality of memory banks, and an error determination unit configured to determine whether an error has occurred in the command signal and generate an error determination signal.06-27-2013
20120269016LATENCY CONTROL CIRCUIT, LATENCY CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.10-25-2012
20110128803CORE VOLTAGE DISCHARGER AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.06-02-2011
20080291758READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA - Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.11-27-2008
20100246294SYSTEM AND METHOD FOR DELAY LOCKED LOOP RELOCK MODE - Embodiments of the present invention describe a memory device comprising a delay line and a feedback circuit coupled to the delay line. The feedback circuit has the capability to adjust a delay interval, which is then locked on the delay line. The feedback circuit is switched off after the delay interval is locked to reduce power consumption. The feedback circuit periodically switches on to adjust and lock the delay interval.09-30-2010
20100226189Delay locked loop circuit including delay line with reduced sensitivity to variation in pvt - A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.09-09-2010
20090040846Programmable Control Block For Dual Port SRAM Application - A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.02-12-2009
20120014196PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.01-19-2012
20100157700APPARATUS AND SYSTEMS FOR VT INVARIANT DDR3 SDRAM WRITE LEVELING - Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period.06-24-2010
20090003096Semiconductor memory device - A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.01-01-2009
20090190418SEMICONDUCTOR MEMORY, METHOD OF CONTROLLING THE SEMICONDUCTOR MEMORY, AND MEMORY SYSTEM - A semiconductor memory comprising an address transition detection circuit for detecting a transition of an address and outputs an address detection signal; an address input circuit for inputting an input address based upon the address detection signal; a command judgment circuit for decoding a command signal input and outputting a command judgment signal; a redundancy circuit for making a redundancy judgment based upon a redundancy judgment signal indicating timing of a redundancy judgment, wherein the redundancy circuit includes a redundancy judgment speed-up circuit for controlling an output of the redundancy judgment signal based upon a predetermined command signal.07-30-2009
20090185437CLOCK-BASED DATA STORAGE DEVICE, DUAL PULSE GENERATION DEVICE, AND DATA STORAGE DEVICE - Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based data storage device includes a dual pulse generating unit which delays a clock signal and then outputs a first clock signal corresponding to inversion of a clock signal and a second clock signal corresponding to the clock signal by using the delayed clock signal when the clock signal shifts, a pull-up wait for outputting a pull-up output signal to an output port, based on the first clock signal outputted from the dual pulse generating unit and an input data signal which has beeb inputted, a pull-down unit for outputting a pull-down output signal to the output port, based on the second clock signal outputted from the dual pulse generating unit and the input data signal inputted which has been inputted, and a latch unit which is disposed between the pull-up and pull-down units, and the output port so as to store at least one output signal outputted f roars the pull-down unit as well as the pull-down unit.07-23-2009
20100014366Semiconductor memory devices having signal delay controller and methods performed therein - A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.01-21-2010
20100265778SEMICONDUCTOR MEMORY DEVICE - A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control circuit that generates the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier, the longer the sense amplifier control circuit sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier, the later the sense amplifier is activated.10-21-2010
20100008168PROGRAMMABLE CONTROL BLOCK FOR DUAL PORT SRAM APPLICATION - A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.01-14-2010
20100008167SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a delay locked loop to generate a delay control signal corresponding to a detected phase difference between reference and feedback clock signals, a delay locked loop (DLL) clock signal, and the feedback clock signal. The memory device further includes a delay time measurement device to measure a first degree of delay between the reference and feedback clock signals and output a delay measurement value, and an output enable signal generation device to delay read command information synchronized with an external clock signal by a second degree of delay between the reference and DLL clock signals. The output enable signal generation device generates the read command information as final output enable signal by synchronizing the read command information with the DLL clock signal according to the delay measurement value and column address strobe (CAS) latency information.01-14-2010
20090003097OUTPUT CONTROL SIGNAL GENERATING CIRCUIT - An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used to take in a read command. The timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits. With this arrangement, a latch margin of a first latch circuit does not depend on the cycle of an external clock. Accordingly, even when a clock has a very high speed, the output can be controlled correctly.01-01-2009
20090154268DLL CIRCUIT, IMAGING DEVICE, AND MEMORY DEVICE - A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.06-18-2009
20090154267Clock signal generating circuit and data output apparatus using the same - A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.06-18-2009
20100246293Tracking Circuit for Reducing Faults in a Memory - A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.09-30-2010
20100085823Optimizing Sram Performance over Extended Voltage or Process Range Using Self-Timed Calibration of Local Clock Generator - A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.04-08-2010
20100118628MEMORY CIRCUIT AND TRACKING CIRCUIT THEREOF - The invention provides a tracking circuit of a memory circuit. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells, a dummy bit line, and an inverter. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for pulling down the voltage of the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled between the dummy cells and the inverter. The inverter inverts the voltage of the dummy bit line to generate the sense amplifier enable signal.05-13-2010
20090207677SEMICONDUCTOR DEVICE UTILIZING DATA MASK AND DATA OUTPUTTING METHOD USING THE SAME - A semiconductor device receives a first data mask signal and a second data mask signal. A data mask control unit outputs a data mask control signal by combining a test mode signal with the first data mask signal. A data clock output unit receives a delay locked loop (DLL) clock and outputs a data clock in response to the data mask control signal. A column address enable (YAE) control signal generating unit generates a column address enable control signal to control the enablement of a column address enable signal. The column address enable control signal generating unit generates the column address enable control signal by combining the test mode signal with a second mask signal.08-20-2009
20100085824Semiconductor device having delay control circuit - A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented.04-08-2010
20090073787METHOD FOR CONTROLLING TIME POINT FOR DATA OUTPUT IN SYNCHRONOUS MEMORY DEVICE - Disclosed is a method for controlling a time point for data output in a synchronous memory device, which varies a time point of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS latency of the synchronous memory device. In other words, the time point to generate the internal read command when CAS latency corresponds to 2N+2 (N=0, 1, 2, . . . ) is delayed by 1tCK as compared with the time point to generate the internal read command when CAS latency corresponds to 2N+1, and the 1tCK is a period of an external clock applied to the synchronous memory device.03-19-2009
20090141571Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM - A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.06-04-2009
20090168568SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.07-02-2009
20090141572VOLTAGE CONTROL APPARATUS AND METHOD OF CONTROLLING VOLTAGE USING THE SAME - A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either a first voltage or a second voltage lower than the first voltage to a word line in response to the burn-in control signal and the burn-in precharge signal.06-04-2009
20120106278SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock.05-03-2012
20120106277REFRESH OPERATION CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND REFRESH OPERATION CONTROL METHOD - A semiconductor memory device includes a bank including a first cell region and a second cell region, an active signal generation unit configured to generate a first row active signal and a second row active signal having different activation periods from each other in response to a refresh command, and an address counting unit configured to count the refresh command and generate a row address, wherein a word line of the first cell region designated by the row address is activated when the first row active signal is activated, and a word line of the second cell region designated by the row address is activated when the second row active signal is activated.05-03-2012
20100118629APPARATUS FOR CONTROLLING I/O STROBE SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS - A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating unit configured to output a detection code according to a voltage level of dummy cell data, which are read out from a dummy cell through at least one read operation, in response to a column select enable signal, and a multiplexer configured to receive the detection code and a default code and output a delay code to delay a sensing enable signal.05-13-2010
20100103754CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY - A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.04-29-2010
20100061167DATA OUTPUT CIRCUIT - A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.03-11-2010
20100061166DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION - In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.03-11-2010
20080239845Semiconductor memory device and method for driving the same - A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in response to the DLL clocks; and a skew compensating unit disposed between the DLL unit and the data output buffering unit to remove a clock skew occurring when the DLL clocks are transferred to the data output buffering unit.10-02-2008
20080239846Delay locked loop and semiconductor memory device with the same - A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking control unit. The delay-locked clock signal generating unit performs a delay locking operation on a clock signal, thereby generating a delay-locked clock signal. The mode signal generating unit enables a fast precharge power-down mode signal in a fast precharge power-down mode. The delay locking control unit controls the delay-locked clock signal generating unit to be activated in a predetermined cycle in response to the fast precharge power-down mode signal.10-02-2008
20080273403STORAGE CELL DESIGN EVALUATION CIRCUIT INCLUDING A WORDLINE TIMING AND CELL ACCESS DETECTION CIRCUIT - A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.11-06-2008
20080291759APPARATUS AND METHOD OF GENERATING OUTPUT ENABLE SIGNAL FOR SEMICONDUCTOR MEMORY APPARATUS - A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop) clock so as to generate an even-numbered divided clock and an odd-numbered divided clock. An even-numbered output enable signal generator generates an even-numbered output enable signal on the basis of an external read command, the timing signal, a CL (CAS Latency), and the even-numbered divided clock. An odd-numbered output enable signal generator generates an odd-numbered output enable signal on the basis of the external read command, a timing signal in which the timing signal is inverted, the CL, and the odd-numbered divided clock. A logical unit logically operates the even-numbered output enable signal and the odd-numbered output enable signal and outputs an output enable signal.11-27-2008
20100034036SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR CONTROLLING A SENSE AMPLIFIER - A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the internal read command signal in response to a test mode signal in a read mode.02-11-2010
20080304340DATA I/O LINE CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O lines located at one side of the switching unit, from a pair of second sub-middle I/O lines, which is coupled to both the pair of the local I/O lines and a data bus sense amplifier located at the other side of the switching unit.12-11-2008
20080273404SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.11-06-2008
20110007587COMMAND LATENCY SYSTEMS AND METHODS - Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required.01-13-2011
20090109772RAM WITH INDEPENDENT LOCAL CLOCK - In one embodiment, a random access memory (RAM) is provided that includes: an array of memory cells arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines; a local clock source that asserts a local clock in response to an assertion of an external clock; a plurality of x-decoders, each x-decoder adapted to assert a corresponding one of the word lines in response to a decoding of an appropriate address, wherein the assertion of a word line couples a corresponding row of the memory cells to their bit lines such that the bit lines are developed with corresponding voltages; and a plurality of sense amplifiers adapted to sense the voltage developments of the bit lines so as to determine a binary content of the memory cells, wherein the local clock source is triggered to de-assert the local clock independently of whether the external clock has been de-asserted.04-30-2009
20090190420Delay locked loop with frequency control - Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.07-30-2009
20090080272DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF GENERATING INFORMATION ABOUT A LOAD CONNECTED TO A DATA PIN OF A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE - A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.03-26-2009
20100271889DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.10-28-2010
20100142296SEMICONDUCTOR MEMORY DEVICE AND DELAY LOCKED LOOP CONTROL METHOD THEREOF - A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the DLL on signal during the start of the specific mode.06-10-2010
20100142295SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a source signal generator configured to generate a source signal having a predetermined pulse width in response to a command signal, and a column selection signal generator configured to generate a column selection signal by controlling a pulse width of the source signal according to a voltage level of an external supply voltage.06-10-2010
20090161456Semiconductor memory device which delays refreshment signal for performing self-refreshment - A semiconductor memory device having two refreshment modes of auto-refreshment and partial self-refreshment imposed on memory cells includes a command decoder which detects one of the refreshment modes from an input command, outputs type data which indicates the detected refreshment mode, and outputs a refreshment signal which indicates the start of refreshment; a mode register in which the type data is set; a signal selection circuit which determines whether or not the refreshment signal is to be delayed, in accordance with the type data set in the mode register, and outputs the refreshment signal, which is delayed or not delayed in accordance with the result of the determination, as a refreshment start signal; and a control circuit which reads the type data set in the mode register based when receiving the refreshment start signal, and performs refreshment corresponding to the type data.06-25-2009
20090129180APPARATUS FOR SENSING DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level.05-21-2009
20110205818SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD FOR ADJUSTING TIMING BETWEEN INTERNAL CLOCK AND COMMAND - A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.08-25-2011
20090273994DUAL MODE ACCESSING SIGNAL CONTROL APPARATUS AND DUAL MODE TIMING SIGNAL GENERATING APPARATUS - A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control apparatus are provided. The dual mode accessing signal control apparatus respectively generates a write delay signal and a read signal during the write and the read process. The memory is thereby capable of self-timing its write and the read process, and is able to generate a wordline signal with a shorter width in the write process to ensure an early start to precharging. As a result, the whole duty period of the memory can be shortened.11-05-2009
20130121094INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP - Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.05-16-2013
20130121095MEMORY CONTROLLER, SYSTEM INCLUDING THE CONTROLLER, AND MEMORY DELAY AMOUNT CONTROL METHOD - A DRAM coupled to a system LSI, the DRAM receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on, outputting the stored test pattern to the system LSI, receiving a delay set value from the system LSI, the delay set value being based on the test pattern, storing the delay set value after the power source of the system LSI is turned off and outputting the stored delay set value to the system LSI, if the power source of the system LSI is turned on again.05-16-2013
20130121096Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.05-16-2013
20090201751SEMICONDUCTOR DEVICE IN WHICH A MEMORY ARRAY IS REFRESHED BASED ON AN ADDRESS SIGNAL - In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and Nε2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM includes a DLL circuit for aligning phase of an internal clock signal with that of an external clock signal that is externally supplied, and a DLL control circuit for exercising control so as to halt operation of the DLL circuit in an interval in which the address signal becomes active one or more times and N−1 times or fewer, this interval being included in an interval in which the signal RAS becomes active N times. The DLL control circuit counts the signal RAS and decodes the value of the count. Operation of the DLL circuit is halted while a prescribed range of count values is being decoded.08-13-2009
20090097341SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DRIVING THE SAME - A semiconductor memory apparatus according to an embodiment of the invention includes a delay enable unit that generates a delay enable signal in response to an external ODT signal and an idle signal, a delay selecting unit that outputs the idle signal or a delay idle signal, which is obtained by delaying the idle signal by a first delay time, in response to the delay enable signal, and a DLL clock control unit that generates a control signal in response to the idle signal or the delay idle signal during a slow power down exit mode.04-16-2009
20090213670ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS - Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.08-27-2009
20090109771Optimizing mode register set commands - In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency. Other embodiments are described and claimed.04-30-2009
20090244997Method for Training Dynamic Random Access Memory (DRAM) Controller Timing Delays - Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (10-01-2009
20090219771Adjusting a Digital Delay Function of a Data Memory Unit - An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (09-03-2009
20090244998SYNCHRONOUS MEMORY DEVICE - A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.10-01-2009
20090244996Circuit Using a Shared Delay Locked Loop (DLL) and Method Therefor - A transceiver (10-01-2009
20100265780SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED POWER CONSUMPTION DURING LATENCY - A semiconductor memory device comprises a latency delay unit that toggles a delay clock signal on during a first interval between a time point where read burst signal is activated and a time point where a latency signal is activated, and subsequently toggling the delay clock signal on during a second interval between a time point where the read burst signal is inactivated and a time point where the latency signal is inactivated.10-21-2010
20090316504SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING ROW MAIN SIGNAL AND CONTROLLING METHOD THEREOF - A semiconductor integrated circuit includes a row main signal generation section configured to provide a row main signal serving as a driving reference for a plurality of row-series circuit units in response to a bank active signal, wherein activation timing of the row main signal is controlled by a test mode signal. row-series12-24-2009
20090257295Randomizing Current Consumption in Memory Devices - In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output interface of at least one of the plurality of data bits based on a randomly selected or pseudo-randomly selected delay value. The memory device can further include a delay block having a plurality delay paths having varying delays, and randomly selecting or pseudo-randomly selecting the delay value can include randomly selecting or pseudo-randomly selecting one of the plurality of delay paths through which to transmit a control signal.10-15-2009
20100157702Semiconductor memory device adopting improved local input/output line precharging scheme - A semiconductor memory device capable of preventing or minimizing bit line disturbance and performing a low-voltage high-speed operation includes a read data path circuit including a bit line sense amplifier, a local input/output line sense amplifier, a column selecting unit to operationally connect bit lines connected to the bit line sense amplifier to local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal, and a local input/output line precharging unit to precharge the pair of local input/output lines by a first precharging unit, equalizing the pair of local input/output lines by an equalizing unit, and to precharge the local input/output lines by a second precharging unit following an elapsed time after the bit line sense amplifier is activated, while the column selection is deactivated.06-24-2010
20090316503CLOCK DRIVER DEVICE AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A clock driver device includes a driving controller configured to generate a clock output enable signal enabled in response to an internal read pulse signal and disabled in response to a data output enable signal and an internal clock signal, and a clock driver configured to generate a driving clock signal by driving the internal clock signal in response to the clock output enable signal and a power-down signal.12-24-2009
20100149892SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device has a DLL circuit capable of suppressing EMI without distorting a DLL clock required in high-speed operation. The semiconductor memory device includes a delay locked loop (DLL) circuit configured to be responsive to a system clock to output a DLL clock having a phase that is changed when electromagnetic interference (EMI) is detected, for the DLL clock to have frequencies within a delay locking range, and a data output circuit configured to output data in synchronization with the DLL clock.06-17-2010
20120195142SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a main word line signal generator configured to generate a main word line signal having a first swing width, a sub-word line signal generator configured to generate a first sub-word line signal and a second sub-word line signal having a second swing width and a third swing width, respectively, a first sub-word line driver configured to drive a corresponding sub-word line with the first sub-word line signal or a negative word line voltage in response to the main word line signal, and a second sub-word line driver configured to drive the corresponding sub-word line with the negative word line voltage in response to the second sub-word line signal.08-02-2012
20100157701DELAY LINE AND MEMORY CONTROL CIRCUIT UTILIZING THE DELAY LINE - A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition, a memory control circuit includes a delay locked loop (DLL) having at least one delay cell. The delay locked loop utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor.06-24-2010
20090116313DATA OUTPUT CONTROL CIRCUIT - A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to an active signal, and to determine an output timing of data corresponding to a read command by counting the system clock and a DLL clock outputted from the DLL circuit 05-07-2009
20090116312Storage Array Including a Local Clock Buffer with Programmable Timing - A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.05-07-2009
20100188911MEMORY-WRITE TIMING CALIBRATION INCLUDING GENERATION OF MULTIPLE DELAYED TIMING SIGNALS - A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path.07-29-2010
20100182858NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING - A nonvolatile semiconductor memory device includes a memory cell, a precharge control circuit, a power supply circuit, a bit line driver, a word line driver, a first multiplexer, and a second multiplexer. The memory cell includes an anti-fuse storage element and a selection transistor. Before data are written into the anti-fuse storage element of the memory cell, the anti-fuse storage element is set up in a precharged state by the precharge control circuit, the bit line driver, the word line driver, the first multiplexer, and the second multiplexer.07-22-2010
20100226188FIRST DELAY LOCKING METHOD, DELAY-LOCKED LOOP, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.09-09-2010
20130215693TRACKING CAPACITIVE LOADS - A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.08-22-2013
20130215694Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments - A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.08-22-2013
20080232179Circuit, system and method for controlling read latency - A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.09-25-2008
20110058433LATENCY CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR CONTROLLING LATENCY - A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.03-10-2011
20090116315SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device has a DLL circuit capable of suppressing EMI without distorting a DLL clock required in high-speed operation. The semiconductor memory device includes a delay locked loop (DLL) circuit configured to be responsive to a system clock to output a DLL clock having a phase that is changed when electromagnetic interference (EMI) is detected, for the DLL clock to have frequencies within a delay locking range, and a data output circuit configured to output data in synchronization with the DLL clock.05-07-2009
20090116314SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device using system clock with a high frequency can maintain a constant margin of operation even with a changed operating environment including voltage level, temperature, and process. The semiconductor memory device includes a data output control circuit configured to control data outputted in synchronization with a falling edge of a system clock using a first output source signal corresponding to a rising edge of the system clock, and to control data outputted in synchronization with the rising edge of the system clock using a second output source signal corresponding to a falling edge of the system clock, and a data output circuit configured to output data, the data output circuit being controlled by the data output control circuit.05-07-2009
20100118630Method and Apparatus for Synchronizing Data From Memory Arrays - According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.05-13-2010
20120195143SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.08-02-2012
20100296352MEMORY CONTROLLER FOR DETECTING READ LATENCY, MEMORY SYSTEM AND TEST SYSTEM HAVING THE SAME - A memory controller includes an I/O circuit, a read latency detector and a clock domain synchronizer. The I/O circuit transmits a first signal to a semiconductor memory device, receives a reflected signal returned from the semiconductor memory device, and delays the reflected signal in response to a delay selection signal to generate a second signal. The reflected signal is provided by reflection of the first signal from the semiconductor memory device. The read latency detector generates the first signal in response to a system clock signal, and generates a read latency signal in response to the system clock signal, a hold signal, and the second signal. The clock domain synchronizer generates the delay selection signal and the hold signal in response to the system clock signal and the second signal.11-25-2010
20100302884Method of preventing coupling noises for a non-volatile semiconductor memory device - Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.12-02-2010
20100302885DELAY LOCKED LOOP AND METHOD AND ELECTRONIC DEVICE INCLUDING THE SAME - A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals. The second delay locked loop receives the data signal, the selected second clock signal, and the plurality of phase resolution control signals, generates a plurality of third clock signals having variable phase resolution based on the selected second clock signal and at least one of the plurality of phase resolution control signals, and performs a locking operation on the plurality of third clock signals and the data signal.12-02-2010
20100322022SEMICONDUCTOR STORAGE DEVICE - The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first DLL circuit generates a first internal clock signal so as to reduce a phase difference between a first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit. The second DLL circuit generates the second internal clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit. With the configuration, input setup and hold time can be shortened, and the frequency of the clock signal can be further increased.12-23-2010
20110002181Delay locked loop using hybrid fir filtering technique and semiconductor memory device having the same - Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (ΣΔ) modulator to operate at a low frequency without generating false lock and glitch noise.01-06-2011
20110002182SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a source signal generation unit configured to generate a source pulse signal having a pulse width which is determined depending on an interval between an input of an active signal and an input of a column command signal, which is inputted after an active command, and a column decoding unit configured to generate a column select signal in response to an address and the source pulse signal.01-06-2011
20110242911COLUMN COMMAND BUFFER AND LATENCY CIRCUIT INCLUDING THE SAME - A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands.10-06-2011
20110242915METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS - Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.10-06-2011
20110110174System and Method of Operating a Memory Device - A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.05-12-2011
20110116330SEMICONDUCTOR DEVICE HAVING ADDITIVE LATENCY - A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.05-19-2011
20110085395OUTPUT ENABLE SIGNAL GENERATING CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.04-14-2011
20090262592METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS - A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled. 10-22-2009
20100008169Latency Control Circuit and Method Thereof and an Auto-Precharge Control Circuit and Method Thereof - A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.01-14-2010
20110211405EXTERNAL SIGNAL INPUT CIRCUIT OF SEMICONDUCTOR MEMORY - In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration.09-01-2011
20110242914CLOCK DELAY ADJUSTMENT CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF THE SAME - A clock signal adjustment circuit in a semiconductor integrated circuit includes: multiple circuit blocks; multiple clock delay circuits supplying delayed clock signals of the input clock signals under the control of the delay control signals to the corresponding circuit blocks; a control circuit conducting a delay test of the circuit blocks; a recovery group memory circuit storing information in the circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; delay setting circuits storing information about the delay value for circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; and a delay setting dispatch control circuit dispatching the delay control signal corresponding to the delay value information stored in the delay setting circuit to the clock delay circuits corresponding to the information about the circuit blocks stored in the recovery group memory circuit.10-06-2011
20110242912Random Access Memory Devices Having Word Line Drivers Therein That Support Variable-Frequency Clock Signals - Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit. The word line driver circuit is further configured to drive the selected one of the plurality of word lines with a second word line signal having a leading edge synchronized with the leading edge of a clock signal and a trailing edge synchronized with an edge of a signal generated by the first delay unit when the one-half period of the clock signal is less than the length of the delay provided by the first delay unit.10-06-2011
20110085394LATENCY CIRCUIT AND SEMICONDUCTOR DEVICE COMPRISING SAME - A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a margin with respect to a read command decoded based on the delay sync signal. The internal read command generator samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock. The latency signal generation unit generates a latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.04-14-2011
20110242913SELF REFRESH CIRCUIT - A self refresh circuit includes a continuous output interrupting unit and a glitch removing unit. The continuous output interrupting unit is configured to receive a delay self refresh signal, transmit a pulse of an internal active signal as a first output active signal and interrupt the transmission of the pulse of the internal active signal during a first time period. The glitch removing unit is configured to generate and output a second output active signal when the first output active signal has a predetermined pulse width.10-06-2011
20090016127DUTY DETECTION CIRCUIT, DLL CIRCUIT USING THE SAME, SEMICONDUCTOR MEMORY CIRCUIT, AND DATA PROCESSING SYSTEM - A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.01-15-2009
20090016126SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.01-15-2009
20090016124Semiconductor memory device having on-die-termination device and operation method thereof - A semiconductor memory device is capable of stably securing an on-die-termination (ODT) latency in spite of PVT variations and various operating speeds. The semiconductor memory device includes a plurality of termination resistors connected to an output pad in series and parallel, a drive controller, a delay path, and a delay control signal generator. The drive controller activates/inactivates the plurality of termination resistors in response to a driving control signal. The delay path delays a termination command by a delay time corresponding to an on-die-termination (ODT) latency to output the driving control signal, wherein the termination command is converted into a delay locked loop (DLL) clock domain signal. The delay control signal generator controls a conversion point of the termination command into the DLL clock domain signal.01-15-2009
20090016128Semiconductor integrated circuits and non-volatile memory devices including semiconductor integrated circuits - A semiconductor integrated circuit may include: a mode register and a clock delay control circuit. The mode register may store latency information corresponding to a plurality of frequencies. The clock delay control circuit may generate a delay clock signal using an external clock signal and the latency information. The delay clock signal may be used to control a timing margin of output data read during synchronous burst read operations of a non-volatile memory. A non-volatile memory device may include the semiconductor integrated circuit and a data output unit. The data output unit may use the delay clock signal to control the timing margin of the output data read during synchronous burst read operations. A memory system may include the semiconductor integrated circuit. A computing system may the semiconductor integrated circuit, as well as one or more of a memory controller, bus, modem, microprocessor, user interface, and battery.01-15-2009
20090016125SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device can determine whether control for supplying termination resistances is normally performed or not by applying a test signal. The device includes a termination resistance driving controller configured to receive a plurality of termination resistance setting signals in synchronization with an external clock and a delay locked loop (DLL) clock to output a plurality of pre-driving signals and a plurality of termination resistance driving signals for a predetermined time. A data pre-driver is configured to output data in synchronization with the external clock. A test driving detector is configured to drive output nodes to a predetermined voltage level in response to a test signal and the plurality of pre-driving signals. A data output buffer is configured to apply termination resistances corresponding to the plurality of termination resistance driving signals to input/output pads, and output the data from the output nodes to the input/output pads.01-15-2009
20120243353DIGITAL DLL FOR TIMING CONTROL IN SEMICONDUCTOR MEMORY - A semiconductor memory includes a delay locked loop (DLL) configured to generate a timing code based on a clock signal. A plurality of memory devices are coupled to the DLL. Each of the plurality of memory devices is configured to generate internal control signals for operating a memory array based on the timing code received from the DLL.09-27-2012
20100054058SYSTEMS AND METHODS FOR ISSUING ADDRESS AND DATA SIGNALS TO A MEMORY ARRAY - Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.03-04-2010
20100054060DELAY LOCKED LOOP AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking control unit. The delay-locked clock signal generating unit performs a delay locking operation on a clock signal, thereby generating a delay- locked clock signal. The mode signal generating unit enables a fast precharge power-down mode signal in a fast precharge power-down mode. The delay locking control unit controls the delay-locked clock signal generating unit to be activated in a predetermined cycle in response to the fast precharge power-down mode signal.03-04-2010
20110176375SEMICONDUCTOR MEMORY DEVICE FOR REDUCING RIPPLE NOISE OF BACK-BIAS VOLTAGE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.07-21-2011
20110103163MULTI-BIT TEST CONTROL CIRCUIT - A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test.05-05-2011
20110149663Semiconductor device and semiconductor memory device - A semiconductor device comprises a memory cell array including memory cells, a first bit line transmitting data stored in a selected memory cells, a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current, a second bit line selectively connected to the first bit line via the first sense amplifier, a second sense amplifier determining a level of the signal voltage, and a sense amplifier control circuit detecting a temperature of the memory cell array during an operation and controlling an end of an activation period of the first and/or second sense amplifiers in accordance with a detection result of the temperature. In the semiconductor device, the sense amplifier control circuit controls to delay the end of the activation period at least at a predetermined high temperature indicated by the detection result relative to at an ordinary temperature.06-23-2011
20100265779Compensatory Memory System - A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.10-21-2010
20100054059SEMICONDUCTOR MEMORY DEVICE - A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.03-04-2010
20100054057Memory Sensing Method and Apparatus - Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.03-04-2010
20120201090POWER SAVINGS MODE FOR MEMORY SYSTEMS - A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.08-09-2012
20110211406ADDRESS DELAY CIRCUIT - An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address.09-01-2011
20090168567SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal.07-02-2009
20110158011SEMICONDUCTOR MEMORY INTERFACE DEVICE AND METHOD - A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.06-30-2011
20120170393PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF-TIMED MEMORY - Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.07-05-2012
20120170390Read stability of a semiconductor memory - A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line. The access control circuitry responds to a data access request signal by increasing a voltage level supplied to the access control line to a first voltage level at a first average rate and then in response to receipt of a further signal increasing the voltage level supplied to the access control line to the predetermined higher voltage level, in such a way that a further average rate of increase of the voltage level from the first to the predetermined higher voltage level is lower than the first average rate of increase to the first level.07-05-2012
20110255356SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.10-20-2011
20110164462DELAY-LOCKED-LOOP CIRCUIT, SEMICONDUCTOR DEVICE AND MEMORY SYSTEM HAVING THE DELAY-LOCKED-LOOP CIRCUIT - A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.07-07-2011
20110255355Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.10-20-2011
20100284232Memory Circuit and Tracking Circuit Thereof - The invention provides a tracking circuit of a memory circuit. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells and a dummy bit line. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for lowering down a dummy bit line signal on the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled to the dummy cells and carries the dummy bit line signal.11-11-2010
20100329050SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.12-30-2010
20100329048PRECHARGE SIGNAL GENERATOR AND SEMICONDUCTOR MEMORY DEVICE - A precharge signal generator having a latch signal generator, an internal signal generator, and a pulse generator is presented. The latch signal generator is configured to generate a latch signal that is activated in response to an auto-precharge command and inactivated in response to an active pulse. The internal signal generator is configured to generate an internal signal activated when a delayed active signal and the latch signal are all activated. The pulse generator is configured to generate a precharge signal including a pulse that is activated in a period for which the internal signal is being active.12-30-2010
20110134712APPARATUS AND METHOD FOR TRIMMING STATIC DELAY OF A SYNCHRONIZING CIRCUIT - A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.06-09-2011
20100097870SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING OPERATION OF DELAY-LOCKED LOOP CIRCUIT - A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.04-22-2010
20100195423SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.08-05-2010
20100195422SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A semiconductor integrated circuit includes: a current difference sense type of a sense amplifier including: an input line connected to memory cells as a target to be read, a reference line connected to reference cells, and a first pre-charge circuit configured to pre-charge the input line and the reference line; a second pre-charge circuit configured to perform pre-charging of the input line and pre-charging of the reference line; and a control circuit configured to control the second pre-charge circuit so that the second pre-charge circuit may perform both the pre-charging of the input line and the pre-charging of the reference line independently of each other, and start both the pre-charging of the input line and the pre-charging of the reference line earlier than pre-charging by the first pre-charge circuit.08-05-2010
20100165763SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory banks each having a plurality of memory cell arrays, a plurality of sense amplification units corresponding to the memory banks, configured to sense data corresponding to a selected memory cell to amplify the sensed data, and a common delay unit configured to delay a plurality of respective bank active signals activated in correspondence with the memory banks by a predetermined time to generate an operation control signal for controlling the sense amplification units.07-01-2010
20090175103SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE - An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.07-09-2009
20100027358Semiconductor memory device capable of read out mode register information through DQ pads - A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a mode register read signal and generate a flag signal and at least one output information signal, and a global I/O line latch unit for transferring the output information signal to a global I/O line in response to the flag signal.02-04-2010
20110051537Address Multiplexing in Pseudo-Dual Port Memory - A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.03-03-2011
20110051536SIGNAL DELAY CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A signal delay circuit that includes a delay unit configured to delay an input signal for a first delay time and output the delayed input signal; a first delay adjusting unit configured to adjust the first delay time according to a variation in a level of a power supply voltage supplied to the delay unit; and a second delay adjusting unit configured to offset an amount of time the first delay time is adjusted by the first delay adjusting unit.03-03-2011
20120147684MEMORY REFRESH APPARATUS AND METHOD - A memory refresh apparatus and method are operable such that in response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.06-14-2012
20120147683SEMICONDUCTOR MEMORY DEVICE - A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.06-14-2012
20110317504MEMORY COMPONENT HAVING A WRITE-TIMING CALIBRATION MODE - In memory component having a write-timing calibration mode, control information that specifies a write operation is received via a first external signal path and write data corresponding to the write operation is received via a second external signal path. The memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid write data, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the first external signal path and outputting the write data on the second external signal path.12-29-2011
20110317503Semiconductor device - A semiconductor device is provided with: a delay circuit including a first delay unit that has a plurality of differential first delay elements which are respectively connected in series, a plurality pairs of first contacts which are respectively provided between the plurality of first delay elements, and a first output circuit that outputs a first delayed signal corresponding to a pair of first contacts selected from among the plurality pairs of first contacts, on receiving a first selection signal; a second delay unit that receives the first delayed signal, and that includes a plurality of single-ended second delay elements which are respectively connected in series, a plurality of second contacts which are respectively provided between the plurality of second delay elements, and a second output circuit that outputs a second delayed signal corresponding to a second contact selected from among the plurality of second contacts, on receiving a second selection signal; and a control circuit that outputs each of the first and second selection signals.12-29-2011
20120063247Temperature Sensing Circuit And Semiconductor Memory Device Using The Same - A temperature sensing circuit comprises a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation, and a comparison unit for comparing the reference voltage to the variable voltage, detecting an ambient temperature and generating a temperature detecting signal.03-15-2012
20120002493OUTPUT ENABLE SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY - An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).01-05-2012
20110063932Boosting voltage levels applied to an access control line when accessing storage cells in a memory - A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of the at least two access control lines in response to an access request, the at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing the access request and a boost signal to a selected one of the at least two access control circuits in dependence upon an address associated with the access request; wherein the at least two access control circuits are each responsive to: receipt of the access request from the routing circuitry to connect the selected access control line to a supply voltage; and receipt of the boost signal from the routing circuitry to disconnect the supply voltage from the access control line and to couple the boost signal to the access control line through the capacitor of the access control circuit to provide a boost to a voltage level on the access control line.03-17-2011
20120008439DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.01-12-2012
20120008438EFFICIENT WORD LINES, BIT LINE AND PRECHARGE TRACKING IN SELF-TIMED MEMORY DEVICE - A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.01-12-2012
20120008437COUNTER CIRCUIT, LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate.01-12-2012
20120008436SIMULATING A REFRESH OPERATION LATENCY - A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component.01-12-2012
20120008435DELAY LOCKED LOOP - A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.01-12-2012
20120008433SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.01-12-2012
20120008434SEMICONDUCTOR SYSTEM AND DEVICE, AND METHOD FOR CONTROLLING REFRESH OPERATION OF STACKED CHIPS - A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.01-12-2012
20120300565SKEW SIGNAL GENERATOR AND SEMICONDUCTOR MEMORY DEVICE - A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.11-29-2012
20100202226Bank precharge signal generation circuit - A bank precharge signal generation circuit includes a precharge signal generation unit for generating a second precharge signal including a pulse, which is generated in a period delayed by a predetermined period as compared to a pulse of a first precharge signal, in response to an all-bank precharge signal, and a bank precharge signal generation unit for receiving the first and second precharge signals and generate first and second bank precharge signals for precharging first and second banks.08-12-2010
20120206983TRACKING SCHEME FOR MEMORY - A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.08-16-2012
20120026814CIRCUIT FOR TRANSMITTING AND RECEIVING DATA AND CONTROL METHOD THEREOF - A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.02-02-2012
20120026813Semiconductor device changing an active time-out time interval - A device includes a plurality of memory areas each including a plurality of memory cells required to perform refresh of information stored therein by a plurality of sense amplifiers, a first control circuit determining, in connection with one refresh requirement signal at a time, a number of refresh-target memory areas to produce a determined number, a second control circuit controlling, in accordance with the one refresh requirement signal at a time, refresh operation with respect to the refresh-target memory areas, and a third control circuit adjusting, in connection with the refresh operation, an active time-out time interval according to the determined number. The active time-out time interval indicates a time interval from a first time instant when the sense amplifiers are activated to a second time instant when word lines related to the refresh-target memory areas are inactivated.02-02-2012
20090135664METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS - A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.05-28-2009
20110069568SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL SENSE AMPLIFIER WITH ON/OFF CONTROL - A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.03-24-2011
20120155201SYSTEM AND METHOD FOR HIDDEN REFRESH RATE MODIFICATION - A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.06-21-2012
20110090750SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS - An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.04-21-2011
20110103162SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: a plurality of memory banks disposed at a predetermined distance from each other in a first direction; a common column selection control unit disposed at an outside region of the plurality of memory banks in the first direction, and configured to commonly control access to column areas of the plurality of memory banks; and a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to the corresponding memory cells of the plurality of memory banks. The common column selection control unit generates the column selection signal, and a delay length of the column selection signal is adjusted based on a length of a transmission path of the column selection signal.05-05-2011
20120120746SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may comprise: an input buffer block configured to receive a write signal and a reference level signal, compare a the write signal with a the reference level signal to generate a first write control signal, and delay the first write control signal by a predetermined time to generate a second write control signal; a first decoder block configured to combine the second write control signal inputted from the input buffer block with externally inputted command signals, and generate a first write command signal; a clock control block configured to generate a clock control signal for determining determine a level of an internal clock signal in response to a level of the first write control signal outputted from the input buffer block; and a write signal control block configured to generate an internal write command signal according to a level of the first write command signal inputted from the first decoder block and the clock control signal inputted from the clock control block.05-17-2012
20100091592CLOCK BUFFER AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.04-15-2010
20120250435SEMICONDUCTOR DEVICE AND METHOD OF COTNROLING THE SAME - A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.10-04-2012
20120120747SEMICONDUCTOR DEVICE - A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal.05-17-2012
20100246295SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY CIRCUIT - A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.09-30-2010
20120127812SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a plurality of first data signals in response to data stored in selected ones of the first memory cells, a plurality of first data electrodes, and a first data control circuit coupled to the first control logic circuit and the first data electrodes. A second semiconductor chip includes a second memory cell array including a plurality of second memory cells, a second control logic circuit accessing the second memory cell array and producing a plurality of second data signals in response to data stored in selected ones of the second memory cells. The second control logic circuit is configured to store second timing adjustment information and to produce a second output timing signal.05-24-2012
20120127811TIMING GENERATION CIRCUIT, SEMICONDUCTOR STORAGE DEVICE AND TIMING GENERATION METHOD - According to an embodiment, a semiconductor storage device includes a memory cell array, a plurality of sense amplifiers and a timing generation circuit. The memory cell array includes a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells provided in intersection portions of the plurality of word lines and the plurality of bit lines. The plurality of sense amplifiers is configured to detect a signal level of the corresponding bit lines. The timing generation circuit includes a timing selection circuit configured to select a timing in a preset order from among timings in which each bit line signal in the plurality of bit lines changes. The timing generation circuit is configured to generate activation timing to activate the plurality of sense amplifiers based on the selected timing.05-24-2012
20100238748SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the delayed reference signal to output a signal for determining a timing of a predetermined operation on a bank selected by the delayed bank address.09-23-2010
20120314518SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address.12-13-2012
20120134223CLOCK GENERATING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is increased when the first phase determination signal takes a first logic level and decreased when the first phase determination signal takes a second logic level, and a phase determining circuit supplied with the first clock signal and a third clock signal, which is produced in response to the second clock signal, and producing a second phase determination signal in response to a difference in phase between the first clock signal and the third clock signal.05-31-2012
20120134222Semiconductor device and method of controlling the same - A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.05-31-2012
20090059694Semiconductor memory device - A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the delayed reference signal to output a signal for determining a timing of a predetermined operation on a bank selected by the delayed bank address.03-05-2009
20120170391MEMORY DEVICE WITH BOOST COMPENSATION - A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.07-05-2012
20120170392INTERNAL VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes first and second bank groups, a first internal voltage control unit configured to generate a first enable pulse which is enabled when a first read operation or a first write operation is performed for banks included in the first bank group, and a first internal voltage generation unit configured to generate and supply a first internal voltage to the first bank group in response to the first enable pulse, wherein an enable period of the first enable pulse is set to be longer in the first write operation than in the first read operation.07-05-2012
20120075942ROW ADDRESS DECODER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight to main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.03-29-2012
20100271890DATA I/O CONTROL SIGNAL GENERATING CIRCUIT IN A SEMICONDUCTOR MEMORY APPARATUS - A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode.10-28-2010
20100271888System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits - A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.10-28-2010
20100271887SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY UNIT - A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern.10-28-2010
20120218843SEMICONDUCTOR DEVICE - Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor device includes a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted.08-30-2012
20120188835INTEGRATED CIRCUIT WITH STAGGERED SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.07-26-2012
20090323443SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configured to determine a pulse width of a column selection signal in response to the column command signal and the reset control signal. An address decoding unit is configured to generate the column selection signal corresponding to a corresponding column address in response to an output signal of the pulse width determination unit.12-31-2009
20120224442CIRCUIT WITH REMOTE AMPLIFIER - A circuit comprises a first driver, a second driver, and a remote sense amplifier. The first driver is configured to generate a first data signal on a first data line. The second driver is configured to generate a control signal on a control signal line. An RC delay of the control signal line is less than an RC delay of the first data line. The remote sense amplifier is configured to receive the first data signal, a second data signal on a second data line, and the control signal. The control signal line is configured for the control signal to enable the remote sense amplifier to amplify the voltage difference between the first data signal and the second data signal at inputs of the remote sense amplifier, if the voltage difference reaches a predetermined value.09-06-2012
20120263000PROGRAMMABLE CONTROL BLOCK FOR DUAL PORT SRAM APPLICATION - A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.10-18-2012
20120262999SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a system clock input block configured to be inputted with a system clock, a data clock input block configured to be inputted with a data clock, a first phase detection block configured to compare a phase of the system clock, generate a first phase detection signal, and determine a logic level of a reverse control signal in response to the first phase detection signal, a second phase detection block configured to compare a phase of a clock acquired by delaying the system clock by a correction time, generate a second phase detection signal, and determine a logic level of a clock select signal in response to the first and second phase detection signals, and a clock select block configured to select and output the data clock or a clock acquired by delaying the data clock.10-18-2012
20120081982VERIFYING A DATA PATH IN A SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a memory array configured to store write data transmitted through data transmission lines and transmit stored data to the data transmission line as read data; a data write unit configured to drive the write data to the data transmission lines in response to a data write command; and a data read unit configured to sense the read data transmitted through the data transmission lines in response to a data read command when a data verification signal is deactivated and sense the write data transmitted through the data transmission lines in response to the data write command when the data verification signal is activated.04-05-2012
20120230135DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.09-13-2012
20080298142CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEVICES - Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.12-04-2008
20120320694Write assist in a dual write line semiconductor memory - A semiconductor memory storage device is disclosed, the memory having a plurality of storage cells. Each storage cell comprises two access control devices, each of the access control devices providing the storage cell with access to or isolation from a respective one of two data lines in response to an access control signal, the two data lines being connected to one data port; access control circuitry for applying the access control signal via one of two access control lines to control a plurality of the access control devices; wherein one of the two access control devices of each storage cell is controlled by the access control signal received from a first of the two access control lines to provide the storage cell with access to or isolation from a first of the two data lines, and one further of the two access control devices is controlled by the access control signal received from a second of the two access control lines to provide the storage cell with access to or isolation from a second of the two data lines. The access control circuitry is responsive to a data access request, the data access request being a write request, to apply a data value to be written to both of the first and second data lines and to apply the access control signal to both of the first and second access control lines. In some cases the access control signal is applied to the second of the two access control lines a predetermined time after it is applied to the first of the two access control lines.12-20-2012
20120269017DELAY CIRCUIT AND LATENCY CONTROL CIRCUIT OF MEMORY, AND SIGNAL DELAY METHOD THEREOF - A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.10-25-2012
20120269015COMMAND PATHS, APPARATUSES, MEMORIES, AND METHODS FOR PROVIDING INTERNAL COMMANDS TO A DATA PATH - Command paths, apparatuses, memories, and methods for providing an internal command to a data path are disclosed. In an example method, a command is received and propagated through a command path to provide an internal command. Further included in the method is determining a difference between a latency value and a path delay difference, the path delay difference representing a modeled path delay difference between the command path and the data path measured in terms of a number of clock periods. The propagation of the command through the command path to the data path is delayed by a delay based at least in part on the difference between the latency value and the path delay difference. The internal command is provided to the data path responsive to an internal clock signal.10-25-2012
20110216612Device - A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.09-08-2011
20110249522METHOD AND CIRCUIT FOR CALIBRATING DATA CAPTURE IN A MEMORY CONTROLLER - A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that receives data from a memory. The comparator has a first input coupled to an output of the FIFO, and a second input coupled to receive a calibration pattern. The calibration pattern is predetermined to match with a first portion of data from the FIFO, and is predetermined to not match with a second portion of data from the FIFO. The detection and adjustment circuit detects if a transition from the first portion to the second portion occurs within a predetermined time period. If the transition is not detected within the time period, a timing of the gating signal is adjusted.10-13-2011
20120092945COMMAND LATENCY SYSTEMS AND METHODS - Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required.04-19-2012
20120092944MEMORY DEVICE HAVING A CLOCK SKEW GENERATOR - A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.04-19-2012
20120287736SRAM Write Assist Apparatus - An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.11-15-2012
20100177578TRI-STATE DRIVER CIRCUITS HAVING AUTOMATIC HIGH-IMPEDANCE ENABLING - Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.07-15-2010
20100202225Data input circuit technical field - A data input circuit comprises a sensing control unit which delays an internal write command by a predetermined period and generates a sense amplifier enable signal in response to a first clock signal, and a data sensing unit which senses align data and transfers the sensed data to a global line in response to the sense amplifier enable signal, wherein the sense amplifier enable signal is enabled at a time point when the align data is inputted in the data sensing unit.08-12-2010
20110158010SKEW DETECTOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing result signal; and a detection signal generation block configured to compare an output signal of the data sensing block with a certain time, and generate a skew detection signal.06-30-2011
20130021858Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System - In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.01-24-2013
20080232180Semiconductor memory device and method for driving the same - A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock signal; an internal command signal generator for generating an internal command signal in response to an external command; a delay circuit for delaying the internal command signal by a delay time corresponding to a delay time of the DLL to output a delayed internal command signal; and an output enable signal generator for generating an output enable signal based on the delayed internal command signal and the DLL clock signal.09-25-2008
20130176800MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE - A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time.07-11-2013
20080219067INDIVIDUAL I/O MODULATION IN MEMORY DEVICES - A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.09-11-2008
20130094311DYNAMIC PHASE SHIFTER AND STATICIZER - A dynamic phase shifter and staticizer circuit and method includes a clock domino configured to receive a phase memory signal from a memory array and a clock signal and output the intermediate signal, and a staticizer configured to receive the intermediate signal from the clock domino and the clock signal and output a static memory signal. The static memory signal is shifted by one clock cycle from the phase memory signal. Setup and holding is done with respect to the clock edge, shifting the output of the clock domino, and the received phase memory signal can borrow into the next cycle when being sampled. The phase memory signal is converted from a half-cycle in length to the static memory signal that is a full-cycle in length.04-18-2013
20130094312VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY - A voltage scaling device of a semiconductor memory device, the voltage scaling device including: a delay tester for determining the number of delay cells of a delay locked loop (DLL) required to cumulatively delay a clock signal having a constant frequency, and which is input to the DLL, by one clock period; a temperature sensor for measuring the temperature of the semiconductor memory device; and a voltage regulator for regulating a supply voltage of a voltage source which provides a chip voltage to the semiconductor memory device in response to the temperature measured by the temperature sensor and a locking value corresponding to the number of delay cells calculated by the delay tester.04-18-2013
20130100751PRECHARGE SIGNAL GENERATION CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR GENERATING PRECHARGE SIGNAL - A precharge signal generation circuit includes a control signal generation unit configured to activate a control signal in response to a read command or write command and a precharge signal generation unit configured to use a clock signal in a period when the control signal is activated to activate a precharge signal at a time point when a delay time passes from an input of the read command or the write command to precharge signal generation circuit.04-25-2013
20130128678POWER SAVING METHODS FOR USE IN A SYSTEM OF SERIALLY CONNECTED SEMICONDUCTOR DEVICES - A semiconductor device comprising (i) internal circuitry for outputting at least one internal clock signal and at least one internal data/control signal for transmission to a next device in a chain of semiconductor devices; (ii) data/control output circuitry for outputting at least one output data/control signal from the at least one internal data/control signal and for releasing the at least one output data/control signal towards the next device via at least one output data/control signal line, the at least one output data/control signal having a first dynamic range; and (iii) clock output circuitry for generating at least one output clock signal from the at least one internal clock signal and for releasing the at least one output clock signal towards the next device via at least one output clock signal line, the at least one output clock signal having a dynamic range different than the first dynamic range.05-23-2013
20100277993Method for Tuning Control Signal Associated with at Least One Memory Device - Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.11-04-2010
20130148450CONTENTION-FREE MEMORY ARRANGEMENT - A memory arrangement includes a plurality of memory blocks, a first group of access ports, and a second group of access ports. Routing circuitry couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block, and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion, and has read access to the first portion but not to the second portion.06-13-2013
20120275246MULTI-TEST APPARATUS AND METHOD FOR SEMICONDUCTOR CHIPS - An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.11-01-2012
20130155793MEMORY ACCESS CONTROL SYSTEM AND METHOD - The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.06-20-2013
20130182516SEMICONDUCTOR DEVICE HAVING COUNTER CIRCUIT - A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal.07-18-2013
20110310684SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply, an input terminal connected to a gate terminal of the P-type MOS transistor and gate terminals of the two or more N-type MOS transistors, an output terminal which is a connection node between the P-type MOS transistor and one of the two or more N-type MOS transistors connected to the P-type MOS transistor, and one or more capacitors connected to the output terminal. The drive capability of the P-type MOS transistor is higher than the overall drive capability of the two or more N-type MOS transistors connected together in series. Therefore, a semiconductor integrated circuit is provided in which fluctuations in the delay time of a delay circuit caused by variations in transistor characteristics can be reduced.12-22-2011
20110310683NON-VOLATILE MEMORY CONTROL - Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.12-22-2011
20110310682DELAY-LOCKED LOOP HAVING LOOP BANDWIDTH DEPENDENCY ON OPERATING FREQUENCY - Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its operating frequency. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its operating frequency. In this specific example, operating frequency is determined. This determination may be made directly, either by measuring operating frequency, or indirectly, by taking a measurement or reading, such as by reading a value for column address select latency. Once the operating frequency is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth of the delay-locked loop's loop filter.12-22-2011
20120020174ASYNCHRONOUS SEMICONDUCTOR MEMORY CAPABLE OF PREVENTING COUPLING NOISE - Disclosed herein is a semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay period has elapsed after the address transition is detected, the delay period is adjusted based on a delay period extension signal.01-26-2012
20120020173Sense Amplifier Enable Signal Generation - System and method for generating a sense amplifier enable (“SAE”) signal having a programmable delay with a feedback loop to control the SAE signal duty cycle, which can be used in SRAM or DRAM, or other kinds of memory cells. An illustrative non-limiting embodiment comprises: a programmable clock chopper, a low pass filter, a bias generator, a comparator, and a feedback control module.01-26-2012
20130194882SEMICONDUCTOR DEVICE HAVING TIMING CONTROL FOR READ-WRITE MEMORY ACCESS OPERATIONS - A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 08-01-2013
20130208554TRACKING MECHANISMS - A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.08-15-2013

Patent applications in class Delay