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365 - Static information storage and retrieval

365189011 - READ/WRITE CIRCUIT

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Class / Patent application numberDescriptionNumber of patent applications / Date published
365194000 Delay 255
365193000 Strobe 212
365198000 Transmission 15
365195000 Inhibit 11
365192000 Radio frequency 2
20110128801SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - In an organic memory which is included in a radio chip formed from a thin film, data are written to the organic memory by a signal inputted with a wired connection, and the data is read with a signal by radio transmission. A bit line and a word line which form the organic memory are each selected by a signal which specifies an address generated based on the signal inputted with a wired connection. A voltage is applied to a selected memory element. Thus writing is performed. Reading is performed by a clock signal or the like which are generated from a radio signal.06-02-2011
20090262591NAND SYSTEM WITH A DATA WRITE FREQUENCY GREATER THAN A COMMAND-AND-ADDRESS-LOAD FREQUENCY - The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.10-22-2009
Entries
DocumentTitleDate
20130028033MEMORY MODULE USING OPTICAL SIGNAL - Disclosed is a memory module which includes a memory chip; an external input/output terminal having an electrical signal input/output terminal and an optical signal input/output terminal; an optical signal processor configured to convert a first optical signal input through the optical signal input/output terminal into a first internal electrical signal and to convert a second internal electrical signal into a second optical signal; and a controller configured to provide a first data signal to the memory chip in response to a first external electrical signal input through the electrical signal input/output terminal or the first internal electrical signal and to transfer the second internal electrical signal to the optical signal processor or to output a second external electrical signal to the electrical signal input/output terminal in response to a second data signal output from the memory chip.01-31-2013
20110194365BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM - Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.08-11-2011
20100103752SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR READING/WRITING DATA THEREOF - A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control signal activated when an address for accessing a memory cell of a complementary bit line is inputted. The write selector is configured to selectively transmit data of a write path in response to the control signal. The read selector is configured to selectively transmit data of a read path in response to the control signal04-29-2010
20130083611FAST-WAKE MEMORY - One or more timing signals used to time data and command transmission over high-speed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different-frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.04-04-2013
20100110805SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of address pads, a plurality of data pads, a mode entry controlling unit configured to control the entry to a data masking mode in response to a write command signal and signals inputted through predetermined pads among the plurality of address pads, a signal classifying unit configured to classify signals inputted sequentially and in parallel through the plurality of address pads into column address signals and data masking signals in response to an output signal of the mode entry controlling unit and a write latency signal, and a pad masking signal generating unit configured to generate pad masking signals to control the masking of data inputted through the plurality of data pads, where the pad masking signals are generated by converting the data masking signals in response to the output signal of the mode entry controlling unit.05-06-2010
20100027356Dynamic On-Die Termination of Address and Command Signals - A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of the RQ bus. Application of a first logic level to the at least one input enables termination of the one or more signal lines. Application of a second logic level to the at least one input disables termination of the one or more signal lines.02-04-2010
20100091590Semiconductor memory apparatus - A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.04-15-2010
20100329047NONVOLATILE MEMORY DEVICE - A nonvolatile memory device, including an X decoder coupling global lines to respective word lines to which memory cells are coupled, a voltage supply unit comprising voltage selection circuits corresponding to the respective global lines and configured to generate operating voltages, wherein each of the voltage selection circuits latches control signals, each determined according to a corresponding line enable signal and a corresponding voltage control signal, and selects and supplies one of the operating voltages in response to the control signals, and a control unit supplying a number of the line enable signals and a number of the voltage control signals to the voltage supply unit.12-30-2010
20130135948SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to an embodiment includes: a memory cell in which data is stored; a word line through which the memory cell is selected in each row; a bit line through which a signal read from the memory cell is transmitted in each column; a speed detector that detects a read speed of the memory cell; and a voltage controller that controls at least one of a voltage at the word line and a cell power supply voltage of the memory cell based on the read speed of the memory cell.05-30-2013
20120182815Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices - A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.07-19-2012
20130051165SEMICONDUCTOR APPARATUS AND DATA TRANSMISSION METHOD THEREOF - A semiconductor apparatus includes a normal data line, an auxiliary data line and a data line selection unit. The normal data line is connected with a data selection unit. The auxiliary data line is connected with the data selection unit. The data line selection unit outputs data to one of the normal data line and the auxiliary data line in response to a command signal.02-28-2013
20090303807Semiconductor device and semiconductor system having the same - A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.12-10-2009
20110007584SEMICONDUCTOR DEVICE - A semiconductor device, including a plurality of control signal generation units each generating a control signal that is enabled when a column enable signal and a row enable signal are enabled, and a plurality of local sense amplifiers each sensing and amplifying data transmitted via a pair of local input/output (I/O) lines and then outputting the amplified data via a pair of global I/O lines, in response to a read or write signal and a corresponding control signal.01-13-2011
20090040844OUTPUT CONTROL DEVICE - An output controller includes a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe (CAS) latency, each of the output enable signals having information relating to a delay time from an activation timing of a CAS signal; and an output driving signal generator for receiving the plurality of output enable signals corresponding to the preset CAS latency and outputting rising and falling output driving signals for controlling an output timing of data.02-12-2009
20120224441SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate first and second block enable signals having a level corresponding to one of a plurality of row selection signals or one of a plurality of column selection signals based on a page size control signal; a first page block configured to enable a plurality of first memory cells selected by the plurality of row selection signals in response to the first block enable signal, and activate data access of memory cells selected among the plurality of selected first memory cells by the plurality of column selection signals and the option column selection signal; and a second page block configured to enable a plurality of second memory cells selected by the plurality of row selection signals in response to the second block enable signal, and activate data access of memory cells selected among the plurality of selected second memory cells by the plurality of column selection signals and the option column selection signal.09-06-2012
20090034350Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same - There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (e.g., restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (e.g., a microprocessor) or a portion of a memory device (e.g., a discrete memory).02-05-2009
20120236664SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a semiconductor memory device including a memory cell array, a plurality of signal lines, and a plurality of signal-line-lead-out portions. In the memory cell array, a plurality of memory cells are arranged. The plurality of signal lines connected to the plurality of memory cells. The plurality of signal-line-lead-out portions are arranged in a periphery of the memory cell array and are connected to the plurality of signal lines. Each of the plurality of signal-line-lead-out portions includes a plug as an electrode whose upper surface and side surface are covered with a passivation film.09-20-2012
20120320693DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE - A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.12-20-2012
20110090749CIRCUIT FOR PROVIDING CHIP-SELECT SIGNALS TO A PLURALITY OF RANKS OF A DDR MEMORY MODULE - A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.04-21-2011
20090141570Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM - A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.06-04-2009
20110128800SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: an address pad; an address pad buffer section configured to selectively receive a signal of the address pad; a data input buffer section configured to selectively receive the signal of the address pad; and a signal control section configured to selectively provide a path of the signal of the address pad to the address buffer section and the data input buffer section.06-02-2011
20100034034METHODS, CIRCUITS, AND SYSTEMS TO SELECT MEMORY REGIONS - Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.02-11-2010
20100034033RECEIVER OF SEMICONDUCTOR MEMORY APPARATUS - A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.02-11-2010
20120033512SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first cells, first lines, second lines, a first cell array, and a signal driver. The first cell has in either a first state or a second state. Retention time in the second state is longer than in the first state. The first cell array has the first cells formed in a matrix the individuals. The first cells are electrically connected by the first, second lines. The signal driver drives the first cells. The signal driver causes the first cells to transition to either the first state or the second state by controlling any one of a voltage, a current, and a charge amount applied to the first cells, or a combination of these, and waveforms of the voltage, current, and charge amount and/or the length of transfer time of at least one of the voltage, current, and charge amount.02-09-2012
20090207676SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED CURRENT CONSUMPTION DURING DATA MASK FUNCTION - The present invention describes a semiconductor memory device having a data mask function and includes a common driving control unit for generating a common driving control signal in response to a data mask signal and a write command signal supplied to the common driving control unit. A plurality of driving units are supplied with the common driving control signal and selectively drive data according to the common driving control signal and transmit the driven data to a plurality of data lines, respectively. Accordingly, a driving and data mask operation of the plurality of driving units is controlled by the common driving control unit, which reduces current consumption and a layout area of the circuit.08-20-2009
20090273991SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND COMPRESSION TEST METHOD THEREOF - A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the plurality of pattern signals to the corresponding banks.11-05-2009
20090097338Memory Device Receiver - A memory device includes a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.04-16-2009
20120106271SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals.05-03-2012
20090296500MEMORY CIRCUIT AND CONTROL METHOD THEREOF - A memory circuit having a global signal driving circuit, which, when a first read signal is inputted from a first bit signal line with a column signal inputted from a column signal line, outputs the first read signal as a global signal from a global signal line, and, when a first driving write signal is inputted from the first bit signal line, inhibits the first driving write signal from being outputted to the global signal line on the basis of a first write signal inputted from a first write signal line.12-03-2009
20090003094SEMICONDUCTOR MEMORY DEVICE HAVING REFRESH MODE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device can control the toggling of signals corresponding to internal addresses during an auto-refresh mode. The semiconductor memory device includes an internal address generator configured to generate a plurality of first word line driving information signals and a plurality of first to seventh address information signals, which are sequentially activated in response to a driving signal and a refresh signal, a toggle controller configured to generate first and second toggle control signals in response to the third to sixth address information signals during an auto-refresh mode or a self-refresh mode, and a driving controller configured to generate a plurality of bit line driving signals and a plurality of second word line driving information signals corresponding to the first to third and seventh address information signals in response to the first and second toggle control signals.01-01-2009
20090168561TEST ENTRY CIRCUIT AND METHOD FOR GENERATING TEST ENTRY SIGNAL - Test entry circuit and method for generating test entry signal including a first source signal generator configured to receive a test signal through a pad to generate a first mode source signal for a first test mode, a second source signal generator configured to count activation transitions of the test signal to generate a second mode source signal for a second test mode and an entry signal generator configured to receive the first and second mode source signals to generate a first test mode entry signal for entering the first test mode and a second test mode entry signal for entering the second test mode.07-02-2009
20090168562SEMICONDUCTOR DEVICE, INFORMATION CONTROL METHOD AND ELECTRONIC DEVICE - A semiconductor device includes a first memory unit, a second memory unit, and a determination unit receiving a first signal permitting a write operation to one of the first memory unit and the second memory unit, and a second signal indicating whether the write operation of information to the first memory unit is finished, wherein the determination unit outputs a signal prohibiting a write operation to the second memory unit, if the second signal indicates the write operation of the information is finished.07-02-2009
20080291756Semiconductor memory device of controlling bit line sense amplifier - A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.11-27-2008
20080316843Semiconductor memory device capable of operating in a plurality of operating modes and method for controlling thereof - A semiconductor memory device capable of operating in a plurality operating modes and a method for controlling the device may be provided. The semiconductor memory device may include a selecting unit and a plurality of control circuits operating in a plurality of operating modes. The selecting unit may transmit a selecting signal to select one of the plurality of operating modes. The plurality of control circuits may control operations of the semiconductor memory device in the plurality of operating modes, and the plurality of control circuits may be either enabled or disabled in response to the selecting signal. The semiconductor memory device and the method of controlling the device may have a capability of providing optimized performance in response to a change of operational conditions by selecting one of a plurality of the operating modes.12-25-2008
20090190416SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.07-30-2009
20090109769SIGNAL DESCRAMBLING DETECTOR - Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component can receive one or more distinct patterns and can evaluate the data values associated with such patterns for each data line of the memory. The descrambler component can determine the bit order of the data signals based on such patterns and can generate a transformation function that can facilitate rearranging data, which can be received from or sent to the memory device, into a predetermined bit order.04-30-2009
20100142293Boosting voltage generating circuit, negative voltage generating circuit, step-down voltage generating circuit, and semiconductor device - In a boosting voltage generating circuit, a boosting circuit unit generates boosting voltage according to a value of boosting voltage output by the boosting voltage generating circuit and an auxiliary boosting circuit unit supplies, immediately before electric current is consumed by a load supplied with the boosting voltage, voltage higher than the boosting voltage corresponding to the amount of current consumed by the load, to the load. The auxiliary boosting circuit unit raises the voltage supplied to the load to an optimum amount before the boosting voltage drops.06-10-2010
20100142294Vertical Transistor Memory Cell and Array - A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion, wherein the source and drain regions are opposing.06-10-2010
20090027979Semiconductor memory device and data sensing method thereof - A semiconductor memory device includes first and second edge drivers configured to generate sensing control signals, a memory cell array between first and second edge drivers, and pluralities of unit sense amplifiers detecting data from the memory cell array in response to the sensing control signals.01-29-2009
20090161451DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE - A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.06-25-2009
20120092943Semiconductor device and test method thereof - plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal.04-19-2012
20090323442SEMICONDUCTOR MEMORY DEVICE AND RESET CONTROL CIRCUIT OF THE SAME - The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and outputs a reset control signal when the states of the monitoring signals are equal, and ends the monitoring of the reset signal in synchronization with the enablement of the reset control signal. An internal circuit receives the reset control signal, and the reset control signal controls the initialization of the internal circuit. When the reset signal maintains the enablement state for a predetermined period, the reset control signal is enabled, making it possible to prevent reset malfunction associated with a glitch occurring in the reset signal.12-31-2009
20110222360SEMICONDUCTOR STORAGE DEVICE AND ITS CELL ACTIVATION METHOD - A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control signal from a substrate potential to a first power supply potential in a first activation period, maintains the voltage level of the first control signal at the first power supply potential in a second activation period subsequent to the first activation period, and raises the voltage level of the first control signal from the first power supply potential to a second power supply potential in a third activation period subsequent to the second activation period.09-15-2011
20090219770Semiconductor memory device and operation method thereof - Semiconductor memory device and operation method thereof includes an output enable signal generator configured to synchronize a read command to a data clock signal to generate an output enable signal according to a CAS latency, a sampling control signal generator configured to generate a sampling control signal that is activated during a period corresponding to an activation timing of the output enable signal and an end timing of data output, a read clock signal generator configured to sample the data clock signal in response to the sampling control signal to generate a read clock signal and a data output circuit configured to output data according to the read clock signal.09-03-2009
20100149889SYSTEM WITH CONTROLLER AND MEMORY - According to the system of the present invention, data (DQ) signals are outputted/received between a controller 06-17-2010
20100149890DEVICES AND METHODS FOR CONTROLLING A SLEW RATE OF A SIGNAL LINE - In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.06-17-2010
20100149891SEMICONDUCTOR MEMORY DEVICE INCLUDING RESET CONTROL CIRCUIT - A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.06-17-2010
20100182854OPERATION GUARANTEE SYSTEM - An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.07-22-2010
20100195419Configurable Write Policy in a Memory System - A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used.08-05-2010
20100226187Semiconductor memory device - A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.09-09-2010
20110110173SIGNAL GENERATING CIRCUIT AND RELATED STORAGE APPARATUS - A signal generating circuit is employed for generating a control in order to control operations of one of a controller and at least a storage unit of a related storage apparatus controlled by the controller. The signal generating circuit includes a voltage inputting unit and a voltage detection unit. The voltage detection unit rapidly switches a voltage level of the control signal according to a voltage to be detected which is generated by the voltage inputting unit. As a result, data damage due to unexpected operations performed by the controller during the power-off period can be avoided.05-12-2011
20100254203VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.10-07-2010
20120195140SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first pad allocated to receive a row address, a second pad allocated to discriminate a first input/output mode and a second input/output mode, a detector configured to generate a detection signal in response to logic levels of the first and second pads, and a column address controller configured to deassert a column address to a logic low level in response to a deasserted detection signal. The semiconductor integrated circuit may selectively support one of first and second memory capacities and one of the first and second input/output modes using the logic levels of the first and second pads.08-02-2012
20090016123SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.01-15-2009
20130135949SEMICONDUCTOR MEMORY APPARATUS, AND SET PROGRAM CONTROL CIRCUIT AND PROGRAM METHOD THEREFOR - A semiconductor memory apparatus includes a program pulse generation block configured to generate a first write control signal, second write control signal and a program completion signal in response to a programming enable signal; a set program control circuit configured to repeatedly generate a set programming enable signal a predetermined number of times in response to an erase command and the program completion signal; and a controller configured to disable the first write control signal in response to the erase command and generate the programming enable signal in response to the set programming enable signal.05-30-2013
20100302883Method of estimating self refresh period of semiconductor memory device - In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh completion signal is generated based on the plurality of internal address signals. The self refresh period is detected based on the refresh reset signal and the refresh completion signal.12-02-2010
20090067267MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE AND HIGH-POWER, LOW WRITE LATENCY MODE AND/OR INDEPENDENTLY SELECTABLE WRITE LATENCY - A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.03-12-2009
20110242906DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE - A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.10-06-2011
20100054054SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a plurality of word lines and a plurality of pairs of bit lines and complementary bit lines that cross the plurality of word lines. A plurality of memory cells is disposed at regions where the word lines and the pairs of bit lines and complementary bit lines cross each other. A voltage control unit includes a plurality of elements connected in parallel, each of which is connected to a power voltage source and is switched on/off based on a control signal that controls an operation of the plurality of memory cells. The voltage control unit controls the voltage of the power voltage source to a predetermined level, thus obtaining a controlled voltage to be applied to the memory cells.03-04-2010
20110075495SEMICONDUCTOR MEMORY APPARATUS AND DRIVING METHOD USINGTHE SAME - Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing.03-31-2011
20120147682MEMORY ELEMENTS HAVING CONFIGURABLE ACCESS DUTY CYCLES AND RELATED OPERATING METHODS - Apparatus and methods are provided for accessing memory elements. An exemplary memory element includes an array of memory cells and a control module. Each memory cell of the array is coupled to an access line, wherein the control module is configured to assert a first signal for a write duty cycle on the access line to enable writing to a first memory cell of the array of memory cells, and the control module is configured to assert a second signal for a read duty cycle on the access line to enable reading from the first memory cell. The write duty cycle and the read duty cycle are each selected from a plurality of possible duty cycles. In an exemplary embodiment, the read duty cycle and the write duty cycle are chosen to optimize a performance parameter for the memory element.06-14-2012
20100246289STORAGE DEVICES WITH SOFT PROCESSING - A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.09-30-2010
20110255353SEMICONDUCTOR INTEGRATED CIRCUIT - A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a current is generated inside a memory circuit to raise the temperature inside the semiconductor integrated circuit.10-20-2011
20110211403BIMODAL MEMORY CONTROLLER - A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller.09-01-2011
20110164461Memory Device - A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals.07-07-2011
20100329045Adjustment of Write Timing in a Memory Device - A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.12-30-2010
20110255352ELECTRONIC CIRCUIT - An electronic circuit for which a coil 10-20-2011
20100214857MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF - An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.08-26-2010
20100195420SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - A semiconductor memory system includes a memory controller and a memory. The memory controller includes a control signal converting unit converting a control signal into a converted control signal including n sequential clock pulses and a target clock pulse activated after a time period has elapsed from a start point of the n sequential clock pulses, and output the converted clock signal, and a controller transmitting unit converting the converted control signal into an optical signal, and transmitting the optical signal to the memory. The memory includes a memory receiving unit converting the optical signal into an electrical signal, and a control signal re-converting unit detecting the time period from the electrical signal, and converting the control signal into a control signal corresponding to the time period.08-05-2010
20100020625ELECTRONIC CIRCUIT DEVICE - To provide an electronic circuit device that can change a characteristic after package sealing and that achieves a reduction in miscellaneous tasks during characteristic setting.01-28-2010
20120039137SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI TEST - A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.02-16-2012
20120044776SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is controlled to be in an active state, in which a data signal can be received, while the control signal is in an active state, and otherwise controlled to be in an inactive state.02-23-2012
20120044777SEMICONDUCTOR DEVICE - By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.02-23-2012
20120008432MEMORY CELL HAVING REDUCED CIRCUIT AREA - The present invention relates to a memory cell having a reduced circuit area, which comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled to a readline and controlled by a wordline. The second transistor is coupled between the first transistor and a low-voltage power supply. The third transistor is coupled to the second transistor and controlled by a bitline. The third transistor controls turn-on and cutoff of the second transistor. Besides, the fourth transistor is coupled to the third transistor and a writeline, and is controlled by the wordline. Thereby, according to the present invention, four transistors form a memory cell, and the objective of saving circuit area can be achieved.01-12-2012
20120008431INTEGRATED CIRCUIT USING METHOD FOR SETTING LEVEL OF REFERENCE VOLTAGE - An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.01-12-2012
20120106272SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a pattern data generator configured to generate certain pattern data in a training operation mode, and an output driver configured to drive the pattern data to output training data with a slew rate corresponding to an external command in the training operation mode.05-03-2012
20120113732PSEUDO-OPEN DRAIN TYPE OUTPUT DRIVER HAVING DE-EMPHASIS FUNCTION, SEMICONDUCTOR MEMORY DEVICE, AND CONTROL METHOD THEREOF - A semiconductor memory device includes a memory cell array, an output driver having a pseudo-open drain (POD) structure and providing read data from the memory cell array in a de-emphasis mode, and control logic controlling the output driver in response to a read command to activate the de-emphasis mode. The control logic activates the de-emphasis mode only during an output period during which the read data is output by the output driver.05-10-2012
20120026812MEMORY WITH TERMINATION CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.02-02-2012
20120250432SEMICONDUCTOR DEVICE - To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device 10-04-2012
20100290295SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a word line coupled to memory cells that transmits a word line signal; at least one word repeater circuit that includes a first load circuit disposed on the word line; a first dummy word line disposed along the word line that transmits a first dummy word line signal; at least one dummy repeater circuit that includes a second load circuit disposed on the first dummy word line; bit lines coupled to the memory cells; column switches that couple the bit lines to data lines, respectively; a column selection line disposed along the word line that transmits a column selection signal for controlling each column switch; and at least one column repeater circuit disposed on the column selection line that outputs the column selection signal in synchronization with the first dummy word line signal input to the first dummy repeater circuit.11-18-2010
20120127808INTEGRATED CIRCUIT MEMORY OPERATION APPARATUS AND METHODS - Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during a first time interval and a second level during a second time interval of a memory operation. The apparatus and methods also include a module configured to reduce difference between a value of a voltage on the second line and a value of a voltage on a node of the device during a first time portion of the second time interval. Additional apparatus and methods are disclosed.05-24-2012
20120213015SENSE AMPLIFIER - A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor form cross coupled sensing pairs. The third PMOS and the fourth PMOS transistors serve as compensation transistors. The third NMOS and the fourth NMOS transistors serve as sensing enabling transistors.08-23-2012
20120213018DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.08-23-2012
20120213017APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.08-23-2012
20120213016SEMICONDUCTOR MEMORY DEVICE - At a succeeding stage of a sense amplifier, a first data latch is provided which has the same bit number as the page length and is controlled to invariably hold the same data as that of the sense amplifier. When a column address strobe (CAS) access begins, data is transferred from the first data latch to an error checking and correcting circuit, and error correction and parity generation are performed in a pipeline process. As a result, the CAS access time and the CAS cycle time are reduced.08-23-2012
20090059691SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI TEST METHOD THEREOF - A semiconductor integrated circuit includes a multi-mode control signal generating section that enables one of up and down mat input/output switch control signals for controlling input/output switches in up and down mats according to up/down information addresses during a read operation mode, a multi-mode decoding section that simultaneously activates multi mat selection signals corresponding to one of the up mats and one of the down mats according to row addresses in an active operation mode, and a mat control section that receives the up and down mat input/output switch control signals and the multi mat selection signals and enables word lines and input/output switches in the mats corresponding to the signals.03-05-2009
20090059690Methods and apparatuses for operating memory - In one embodiment a low voltage high performance memory system is disclosed. The system can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and an supply current controller to reduce current to at least a portion of the bit cell and to supply current to another portion of the cell in response to a write control signal and a data signal during a bit cell transition. Reducing the current to a portion of the bit cell and supplying current to another portion of the bit cell during transition can allow the bit cell to transition to a different state faster and can reduce the effects of device variations that manifest during low voltage operation. Other embodiments are also disclosed.03-05-2009
20120176849SEMICONDUCTOR APPARATUS AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.07-12-2012
20120250431SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a first programming command cycle, and generate a second reset signal by logically combining a second plane selection signal and the control pulse signal which again pulses after a second programming setup pulse signal pulses during a second programming command cycle after the first programming command cycle. A plurality of first page buffers allocated to the first plane are reset in response to the first reset signal, and a plurality of second page buffers allocated to the second plane are reset in response to the second reset signal.10-04-2012
20120188832MEMORY CHANNEL HAVING DESKEW SEPARATE FROM REDRIVE - A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.07-26-2012
20120081980MEMORY - A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal.04-05-2012
20100329046INTEGRATED CIRCUIT MEMORY OPERATION APPARATUS AND METHODS - Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during a first time interval and a second level during a second time interval of a memory operation. The apparatus and methods also include a module configured to reduce difference between a value of a voltage on the second line and a value of a voltage on a node of the device during a first time portion of the second time interval. Additional apparatus and methods are disclosed.12-30-2010
20120327728METHOD AND APPARATUS FOR MEMORY COMMAND INPUT AND CONTROL - Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.12-27-2012
20120269013SIGNAL PROCESSING CIRCUIT - A signal processing circuit including a nonvolatile storage circuit with a novel structure. The signal processing circuit includes a circuit that is supplied with a power supply voltage and has a first node to which a first high power supply potential is applied, and a nonvolatile storage circuit for holding a potential of the first node. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer, and a second node that is brought into a floating state when the transistor is turned off. A second high power supply potential or a ground potential is input to a gate of the transistor. When the power supply voltage is not supplied, the ground potential is input to the gate of the transistor and the transistor is kept off. The second high power supply potential is higher than the first high power supply potential.10-25-2012
20110228618SYSTEM WITH CONTROLLER AND MEMORY - According to the system of the present invention, data (DQ) signals are outputted/received between a controller 09-22-2011
20110235445METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF REGISTER FILES - A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS devices in each bit cell of the register file during write and/or read operations of the register file. By doing so, the register file is able to operate at a lower minimum operating voltage.09-29-2011
20100232238DUAL PORT MEMORY DEVICE, MEMORY DEVICE AND METHOD OF OPERATING THE DUAL PORT MEMORY DEVICE - A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port memory device accesses a memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface. The dual port memory device accesses a memory array according to the first type memory interface or the second type memory interface in response to a selecting signal. Therefore, the dual port memory device can be coupled to a processor with a first interface (e.g., PSRAM or SRAM interface) and a processor with a second interface (e.g., SDRAM interface).09-16-2010
20100232239SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.09-16-2010
20120087195SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.04-12-2012
20100177577SIGNAL TRANSFER APPARATUS AND METHODS - Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.07-15-2010
20120140583MULTI-CHIP MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME - A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.06-07-2012
20080253206METAL PROGRAMMABLE SELF-TIMED MEMORIES - A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.10-16-2008
20100091589SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving the first word lines; a second driver region at another side of the memory block in the first direction driving the second word lines; a sensing region at a side of the memory block in the second direction controlling the bit lines responsive to signals from drive lines; a first conjunction region at an intersection of the first driver and sensing regions including a first driver driving the drive lines responsive to signals from control lines; and a second conjunction region at an intersection of the second driver and sensing regions, including a second driver driving the drive lines responsive to signals from the control lines.04-15-2010
20130176798MECHANISM FOR PEAK POWER MANAGEMENT IN A MEMORY - A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.07-11-2013
20080219065DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF GENERATING INFORMATION ABOUT A LOAD CONNECTED TO A DATA PIN OF A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE - A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.09-11-2008
20130114357SEMICONDUCTOR MEMORY APPARATUS, AND SUCCESSIVE PROGRAM CONTROL CIRCUIT AND PROGRAM METHOD THEREFOR - A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal in response to a programming enable signal; a successive program control circuit configured to generate a successive programming enable signal in response to received program addresses and data count signals as a buffered program command or a buffered overwrite command; and a controller configured to generate the programming enable signal in response to the successive programming enable signal.05-09-2013
20130094309TRACKING BIT CELL - A memory macro includes a tracking circuit and a plurality of memory cells. The tracking circuit has tracking transistors configured to receive a tracking voltage value. Each memory cell of the plurality of memory cells has memory transistors configured to receive a cell voltage value different from the tracking voltage value. The tracking circuit is configured to generate a tracking signal based on which a reading signal of a memory cell of the plurality of memory cells is generated.04-18-2013
20130094307BIT LINE VOLTAGE BIAS FOR LOW POWER MEMORY DESIGN - In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.04-18-2013
20130114356SEMICONDUCTOR MEMORY APPARATUS, AND DIVISIONAL PROGRAM CONTROL CIRCUIT AND PROGRAM METHOD THEREFOR - A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal; a divisional program control circuit configured to generate a divisional programming enable signal according to a predetermined number of program division times, in response to the program completion signal; and a controller configured to generate the programming enable signal in response to the divisional programming enable signal.05-09-2013
20110267906Measuring SDRAM Control Signal Timing - Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to and from the SDRAM under test, the oscilloscope display with a memory bus data signal (‘DQ’) and a memory bus clock signal (‘DQS’) from the SDRAM under test.11-03-2011
20110273945TECHNIQUES TO IMPROVE THE OPERATIONS OF A MEMORY DEVICE - A method and system to improve the operations of a memory device by reducing its bit line leakage, power consumption, and read access time. The memory device has a static read word line for each of its bit cells and domino logic for each of its bit line. Each bit line of the memory device is coupled with a gating logic that is activated using a clocked signal. This eases the timing requirement of the read word lines of the memory device and the read word lines do not form the critical path of the access time of the memory device. The leakage current of the memory device in inactive mode is reduced by switching off the pre-charge circuit and/or the keeper circuit of each bit line. Each bit line is pre-charged on demand prior to the evaluation of each bit line.11-10-2011
20130148448MEMORY SYSTEM AND DATA TRANSMISSION METHOD - A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.06-13-2013
20130094308NEGATIVE WORD LINE DRIVER FOR SEMICONDUCTOR MEMORIES - A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.04-18-2013
20100315890MEMORY ARRAY WITH CORRESPONDING ROW AND COLUMN CONTROL SIGNALS - Some embodiments regard a method comprising: controlling a row of cells of a memory array with a first signal; controlling a column of cells of the memory array with a second signal; transferring data from a cell activated by both the first signal and the second signal to a pair of bit lines associated with the cell; and using the data from the pair of bit lines as read data and as data written back to the cell to ensure the cell stores valid data.12-16-2010
20120287735CURRENT CONTROL CIRCUIT - A current control device is disclosed, which reduces a standby current of a semiconductor memory device and a turn-on current of a transistor. The current control device includes an input controller configured to combine a trigger signal and a set signal controlling a circuit operation status, and a drive unit configured to drive an output signal of the input controller, wherein the drive unit includes a current controller for selectively providing a ground voltage in response to an activation status of a pull-down driving signal.11-15-2012
20130194881AREA-EFFICIENT MULTI-MODAL SIGNALING INTERFACE - One or more pins may be modally assigned to either the command/address (C/A) or data (DQ) blocks of a uniform-package, multi-modal PHY (physical signaling interface) of a memory controller, thus enabling those pins to be used as C/A pins when the PHY is connected to some memory types, and as DQ pins when the PHY is connected to other memory types.08-01-2013

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