Class / Patent application number | Description | Number of patent applications / Date published |
365190000 | For complementary information | 17 |
20080205169 | DEVICE FOR STORING A BINARY STATE - Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa. | 08-28-2008 |
20080266989 | SRAM CIRCUITRY - A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry. | 10-30-2008 |
20080273402 | APPARATUS FOR IMPLEMENTING DOMINO SRAM LEAKAGE CURRENT REDUCTION - A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit. | 11-06-2008 |
20080316842 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR BROADCASTING WRITE OPERATIONS - A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures of an address space. Such write operation is then replicated to produce a plurality of write operations. To this end, the write operations may be broadcasted to a plurality of targets. At least one of the targets includes another one of the apertures that produces at least one additional write operation. | 12-25-2008 |
20090016122 | DUAL WORD LINE OR FLOATING BIT LINE LOW POWER SRAM - Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit. | 01-15-2009 |
20090021997 | METHODS AND APPARATUS FOR IMPROVED WRITE CHARACTERISTICS IN A LOW VOLTAGE SRAM - Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit. | 01-22-2009 |
20090073786 | EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND THOSE INCORPORATING EMBEDDED DRAM - An early write with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM. The technique of the present invention allows for early writes to DRAM arrays with direct bit, byte or word data masking capability. | 03-19-2009 |
20090080271 | Memory Cell, Memory Device, Device and Method of Accessing a Memory Cell - Implementations are presented herein that relate to a memory cell, a memory device, a device and a method of accessing a memory cell. | 03-26-2009 |
20090109768 | SRAM Device with Enhanced Read/Write Operations - An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device. | 04-30-2009 |
20100177576 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated. | 07-15-2010 |
20110013467 | System and Method for Reading Memory - A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the precharge circuit being operative to remain in the charging state at time when the storage elements assert the stored bits of data on the bit line. The memory may be a single-ended, static random access memory (“SRAM”). The SRAM circuits of the invention may be incorporated into each of a plurality of individual computers arrayed on a single die. | 01-20-2011 |
20120230134 | DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE - The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line. | 09-13-2012 |
20130010551 | SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES - A memory with extra digit lines in full size end arrays with an open digit architecture can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO. | 01-10-2013 |
20130229883 | SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES - A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO. | 09-05-2013 |
20130265834 | APPARATUSES AND METHODS FOR IMPROVED MEMORY OPERATION TIMES - Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus. | 10-10-2013 |
20130272078 | STORAGE CONTROLLING APPARATUS, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROLLING METHOD - Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data. | 10-17-2013 |
20140153347 | INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY - An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier. | 06-05-2014 |