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Including level shift or pull-up circuit

Subclass of:

365 - Static information storage and retrieval

365189011 - READ/WRITE CIRCUIT

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DocumentTitleDate
20130028031CIRCUIT AND METHOD FOR REDUCING LEAKAGE CURRENT - A circuit comprises a first voltage source, a second voltage source, a first switch, firsts transistors, and a control circuitry. The first switch is configured to selectively couple the first voltage source or the second voltage source to a first signal line. The first transistors are in an IO circuitry and have first bulks configured to receive the first signal line. The control circuitry is configured to receive a clock and a command signal on a command signal line, and generate a first control signal on a first control signal line to control the first switch based on the clock and the command signal.01-31-2013
20080316839MEMORY CELL ARRAY AND METHOD OF CONTROLLING THE SAME - To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage.12-25-2008
20100085820SEMICONDUCTOR MEMORY DEVICE - There is provided a semiconductor memory device having a plurality of memory cell layers which can be used even if part of the memory cell layers is determined as defective. The semiconductor memory device includes a stacked memory cell array having a laminated plurality of memory cell layers, each of which has a plurality of blocks; a layer quality information storing circuit (04-08-2010
20110194362WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT - A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.08-11-2011
20090122621CIRCUIT FOR CONTROLLING SIGNAL LINE TRANSMITTING DATA AND METHOD OF CONTROLLING THE SAME - A circuit for controlling a signal line transmitting data. The circuit includes a data level controller that, when the level of the data transmitted through the signal line is changed, controls the level of the data to be lower than an external power supply voltage level and higher than a ground voltage level after a predetermined time.05-14-2009
20090122622LEVEL SHIFTER WITH REDUCED LEAKAGE CURRENT AND BLOCK DRIVER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted to disable the output signal in response to the input signal. The enable unit comprises; a shifting voltage terminal adapted to receive the boost voltage, a control node, a shifting unit disposed between the shifting voltage terminal and the control node and responsive to the output signal, such that a voltage having a difference with the boost voltage lower than a voltage of the output signal is provided to the control node, whereby the output signal is boosted by the positive boost voltage, a control PMOS transistor disposed between the control node and the output signal and gated by the input signal, and bulk voltage generation unit adapted to generate a predetermined bulk voltage having a voltage difference with the boost voltage lower than that of the control node to a bulk of the control PMOS transistor.05-14-2009
20130039133Data Storage for Voltage Domain Crossings - According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.02-14-2013
20130039132LINE DRIVER CIRCUITS, METHODS, AND APPARATUSES - Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.02-14-2013
20120182813POWER SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE POWER SUPPLY CIRCUIT - According to one embodiment, a power supply circuit, which generates a power supply voltage which is applied to a memory cell array including a plurality of memory cells disposed at intersections between a plurality of word lines and a plurality of bit lines, comprises a first boost circuit configured to boost an input voltage, a first voltage step-down circuit having an input connected to an output of the first boost circuit, and a voltage control circuit configured to control the first boost circuit and the first voltage step-down circuit. The voltage control circuit is configured to generate, not via the first voltage step-down circuit, a voltage which is boosted by the first boost circuit, when a first voltage is transferred to a non-selected memory cell.07-19-2012
20130070542Replica Circuit and It's Applications - A replica circuit includes: a first conductivity type first transistor; a first current path including a first conductivity type second transistor and a second conductivity type third transistor; a second current path including a first conductivity type fourth transistor configured so that current equivalent to a current flowing through the first transistor flows through the fourth transistor, and a second conductivity type fifth transistor configured so that current equivalent to a current flowing through the third transistor flows through the fifth transistor, the fourth transistor and the fifth transistor being connected in series; a second conductivity type sixth transistor configured so a current equivalent to a current flowing through the third transistor flows through the sixth transistor; a first control configured to supply a reference voltage to the drain of the first transistor; and a second control configured to supply the reference voltage to the drain of the fourth transistor.03-21-2013
20120218835SEMICONDUCTOR APPARATUS WITH OPEN BIT LINE STRUCTURE - A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.08-30-2012
20090268531Semiconductor memory device with adjustable selected work line potential under low voltage condition - A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.10-29-2009
20130215687Method and Apparatus for Dynamic Sensing Window in Memory - A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and erase operations. Such operations change a distribution of the data values stored in the memory group.08-22-2013
20130215688VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.08-22-2013
20090231932Semiconductor Device and Method Comprising a High Voltage Reset Driver and an Isolated Memory Array - A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set of voltages of the memory array may be shifted with respect to a reset voltage. The reset driver may drive the reset voltage and the reset driver may have at least one extended drain transistor in the grounded substrate.09-17-2009
20090231931LOW POWER MEMORY ARCHITECTURE - A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.09-17-2009
20100085818Semiconductor memory device - A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to a test mode signal.04-08-2010
20100085819Burst length control circuit and semiconductor memory device using the same - A burst length control circuit capable of performing read and write operations in high speed according to a burst length and a semiconductor memory device using the same includes a clock signal generating unit for generating first and second internal clock signals from a clock signal in response to a first and second burst signals, a control signal generating unit for driving in response to the first and second internal clock signals, wherein the control signal generating unit for generating first and second control signals, enable sections of the first and second control signals being controlled according to the first and second burst signals at a read operation or write operation, and a burst termination signal generating unit for generating a burst termination signal in response to the first and second burst signals. The first control signal is disabled in response to the burst termination signal.04-08-2010
20130163350LEVEL-SHIFT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A level-shift circuit with simpler circuit structure is provided. The level-shift circuit includes a first transistor in which a first power source potential is applied to a source electrode and a first gate electrode and a second power source potential is applied to a second gate electrode, and an inverter circuit to which a first input signal is applied and either a third power source potential or a potential obtained by subtracting an amount of change in the threshold voltage of the first transistor from the first power source potential is supplied as a power source voltage and from which a first output signal is output. A channel formation region of the first transistor is formed in an oxide semiconductor film.06-27-2013
20110280088SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL SHIFTING - A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.11-17-2011
20110286291SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS - A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.11-24-2011
20110286289SYSTEM AND METHOD OF SELECTIVELY VARYING SUPPLY VOLTAGE WITHOUT LEVEL SHIFTING DATA SIGNALS - An electronic system implements a plurality of voltage domains, at least one of which has a selectively variable supply voltage, without requiring the use of a large number of level shifters (e.g., for each data and/or address line). The supply voltage for a first domain is set equal or nearly equal to that of a second domain for a first duration, when the two domains are connected for data transfer across a system bus. When the first domain is isolated from the bus, its supply voltage is set differently from that of the second domain for a second duration. In the second duration, the first domain may have a higher supply voltage, e.g., to perform high-performance computational tasks. Alternatively, it may have a lower supply voltage, to conserve power, if its computational task is less demanding.11-24-2011
20110141830SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a sense amplifier configured to sense and amplify data loaded into a bit line pair, a power line equalize signal generation unit configured to generate a power line equalize signal which is activated until the bit line sense amplifier is enabled after a bit line equalize signal is deactivated, a power line equalizing unit configured to supply a precharge voltage to a pull-up power line and a pull-down power line of the bit line sense amplifier when the power line equalize signal is activated, a pull-up driving unit configured to drive the pull-up power line of the bit line sense amplifier to a pull-up voltage, and a pull-down driving unit configured to drive the pull-down power line of the bit line sense amplifier to a pull-down voltage.06-16-2011
20110134710Level shift circuit - A feedback circuit by which an output of a memory device for storing level-shifted data can be fed back to the input side includes inverters, resistors, and transistors. The resistance value of combined resistance for pulling up or down first and second switching devices is varied in accordance with the output of the memory device by the feedback circuit, so that malfunction caused by dv/dt noise can be dealt with out generating any through current. In this manner, it is possible to provide a level shift circuit which can deal with malfunction causing dv/dt noise regardless of an on or off state of a high-potential-side switching device, while generation of a through current can be suppressed.06-09-2011
20100039873SENSE AMPLIFIER DRIVING CONTROL CIRCUIT AND METHOD - A sense amplifier driving control circuit has a stable discharge characteristic by differently controlling the discharge of a node having a driving voltage according to the change of an organization of a semiconductor memory device. The sense amplifier driving control circuit includes a pull-down driving block configured to provide a pull-down voltage for a pull-down operation of the sense amplifier, a pull-up driving block configured to sequentially provide a first voltage for the overdrive and a second voltage for the normal drive as a pull-up voltage for a pull-up operation of the sense amplifier, wherein a voltage level of the second voltage is lower than that of the first voltage, and a discharging block configured to discharge the node having the second voltage by controlling a amount of the discharging according to an organization of the semiconductor memory device.02-18-2010
20100034032DATA OUTPUT CIRCUIT IN A SEMICONDUCTOR MEMORY APPARATUS - A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.02-11-2010
20090147596Method to improve the write speed for memory products - A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip.06-11-2009
20110069563VOLTAGE SHIFTER FOR HIGH VOLTAGE OPERATIONS - A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage is connected to an output branch and to a selection circuit, which receives a selection signal that controls switching of the latch stage. The latch stage is coupled to the supply line and to a reference potential line, which receives a reference voltage that can vary between a first reference value, when the supply voltage has the first operating value, and a second reference value, higher than the first reference value, when the supply voltage has the second operating value. An uncoupling stage is arranged between the latch stage and the selection circuit and uncouples them in the second operating condition, when the supply voltage and the reference voltage are at their second, high, value.03-24-2011
20110149661MEMORY ARRAY HAVING EXTENDED WRITE OPERATION - In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines associated with the plurality of rows of the SRAM cells; and a selected word-line driver configured during an extended write operation to drive a selected one of the plurality of word-lines with a write word-line signal having an extended duration. Other embodiments may be described and claimed.06-23-2011
20100118623Method of operating semiconductor devices - A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device.05-13-2010
20090080268Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.03-26-2009
20090285039METHOD AND APPARATUS FOR LOCALLY GENERATING A VIRTUAL GROUND FOR WRITE ASSIST ON COLUMN SELECTED SRAM CELLS - A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally raising the source voltage to increase the write ability of the SRAM cell; wherein locally raising the source voltage comprises locally generating a virtual source/ground node for boosting the write ability of a column of SRAM cells without using an additional on-chip or off-chip supply; thereby decreasing the voltage differential across the source and supply of the column of SRAM cells during a write, and restoring the standard chip differential during a read.11-19-2009
20120294096Memory Device and Semiconductor Device Including the Memory Device - A memory device includes a level shifter which includes a first input terminal, a second input terminal, a first output terminal configured to output a first signal, and a second output terminal configured to output an inverted signal of the first signal, a first buffer, a second buffer, a first node, and a second node. The first node, where an output terminal of the first buffer and the first input terminal of the level shifter are connected, is configured to hold a first data. The second node, where an output terminal of the second buffer and the second input terminal of the level shifter are connected, is configured to hold a second data.11-22-2012
20120294095Dynamic Level Shifter - A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.11-22-2012
20110199839WEAK BIT COMPENSATION FOR STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, wherein the current path block is connected to the data line and the data line bar.08-18-2011
20090168557Ultra wide voltage range register file circuit using programmable triple stacking - Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described.07-02-2009
20080239839METHOD FOR USING A SPATIALLY DISTRIBUTED AMPLIFIER CIRCUIT - An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.10-02-2008
20090003090Impedance adjusting circuit and semiconductor memory device having the same - An impedance adjusting circuit includes: a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance; a transmission line circuit configured to transfer the first calibration code during a first section and to transfer the second calibration code during a second section; and a termination resistor circuit adapted to match an impedance with a resistance determined by receiving the first and second calibration codes.01-01-2009
20080304337METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 212-11-2008
20110205815Decoder circuit of semiconductor storage device - The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.08-25-2011
20080304336SEMICONDUCTOR MEMORY DEVICE WITH ZQ CALIBRATION - A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibration codes to determine a termination resistance value, a test mode signal generating unit for generating a test mode signal which is enabled in the test mode for outputting the calibration codes, and a test mode control unit for selectively outputting the data or the calibration codes in response to the test mode signal.12-11-2008
200901685581-TRANSISTOR TYPE DRAM DRIVING METHOD WITH AN IMPROVED WRITE OPERATION MARGIN - A 1-transistor type DRAM driving process writes a data bit that corresponds to a level applied to a bit line. A first hold period holds data by deactivating a word line of an NMOS transistor and precharging a source and bit line. After the first hold period, a complex operation period operates the NMOS transistor and a bipolar transistor by activating the word line of the NMOS transistor, shifting the source line voltage to a ground voltage, and shifting the bit line voltage to a corresponding multi level bit voltage level. After the complex operation period, a bipolar transistor operation period operates only the bipolar transistor by deactivating the word line of the NMOS transistor. After the bipolar transistor operation period, a second hold period holds the data by precharging the source and bit lines of the NMOS transistor and the bit level applied to the bit line is written.07-02-2009
20110188326DUAL RAIL STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control.08-04-2011
20110205814SENSE AMPLIFIER AND METHOD OF SENSING DATA USING THE SAME - Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from charging.08-25-2011
20090185434OPERATIONAL MODE CONTROL IN SERIAL-CONNECTED MEMORY BASED ON IDENTIFIER - Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be placed in a low power consumption mode, while maintaining input/output components in an active operational mode. Conveniently, aspects of the disclosed system reduce off current without adding many logic blocks into the memory devices.07-23-2009
20090021990MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF - A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.01-22-2009
20130121089SYSTEMS AND METHODS FOR REDUCING PEAK POWER CONSUMPTION IN A SOLID STATE DRIVE CONTROLLER - In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.05-16-2013
20090251975Circuit and Method for a Sense Amplifier with Instantaneous Pull Up/Pull Down Sensing - A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the complementary bit lines and to simultaneously restore the value stored in the memory cell. A differential output signal generator circuit is provided to instantaneously supply the pull up and pull down voltages. In another preferred embodiment the signal generator provides the pull up and pull down voltages at a first level and subsequently increases the pull up voltage to a voltage greater than the positive supply voltage and decreases the pull down voltage. A method of sensing is disclosed wherein the sense and restore actions are performed instantaneously to provide memory cell sensing with greater tolerance of device mismatches.10-08-2009
20090219768SEMICONDUCTOR MEMORY DEVICE HAVING SHARED BIT LINE SENSE AMPLIFIER SCHEME AND DRIVING METHOD THEREOF - A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper cell array in response to an upper bit line disconnection signal; a lower bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of a lower cell array in response to a lower bit line disconnection signal; an upper bit line equalization unit for equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and a lower bit line equalization unit for equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal.09-03-2009
20090122620Systems and Methods for Low Power, High Yield Memory - A system for low power, high yield memory is described. The system includes a memory cell configured to receive a memory supply voltage. The system further includes a memory supply voltage control circuit configured to modify the memory supply voltage from a first memory supply voltage level to a second memory supply voltage level for a write to the memory cell.05-14-2009
20120195139MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.08-02-2012
20120033508LEVEL SHIFTER FOR USE WITH MEMORY ARRAYS - In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first voltage domain to the second voltage domain; and (4) isolation circuitry that selectively isolates the first voltage domain from the second voltage domain so as to selectively prevent current flow between the first voltage domain and the second voltage domain. Numerous other aspects are provided.02-09-2012
20100157695VOLTAGE SHIFTING WORD-LINE DRIVER AND METHOD THEREFOR - A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected to a level shifter to shift the corresponding select signal so that the driver module provides a level-shifted signal at the first word-line in response to assertion of the first select signal. A single level shifter can be connected to multiple driver modules, thereby reducing the area required to implement level-shifting for multiple word-lines.06-24-2010
20100259999KEEPERS, INTEGRATED CIRCUITS, AND SYSTEMS THEREOF - A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.10-14-2010
20100238744Semiconductor stroage device - A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BL09-23-2010
20090303804SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes an overdriving control circuit configured to generate a first drive signal and a second drive signal in response to an internal signal of an active command mode, an equalizing signal generating unit configured to generate an equalizing signal which is controlled with an overdriving voltage VPP level higher than a normal drive voltage during a first duration of an activation period and with the normal drive voltage VDD during a second duration of the other activation period after the first duration in response to the first drive signal and the second drive signal, and an equalization unit configured to equalize first and second lines in response to the equalizing signal.12-10-2009
20090116307LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE - A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.05-07-2009
20100054051MEMORY DEVICE AND METHOD THEREOF - The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field effect transistor. The control electrodes of the p-type field effect transistor and the n-type field effect transistor are connected together as part of a common node. In addition, a current electrode of the p-type field effect transistor and a current electrode of the n-type field effect transistor are connected together to form a common node.03-04-2010
20100039872Dual Power Scheme in Memory Circuit - A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder is configured to receive the higher level address signal and, in response, provide word line signals. Write drivers receive low level data input signals and configure bitlines in response to the received input. Memory cells are responsive to the word line signals and to the configured bit lines for storing data therein.02-18-2010
20100195417SEMICONDUCTOR DEVICE, CIRCUIT OF CONTROLLING SIGNAL LINES AND METHOD OF CONTROLLING SIGNAL LINES - A semiconductor device includes first and second lines, and a switch between the first and second lines. The switch temporary and electrically connects the first and second lines to each other, when the first signal line is transitioned from a first level to a second level while the second signal line is transitioned from the second level to the first level.08-05-2010
20090040840SEMICONDUCTOR MEMORY DEVICE AND METHOD OF COMPENSATING FOR SIGNAL INTERFERENCE THEREOF - A semiconductor memory device includes a memory cell array including a plurality of memory cell array blocks, a plurality of pairs of first data lines for transceiving data with corresponding memory cell array blocks, a plurality of column selection signal lines disposed in an orthogonal direction to the pairs of first data lines, and a plurality of pairs of second data lines to transceive data with corresponding pairs of first data lines of the pairs of first data lines. The memory cell array includes a signal interference compensator that shifts a voltage level of a second data line signal of one of the pair of second data lines interfered by a column selection signal line, to a voltage level of a first data line signal of other of the pair of second data lines not interfered so as to compensate for a signal interference.02-12-2009
20110235442Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.09-29-2011
20100195416Anti-fuse circuit and semiconductor memory device - An anti-fuse circuit uses first to fifth power supplies which have first to fifth power supply voltages, respectively, in the order of highest to lowest during writing. The anti-fuse circuit includes: a first level shift circuit which is connected to the second to fourth power supplies and which converts a first logic signal that changes between the third and fourth power supply voltages into a second logic signal that changes between the second and fourth power supply voltages; a second level shift circuit which is connected to the first, second, and fourth power supplies and which converts the second logic signal into a third logic signal that changes between the first and fourth power supply voltages; a transistor having a source connected to the first power supply and a gate connected to the third logic signal; and an anti-fuse element having one end connected to the drain of the transistor and the other end connected to the fifth power supply.08-05-2010
20080291752Semiconductor Device - A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line. The semiconductor device may include a data transfer unit which receives first data, and outputs second data obtained by driving the first data to a predetermined level to a data transfer line; a data receiver which receives the second data transferred via the data transfer line; a delay which outputs a plurality of delay signals respectively obtained by delaying the second data outputted from the data transfer unit by different delay periods; a delay controller which selects one of the delay signals in accordance with an operation mode of the semiconductor device, and outputs at least one adjustment signal for adjusting a driving period of the data transfer unit for the first data based on the delay period of the selected delay signal; and a transfer controller which receives the first data and the at least one adjustment signal, and outputs at least one transfer control signal for controlling the operation of the data transfer unit, based on the received first data and adjustment signal.11-27-2008
20080285359Level-shifter circuit and memory device comprising said circuit - A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second circuit adapted to transfer the preset voltage level to a third circuit connected to a preset negative voltage value. The third circuit is connected to a further voltage at a positive or nil level and is adapted to supply an output voltage to the preset negative level or to the positive or nil level.11-20-2008
20100302880DUAL POWER RAIL WORD LINE DRIVER AND DUAL POWER RAIL WORD LINE DRIVER ARRAY - A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is coupled between the word line and a node. A pull-down unit is coupled between the node and a ground. A pull-up unit is coupled between the node and a second supply voltage higher than or equal to the first supply voltage. The signal buffering unit provides a word line signal corresponding to the predecode signal to the memory array via the word line when the pull-down unit is turned on by the predecode signal and a first pulse signal and the pull-up unit is turned off by a second pulse signal. There is no level shifter on a critical timing path of the dual power rail word line driver.12-02-2010
20130135947SEMICONDUCTOR DEVICE HAVING PLURAL SELECTION LINES - The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.05-30-2013
20110026335POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal.02-03-2011
20090067265SEMICONDUCTOR STORAGE DEVICE - A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell. The plurality of step-down circuits are connected to the bit line, and the plurality of step-down circuits are controlled by step-down control signals different to each other.03-12-2009
20090067264SEMICONDUCTOR MEMORY DEVICE WITH NORMAL AND OVER-DRIVE OPERATIONS - A semiconductor memory device having a driver configured to sequentially perform over-driving and normal driving operations is presented. The semiconductor memory device includes a driver that outputs a drive signal, that over-drives the drive signal with an over-drive voltage having a voltage level higher than a normal drive voltage, and then subsequently normally drives the drive signal with the normal drive voltage. The semiconductor memory device also includes a drive voltage adjuster that detects a level of the over-drive voltage and compensates for a change in the voltage level of the normal drive voltage in response to the detected level of the over-drive voltage.03-12-2009
20110026334BIDIRECTIONAL EQUALIZER WITH CMOS INDUCTIVE BIAS CIRCUIT - An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as an output driver circuit when the output data is being transmitted and as an on die termination circuit when the input data is being received, and an active inductive bias circuit connected to the data port in parallel with the impedance matching circuit, and configured to adjust the impedance of the data port to the channel during transmission of the output data as a function of output data frequency and adjust the impedance of the data port to the channel during receipt of the input data as a function of input data frequency.02-03-2011
20110085389METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY - A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCC04-14-2011
20120243344ROW ADDRESS DECODING BLOCK FOR NON-VOLATILE MEMORIES AND METHODS FOR DECODING PRE-DECODED ADDRESS INFORMATION - Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.09-27-2012
20100054052SEMICONDUCTOR MEMORY - A semiconductor memory is provided which includes a word line coupled to a transistor of a memory cell; a word driver configured to activate the word line; a first resistance portion configured to couple the word line to a low-level voltage line in accordance with an activation of the word line and to decouple the coupling after a first period in an activation period of the word line elapses; a second resistance portion configured to couple the word line to a high-level voltage line in a second period in the activation period; and a third resistance portion configured to couple the word line to the low-level voltage line in the second period, a resistance of the third resistance portion being higher than a resistance of the first resistance portion, wherein a high-level voltage of the word line in the second period is lower than that of the high-level voltage line.03-04-2010
20110249518Circuits, Systems, and Methods for Dynamic Voltage Level Shifting - Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.10-13-2011
20090213669HIGH VOLTAGE SWITCH CIRCUIT HAVING BOOSTING CIRCUIT AND FLASH MEMORY DEVICE INCLUDING THE SAME - A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit precharges an output node to a set voltage in response to an enable signal. The feedback circuit supplies a feedback voltage to an input node in response to a switch control voltage generated from the output node when the output node is precharged. The boosting circuit boosts the feedback voltage and outputs a boosting voltage to the output node, in response to clock signals, thereby increasing the switch control voltage. The high voltage switch is turned on or off in response to the switch control voltage, and is turned on to receive a high voltage and output the received high voltage. The boosting circuit includes an amplification circuit of a cross-coupled type.08-27-2009
20100284230METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a first time period, cutting off the supply of the variable voltage to the first bit line, after the first time period, and precharging the first bit line to a second voltage level through a sense node of the selected page buffer, which is in a precharge state, evaluating a voltage of the first bit line, after the precharging of the first bit line, so that the voltage of the first bit line is shifted according to a program state of the selected memory cell, and sensing the voltage of the evaluated first bit line and latching data in the selected memory cell.11-11-2010
20110211398MEMORY DEVICE AND ASSOCIATED MAIN WORD LINE AND WORD LINE DRIVING CIRCUIT - A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected.09-01-2011
20080198673SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD FOR THE DEVICE - This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells; a sense node pair connected to the bit line pair and transmitting data stored in the memory cells; transfer gates connected between the bit line pair and the sense node pair; latch circuits latching a high-level potential in one sense node of the sense node pair, and latching a first low-level potential in the other sense node of the sense node pair; and a level shifter applying a second low-level potential lower than the first low-level potential to one bit line of the bit line pair according to the electric potentials latched in the sense node pair at the time of writing data or writing back data.08-21-2008
20110255351Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.10-20-2011
20110075491SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DRIVING BIT-LINE SENSE AMPLIFIER - Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.03-31-2011
20110080793SENSING AMPLIFIER APPLIED TO AT LEAST A MEMORY CELL, MEMORY DEVICE, AND ENHANCEMENT METHOD FOR BOOSTING THE SENSING AMPLIFIER THEREOF - A sensing amplifier consists of a sensing circuit, a boosting circuit, at least one bit-line isolating circuit, and at least a P-sensing enhancement circuit. The sensing circuit is disposed between a sensing line and a complementary sensing line. The boosting circuit boosts the sensing line and the complementary sensing line during a boosting stage. The bit-line isolating circuit is coupled to the sensing circuit for controlling whether to isolate a bit line/complementary bit line from the sensing line/complementary sensing line. The P-sensing enhancement circuit is coupled to the sensing line, the complementary sensing line, and a reference voltage. When the bit-line isolating circuit isolates the bit line from the sensing line and isolates the complementary bit line from the complementary sensing line, a voltage level of the bit line or the complementary bit line is pulled up to the reference voltage by the P-sensing enhancement circuit during an enhancement stage.04-07-2011
20110085390WORD-LINE LEVEL SHIFT CIRCUIT - A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.04-14-2011
20100165753METHOD AND APPARATUS FOR REDUCING LEAKAGE IN BIT LINES OF A MEMORY DEVICE - A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of a respective one of the bit lines. A logic circuit that has a plurality of transistors and each transistor is coupled with the respective one of the bit lines and with a respective one of the nodes to reduce leakage of the bit lines when the transistors are deactivated. A just in time pre-charge method is also used to avoid the requirement of an additional pre-charge device to prevent excessive charge sharing while enabling the reduction of leakage of the bit lines.07-01-2010
20100165754SIGNAL SYNCHRONIZATION IN MULTI-VOLTAGE DOMAINS - A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.07-01-2010
20100157697SEMICONDUCTOR DEVICE AND SYSTEM - A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input circuit in a first mode and activates the second input circuit in a second mode. The control circuit controls the first input circuit and the second input circuit such that the first input circuit and the second input circuit are activated during a certain time period when switching between the first mode and the second mode.06-24-2010
20110261631SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.10-27-2011
20090175096SEMICONDUCTOR DEVICE AND METHOD FOR BOOSTING WORD LINE - A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.07-09-2009
20100061164FAIL-SAFE HIGH SPEED LEVEL SHIFTER FOR WIDE SUPPLY VOLTAGE RANGE - The present invention discloses a fail-safe level shifter switching with high speed and operational for a wide range of voltage supply. The level shifter includes a cascode module, and one or more speed enhancer modules. The cascode module is receiving one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.03-11-2010
20110063927Semiconductor device using plural internal operation voltages and data processing system using the same - A semiconductor device includes an input buffer that receives an address signal having a first amplitude, a level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude, an address controller that receives the address signal output from the level shifter, address decoders that generate a decode signal by decoding the address signal output from the address controller, and level shifters that convert an amplitude of the address signal or of the decode signal from the second amplitude to the first amplitude such that at least an amplitude level of the decode signal becomes the first amplitude.03-17-2011
20110317499SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY ADDRESS DECODING - A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.12-29-2011
20120014192Two stage voltage level shifting - A voltage level shifter for shifting an output signal from a first voltage level to a second voltage level and then to a further boosted second voltage level is disclosed. The voltage level shifter comprises: an input for receiving an input signal; an output for outputting an output signal; a first power supply input for connecting to a first voltage source supplying said first voltage level; a second power supply input for connecting to a second voltage source supplying said second voltage level; and a third power supply input for connecting to a third voltage source supplying said boosted second voltage level; said voltage level shifter being responsive to a predetermined change in said input signal to isolate said first power supply input from said output and to connect said second power supply input to said output and being responsive to said output signal attaining a predetermined value to connect said third power supply input to said output and to isolate said second power supply input from said output.01-19-2012
20090262588POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (LSIFF) AND A CLOCK CONTROLLED DATA RETENTION SCHEME - An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.10-22-2009
20120155194Wordline voltage control within a memory - A memory circuit 06-21-2012
20110128799LEVEL SHIFTING CIRCUIT AND NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal or a second shifting signal to a level of a pumping voltage in response to the select signal and the driving control signal; a first switching unit configured to apply a program voltage to a word line when the first shifting signal is enabled to the level of the pumping voltage; and a second switching unit configured to apply a pass voltage to the word line when the second shifting signal is enabled to the level of the pumping voltage.06-02-2011
20100238745Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.09-23-2010
20120134221WORD-LINE LEVEL SHIFT CIRCUIT - A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.05-31-2012
20120134220WRITE ASSIST CIRCUITRY - A circuit includes a word line driver for driving a world line and a tracking word line driver for driving a tracking word line. The pulse width of a world line signal on the world line is driven to be larger than that of a tracking world line signal on the tracking world line to assist writing under difficult conditions. Because the tracking word line signal is activated later than the word line signal being activated but is deactivated at the same time with the word line, the pulse width of the word line signal is larger.05-31-2012
20120134219MODE CHANGING CIRCUITRY - A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.05-31-2012
20090059687Semiconductor memory device and layout method thereof - Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and a fourth precharger. The semiconductor memory device may include a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal. The semiconductor memory device may further include first, second, third and fourth prechargers. The first and third prechargers may be configured to precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation.03-05-2009
20090059686Sensing scheme for the semiconductor memory - The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and a bit line-bar during non-accessing mode. During data accessing mode, one P-type device of an SRAM memory cell pulls up bit line or bit line-bar node slowly to minimize the inductive coupling noise and VDD, Ground bouncing, hence allows smaller amount of differential voltage input to the sense amplifier and results in lower power consumption. A self-timer counts the needed time and sends a signal to enable the current driven sense amplifier and to turn off the word line to avoid further pulling up the bit line or bit line-bar voltage and to reduce the power dissipation.03-05-2009
20120075937Semiconductor Memory Device - A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to a test mode signal.03-29-2012
20120176848SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING BIT LINE EQUALIZING SIGNAL - A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal.07-12-2012
20100008162SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING BIT LINE EQUALIZING SIGNAL - A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal.01-14-2010
20120314516Performing Stuck-At Testing Using Multiple Isolation Circuits - A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.12-13-2012
20120257464SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a real memory cull; a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal; a replica circuit including a plurality of replica units connected in series, each of replica units including a plurality of dummy memory cells connected in parallel, wherein one of dummy memory cells of one of replica units is accessed in response to data which is read from one of dummy memory cells of one of replica units of a prior stage; and an operation control circuit configured to activate a dummy access signal to access one of dummy memory cells of one of replica units of a first stage in response to a read command, and to activate the sense amplifier enable signal in response to data read from one of replica units of a last stage.10-11-2012
20120257463DRIVER CIRCUIT - A driver circuit includes pull-up and pull-down drivers driven by separate pre-drivers operating between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based on both the pull-up driver and the pull-down driver.10-11-2012
20090003091Semiconductor Device - There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.01-01-2009
20110122712Controlling voltage levels applied to access devices when accessing storage cells in a memory - A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line.05-26-2011
20080298141BIT LINE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for generating an overdriving signal defining an overdriving period in response to an active command; an overdriving control signal generator for receiving the overdriving signal to generate an overdriving control signal for selectively performing an overdriving operation according to a voltage level of an overdriving voltage; and a second driver for driving the normal driving voltage terminal to the overdriving voltage in response to the overdriving control signal.12-04-2008
20080298140MEMORY STRUCTURE WITH WORD LINE BUFFERS - A memory comprises a plurality of memory cells. A row decoder module selectively drives word lines using a voltage level to access selected ones of the memory cells. A first regeneration module selectively pulls the voltage level on one of the word lines to one of first and second predetermined voltage levels. At least one of the memory cells of the one of the word lines is located between the first regeneration module and the row decoder module.12-04-2008
20120327726Methods and Circuits for Dynamically Scaling DRAM Power and Performance - A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.12-27-2012
20120269011VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.10-25-2012
20110228617TECHNIQUES FOR REDUCING A VOLTAGE SWING - Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region. The apparatus for reducing a voltage swing may also comprise a first voltage supply coupled to the source line configured to supply a first voltage and a second voltage to the source line, wherein a difference between the first voltage and the second voltage may be less than 3.5V.09-22-2011
20120275243SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first switch configured to couple a bit line to a first input/output line in response to an output selection signal including a pulse which is generated in response to a read command or write command; and a second switch configured to couple the first input/output line to a second input/output line in response to a switching control signal which is enabled after the output selection signal is enabled.11-01-2012
20100202220MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING BIT LINE EQUALIZATION VOLTAGES - A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.08-12-2010
20130016575Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.01-17-2013
20110158007MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.06-30-2011
20080225611METHOD AND APPARATUS FOR IMPROVING SRAM CELL STABILTY BY USING BOOSTED WORD LINES - The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.09-18-2008
20080225610Write driver of semiconductor memory device and driving method thereof - A write driver of a semiconductor memory device over drives a local input/output line at a write operation in order to transmit data provided in a global input/output line to a core area at a stable voltage level. Therefore the write driver charges a stable voltage level corresponding to data inputted at the write operation in a cell capacitor. The write driver includes a pull-up/pull-down driver for pull-up/pull-down driving a second data line depending on data loaded on a first data line, a pulse generation circuit for generating pull-up over driving pulses activated for a predetermined time period at the initial time of an interval that the second data line is pull-up driven, and an over driver for pull-up driving the second data line by an over driving voltage higher than a pull-up voltage of the pull-up/pull-down driver in response to the pull-up over driving pulses.09-18-2008
20120250427Multi-Mode Interface Circuit - An interface circuit having a first signal path and a second signal path is disclosed. The first and second signal paths are coupled between a first and second nodes, wherein the first node is coupled to receive signals from a source external to an integrated circuit upon which the interface circuit is implemented. Each of the first and second signal paths include circuitry implemented with transistors rated at higher voltages than internal circuitry coupled to receive signals therefrom. The first and second signal paths may utilize different circuit topologies. The interface may thus be used in environments where external circuitry coupled to the external input node conforms to one of a number of different standards (e.g., LPDDR1 and LPDDR2).10-04-2012
20130135946DUAL RAIL MEMORY ARCHITECTURE - A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain.05-30-2013
20110267902Semiconductor device - A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply voltage to the drive circuit, selects the first voltage and, when supplying a power supply voltage to an internal device, selects the second voltage; and a step-up circuit that, when the first voltage selected by the selector is input, boosts the first voltage to a third voltage and outputs the third voltage as the power supply voltage to the drive circuit and, when the second voltage selected by the selector is inputted, boosts the second voltage to a fourth voltage and outputs the fourth voltage as the power supply voltage to the internal device.11-03-2011
20110273940LEVEL SHIFTING CIRCUIT - A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed.11-10-2011
20120275244SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CIRCUIT - A semiconductor integrated circuit includes: a fuse; a first driving unit configured to drive a sensing node in response to a first fuse sensing signal; a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.11-01-2012
20130182514Mimicking Multi-Voltage Domain Wordline Decoding Logic for a Memory Array - Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.07-18-2013
20130155789DATA SENSING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - An memory device includes a bit line, an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the bit line in response to a voltage level of the bit line and a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the bit line in response to the voltage level of the bit line.06-20-2013
20120014193CHARGE PUMP CIRCUIT, NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM - Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate node concerned. A charge pump circuit includes a step-up capacitor configured by a first capacitance and a second capacitance coupled in series, a capacitance driver, and a protection circuit. The protection circuit is set at a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated. Accordingly, relaxation of the withstand voltage of the step-up capacitor is achieved, and reduction of the pump efficiency is avoided.01-19-2012
20120092939SINGLE-ENDED SENSING SCHEME FOR MEMORY - A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.04-19-2012

Patent applications in class Including level shift or pull-up circuit