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Including signal comparison

Subclass of:

365 - Static information storage and retrieval

365189011 - READ/WRITE CIRCUIT

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DocumentTitleDate
20110199838SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a three-dimensional memory cell array, write drivers, and a program voltage control circuit. In the three-dimensional memory cell array, memory cells are three-dimensionally arranged. The write drivers are arranged to be distributed under the three-dimensional memory cell array and apply a program voltage to the memory cells during writing in the memory cells. The program voltage control circuit is arranged around the three-dimensional memory cell array and performs control for making the write drivers to generate the program voltage.08-18-2011
20100142288NEGATIVE WORD LINE VOLTAGE GENERATOR FOR SEMICONDUCTOR MEMORY DEVICE - A negative word line voltage generator for semiconductor memory device includes a comparison unit configured to compare a reference voltage and a feedback voltage and to output a comparison result as an output signal, a pull-down driving unit configured to pull down a negative word line voltage in response to an output signal of the comparison unit, a sub pull-down driving unit configured to pull down a voltage level of the negative word line voltage node additionally during an activation period of a precharge signal, and a feedback unit configured to provide the feedback voltage corresponding to a voltage level of the negative word line voltage.06-10-2010
20130028029METHOD OF CONTROLLING OPERATIONS OF A DELAY LOCKED LOOP OF A DYNAMIC RANDOM ACCESS MEMORY - A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM) is provided herein. A phase detector of the DLL compares an external clock signal with a feedback clock signal to generate a first control signal. A delay line circuit of the DLL delays the external clock signal according to the first control signal. A detector of the DRAM detects variations of the first control signal to determine a length of an enable period of an enable signal. The delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode.01-31-2013
20110182127SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.07-28-2011
20090147593OUTPUT DRIVER OF SEMICONDUCTOR MEMORY APPARATUS - An output driver of a semiconductor memory apparatus comprises a voltage dividing block configured to generate divide voltages by dividing an internal voltage, a threshold voltage detecting block configured to generate a detecting voltage corresponding to a change in a threshold voltage of a transistor, a drive capability control signal generating block 06-11-2009
20090059681SEMICONDUCTOR MEMORY DEVICE - Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detection circuit to generate a uniform core voltage.03-05-2009
20100061160DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH, INTEGRATED CIRCUIT WITH THE SAME AND METHOD FOR ON DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH - A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit.03-11-2010
20090196109RANK SELECT USING A GLOBAL SELECT PIN - Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.08-06-2009
20090268529Sense amplifier control circuit for semiconductor memory device and method for controlling sense amplifier control circuit - A sense amplifier control circuit for a memory device is provided. The sense amplifier control circuit for a memory device including: a level detection unit configured to generate a level detection signal by detecting a core voltage level in an active operation interval; and a control unit configured to generate a pulse signal to control a sensing start time of a bit line detection signal by varying a delay time according to the level detection signal.10-29-2009
20080259697SEMICONDUCTOR MEMORY DEVICE HAVING OUTPUT IMPEDANCE ADJUSTMENT CIRCUIT AND TEST METHOD OF OUTPUT IMPEDANCE - A semiconductor device has an output impedance adjustment circuit for automatically adjusting an output impedance of an output circuit including transistors connected in parallel. The output impedance adjustment circuit comprises: a replica circuit including a circuit portion of the substantially same configuration as the output circuit; a comparator for comparing a magnitude of the output impedance of the replica circuit with a reference resistor and for outputting a comparison result as an internal counter control signal; a switching controller selectively switching between an external counter control signal from outside and the internal counter control signal; and a counter circuit for performing a count operation selectively according to the internal or the external counter control signal and for outputting a count value as an adjustment code which is supplied to the output circuit and the replica circuit so that each transistor is controlled to be on/off based on the adjustment code.10-23-2008
20100008158Read Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology - Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.01-14-2010
20130077414MEMORY APPARATUS - A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.03-28-2013
20130033944INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh signal and a power-down mode signal and output the selection reference voltage; a driving signal generation unit configured to compare the selection reference voltage with a negative word line voltage applied to an unselected word line and generate a driving signal; and a driving unit configured to change the negative word line voltage in response to the driving signal.02-07-2013
20100322016RETENTION OF DATA DURING STAND-BY MODE - An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is configured to selectively alter the voltage provided at each said storage array node during stand-by mode. The storage device may further comprise a storage array operatively coupled to said Rail to Rail voltage adjustor and a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during stand-by mode.12-23-2010
20130070540VOLTAGE REGULATION FOR 3D PACKAGES AND METHOD OF MANUFACTURING SAME - Disclosed herein are structures and related processes for effectively regulating power among slave chips in a 3D memory multichip package that employs TSVs for interlevel chip connections. The disclosed techniques employ individual voltage regulators on one or more of the slave chips for accurate level control of internal voltages, for example, word line driver voltage (VPP), back bias voltage (VBB), data line voltage (VDL), and bit line pre-charge voltage/cell plate voltage (VBLP/VPL). Employing regulators on one or more of the slave chips not only allows for precise regulation of power levels during typical memory stack operation, but also provides tolerance in small variations in power levels caused, for example, by manufacturing process variations. Moreover, less chip real estate is used as compared to techniques that provide complete power generators on each chip of a multichip stack.03-21-2013
20130051158INTEGRATED CIRCUIT, TESTING APPARATUS FOR INTEGRATED CIRCUIT, AND METHOD OF TESTING INTEGRATED CIRCUIT - Provided are a redundant memory; a generator that generates a test pattern, and an expected value of data expected to be output from the redundant memory, in response to the test pattern being supplied to the redundant memory; a comparator that compares the expected value generated by the generator, against data output from the redundant memory in response to the test pattern being supplied to the redundant memory; a storage that stores a result of the comparison by the comparator; and a write controller that writes the comparison result to the storage while relating the comparison result to location information in the redundant memory where the comparison result is produced, if the comparison result by the comparator indicates a mismatch, while suppressing the comparison result from being written to the storage, if the comparison result by the comparator indicates a match.02-28-2013
20090323436Refresh signal generating circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.12-31-2009
20120218833LEAKAGE MEASUREMENT SYSTEMS - Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.08-30-2012
20080266987DRAM WITH WORD LINE COMPENSATION - In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access transistor adapted to couple a storage cell to the corresponding bit line if its gate voltage is raised; and a word line compensation circuit adapted to compensate for a capacitively-coupled voltage increase on the corresponding bit line if the access transistor's gate voltage is raised.10-30-2008
20110013465INTEGRATORS FOR DELTA-SIGMA MODULATORS - Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.01-20-2011
20090268530Trigger Circuit of a Column Redundant Circuit and Related Column Redundant Device - A trigger circuit for triggering corresponding memory cells of a column redundant circuit includes a determining circuit for generating a determining signal according to an accessed row address, and a plurality of comparing circuits jointly electrically connected to the column redundant circuit for receiving the determining signal, each of the comparing circuits selectively generating a trigger signal to the column redundant circuit according to the determining signal and an accessed column address.10-29-2009
20090059682SEMICONDUCTOR MEMORY DEVICE HAVING ANTIFUSE CIRCUITRY - A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals.03-05-2009
20120224436Setting a Reference Voltage in a Memory Controller Trained to a Memory Device - Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.09-06-2012
20120195137SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF - A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.08-02-2012
20090238010SYSTEMS AND DEVICES INCLUDING MULTI-TRANSISTOR CELLS AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices, including devices having a plurality of data cells. In some embodiments, each data cell includes a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain.09-24-2009
20090231930INTERNAL VOLTAGE GENERATING CIRCUIT HAVING SELECTIVELY DRIVEN DRIVERS IN SEMICONDUCTOR MEMORY APPARATUS - An internal voltage generating circuit of a semiconductor memory apparatus includes a first voltage generating unit to output a first output voltage to a common node, the first output voltage is generated in response to a first reference voltage, and a second voltage generating unit to output a second output voltage to the common node, the second output voltage is generated in response to a second reference voltage.09-17-2009
20090046518WRITE VOLTAGE GENERATING CIRCUIT AND METHOD - Provided are a write voltage generating circuit of a non-volatile memory cell and a write voltage generating method. The write voltage generating circuit includes a voltage generating unit providing a preliminary write voltage at a level below a defined target level, a voltage sensing unit receiving the preliminary write voltage and a reference signal, and in response to a comparison between the preliminary write voltage and the reference signal generating a start signal, and a switching unit generating and applying a write voltage derived from the preliminary write voltage at a writeable level to a non-volatile memory cell during the write operation in response to the start signal, wherein the writeable level is less than the target level.02-19-2009
20120236660TEST SYSTEM AND TEST METHOD FOR MEMORY - The test system for memory includes a controlling device, an address generating device, a data disturbing device and a comparing device. The controlling device is used for writing a first data into a memory. The address generating device is used for generating a plurality of first addresses and a plurality of second addresses corresponding to the memory. The data disturbing device is used for disturbing the first data using the first addresses to obtain a second data, and disturbing the second data using the second addresses to obtain a third data. The comparing device is used to for comparing the third data and the first data.09-20-2012
20110280086SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells, and a filling command determiner that receives a command signal and an address signal and determines whether the command signal corresponds to a filling command. Upon determining that the command signal corresponds to a filling command, the filling command determiner connects a first source voltage to a bitline and connects a second source voltage to a complementary bitline corresponding to the bitline. The bitline is connected to a selected memory cell corresponding to the address signal.11-17-2011
20090207671Memory data detecting apparatus and method for controlling reference voltage based on error in stored data - Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.08-20-2009
20110007577ACCESSING METHOD AND A MEMORY USING THEREOF - A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.01-13-2011
20100014361SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory device includes a bit line sense amplifier for performing an amplification operation using a normal driving voltage or an overdriving voltage to sense and amplify data applied to bit lines, a normal driving voltage compensator configured to drive a normal driving voltage terminal according to a voltage level of the normal driving voltage terminal and target normal driving voltage levels, and a discharge enable signal generator configured to generate a discharge enable signal by adjusting an activation period of the discharge enable signal according to the overdriving voltage.01-21-2010
20100103751CIRCUIT WITH A MEMORY ARRAY AND A REFERENCE LEVEL GENERATOR CIRCUIT - A circuit comprises an array of memory cells (04-29-2010
20090059684Method and Apparatus for Storing Data in a Write-Once Non-Volatile Memory - An apparatus and method for forming a write-once non-volatile memory cell. A memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETS has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.03-05-2009
20090310429SINGLE-ENDED DIFFERENTIAL SIGNAL AMPLIFICATION AND DATA READING - A method and system that can be used with signals read from a memory cell or other feature that varies in amplitude as a function of the data being read. The data read from the memory cell may be of the type that decreases in voltage when a ‘low’ is being read and that remains at a predetermined voltage when a ‘high’ is being read. The method and system may vary a reference to voltage used to judge whether the data is being read ‘low’ or ‘high’.12-17-2009
20110194360SEMICONDUCTOR DEVICE AND METHOD OF DETECTING ABNORMALITY ON SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of word lines; a word line driver; a first detection circuit; and a control circuit. The plurality of word lines is connected to gates of a plurality of memory cell transistors, respectively. The word line driver supplies one of a selection voltage and a non-selection voltage to each of the plurality of word lines. The first detection circuit detects a first current flowing into the word line driver through a wiring supplying the selection voltage when the selection voltage is supplied to one of the plurality of word lines through the word line driver. The control circuit detects abnormality of the plurality of word lines and the word line driver based on the first current.08-11-2011
20120033506SEMICONDUCTOR DEVICE - A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.02-09-2012
20090244990SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to the first bit line; a second memory cell connected to the second bit line; a first reference cell acting as the reference cell; a second reference cell acting as another reference cell; a potential line that supplies the reference potential to the first and second reference cells; and a dummy cell comprising a coupling capacitor that stabilizes potential of the potential line.10-01-2009
20090190411Semiconductor memory device and control method - A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is controlled to be turned on during a normal operation mode and to be turned off at least when reading data during a parallel test mode, and a comparator circuit that inputs in parallel and compares a signal of each separated part of the each data output line separated by the plurality of the gate circuit being turned off.07-30-2009
20120106267CIRCUIT FOR GENERATING REFERENCE VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - A reference voltage generating circuit in a semiconductor memory apparatus comprises a driving control signal generating unit configured to generate a driving control signal according to a temperature variation, wherein the driving control signal generating unit is enabled in response to a power-up signal, a driving unit configured to control a voltage level, which is applied to a voltage transfer node, in response to the power-up signal and the driving control signal, and a reference voltage generating unit configured to generate a reference voltage when a voltage level on the voltage transfer node is higher than a predetermined voltage level.05-03-2012
20090262586SEMICONDUCTOR MEMORY DEVICE VOLTAGE GENERATING CIRCUIT FOR AVOIDING LEAKAGE CURRENTS OF PARASITIC DIODES - A voltage generating circuit for semiconductor memory devices for use in avoiding the occurrence of leakage currents associated with parasitic diodes is presented. The circuit controls and stabilizes the generation of a fedback negative voltage to prevent parasitic diode malfunctions by a in a wordline driver. The voltage generating circuit includes a controller being fedback the negative voltage and detecting a potential difference between backbias voltage provided to a substrate of the cell and the negative voltage to generate a control signal. The voltage generating circuit also includes a voltage generator being fedback the negative voltage to detect a level thereof, and which subsequently generates and provides the negative voltage in response to the detected results of the negative voltage and the control signal.10-22-2009
20080212380Self-refresh control circuit for detecting current flowing from current generator and semiconductor device including same - A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating circuit and the second constant current generating circuit and converting the constant currents inputted from the first constant current generating circuit and the second constant current generating circuit into a test refresh cycle used for setting the refresh cycle.09-04-2008
20100061159SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each of the data input driver and the data output driver is controlled by the detection signal.03-11-2010
20090296496METHOD AND CIRCUIT FOR TESTING A MULTI-CHIP PACKAGE - A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.12-03-2009
20080239835Semiconductor memory device with high voltage generator - A semiconductor memory device which prevents a drop of the level of an external voltage due to generation of high voltage, thereby ensuring an effective data window. The semiconductor memory device includes a level detecting unit and a voltage generating unit. The level detecting unit is configured to detect a level of an internal voltage based on a reference voltage to output a level detection signal. The voltage generating unit is configured to generate the internal voltage by selectively pumping an external voltage according to the level detection signal and a refresh signal.10-02-2008
20080239834SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.10-02-2008
20100054049SEMICONDUCTOR DEVICE - The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.03-04-2010
20090168552Semiconductor memory device and method for operating the same - A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.07-02-2009
20080279018REDUNDANCY CIRCUIT CAPABLE OF REDUCING TIME FOR REDUNDANCY DISCRIMINATION - A redundancy circuit in a semiconductor memory apparatus includes a comparison signal receiving unit to receive a plurality of comparison signals and a fuse enable signal in parallel, wherein the comparison signals are generated by comparing a plurality of row address signals to a plurality of fuse address signals; and a redundancy control signal generating unit for providing a redundancy control signal by controlling an output signal path of the comparison signal receiving unit in response to a signal level of a row address enable signal. The comparison signal receiving unit receives the plurality of the comparison signals and the fuse enable signal while the row address enable signal is activated.11-13-2008
20080304335Semiconductor memory device including apparatus for detecting threshold voltage - A semiconductor device including a threshold voltage detector and a boosted voltage generating unit. The threshold voltage detector detects a threshold voltage level of cell transistors and outputs a detected threshold voltage level. The boosted voltage generating unit changes a target level of a boosted voltage in response to the detected threshold voltage level. The threshold voltage detector includes a detected current generating unit and a detected voltage generating unit. The detected current generating unit has a plurality of cell transistors in a cell array and generates a detected current whose amplitude varies corresponding to an average level of the threshold voltages of the cell transistors. The detected voltage generating unit generates the detected threshold voltage level whose level is determined corresponding to the amplitude of the detected current.12-11-2008
20120287731SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a plurality of memory blocks; and a plurality of temperature sensors disposed adjacent to the respective memory blocks and configured to output a plurality of preliminary temperature sensing signals whose voltage levels are controlled in response to temperature change. A preliminary temperature sensing signal indicating the highest temperature among the plurality of preliminary temperature sensing signals is detected and used as a temperature sensing signal.11-15-2012
20080212379Semiconductor Memory Device - When writing 16-bit write data to the memory array 09-04-2008
20120033507ON DIE THERMAL SENSOR OF SEMICONDUCTOR MEMORY DEVICE - An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage.02-09-2012
20080239833Readout of multi-level storage cells - A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state.10-02-2008
20090161448SEMICONDUCTOR MEMORY DEVICE OVERDRIVING FOR PREDETERMINED PERIOD AND BITLINE SENSE AMPLIFYING METHOD OF THE SAME - A semiconductor memory device overdriving for a predetermined period when sense amplifying a bitline. An overdriving control unit generates an overdriver enabling signal having an enabling period including a point to enable a bitline sense amplifier and a point to select a column. An overdriver provides an overdrive voltage of a level higher than that of a normal pull-up drive voltage to a pull-up node of the bitline sense amplifier in response to the overdriver enabling signal. The data line pair provides a sufficient difference in potential even for a tRCD_min condition by preventing a drop in the potential of the bitline using the overdrive operation when selecting a column.06-25-2009
20110267900SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a pad, an impedance calibration circuit configured to provide a first code value corresponding to an impedance value coupled to the pad, a PVT sensing control circuit configured to provide a second code value corresponding to a PVT variation, and an output driver configured to receive data and to pull up or pull down the pad in response to the first code value and second code value.11-03-2011
20120140577MULTI-CHIP PACKAGE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and output circuits configured to output the comparison data received in parallel from the data comparison circuit. The comparison data is outputted through a selected one of the output circuits according to an enable signal generated based on the chip ID information.06-07-2012
20080316838Redundancy memory cell access circuit and semiconductor memory device including the same - A redundancy memory cell access circuit includes a first control unit, a second control unit, and an accessing unit. The first control unit compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison. The accessing unit allows access to a redundancy memory cell corresponding to the unprogrammed signal when the first redundancy enable signal from the first control unit or a second redundancy enable signal from the second control unit is activated. Thus, the redundancy memory cell access circuit is tested simultaneously with testing of the redundancy memory cell for minimized testing and programming times.12-25-2008
20080316837SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING POTENTIAL LEVEL OF POWER SUPPLY LINE AND/OR GROUND LINE - Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.12-25-2008
20090185432SEMICONDUCTOR MEMORY DEVICE - A charge driving circuit and a discharge driving circuit occupy a relatively small area and maintain driving force in a semiconductor memory device having a plurality of banks. The semiconductor memory device includes multiple banks, a common discharge level detector configured to detect a voltage level of internal voltage terminals on the basis of a first target level in response to active signals corresponding to the respective banks, and a discharge drivers assigned to the respective banks. The discharge drivers are configured to drive the internal voltage terminals to be discharged in response to the respective active signals and respective discharge control signals outputted from the common discharge level detector.07-23-2009
20090052261DATA STROBE BUFFER AND MEMORY SYSTEM INCLUDING THE SAME - A data strobe buffer and a memory system including the data strobe buffer are provided. The data strobe buffer includes: a first input/output node; a first driver coupled to the first input/output node, the first driver configured to output a first data strobe signal to the first input/output node during a write operation; and a first receiver coupled to receive a second data strobe signal from the first input/output node and output a third data strobe signal during a read operation when the data strobe buffer is in a first or second mode, the first receiver configured to compare the second data strobe signal with a first reference voltage and output a result of the comparison as the third data strobe signal when the data strobe buffer is in the first mode, the receiver further configured to not compare the second data strobe signal with the first reference voltage when the data strobe buffer is in the second mode.02-26-2009
20110141824LEAKAGE COMPENSATED REFERENCE VOLTAGE GENERATION SYSTEM - An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.06-16-2011
20090097332Semiconductor memory device - A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a source line voltage generation unit configured to generate a source line target voltage, receive an source line output voltage from the source line driver, compare the level of the source line output voltage with the level of the source line target voltage, generate a source line voltage of which the level is adaptively varied according to a temperature, and a sense amplifier configured to sense a difference in current flowing through the bit lines in response to data read from a selected memory cell, amplify the difference to a level having high output driving capability and output the amplified current.04-16-2009
20090316497SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY - A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by comparing data read from the nonvolatile memory with the enabled data for comparison, and a path configured to output the result of comparison output from the check circuit to outside the semiconductor device, wherein no path to output the data read from the nonvolatile memory to outside the semiconductor device is in existence.12-24-2009
20120195138INTERNAL VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an internal voltage generating circuit and a memory cell. The internal voltage generating circuit is configured to compare a temperature voltage, which has a level varying with a predetermined slope according to a level change of an internal voltage, with a variable reference voltage, which has a level varying according to a temperature change, and pump the internal voltage. The memory cell includes a cell transistor having a threshold voltage controlled according to the internal voltage.08-02-2012
20120140575PROCESS TOLERANT LARGE-SWING SENSE AMPLFIER WITH LATCHING CAPABILITY - A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces design complexity, reduces power consumption, and reduces the physical footprint of the circuit. In addition, the sense amplifier provides write-through functionality through the read data bus.06-07-2012
20090116302Semiconductor memory device - A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.05-07-2009
20100182850DYNAMIC LEAKAGE CONTROL FOR MEMORY ARRAYS - A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.07-22-2010
20120195136Semiconductor device - A semiconductor device according to the present invention includes plural controlled chips CC08-02-2012
20090073780Memory device for detecting bit line leakage current and method thereof - A memory device may include a plurality of bit line pairs, at least one local data line pair, and/or a bit line leakage current measurement unit. The at least one local data line pair may be connected to the bit line pairs in response to a column selection signal. The bit line leakage current measurement unit may be configured to monitor a direct drain quiescent current (IDDQ) flowing though at least one measurement line connected to the at least one local data line pair in response to a test mode signal.03-19-2009
20090168553Semiconductor memory device and method of operating the same - Semiconductor memory device and method of operating the same includes an enable signal generator configured to generate first and second enable signals having activation timings determined in response to activation of an active command, the first enable signal being deactivated after a first time from a deactivation timing of the active command, and the second enable signal being deactivated after a second time longer than the first time from the deactivation timing of the active command. Internal voltage generators are configured to generate internal voltages. At least one of the internal voltage generators is turned on/off in response to the first enable signal, and at least one other of the internal voltage generators is turned on/off in response to the second enable signals.07-02-2009
20080310241Semiconductor memory device having memory cell and reference cell connected to same sense amplifier and method of reading data thereof - A semiconductor memory device includes a sense amplifier, first and second bit lines connected to the sense amplifier, a first reference cell connected to the first bit line, and a second reference cell connected to the second bit line. A reference potential is simultaneously written to the first and second reference cells. Further, a dummy cell may be provided to be simultaneously, with the reference cell, with the reference potential.12-18-2008
20090109763Semiconductor memory device and method of defective cell test - A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the object cell and the counter cell from the common bit line, and hence, determines whether the object cell is normal or defective, based on a voltage level of the common bit line. Thereby, the defective cell in the semiconductor memory device can be reliably detected.04-30-2009
20100302877MEMORY DEVICE HAVING REDUCED STANDBY CURRENT AND MEMORY SYSTEM INCLUDING SAME - A memory device includes a plurality of banks, a first generator generating standby current in response to a standby signal, and a switching circuit supplying the standby current to at least one of the plurality of banks in response to a plurality of active signals.12-02-2010
20090116303Semiconductor memory device - A semiconductor memory device can generate an under_drive voltage that maintains a predetermined level stably even in case of a change in the operation mode of the semiconductor memory device or the level of an external power supply voltage. The semiconductor memory device, which includes an external power supply voltage detector configured to detect a level of an external power supply voltage to generate the external voltage detection signal, an under_drive voltage detector configured to detect a voltage level of an under_drive voltage to generate the under_drive voltage detection signal, and an under_drive voltage generator configured to generate the under_drive voltage in response to the under_drive voltage detection signal with a variable driving force in response to the external voltage detection signal.05-07-2009
20100302876PACKAGE APPARATUS AND METHOD OF OPERATING THE SAME - A package apparatus includes at least one memory chip, a voltage detection circuit configured to make a determination of whether a voltage supplied to the memory chip is a specific voltage or higher, and a controller configured to control an operation of the memory chip based on a result of the determination.12-02-2010
20100322017CARD AND HOST DEVICE - A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.12-23-2010
20100322018Temperature Compensation Circuit and Method for Sensing Memory - A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.12-23-2010
20090067262VOLTAGE GENERATING UNIT OF SEMICONDUCTOR MEMORY DEVICE - A voltage generating unit of a semiconductor memory device makes it possible to reduce a peak current value when generating a high voltage. The voltage generating unit of the semiconductor memory device includes a detecting unit configured to detect a voltage level of a high voltage by comparing a reference voltage with a fed-back high voltage, an oscillating unit configured to generate a plurality of clock signals with different operation time points on the basis of an output signal of the detecting unit, and a plurality of pumping units configured to generate the high voltage according to pumping control signals based on the clock signals.03-12-2009
20110249514METHODS AND APPARATUS FOR STROBE SIGNALING AND EDGE DETECTION THEREOF - A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations.10-13-2011
20110019487APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line.01-27-2011
20110044117SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an enable signal generating unit for generating an enable signal in response to an active signal and an internal voltage driving unit driven by the active signal and the enable signal, wherein the internal voltage driving unit drives an internal voltage by comparing the internal voltage and a reference voltage and then generating first and second driving signals, and wherein the enable signal generating unit receives the second driving signal and then determines enablement of the enable signal.02-24-2011
20090034344Methods and apparatus for strobe signaling and edge detection thereof - A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations.02-05-2009
20090034343DATA RETENTION MONITOR - A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.02-05-2009
20110116327Memory Devices Having Adjustable Refresh Cycles Responsive to Temperature Changes - An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.05-19-2011
20110085388SYSTEM IN PACKAGE INTEGRATED CIRCUIT WITH SELF-GENERATING REFERENCE VOLTAGE - This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage.04-14-2011
20090323437Method and Apparatus for Data Inversion in Memory Device - The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.12-31-2009
20100135087READING OF THE STATE OF A NON-VOLATILE STORAGE ELEMENT - A method for reading of the state of a non-volatile memory element including conditioning the frequency of a first oscillator to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the first oscillator, according to the state of the storage element.06-03-2010
20110096611Semiconductor device and semiconductor system having the same - A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.04-28-2011
20100097867INTERNAL SOURCE VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a driving current to flow from a third node to a fourth node. An internal voltage driver transfers an external source voltage to an output node responsive to the comparison voltage. A driving current generator increases the driving current flowing from the third node to the fourth node responsive to the voltage of the first node which rises when the internal source voltage abruptly drops. The internal source voltage generating circuit is insensitive to variation of an external source voltage, exhibits improved response time when an internal source voltage abruptly drops, and stably generates an internal source voltage.04-22-2010
20100097866SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array provided with a main memory cell array including a plurality of memory cells, and a dummy column including a plurality of dummy memory cells, a dummy readout current control section configured to control a current value of a dummy readout current of the dummy memory cell in such a manner that the current value becomes between the current values of the readout currents in first and second states of the memory cell, and a sense section provided with a sense amplifier configured to receive a readout current in one of the first and second states, or dummy readout current as an input, comparing these currents with each other, and outputting the currents.04-22-2010
20080247243Semiconductor memory device including post package repair control circuit and post package repair method - Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.10-09-2008
20090190412NONVOLATILE MEMORY DEVICE WITH LOAD-FREE WIRED-OR STRUCTURE AND AN ASSOCIATED DRIVING METHOD - A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to pull the internal output line to an output drive voltage in response to a bitline voltage on one of the bitlines coupled to the page buffer.07-30-2009
20080253201APPARATUS AND METHOD FOR CALIBRATING ON-DIE TERMINATION IN SEMICONDUCTOR MEMORY DEVICE - An on-die termination circuit in a semiconductor memory apparatus can comprise a comparing block for comparing a reference voltage with a code voltage corresponding to a code and outputting a comparison signal, a counting block for changing the code based on the comparison signal, and controlling block for controlling the counting block based on a match result of previous and current values of the comparison signal.10-16-2008
20110134708METHOD AND SYSTEM FOR CONTROLLING REFRESH TO AVOID MEMORY CELL DATA LOSSES - A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.06-09-2011
20110134709SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY - A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by comparing data read from the nonvolatile memory with the enabled data for comparison, and a path configured to output the result of comparison output from the check circuit to outside the semiconductor device, wherein no path to output the data read from the nonvolatile memory to outside the semiconductor device is in existence.06-09-2011
20100214853NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage distribution, to compare the measured threshold voltage distribution with a reference threshold voltage distribution, and to determine a read voltage having a least amount of errors upon the read operation being performed.08-26-2010
20100195414LEVEL DETECTOR, INTERNAL VOLTAGE GENERATOR INCLUDING LEVEL DETECTOR, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING INTERNAL VOLTAGE GENERATOR - A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.08-05-2010
20090175094CURRENT SENSING METHOD AND APPARATUS FOR A MEMORY ARRAY - A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.07-09-2009
20090175093APPARATUS FOR CONTROLLING COLUMN SELECTING SIGNAL FOR SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - An apparatus for controlling a column selecting signal of semiconductor memory apparatus comprising a column decoder that outputs a first column selecting signal, a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of the first column selecting signal, and an output control unit that outputs the first column selecting signal or the second column selecting signal in response to the input of a predetermined voltage detecting signal.07-09-2009
20110216607METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.09-08-2011
20100054048METHOD AND APPARATUS FOR PROGRAMMING AUTO SHUT-OFF - A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed.03-04-2010
20100008159Differential Sense Amplifier - A differential sense amplifier can perform data sensing using a very low supply voltage.01-14-2010
20120307571Sense Amplifier Circuit - A sense amplifier circuit comprises a first inverter configured to provide a first trigger point during a pre-charge stage of a READ operation of a memory cell and provide a second trigger point either lower or higher than the first trigger point during a sense stage of the READ operation of the memory cell. The sense amplifier circuit further comprises a plurality of inverters coupled between an output of the first inverter and an output of the sense amplifier and a pre-charge device. The sense amplifier circuit having a dynamic trigger point can deliver faster data access time as well as less power consumption.12-06-2012
20120307572SEMICONDUCTOR DEVICE - The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.12-06-2012
20110305094NON-VOLATILE MEMORY DEVICE WITH RECONNECTION CIRCUIT - An electrically programmable non-volatile memory device includes a plurality of memory cells, a plurality of lines for selectively biasing the memory cells, reconnection circuitry for reconnecting a pair of selected lines having different voltages, and a controller for controlling the memory device. The reconnection means includes a discharge circuit for discharging one of the selected lines being at the higher voltage in absolute value, an equalization circuit for equalizing the selected lines, a comparator circuit for measuring an indication of a voltage difference between the selected lines, and an evaluation circuit responsive to an enabling signal from the controller for activating the discharge circuit until an absolute value of the voltage difference exceeds a threshold value and for disabling the discharge circuit and enabling the equalization circuit when the absolute value of the voltage difference reaches the threshold value.12-15-2011
20110317498NON-VOLATILE STORAGE DEVICE - There is provided a non-volatile storage device including: a memory array section arrayed with plural non-volatile memory cells for electronically writable data storage; plural bit lines that are connected to respective memory cells and have voltage levels that change according to the data stored in the memory cells; a supply section that supplies a voltage of a reference level to act as a comparator reference when determining data stored in the memory cells; a comparator section that compares the voltage level of the bit line connected to the memory cell subject to reading against the reference level supplied by the supply section; and a charging section that, in preparation for comparison by the comparator section, charges the bit line connected to the memory cell subject to reading to the voltage of the reference level supplied by the supply section.12-29-2011
20100309734METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVICE FOR MONITORING MEMORY CIRCUITS AND CORRESPONDING INTEGRATED CIRCUIT - An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.12-09-2010
20120044774SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.02-23-2012
20120057415NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer groups and the respective I/O lines in response to a normal control clock signal.03-08-2012
20120002488Current detection method - A current detection method for detecting whether data are stored in a memory unit includes the steps of: (A) respectively inputting two currents into a detection current input end and a reference current end; (B) reading out a current of the detection current input end by a first switching element and a current of the reference current end by a second switching element; (C) respectively converting the current read out by the first switching element and the current read out by the second switching element into two voltages, and respectively transmitting the two voltages to two input ends of a comparator; and (D) outputting a voltage signal for determining whether the data are stored in the memory unit by the comparator. The current detection method of the present invention has the fast detection speed, low power consumption and simple operation.01-05-2012
20120008428DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A data output circuit for a semiconductor memory device includes a first driver configured to output a first drive control signal in response to a data signal, a drive controller configured to compare a voltage level of the first drive control signal with a reference voltage and output a second drive control signal, and a second driver configured to drive an output terminal in response to the first drive control signal and additionally drive the output terminal in response to the second drive control signal.01-12-2012
20120014191SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device of an embodiment includes memory cells 01-19-2012
20120300560SEMICONDUCTOR MEMORY DEVICES INCLUDING PRECHARGE USING ISOLATED VOLTAGES - A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells storing data; a sense amplifier coupled to the memory cell array and configured to sense voltage differences between the complementary pairs of bit lines and amplify the voltage differences; and at least one voltage driver configured to provide either a predetermined voltage or a first power supply voltage to the memory cell array to increase a sensing margin of the semiconductor memory device. The semiconductor memory device increases respective potential differences between complementary pairs of bit lines using a voltage isolated in the memory cell array.11-29-2012
20120026806DATA INPUT CIRCUIT - A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.02-02-2012
20120063243APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE - A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.03-15-2012
20120026805SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION - An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level.02-02-2012
20120063244VOLTAGE GENERATOR, NONVOLATILE MEMORY DEVICE COMPRISING VOLTAGE GENERATOR, AND METHOD OF OPERATING VOLTAGE GENERATOR - A voltage generator comprises a first booster that generates a first high voltage, and a second booster that generates a second high voltage by boosting an external voltage. The first booster comprises a comparator that controls a boosting operation with reference to the fed back first high voltage and uses the second high voltage as a drive voltage.03-15-2012
20130010547SEMICONDUCTOR DEVICE AND METHODS OF OPERATING THE SAME - A method of operating a semiconductor device includes programming selected memory cells by supplying a selected word line with a program voltage which increases and supplying the remaining unselected word lines with a first pass voltage which is substantially constant; and programming the selected memory cells while supplying first unselected word lines adjacent to the selected word line with a second pass voltage increasing in proportion to the program voltage, when a difference between the program voltage and the first pass voltage reaches a critical voltage difference.01-10-2013
20130010546Apparatus and method for receiving a differential data strobe signal - A differential data strobe receiver is provided which is configured to receive a differential data strobe signal at a first strobe input and a second strobe input, wherein transitions of the differential data strobe signal indicate sample points for an associated data signal. The differential data receiver is configured to identify the transitions of the differential strobe signal by differentially comparing values of the differential strobe signal received at the first strobe input and the second strobe input. The differential data strobe receiver comprises strobe gating circuitry configured to generate a strobe gating signal, wherein the associated data signal can only be sampled in dependence on the differential data strobe signal when the strobe gating signal is asserted and strobe input termination circuitry configured selectively to provide a first termination connection for the first strobe input and a second termination connection for the second strobe input. The differential data strobe receiver is configured, prior to receiving the differential data strobe signal in association with the associated data signal, to participate in an initial gate training process to determine a gating delay used to phase align the strobe gating signal with respect to the differential data strobe signal and the strobe input termination circuitry is configured to provide an asymmetric configuration of the first termination connection and the second termination connection during the initial gate training process.01-10-2013
20120120738SEMICONDUCTOR DEVICE - The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.05-17-2012
20120120739SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.05-17-2012
20120120737REPAIR CIRCUIT AND CONTROL METHOD THEREOF - A semiconductor memory apparatus including a repair circuit may comprise: a fuse set block configured to store a repair address, compare the repair address with an input address, and generate a primary repair signal; and a redundancy control block configured to receive the primary repair signal, determine whether a repair cell in a repair memory designated by the primary repair signal is failed or not, and generate a secondary repair signal which repair the failed repair cell with another repair cell in the repair memory.05-17-2012
20120314512CACHE MEMORY AND METHOD FOR DRIVING THE SAME - A cache memory which can operate with less power consumption and has an improved cache hit rate and a method for driving the cache memory are provided. Two data storage portions (a first storage portion and a second storage portion) and one data transfer portion are provided in one memory cell in a memory set included in a cache memory, and arranged so that data can be transferred between the two storage portions via the data transfer portion. One of the two data storage portions can store data input from the outside and output data to a comparison circuit paired with the memory set.12-13-2012
20120163102MULTI-PORT MEMORY ARRAY - A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.06-28-2012
20120218834SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal.08-30-2012
20100067312SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a memory core and a fail detection circuit. The memory core includes a memory cell array having a plurality of memory cells. The fail detection circuit compares read data with test data to generate a comparison signal representing whether each of the memory cells is failed or not, and accumulates and stores fail information of the memory cells corresponding to a plurality of addresses to output accumulated fail information. The read data are read out from the memory cells in which the test data are written.03-18-2010
20120134218CHARGE PUMP CONTROL SCHEME USING FREQUENCY MODULATION FOR MEMORY WORD LINE - A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.05-31-2012
20120230127Providing Row Redundancy to Solve Vertical Twin Bit Failures - A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.09-13-2012
20090059683Semiconductor memory device - A semiconductor memory device that includes a first high voltage oscillator configured to generate a first control pulse in response to a first enable signal, a level shifter configured to generate a high voltage control pulse by boosting a level of the first control pulse using a source high voltage, and a first high voltage generator configured to generate a high voltage by boosting an external power supply voltage in response to the high voltage control pulse.03-05-2009
20120170386Hybrid Read Scheme for Multi-Level Data - Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal S07-05-2012
20120176847METHODS AND APPARATUS FOR VOLTAGE SENSING AND REPORTING - Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.07-12-2012
20120314513SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.12-13-2012
20120257462REPAIR METHOD AND INTEGRATED CIRCUIT USING THE SAME - An integrated circuit includes: a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and a fail address storage unit configured to store the fail address.10-11-2012
20120188830SEMICONDUCTOR MEMORY DEVICE CORRECTING FUSE DATA AND METHOD OF OPERATING THE SAME - A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.07-26-2012
20120081975SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When a leakage type determining circuit determines that leakage current components of a gate leakage and a substrate leakage are larger in a resume standby mode, a VDDR regulator generates a power supply voltage VDDR at a first voltage level lower than a power supply voltage VDD, and supplies the voltage as a power supply voltage VDDR04-05-2012
20120320688SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.12-20-2012
20120327724SEMICONDUCTOR MEMORY WITH REDUNDANT WORD LINES, SYSTEM, AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY - A semiconductor memory has a memory cell array having a plurality of real word lines, a plurality of redundant word lines, a plurality of bit lines crossing with the real and redundant word lines, a plurality of memory cells provided at crossing section of the real and redundant word lines and the bit lines, and a row selection circuit for selecting the real word line or the redundant word line in accordance with a row address being supplied. The row selection circuit selects the real word line or the redundant word line at an ordinary operation, and multi-selects the redundant word lines at a first test mode.12-27-2012
20120269010MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.10-25-2012
20110235440Nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes: a sense amplifier; bit lines coupled to the sense amplifier; memory cell transistors and dummy cell transistors coupled in parallel with the bit lines; and a current generating circuit that supplies a test current to current nodes. Either of the source and the drain of each of the dummy cell transistors is coupled to a bit line and the other is coupled to a current node. In a read operation test, the current generating circuit is activated and then the dummy cell transistors are turned on. The sense amplifier compares the test current passed through a bit line with a reference current and outputs output data corresponding to the result of the comparison.09-29-2011
20120140576MEMORY DEVICE, TEST OPERATION METHOD THEREOF, AND SYSTEM INCLUDING THE SAME - A test operation method of a memory device is provided. The test operation method includes a reference current generator generating a reference current and providing a reference voltage generated based on the reference current to one of input terminals of a sense amplifier; providing a read voltage generated based on a read current of a memory cell to another one of the input terminals of the sense amplifier; and the sense amplifier comparing the reference voltage with the read voltage.06-07-2012
20120140579MULTI-CHIP PACKAGE AND OPERATING METHOD THEREOF - A multi-chip package includes a voltage generating circuit configured to generate a power source voltage and a plurality of memory chips coupled to the voltage generating circuit to each receive the power source voltage, wherein the memory chips are each configured to postpone an operation if the power source voltage is lower than a target voltage and perform the operation when the power source voltage reaches the target voltage.06-07-2012
20120140578SEMICONDUCTOR DEVICE HAVING PLURAL INTERNAL VOLTAGE GENERATING CIRCUITS AND METHOD OF CONTROLLING THE SAME - Such a device is disclosed that includes a terminal, a first voltage generator generating, when activated, a voltage at the terminal and stopping, when deactivated, generating the voltage, and a second voltage generator generating, when activated, the voltage at the terminal and stopping, when deactivated, generating the voltage. The first voltage generator being configured to be activated in response to a first control signal taking an active level and deactivated in response to the first control signal taking an inactive level, and the second voltage generator being configured to be activated in response to each of the first control signal and a second control signal taking an active level and deactivated in response to at least one of the first and second control signal taking an inactive level.06-07-2012
20130016574SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REFRESH CHARACTERISTICS - A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.01-17-2013
20110141825SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND ELECTRONIC EQUIPMENT - A semiconductor integrated circuit system comprises a semiconductor memory device including a memory cell array having a plurality of memory cells; a monitor circuit for monitoring characteristics of the memory cells; and a voltage output circuit connected to the semiconductor memory device to supply a power supply voltage to the semiconductor memory device; the voltage output circuit being configured to change an output voltage according to an output of the monitor circuit.06-16-2011
20130021855SEMICONDUCTOR MEMORY DEVICE - The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.01-24-2013
20130021854ANTI-FUSE CIRCUIT - An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.01-24-2013
20120243343METHODS FOR SENSING MEMORY ELEMENTS IN SEMICONDUCTOR DEVICES - A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combine (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.09-27-2012
20080253200Reading of the State of a Non-Volatile Storage Element - A method for reading of the state of a non-volatile memory element, comprising adjusting including conditioning the frequency of a first oscillatory to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the first oscillator, according to the state of the storage element.10-16-2008
20100091584MEMORY DEVICE AND METHODS THEREOF - A memory device is disclosed that includes multiple bit cells, whereby each bit cell is capable of being programmed to more than two states. A value stored at the memory device is determined by comparing the information stored at three or more of the bit cells. In an embodiment, the bit cell includes a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (FET) device, and the information stored at the bit cell can be represented by a corresponding level of charge stored in the body of the device.04-15-2010
20080225608SEMICONDUCTOR MEMORY DEVICE AND CONTROL SIGNAL GENERATING METHOD THEREOF - A semiconductor memory device and a control signal generating method thereof. The semiconductor memory device may include a voltage range detector configured to generate a voltage detecting signal corresponding to a range of a level of an external power voltage. A control signal generating portion may be used to generate a control signal corresponding to the range of the level of the external power voltage responsive to the voltage detecting signal. As a result, the semiconductor memory device can perform an operation for satisfying an access time characteristic according to a specification responsive to the control signal.09-18-2008
20080225607DIVISION-BASED SENSING AND PARTITIONING OF ELECTRONIC MEMORY - Providing distinction between overlapping threshold levels of one or more multi-cell memory devices is described herein. By way of example, a system can include a sensing component that can measure a level associated with a first memory cell. The system can also include a comparison component that can compare the measured level associated with the first memory cell level to non-overlapping threshold levels, wherein such measurement can be used to determine a unique bit level associated with a second memory cell. By way of further example, methodologies are described for accurately measuring a bit level of a first cell of a dual-cell memory device, by comparing a second cell value to non-overlapping threshold values, as measured with respect to the second reference point.09-18-2008
20130141991Boosting Memory Module Performance - Power supplied to a memory module is provided. A first voltage is supplied to a first power distribution pathway, the first voltage being from a voltage supplied to a printed circuit board on which the memory module resides. A second voltage is generated, the second voltage being generated by a voltage regulator. The second voltage is supplied to a second power distribution pathway.06-06-2013
20080219060DEVICE AND METHOD FOR INTERNAL VOLTAGE MONITORING - A memory device and method for internal voltage monitoring is disclosed. One embodiment includes at least one error register configured to store a particular error flag during the stress test. This error flag is generated if the supply voltage applied at the memory device during the test method in the memory device or an internally generated voltage of the memory device lies below a predetermined threshold value.09-11-2008
20120250426Apparatus and Method to Adjust Clock Duty Cycle of Memory - An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.10-04-2012
20130170305PARALLEL TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.07-04-2013
20130094304NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes: a driving voltage generation unit configured to generate a driving voltage of a core bias line included in a memory cell current path; a comparison unit configured to compare a voltage level of the core bias line with a predetermined limit level in response to a virtual negative read signal; and a compensation driving unit configured to compensation-drive the core bias line in response to an output signal of the comparison unit.04-18-2013
20130114353MEMORY METHODS AND SYSTEMS WITH ADIABATIC SWITCHING - A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates.05-09-2013
20110273937SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.11-10-2011
20110228616Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency - A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM 09-22-2011
20130135944DUAL POWER SUPPLY MEMORY ARRAY HAVING A CONTROL CIRCUIT THAT DYANMICALLY SELECTS A LOWER OF TWO SUPPLY VOLTAGES FOR BITLINE PRE-CHARGE OPERATIONS AND AN ASSOCIATED METHOD - Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator compares the first supply voltage on a first power supply rail to a second supply voltage on a second power supply rail and outputs a voltage difference signal. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, than a control circuit ensures that the complementary bitlines connected to a memory cell are pre-charged to the first supply voltage. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage. Also disclosed is an associated method.05-30-2013
20120275241SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR DRIVING THE SAME - A method for driving a semiconductor memory device includes controlling a plurality of erase voltages for a plurality of memory blocks, respectively, comparing the plurality of controlled erase voltages, and determining whether or not to enable the plurality of memory blocks for a subsequent write operation in response to a result of the comparison.11-01-2012
20100315887SEMICONDUCTOR MEMORY DEVICE HAVING PHYSICALLY SHARED DATA PATH AND TEST DEVICE FOR THE SAME - A semiconductor memory device includes a plurality of chips, a data path that is physically shared by the plurality of chips, a data input/output pad, and a data output driver. The data output driver is configured to receive merged data that includes data merged from a set of chip data read from the plurality of chips, compare the merged data to first reference data in a test mode, compare the merged data to second reference data in a test mode, and based on the comparisons, apply an output voltage at a data input/output pad.12-16-2010
20130182513MEMORY SYSTEM CAPABLE OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE - Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.07-18-2013
20130155786DATA SENSING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A data sensing circuit includes: a current source configured to supply a reference current to an output line; a switching precharging unit configured to couple an input line with the output line during a precharge operation of the input line; and a current sinking unit configured to sink a current from the output line in response to a voltage level of the input line.06-20-2013
20110286287SEMICONDUCTOR MEMORY DEVICE WITH OPTIMUM REFRESH CYCLE ACCORDING TO TEMPERATURE VARIATION - Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage.11-24-2011
20110310678Sensing Circuit for Memory Cell Supplied with Low Power - An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate connected to a memory cell for receiving an output current of the memory cell. The N-type MOSFET has a drain connected to a drain of the first P-type MOSFET, and has a source connected to ground. The inverter has an input terminal connected to the drain of the first N-type MOSFET. The voltage at an output terminal of the inverter is used for indicating the program state or the erase state of the memory cell. The reference transistor has a gate connected to a reference signal, and has a drain connected to the gate of the P-type MOSFET.12-22-2011
20130188429TEMPERATURE-DEPENDENT SELF-REFRESH TIMING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.07-25-2013
20130188430SYSTEMS AND METHODS FOR VOLTAGE SENSING AND REPORTING - Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.07-25-2013
20120020170REFERENCE VOLTAGE REGULATOR FOR EDRAM WITH VSS-SENSING - In a method of operating a reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level, an oscillator sends requests for sampling and correction to a control block between accesses of the eDRAM. The control block sends a pulse defining a time interval during which sampling and correction occurs to a pulse generator. A reference generator provides the reference level to a comparator. The comparator compares the reference level with a sampling of a reference voltage to decide if the reference voltage requires correction. The comparator sends a correction request to a pulse generator if the reference voltage requires correction. The pulse generator generates a correction pulse for a driver according to the correction request from the comparator. The driver adjusts the reference voltage during the correction pulse.01-26-2012
20130194878SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR MEMORY CIRCUIT - The semiconductor device including a memory circuit is configured to include a mode switching circuit additionally provided with a data comparison circuit which detects that a serial signal supplied to an input terminal for communication and a serial signal supplied to an input terminal used for a purpose other than communication are reversed from each other, a decoder circuit which detects that a serial signal carries predetermined data and which outputs a detection signal, a control signal generating circuit which generates a control signal, and a circuit which outputs a signal for switching to a test mode on the basis of the signals.08-01-2013

Patent applications in class Including signal comparison