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Having particular data buffer or latch

Subclass of:

365 - Static information storage and retrieval

365189011 - READ/WRITE CIRCUIT

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DocumentTitleDate
20080279015REGISTER FILE - A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.11-13-2008
20130044551SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell connected to a read bit line and a pair of write bit lines, and a data amplifier connected to the read bit line. A precharge potential resetting circuit uses a function of generating precharge potentials to the pair of write bit lines based on data of the memory cell amplified by the data amplifier to set the precharge potentials of the non-selected pair of write bit lines to have a potential relationship corresponding to the data stored by the memory cell. As a result, data destruction of the non-selected memory cell during write operation is reduced or prevented, and the speed of operation is increased and the area is reduced.02-21-2013
20090196107SEMICONDUCTOR DEVICE AND ITS MEMORY SYSTEM - A semiconductor device selects one mask pattern among from a plurality of the mask patterns, which are stored in a mask resister circuit for mask controlling of a bit width (vertical axis), by a mask pattern selection signal, and controls input and output of data based on the selected mask pattern and a mask control signal of a bit string (horizontal axis), when inputting and outputting data having the consecutive bit string (horizontal axis) and a plurality of the bit widths (vertical axis). A read data converter circuit and a write data converter circuit select to mask or unmask each data signal during burst reading or writing, and masks the data signal. The masked data signal is not written in a memory cell by inactivating a write data buffer circuit during writing, and is not read out by inactivating a data driver circuit connecting with an external input and output terminal.08-06-2009
20110128795SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - A sense amplifier prevents a reduction in sensing margin occurring when data forms an island pattern. The sense amplifier includes a first inverter having an input terminal connected to a bit line and an output terminal connected to a bar bit line, and a second inverter having an input terminal connected to the bar bit line and an output terminal connected to the bit line. The first and second inverters are configured to receive a pull-up voltage through different pull-up voltage lines, respectively.06-02-2011
20080259696DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES - An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.10-23-2008
20080259694Semiconductor Device - A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 10-23-2008
20090122619Enhanced DRAM with Embedded Registers - An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.05-14-2009
20100118619BUFFER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response to a level of a reference voltage; and a buffering unit configured to generate an output signal by buffering an input signal depending on the reference voltage and control a transition section of the output signal depending on a level of the compensation voltage.05-13-2010
20100074031TEST MODE SIGNAL GENERATOR FOR SEMICONDUCTOR MEMORY AND METHOD OF GENERATING TEST MODE SIGNALS - A test mode signal generator for a semiconductor memory device includes a test mode entry control unit that receives test entry mode setting addresses inputted in response to a test mode register set signal. The test mode entry control unit outputs a plurality of test entry mode signals and a test mode set signal according to the test entry mode setting addresses. A latch unit latches test address decoding signals in response to the test mode set signal, and outputs test mode signals by allowing the latched test address decoding signals to be controlled by the respective test entry mode signals. A test mode signal is generated for each test entry mode, so that the number of test modes is increased without increasing the number of addresses for supporting test modes.03-25-2010
20130033943DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A data input/output circuit includes: an amplification unit configured to generate a data signal by amplifying data of a first input/output line coupled to a bank during a read operation, and generate a driving signal by amplifying data of a second input/output line coupled to a data input/output pad during a write operation; a read driving unit configured to drive the second input/output line in response to the data signal during the read operation; and a write driving unit configured to drive the first input/output line in response to the driving signal during the write operation.02-07-2013
20130033942SYSTEM-IN PACKAGE INCLUDING SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DETERMINING INPUT/OUTPUT PINS OF SYSTEM-IN PACKAGE - A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.02-07-2013
20100103746MULTI-PHASE DUTY-CYCLE CORRECTED CLOCK SIGNAL GENERATOR AND MEMORY HAVING SAME - Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals.04-29-2010
20130083609SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER CIRCUIT IN WHICH IMPEDANCE THEREOF CAN BE CONTROLLED - Disclosed herein is a device that includes first and second buffer circuits electrically connected to a terminal and an output control circuit activating the first buffer circuit and deactivating the second buffer circuit in a first state and activating one of the first and second buffer circuits and deactivating the other of the first and second buffer circuits based on input data in a second state. The output control circuit is brought into one of the first and second states.04-04-2013
20090161444PAGE BUFFER AND PROGRAMMING METHOD OF A NON-VOLATILE MEMORY DEVICE - A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node.06-25-2009
20090154257MEMORY SYSTEM AND CONTROL METHOD FOR MEMORY - The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.06-18-2009
20130208547APPARATUSES AND METHODS FOR LINE CHARGE SHARING - Apparatuses and methods for charge sharing between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit, The charge sharing circuit may be coupled to the first line and the second line and configured to receive a first data signal and a second data signal. The charge sharing circuit may be further configured to cause charge to be shared between the first line and the second line responsive, at least in part, to the first data signal and the second data signal having different logic levels.08-15-2013
20120182812SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse, and a storage unit for storing the decoded address signal, the decoded command signal and a data signal in response to the suspend pulse and providing the decoded address signal, the decoded command signal and the decoded data signal as a stored address signal, a stored command signal and a stored data signal, respectively, in response to the resume pulse.07-19-2012
20130070539DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION - A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.03-21-2013
20130070535NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a control logic configured to generate an internal command in response to an internal clock, a finite state machine configured to generate a plurality of current state signals in a program pulse and verify pulse setup operation for a program operation and a program verify operation in response to the internal command, after a program operation using a program pulse and a program verify operation using a program verify pulse are completed, and a glue logic configured to generate check control signals for checking a plurality of page buffers of the page buffer unit in response to the plurality of current state signals in the setup operation.03-21-2013
20130070537SEMICONDUCTOR DEVICE OPERATES ON EXTERNAL AND INTERNAL POWER SUPPLY VOLTAGES AND DATA PROCESSING SYSTEM INCLUDING THE SAME - The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance adjustment signal and a data signal and making the output buffer drive the output terminal to a first logic level designated by the data signal with impedance designated by the impedance adjustment signal, and a level shifter coupled between the output buffer and the first control circuit. The second power supply voltage is smaller in level than the first power supply voltage. The level shifter includes a first circuit portion operating on the second power supply voltage and a second circuit portion operating on the first power supply voltage.03-21-2013
20130070536SEMICONDUCTOR DEVICE LATCHING DATA SIGNAL IN RESPONSE TO STROBE SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal.03-21-2013
20130070538SEMICONDUCTOR MEMORY DEVICE AND DATA READING METHOD - A semiconductor memory device includes two memory cell arrays, a sense amplifier shared by the two memory cell arrays; and a control circuit configured to control data readout from the two memory cell arrays. Each memory cell array includes word lines, two or more bit lines, a dummy word line, memory cells provided at intersections of the bit lines and the word lines, and dummy cells provided at intersections of selected bit lines and the dummy word line. When the control circuit reads data from one memory cell array, the control circuit activates the dummy word line included in the other memory cell array and generates, with the dummy cell included in the other memory cell array, a reference level of the sense amplifier.03-21-2013
20110002176SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a repair node; a fuse, one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; a latch unit configured to latch a signal at the repair node; and a switch unit coupled between the latch unit and the repair node and configured to selectively transfer the signal from the repair node to the latch unit.01-06-2011
20130088926TRACKING MECHANISMS - A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.04-11-2013
20130051157SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD THEREOF - A semiconductor memory device includes a memory core configured to sequentially activate first and second banks in response to first and second bank active signals which are sequentially enabled in response to first and second enable signals when a self-refresh operation is to be performed, select a word line by row addresses, and perform a refresh operation for memory cells which are connected with the word line; and an address counter configured to perform a counting operation for the row addresses in response to a counter signal, and interrupt the counting operation for the row addresses in a case where both the first and second banks are not activated when the self-refresh operation is ended.02-28-2013
20130088930NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address.04-11-2013
20130088929LOW POWER MEMORY CONTROLLERS - A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.04-11-2013
20130088928MEMORY SYSTEM COMPRISING NON-VOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a first memory region and a second memory region. The nonvolatile memory device is programmed by storing program data in the first memory region, performing coarse programming and fine programming to store the program data in the second memory region, and in response to a read request, accessing the program data from the first memory region or the second memory region according to a fine program flag indicating whether the coarse programming has been completed.04-11-2013
20130088927SYSTEM AND METHOD FOR GENERATING A CLOCK - A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro.04-11-2013
20090303802SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM HAVING TERMINATION RESISTOR UNITS - A semiconductor memory module includes a memory module board having at least one semiconductor memory device. The semiconductor memory device includes a data input buffer that receives data and a first reference voltage via first and second input terminals, a command/address buffer that receives a command/address signal and a second reference voltage via first and second input terminals, and a first termination resistor unit connected to the first input terminal of the data input buffer. The semiconductor memory module further includes a second termination resistor unit located on the memory module board and connected to an internal command/address bus. The first termination resistor unit includes a first resistor connected between a first voltage source and the first input terminal of the data input buffer, and the second termination resistor unit includes a second resistor connected between a second voltage source and the first input terminal of the command/address input buffer.12-10-2009
20120218832DATA TRANSMISSION CIRCUIT - A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to transmit the driving voltage when any one of a write enable signal and a read enable signal is enabled; and a data transmission unit configured to be driven by receiving the driving voltage, transmit a signal of a DQ pad as data in response to the write enable signal, and transmit the data to the DQ pad in response to the read enable signal.08-30-2012
20120218831INTEGRATED CIRCUIT FOR STORING INFORMATION - An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.08-30-2012
20090091987Multiple memory standard physical layer macro function - A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.04-09-2009
20090091986CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR A LINEAR OUTPUT DRIVER - Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages. The driver circuit includes a pull-up circuit and a pull-down circuit, each having two or more current paths that either source currents to or sink currents from the output node. The addition of the third current path provides additional current such that the sum of the total currents have a magnitude that changes linearly as the output voltage at the output node is being driven.04-09-2009
20130070534PROGRAMMABLE CURRENT-LIMITED VOLTAGE BUFFER, INTEGRATED-CIRCUIT DEVICE AND METHOD FOR CURRENT-LIMITING A MEMORY ELEMENT - A programmable current-limited voltage buffer 03-21-2013
20130058172Code-Based Differential Charging of Bit Lines of a Sense Amplifier - A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.03-07-2013
20120307570METHOD FOR RELAYING DATA TO MEMORY ARRAY - A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.12-06-2012
20120188829CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING DATA SIGNALS - Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.07-26-2012
20120188827BURST ORDER CONTROL CIRCUIT - A burst order control circuit includes a signal transmitting unit transmitting a second address as first and second signals in response to a mode signal and a first address, a signal delay unit delaying a read command, the first signal, and the second signal to generate a delayed read command, a first delayed signal, and a second delayed signal, a signal generating unit configured to generate a burst signal in response to the first address and generate first and second transmission signals in response to the delayed read command and the first and second delayed signals, and an output unit sorting and outputting a plurality of data in response to the burst signal, the first transmission signal, and the second transmission signal.07-26-2012
20110013464Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device - The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line.01-20-2011
20090285033SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is constituted of a plurality of fuses (or anti-fuses) used for internal voltage adjustment or timing adjustment after manufacturing, a selector for sequentially selecting the fuses, and a single-direction latch circuit for latching a fuse breakdown determination result which is produced by determining whether or not each fuse selected by the selector is broken down and which is varied in a single direction from the low level to the high level or in a single direction from the high level to the low level. The semiconductor memory device allows the fuse breakdown determination to progress with a high reliability by use of a relatively small chip area and to cope with a failure in which one or more fuses are accidentally short-circuited to an unwanted potential.11-19-2009
20090268528Semiconductor memory device and access method thereof - Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.10-29-2009
20100002525Array Data Input Latch and Data Clocking Scheme - A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.01-07-2010
20130064019DATA STORAGE CIRCUIT THAT RETAINS STATE DURING PRECHARGE - A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.03-14-2013
20130064020SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.03-14-2013
20090010077SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL - A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.01-08-2009
20100085815Command Generation circuit and semiconductor memory device - There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.04-08-2010
20130163347SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a D flip-flop may be saved.06-27-2013
20080304334SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING ON-DIE TERMINATION CIRCUIT AND ON-DIE TERMINATION METHOD - A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.12-11-2008
20130163348SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device and a method for operating the same are provided relating to a nonvolatile memory device for sensing data using resistance change. The semiconductor device comprises a verification read control unit configured to sequentially output verification read data received from a sense amplifier into a global input/output line in response to a test signal, and a read data latch unit configured to store sequentially the verification read data received from the global input output line in response to a latch enable signal in activation of the test signal.06-27-2013
20090073779Semiconductor storage device including counter noise generator and method of controlling the same - A semiconductor storage device according to one aspect of the present invention includes a reference voltage source connected to a capacitor of a cell included in a memory, a buffer circuit holding data to be written in the cell, and a counter noise generator outputting a counter noise current canceling a noise current generated by rewriting the data in the cell to the reference voltage source according to the data held in the buffer circuit.03-19-2009
20120057414DATA INPUT CIRCUIT OF NONVOLATILE MEMORY DEVICE - The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch normal data or redundancy data received through the internal global data line in response to a plurality of respective latch signals, and an output multiplexer configured to sequentially output the latched data in response to a plurality of selection signals.03-08-2012
20100302873MODE-REGISTER READING CONTROLLER AND SEMICONDUCTOR MEMORY DEVICE - A mode-register reading controller includes a switching signal generator, first and second transmitters, and a control signal generator. The switching signal generator generates a switching signal that is activated when the reset command is input during a mode-register reading operation. The first transmitter buffers and transfers the mode-register read signal in response to the switching signal. The second transmitter, in response to the switching signal, delays and transfers the enable signal at a predetermined delay time. The control signal generator receives a signal from one of the first and second transmitters and generates a first control signal and a second control signal for transferring the data into a data output buffer from the input/output line.12-02-2010
20090207670DATA OUTPUT BUFFER WHOSE MODE SWITCHES ACCORDING TO OPERATION FREQUENCY AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.08-20-2009
20100254199SRAM CELL WITH READ BUFFER CONTROLLED FOR LOW LEAKAGE CURRENT - An integrated circuit and methods of operating an integrated circuit and reducing a leakage current of an integrated circuit are provided. A functional memory of the integrated circuit includes row and column periphery units and an array of memory cells having a core storage element and a read buffer. Also included are read word lines that provide row access, and read bit lines that provide column access to the core storage element and the read buffer of a memory cell. The functional memory further includes a read buffer supply line that is connected to the read buffer, wherein the read buffer supply line is switchable between an operating mode output and a low-power mode output of a read buffer supply that is separate from core storage element supplies.10-07-2010
20090244988COMPILED MEMORY, ASIC CHIP, AND LAYOUT METHOD FOR COMPILED MEMORY - Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A logic of the decoder unit is formed by assigning a bit of the address signal to identify the memory blocks and the couple control units lower than a bit of the address signal to identify the word line groups. Accordingly, the numbers of word lines disposed at the memory blocks can be equalized with each other, and lengths of the bit lines can be shortened. As a result, a wiring delay of each of the bit lines can be minimized, and an access time of a compiled memory can be shortened.10-01-2009
20100118620Semiconductor Device - A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.05-13-2010
20110128797SENSE AMPLIFYING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.06-02-2011
20110128796DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.06-02-2011
20110128794APPARATUS AND METHOD FOR CONTROLLING OPERATION TIMING IN SEMICONDUCTOR MEMORY DEVICE - An apparatus for controlling an operation timing in a semiconductor memory device, comprising: a shift information generator configured to generate shift information based on data path delay information and latency information; and a shift register configured to shift a command based on the shift information and produce a shifted command to control an operation timing.06-02-2011
20090207668DATA STROBE CLOCK BUFFER IN SEMICONDUCTOR MEMORY APPARATUS, METHOD OF CONTROLLING THE SAME, AND SEMICONDUCTOR APPARATUS HAVING THE SAME - A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.08-20-2009
20120287728NONVOLATILE MEMORY DEVICE - A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode.11-15-2012
20120287727DRAM REFRESH METHOD AND SYSTEM - A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times.11-15-2012
20110286285SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.11-24-2011
20110286286SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.11-24-2011
20120099387NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME USING DIFFERENT PRECHARGE VOLTAGES - A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between adjacent first and second doping regions among the multiple regions, each of the cell strings including multiple cell transistors stacked in a third direction perpendicular to the substrate. The page buffers are connected to the cell strings through bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation. Levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.04-26-2012
20090201745SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 08-13-2009
20110292741Memory Apparatus and Associated Method - A memory apparatus includes a plurality of first bit columns for constructing a common memory space and at least one reserve second bit column. A column address of a damaged first bit column is recorded as a predetermined column address. When a byte column is accessed, data recorded in the first bit columns and the second bit columns are respectively latched in a first latching device and a second latching device. In the event that the latched access data is accessed, data is outputted by comparing the predetermined column address of each first bit column and an access column address, and when the access column address matches with the predetermined column address, data is outputted via the second latching device; otherwise, the data is outputted via the first latching device.12-01-2011
20110292742Stacked Semiconductor Memory Device, Memory System Including The Same, And Method Of Repairing Defects Of Through Silicon Vias - A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.12-01-2011
20110292740SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a data alignment unit configured to align serial input data in response to a data strobe signal, a data latching unit configured to latch an output signal of the data alignment unit in response to first and second synchronization pulse signals which are activated according to BL information during a write operation, and a data output unit configured to output an output signal of the data latching unit to a plurality of global data lines in response to a data input strobe signal corresponding to the BL information.12-01-2011
20110292739SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a data alignment unit configured to align data, which are sequentially inputted, in response to a data strobe signal, a latching operation control unit configured to receive the data strobe signal, and generate a latching control signal after an interval between a write operation and a next write operation elapses, a data latching unit configured to latch output signals of the data alignment unit in response to the latching control signal, and a data synchronization output unit configured to synchronize output signals of the data latching unit in response to a data input strobe signal, and output the synchronized signals to a plurality of data lines.12-01-2011
20090273987DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus includes: a control unit that outputs a first standby instruction signal, a second standby instruction signal, a first output instruction signal, and a second output instruction signal in response to an input of a standby instruction signal, an output instruction signal, a first test signal, and a second test signal; a first output driver that causes first data to be output or to enter a standby state according to whether or not the first standby instruction signal or the first output instruction signal is enabled; and a second output driver that causes second data to be output or to enter a standby state according to whether or not the second standby instruction signal or the second output instruction signal is enabled.11-05-2009
20090303801Carbon nanotube memory including a buffered data path - Carbon nanotube memory comprises a buffered data path including a forwarding write line and a returning read line for transferring data. Furthermore, bit line is multi-divided for reducing parasitic capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives a memory cell output through the bit line, a segment sense amp receives a local sense amp output, and a global sense amp receives a segment sense amp output. By the sense amps, a voltage difference in the bit line is converted to a time difference for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as reference signal. Additionally, alternative circuits and memory cell structures for implementing the memory are described.12-10-2009
20090103376SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device related to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a first interface part having a predetermined number of pins, a second interface part having a smaller number of the pins than the first interface part, a data pattern latch part which stores an externally input data pattern, a comparison part which compares the data pattern input or preliminarily set from the data pattern latch part with data which is read from the memory cell array, and a comparison result output part arranged in the second interface part, and which outputs a comparison result of the comparison part.04-23-2009
20090196108SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE TEST METHOD - A semiconductor memory device having a first memory block used when it is determined to be used in a first case, a second memory block used as an alternative of the first memory blocks when it is determined to be used in a second case, a write section that writes determination data into the first memory block for making a determination at the time of the determination and writes the determination data into the second memory block and a read section that reads the determination data written into the first memory block by the write section for making a determination at the time of the determination and reads the determination data written into the second memory block by the write section.08-06-2009
20090273985SEMICONDUCTOR DEVICE HAVING MULTIPLE I/O MODES - Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes and a data detector configured to detect the data in response to the data strobe signal output from the phase controller.11-05-2009
20090244987Dynamic Column Block Selection - Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.10-01-2009
20090231929MEMORY AND CONTROL UNIT - A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data.09-17-2009
20100091582ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.04-15-2010
20100091583MEMORY DEVICE HAVING LATCH FOR CHARGING OR DISCHARGING DATA INPUT/OUTPUT LINE - A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.04-15-2010
20100110802SEMICONDUCTOR DEVICE - A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.05-06-2010
20130010545MEMORY INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE - There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access.01-10-2013
20090168546Semiconductor memory device and method for operating the same - A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with the second clock to output a buffered second clock having the same frequency as the first clock, a data output circuit configured to output an internal data in response to the buffered second clock, a delay unit configured to delay the buffered second clock by a predetermined time, and a phase detector configured to detect a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and to output the detection result.07-02-2009
20090168548DATA OUTPUT CIRCUIT IN SEMICONDUCTOR MEMORY APPARATUS - A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data.07-02-2009
20090147592Memory Circuit with Decoupled Read and Write Bit Lines and Improved Write Stability - In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.06-11-2009
20090147591MEMORY CIRCUIT WITH HIGH READING SPEED AND LOW SWITCHING NOISE - A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.06-11-2009
20080266986TIMING IMPROVEMENTS BY DUAL OUTPUT SYNCHRONIZING BUFFER - Provided are a system and method for timing improvements by dual output synchronizing buffer. The method comprises providing at least two outputs on a synchronizing first-in-first-out buffer (“FIFO”) in a combinational logic circuit. The method further includes latching data into the FIFO. The method also includes alternating which of the two outputs by which the data is latched out of the FIFO, thereby extending timing in the combinational logic circuit.10-30-2008
20110261628256 Meg dynamic random access memory - A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.10-27-2011
20090310428MIS-TRANSISTOR-BASED NONVOLATILE MEMORY FOR MULTILEVEL DATA STORAGE - A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.12-17-2009
20100118618SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA BUS INVERSION FUNCTION - A semiconductor integrated circuit includes a data bus inversion (DBI) flag generating unit to generate DBI flag signals using a plurality of output data sets, a data inverting unit to invert the plurality of output data sets according to the DBI flag signals and transmit the plurality of output data sets through global transmission lines, and a plurality of data output units to output the plurality of output data sets, which are transmitted through the global transmission lines by pads.05-13-2010
20120033505SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.02-09-2012
20090207669PAGE BUFFER CIRCUIT OF MEMORY DEVICE AND PROGRAM METHOD - A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.08-20-2009
20090097328METHOD OF DETECTING A LIGHT ATTACK AGAINST A MEMORY DEVICE AND MEMROY DEVICE EMPLOYING A METHOD OF DETECTING A LIGHT ATTACK - A memory device having a plurality of memory cells employs a method to detect a light attack on the memory device. The method utilizes at least one memory cell to detect a light attack when the memory cell is in an inactive state, and outputs a signal indicating whether a light attack is detected. In one case, the method includes turning off all of the memory cells of memory blocks of the memory device that are not currently being accessed for a read/write operation; sensing a leakage current of at least one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation; and detecting a light attack on the memory device when a leakage current of the one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation is greater than a threshold.04-16-2009
20090046517SEMICONDUCTOR DEVICE - In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.02-19-2009
20090273986Non-Volatile Memory With Redundancy Data Buffered in Remote Buffer Circuits - A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.11-05-2009
20120106266Apparatus For Measuring Data Setup/Hold Time - An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a flag signal generating unit for generating flag signals according to the internal clock signal and the data signals, and a counter for producing the counting signals in response to the flag signals.05-03-2012
20110170362SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed is a semiconductor integrated circuit in which the number of bus lines is reduced and current consumption during operation can be lessened. The semiconductor integrated circuit includes a circuit unit (e.g., a memory cell array plate) which is divided into a plurality of banks (bank 07-14-2011
20090201746PARALLEL-TO-SERIAL DATA SORT DEVICE - A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.08-13-2009
20090262585INPUT BUFFER AND METHOD WITH AC POSITIVE FEEDBACK, AND A MEMORY DEVICE AND COMPUTER SYSTEM USING SAME - An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of the input signal transitioning through the magnitude of the reference signal. The comparator intensifies the output signal in response to the positive feedback from the output of the comparator while the output signal transitions from the first logic state to the second logic state.10-22-2009
20090279367POWER SAVING SENSING SCHEME FOR SOLID STATE MEMORY - Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.11-12-2009
20090285035Pipelined wordline memory architecture - A method is provided for reducing semiconductor memory wordline propagation delays of long wordlines by inserting pipeline registers in the wordlines between groups of memory cells.11-19-2009
20090285032Self pre-charging and equalizing bit line sense amplifier - A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors.11-19-2009
20110199836BIT-LINE SENSE AMPLIFIER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND METHOD OF TESTING BIT-LINE MICRO-BRIDGE DEFECT - The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.08-18-2011
20090290434DUAL FUNCTION DATA REGISTER - A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.11-26-2009
20090290436TEST CIRCUIT FOR MULTI-PORT MEMORY DEVICE - A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.11-26-2009
20090290435NONVOLATILE MEMORY DEVICE AND METHOD OF TESTING THE SAME - A nonvolatile memory device includes a clock input stage configured to receive a clock signal for a test, a control signal output unit configured to output data input-output (IO) control signals according to the clock signal, n number of IO stages for data IO, and n number of storage units connected to the respective n number of IO stages and configured to temporarily store data to be exchanged between the respective n number of IO stages and internal circuits according to the respective data IO control signals. The n number of storage units are further commonly connected to a first IO stage of the n number of IO stages and configured to sequentially input or output data through the first IO stage in a test mode according to the respective data IO control signals.11-26-2009
20090296494PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER - In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.12-03-2009
20090296495SYSTEM AND METHOD FOR CAPTURING DATA SIGNALS USING A DATA STROBE SIGNAL - A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.12-03-2009
20090097331INTERLEAVED INPUT SIGNAL PATH FOR MULTIPLEXED INPUT - System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner. In another embodiment, the command path includes a plurality of command latches that latch commands from the input signals in an interleaved manner and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner.04-16-2009
20090244986Semiconductor memory device and methods thereof - A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include a memory cell configured to store data, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type. A first example method may include storing at least one data pattern in a storage unit, outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation and blocking access to the memory cell during read operations of the second type. A second example method may include storing at least one fixed data pattern within a storage unit, the at least one fixed data pattern only accessible during read operations of a first type, storing normal data within at least one memory cell, the normal data only accessible during read operations of a second type and blocking access to the at least one memory cell during an execution of read operations of the second type.10-01-2009
20090168549Data output buffer circuit and semiconductor memory device includig the same - The example embodiments provide a data output buffer circuit which includes a pre-driver configured to adjust a slew rate of an input signal, a main driver configured to output signal supplied from the pre-driver, and a ZQ calibration circuit configured to control the pre-driver so as to decrease the slew rate when an operation voltage increases, and increase the slew rate when the operation voltage is decreased.07-02-2009
20080212378DATA LATCH CONTROLLER OF SYNCHRONOUS MEMORY DEVICE - Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the control signals being synchronized with rising and falling edges of the divided signal; and a latch unit for latching data corresponding to the bits by means of the control signals, and outputting the data for the detection and amplification of the data. The data input circuit may include a first delay unit for delaying the data in order to match setup-hold time, a second delay unit for performing delay for adjusting the data outputted from the latch unit, and a third delay unit for performing delay for adjusting the write strobe signal outputted from the latch unit.09-04-2008
20100110803SEMICONDUCTOR MEMORY DEVICE THAT CAN PERFORM SUCCESSIVE ACCESSES - To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and second data lines that connect the input/output circuit to a memory cell array. The input/output circuit includes a write buffer that supplies the write data on the write path to the first data line, a read amplifier that supplies the read data supplied to the read path through the second data line, and a bypass circuit that supplies the write data on the write path to the read path in response to detection of matching between a write address and a read address. Thus, data collisions can be avoided.05-06-2010
20100110801SEMICONDUCTOR DEVICE - A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of the external power supply voltage.05-06-2010
20100103749SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell region including memory cells that store data. An input buffer is disposed on one side of the memory cell region. On the other hand, an output buffer is disposed on another side opposite to the input buffer in the memory cell region.04-29-2010
20100103750ANTIFUSE REPLACEMENT DETERMINATION CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY DEVICE - An antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge at the node self-discharge via the antifuse element after the charging of the node is completed; a comparison and determination circuit for comparing the voltage at the node of the antifuse element with a plurality of reference voltages when a predetermined time has elapsed after the completion of the charging of the node; and a determination part for determining, based on a determination result with respect to the comparison using the plurality of reference voltages in the comparison and determination circuit, whether or not replacement of the bad memory cell has been performed normally by using the antifuse element.04-29-2010
20100103748CLOCK PATH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal.04-29-2010
20100103747Memory device and method of operating such a memory device - A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column. Each sub-array access circuitry comprises propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the associated sub-array during a read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array nearer the second end of the sub-array column. The propagation circuitry receives a control signal for identifying which of its first or second inputs should be used to produce the output read data value. As a result, an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry. This provides a particularly simple technique for propagating the read data value to the global access circuitry, which has both predictable timing, and consumes low power.04-29-2010
20090168547APPARATUS AND METHODS FOR A DATA INPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY APPARATUS - A data input circuit for a semiconductor memory apparatus includes a data latch block that, according to a data strobe signal, latches data and outputs the latched data; a data output controlling unit that determines a phase difference between the data strobe signal and a clock signal, and activates a data output control signal; and a data delay block that, when the data output control signal is activated, delays the data output from the data latch block for a predetermined time, and outputs the delayed data.07-02-2009
20100061158LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD - Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.03-11-2010
20100061156METHOD OF CONTROLLING MEMORY AND MEMORY SYSTEM THEREOF - The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.03-11-2010
20110267899NON-VOLATILE MEMORY DEVICE AND NON-VOLATILE MEMORY SYSTEM HAVING THE SAME - A non-volatile memory device may include a memory cell array, a page buffer, a column decoder, a column selection circuit and a repair circuit. The memory cell array includes normal memory cells and redundancy memory cells. In one example, the page buffer may load normal data and redundancy data from the memory cell array. The column decoder may generate a normal column selection signal and a redundancy column selection signal in response to a column address. The column selection circuit may select the normal data and redundancy data in response to the normal column selection signal and redundancy column selection signal. The repair circuit may then output one of the normal data and redundancy data.11-03-2011
20080239832FLASH MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A flash memory device includes a data input/output pad and a core region in which a plurality of unit cells are arranged. A data input buffer is configured to receive command and address data through the data input/output pad and transfer the received command and address to the core region. A data output buffer is configured to output the data through the data input/output pad, and a data input controller is configured to detect an outputting of the data and disable the data input buffer.10-02-2008
20120170383INTEGRATED CIRCUIT, SYSTEM INCLUDING THE SAME, MEMORY, AND MEMORY SYSTEM - A system includes integrated circuit chip including a first buffer configured to receive signals and a second buffer configured to receive signals, wherein the first buffer receives signals of a higher frequency than the second buffer, a controller chip configured to control the integrated circuit chip, an I/O channel formed between the controller chip and the integrated circuit chip to transfer a first signal and a second speed signal, wherein the first signal has a higher frequency than the second signal, and a status channel formed between the controller chip and the integrated circuit chip to transfer at least one status signal, wherein the integrated circuit chip is configured to select one of the first buffer and the second buffer and actives the selected buffer in response to the at least one status signal and receive a signal transferred through the I/O channel.07-05-2012
20120170382SEMICONDUCTOR MEMORY DEVICE, TEST CIRCUIT, AND TEST OPERATION METHOD THEREOF - A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.07-05-2012
20100128538DATA RECEIVING CIRCUIT - A variable delay circuit provides an adjustable delay to a strobe signal. An input latch circuit latches each bit data included in internal serial data by a strobe signal delayed by the variable delay circuit. A delay set unit adjusts a delay amount provided to the strobe signal by the variable delay circuit. While a calibration operation is being executed in which a known calibration pattern is inputted as serial data, the delay set unit statistically acquires output latch data of the input latch circuit, and adjusts the delay amount such that probabilities of occurrence of 1 and 0 becomes a predetermined ratio.05-27-2010
20090168551LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD - Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.07-02-2009
20080279016SIMPLIFIED-DOWN MODE CONTROL CIRCUIT UTILIZING ACTIVE MODE OPERATION CONTROL SIGNALS - A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level.11-13-2008
20080310239Device for writing data into memory and method thereof - A device for writing data into a memory and a method thereof. The memory comprises a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The data is divided into a plurality of segments. The segments are written into first memory cells of the memory cells of the memory arrays in sequence. The segments are written into second memory cells of the memory cells of the memory arrays when the first memory cells of the memory cells of the memory arrays are full, and so forth till the operation of writing the segments into the memory is completed.12-18-2008
20080239831Clock synchronizer - Disclosed herein are synchronization latch solutions.10-02-2008
20080253199PARALLEL DATA STORAGE SYSTEM - A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.10-16-2008
20110007576SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY SEMICONDUCTOR DEVICE FOR CONTROLLING OUTPUT DATA - Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.01-13-2011
20080212377SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a pair of sense nodes connected to the bit lines, and transmitting the data of the memory cells; transfer gates connected between the bit lines and the sense nodes; a latch circuit latching a first high level potential to one of the pair of sense nodes, and latching a low level potential to the other sense node of the pair of sense nodes; and a level shifter applying a second high level potential higher than the first high level potential to one of the pair of bit lines according to the potentials latched to the pair of sense nodes during a data write operation or a data write-back operation.09-04-2008
20090190410USING DIFFERENTIAL DATA STROBES IN NON-DIFFERENTIAL MODE TO ENHANCE DATA CAPTURE WINDOW - A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself, or other causes. The differential input strobes of the data capture circuit are input into individual input buffers, each compared against a reference voltage individually, as well as a data input pin. The outputs from these buffers are maintained separate from each other all the way to the point where the input data is latched. In latching the input data, data ones are latched entirely based on input signals derived from a rising edge (both strobes and data), and zeros are latched entirely based on input signals derived from a falling edge (both strobes and data).07-30-2009
20080291747Buffered Memory Device - A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.11-27-2008
20100142287SYSTEM AND METHOD FOR PROVIDING TEMPERATURE DATA FROM A MEMORY DEVICE HAVING A TEMPERATURE SENSOR - A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path.06-10-2010
20110205812SEMICONDUCTOR DEVICE - A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the data bus in a first operation mode and supplying data from outside to the sense amplifier via the write amplifier, the data bus, and the transistors in a second operation mode, and a control circuit supplying an electric potential to gate electrodes of first transistors that establish the electrical connection depending on the address, wherein in a first operation mode, the control circuit supplies a first electric potential to the gate electrodes of the first transistors, so that the first transistors exhibit a first impedance value and in the second operation mode, the control circuit supplies a second electric potential to gate electrodes of the first transistors, so that the first transistors exhibit a second impedance value, an absolute value thereof being lower than that of the first impedance value.08-25-2011
20090161446INPUT CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE ENSURING ENABLED DATA INPUT BUFFER DURING DATA INPUT - An input circuit of a semiconductor memory device that prevents data from being input into a data input buffer prior to the enablement of the data input buffer. The input circuit includes an input buffer enabling control unit that generates an input buffer enabling signal which is enabled before a point at which data is input and which has an enabling period of at least a predetermined burst length. A data input buffer is controlled by the input buffer enabling signal, and the data input buffer buffers and outputs the data during the enabling period of the input buffer enabling signal.06-25-2009
20110267898SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a clock transmission unit configured to selectively output a data strobe clock signal or a phase correction clock signal based on an operation mode, and a data latch unit configured to latch a plurality of data signals under a control of a clock signal which is outputted from the clock transmission unit.11-03-2011
20110188323DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY AND RELATED METHOD - Various embodiments of a data output circuit of a semiconductor memory and related method are disclosed. In one exemplary embodiment, a data output circuit may include a plurality of global lines, a sense amplifier block configured to output a plurality of data to the plurality of global lines at different timings, a pipe latch block configured to latch the plurality of data transmitted through the plurality of global lines at different timings, and a control unit configured to control output timings of the plurality of data from the sense amplifier block and latch timings of the pipe latch block using an address signal.08-04-2011
20110188322MEMORY DEVICE WITH DATA PATHS FOR OUTPUTTING COMPRESSED DATA - A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer.08-04-2011
20090027974MEMORY CONTROL METHOD AND MEMORY CONTROL CIRCUIT - A memory control method includes: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate a plurality of phase detection results in response to the delayed data strobe signals so as to correspond to the delayed data strobe signals; latching write data carried by a data signal according to rising/falling edges of the data strobe signal; performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and in a situation where the data strobe signal leads the clock signal, delaying or bypassing the odd/even data carried by the data separation signal according to the phase detection results. A memory control circuit is provided.01-29-2009
20090161447SEMICONDUCTOR MEMORY INPUT/OUTPUT DEVICE - A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe signal to a selection pad and a lower input buffer for receiving a lower data mask signal from the selection pad, and selecting one operation of the lower output buffer and the lower input buffer, and an upper input/output unit including an upper output buffer for outputting an inverted read data strobe signal to the second selection pad and an upper input buffer for receiving an upper data mask signal from the second selection pad, and selecting one operation of the upper output buffer and the upper input buffer.06-25-2009
20090161445SEMICONDUCTOR MEMORY DEVICE AND DATA MASKING METHOD OF THE SAME - A semiconductor memory device has a data masking function during a write operation. The semiconductor memory device includes a data mask input unit that receives a data mask signal. A data input unit receives data and delays the output of the data more than the output of the data mask signal. A write driver selectively drives the data outputted from the data input unit according to the data mask signal outputted from the data mask input unit. The semiconductor memory device ensures that the data mask signal is inputted into the write driver prior to the input of the data, thus preventing a timing mismatch between data and the data masking signal and poor data masking.06-25-2009
20090129173SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.05-21-2009
20090129172HIGH RELIABLE AND LOW POWER STATIC RANDOM ACCESS MEMORY - Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.05-21-2009
20080316835Concurrent Multiple-Dimension Word-Addressable Memory Architecture - An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.12-25-2008
20120069686LATCH TIMING ADJUSTMENT DEVICE AND MEMORY ACCESS SYSTEM USING THE SAME - A latch timing adjustment device includes: first to third variable delay sections configured to delay a strobe signal by first to third variable delay amounts, respectively; first to third data latch sections configured to latch a data signal in response to the outputs of the first to third variable delay sections, respectively; a comparison section configured to perform comparison between the outputs of the first and second data latch sections and comparison between the outputs of the second and third data latch sections; and a delay adjustment section configured to adjust the first and third variable delay amounts based on the comparison results from the comparison section, and adjust the second variable delay amount based on the first and third variable delay amounts adjusted.03-22-2012
20120069684SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes a memory cell array includes data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the data storage units, and a flag bit column which stores, for each row, a flag for identifying presence/absence of logic reversal of data stored in the data storage units.03-22-2012
20120069685Semiconductor device having optical fuse and electrical fuse - A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring.03-22-2012
20090185431SEMICONDUCTOR DEVICE - The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.07-23-2009
20090003086Semiconductor memory device including output driver - A semiconductor memory device has a data output device. The data output device is provided with a slew rate control unit for detecting a transition number of a plurality of output data to output slew rate control information; and an output driving unit for driving the plurality of output data with a pull-up drivability and a pull-down drivability adjusted based on the slew rate control information.01-01-2009
20130121087SEMICONDUCTOR MANUFACTURING METHOD - A memory bit cell includes a latch, a write port coupled to the latch, and a read port coupled to the latch. The write port includes a first set of devices having a first threshold voltage and a second set of devices having a second threshold voltage that is greater than the first threshold voltage. The read port includes a third set of devices having a third threshold voltage that is less than the first threshold voltage.05-16-2013
20130121088MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR - A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.05-16-2013
20090052260SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.02-26-2009
20110228615SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes unit structures. Each unit structure includes bit lines, memory cells, sense amplifiers, a first data line, a computing circuit, a second data line, and data latches. The bit lines are connected to memory cells. The sense amplifiers are connected to respective bit lines adjacent to each other. The first data line is commonly connected to the sense amplifiers. The computing circuit is connected to the first data line. The second data line is connected to the computing circuit. The data latches are connected to the second data line. The unit structures are independent from one another. At least one of the unit structures is a spare unit structure. One of the unit structures is configured to be replaceable with the spare unit structure.09-22-2011
20110141823SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array, and first to third latch circuits. The first latch circuits hold information as to whether an associated column is defective. A pointer is set in the second latch circuits. The third latch circuits hold write data or read data. One of the third latch circuits is activated at a time the pointer is set to an associated second latch circuit when an associated first latch circuit holds the information indicating that the associated column is not defective. The pointer is sequentially shifted among the second latch circuits in synchronization with a clock. In shifting the pointer, the pointer skips one of the second latch circuits associated with one of the first latch circuit which holds the information indicating that the associated column is defective.06-16-2011
20090086552SEMICONDUCTOR MEMORY DEVICE AND ITS DRIVING METHOD - A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from the first latch, a second latch that selectively latches the output signal from the first latch in response to the control signal and a mode decoder that decodes an output signal from the second latch to output an operation mode.04-02-2009
20090168550Output port, microcomputer and data output method - An output port circuit includes a plurality of output buffers; a plurality of first holding circuits configured to hold output data to be outputted to the plurality of output buffers; a plurality of second holding circuits configured to hold output data to be outputted to the plurality of first holding circuits; and a plurality of third holding circuits configured to hold bit pattern data for individually setting whether the output data of the plurality of second holding circuits are latched by the plurality of first holding circuits. Data input to the plurality of second holding circuits and data input to the plurality of third holding circuits are controlled at a same timing.07-02-2009
20080316836Ground biased bitline register file - In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is not performing a write operation. Ground biased read control circuitry is used to bias a read bitline when the memory cell is not performing a read operation.12-25-2008
20090213664NONVOLATILE MEMORY UTILIZING MIS MEMORY TRANSISTORS WITH FUNCTION TO CORRECT DATA REVERSAL - A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.08-27-2009
20090257286APPARATUS AND METHOD FOR OUTPUTTING DATA IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for outputting data in a semiconductor integrated circuit includes a clock generation block configured to activate a first clock signal for outputting a data signal and a second clock signal for outputting a data strobe signal based on a predetermined timing, and a data output block configured to latch a pre-data signal and a pre-data strobe signal in response to the first clock signal and the second clock signal, respectively.10-15-2009
20090097329Semiconductor storage device and high-speed address-latching method - A semiconductor storage device includes: an input buffer that receives address data and command data; a first through-latch-type latch circuit that latches the command data in synchronism with a rising edge of a clock signal; and a second through-latch-type latch circuit that latches the address data in synchronism with a falling edge of the clock signal.04-16-2009
20080259695Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices - A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input port that is configured to receive a control signal that identifies a type of signal that is input to the first input port. Related methods of testing semiconductor memory devices are also provided.10-23-2008
20080259693Semiconductor Device - A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.10-23-2008
20090257285SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal, and a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin, wherein the input signal is one of an input command signal and an input address signal.10-15-2009
20100149883SEMICONDUCTOR DEVICE - In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.06-17-2010
20090316493SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.12-24-2009
20120195133SEMICONDUCTOR MEMORY DEVICE HAVING DATA COMPRESSION TEST CICUIT - A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.08-02-2012
20120195132SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes an input register which latches, by a second unit, data which are read from a memory cell array by a first unit, a bit state-counter which counts a bit state of the data latched in the input register, a frame size-setup register which latches the first unit, an input data-counter which detects whether or not a total number of the data input to the input register reaches to the first unit, an accumulation circuit which accumulate a value counted by the bit state-counter, a threshold value-register which latches a threshold value for detecting whether or not an erase area of the memory cell array is accessed, a comparison circuit which compares an accumulated value of the accumulation circuit and the threshold value with each other, and a product storage-register which latches a result of the comparison circuit.08-02-2012
20100177573SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVING METHOD - A memory includes a latch circuit latching data from a first and a second bit lines to a first and a second sense nodes; a first data line reading-out the data from the first sense node to an outside; a second data line reading-out the data from the second sense node to the outside; a first write transistor connected between the first bit line and the first or second data line without via the first and second sense node; and a second write transistor connected between the second bit line and the first or second data line without via the first and second sense node, wherein in a write operation, the first write transistor transmits the data from the first or second data line to the first bit line, or the second write transistor transmits the data from the first or second data line to the second bit line.07-15-2010
20100177572SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING PAGE SIZE - A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.07-15-2010
20100177571MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD - A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.07-15-2010
20120140573SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.06-07-2012
20120140572SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a switching element coupled between a power supply line and an output terminal of a power supply circuit for supplying a power supply voltage, wherein the switching element is configured to be turned on in response to a standby signal, a page buffer including a plurality of latch circuits, wherein a voltage input terminal of at least one of the latch circuits is coupled to the output terminal of the power supply circuit and a voltage input terminal of at least another one of the latch circuits is coupled to the power supply line, and a control logic circuit configured to generate the standby signal according to an operation mode of the semiconductor memory device.06-07-2012
20100002526Latch-based Random Access Memory - A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.01-07-2010
20100002527POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE - A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.01-07-2010
20100188907SEMICONDUCTOR DEVICE, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A semiconductor device including a first switch coupled to a first power supply line, a second switch coupled to the first switch and to a second power supply line, and a storage part provided in a path which is between the second power supply line and the first switch, and having a high resistance state and a low resistance state, and wherein the first switch is turned on and the second switch is turned off when a resistance state of the storage part is in a high resistance state.07-29-2010
20090316495SEMICONDUCTOR DEVICE TESTABLE ON QUALITY OF MULTIPLE MEMORY CELLS IN PARALLEL AND TESTING METHOD OF THE SAME - A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.12-24-2009
20090316496INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY - An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.12-24-2009
20090316494SEMICONDUCTOR MEMORY DEVICE HAVING PLURALITY OF TYPES OF MEMORIES INTEGRATED ON ONE CHIP - A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.12-24-2009
20100188906STROBE APPARATUS, SYSTEMS, AND METHODS - A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.07-29-2010
20100182849Synchronous semiconductor device and data processing system including the same - A semiconductor device includes first, second and third terminals respectively receiving first, second and third input signals from outside, first, second and third input buffers respectively coupled to the first, second and third terminals, the first, second and third input buffers producing first, second and third buffered signals responsive to the first, second and third input signals, respectively, and first and second gate circuits respectively coupled to the first and second input buffers, the first and second gate circuits coupled to the third input buffer in common, the first and second gate circuits respectively driving output nodes thereof in response to the first and second buffered signals when the third buffered signal is activated, and each of the first and second gate circuits holding the output nodes thereof at a fixed level irrelatively to the first and second buffered signals when the third buffered signal is inactivated.07-22-2010
20130215685MEMORY DEVICE HAVING SENSING CIRCUITRY WITH AUTOMATIC LATCHING OF SENSE AMPLIFIER OUTPUT NODE - A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to bitlines associated with respective columns of the memory cells of the memory array. The sensing circuitry comprises, for at least a given one of the bitlines of the memory array, a sense amplifier configured to sense data on the given bitline, with the sense amplifier having at least one internal node and at least one output node. The sensing circuitry further comprises a latch circuit having a data input coupled to the output node and a control input coupled to the internal node, with the latch circuit being configured to latch sensed data from the output node responsive to a signal at the internal node.08-22-2013
20130215686REFERENCE GENERATOR WITH PROGRAMMABLE M AND B PARAMETERS AND METHODS OF USE - A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.08-22-2013
20100220534Memory Device with Reduced Buffer Current During Power-Down Mode - A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.09-02-2010
20100226184DATA INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the data input/output buffer, in response to the first driving control signal. A second timing control unit controls an active timing of a second control signal to output a second driving control signal. A second data input/output unit transmits the write data from the global input/output line to a local input/output line or transmits the read data from the local input/output line to the global input/output line, in response to the second driving control signal.09-09-2010
20100238741SEMICONDUCTOR DEVICE AND WRITE CONTROL METHOD FOR SEMICONDUCTOR DEVICE - To include a memory cell array that stores therein data in a reversible manner, an antifuse circuit that stores therein data in a nonvolatile manner, a sense amplifier array that temporarily holds data that is read from the memory cell array of data to be written in the memory cell array, and a control circuit that performs a control for writing the data held in the sense amplifier array in the antifuse circuit. According to the present invention, it is not required to provide any dedicated latch circuit for each antifuse element. Therefore, a writing process of writing data in the antifuse circuit can be performed at high speed without causing an increase of the chip dimension due to a dedicated latch circuit.09-23-2010
20100238740SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 109-23-2010
20110058430Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage.03-10-2011
20110058429LOW POWER SHIFT REGISTER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift dock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.03-10-2011
20090116301INTERNAL DATA COMPARISON FOR MEMORY TESTING - Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data comparison test mode. The data comparison test mode systematically searches for addresses of defective columns by comparing a sensed data value to an expected data value at various levels of decoding. Upon detection of a defective column, the address value for each level of decoding is stored and can be used in redundancy selection to replace the defective columns with redundant columns. The comparison is internal to the memory device such that the test mode is independent of external testers and can be run after fabrication, even by an end user, thus allowing repair after fabrication and installation. The comparisons are facilitated by compare logic inserted into the data path.05-07-2009
20090116300SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the semiconductor memory device, when a test operation is activated.05-07-2009
20090116299Semiconductor memory device and method for operating the same - A semiconductor memory device is capable of generating a desired output enable signal without increasing an initial count value and bit number and generating a desired final output enable signal, without unnecessary reset operations, by reflecting CAS latency information on an external clock count value. The semiconductor memory device includes a first output enable signal generating unit configured to compare a first count value, which is obtained by counting a delay locked loop (DLL) clock, with a second clock count value, which is obtained by counting an external clock until a read command is input, and output a first output enable signal, and a final output enable signal generating unit configured to output, as a final output enable signal, one of the first output enable signal and a plurality of output enable signals generated by shifting the first output enable signal, according to a column address strobe (CAS) latency.05-07-2009
20100142286AUTO-PRECHARGE SIGNAL GENERATOR - An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.06-10-2010
20090285034LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - To provide a latency counter capable of increasing the signal quality of outputted internal commands. There is provided a point-shift FIFO circuit controlled by count values of a counter circuit. The point-shift FIFO circuit includes: a first wired-OR circuit that combines outputs of first latch circuits; a second wired-OR circuit that combines outputs of second latch circuits; a gate circuit that combines outputs of the first and second wired-OR circuits; and reset circuits that reset the first and second wired-OR circuits, respectively, based on the count value of the counter circuit. According to the present invention, as compared to a case that outputs of all the latch circuits are wired-OR connected, output loads are more reduced. Thus, a high signal quality can be obtained.11-19-2009
20120195134DATA ALIGNMENT CIRCUIT - A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.08-02-2012
20100195412SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM - The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized(FIG. 08-05-2010
20090040838DELAY LOCKED OPERATION IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling a delay of the internal clock such that a data output timing is synchronized with the system clock; a data output buffer for synchronizing data with the delay locked internal clock, thereby outputting the data, and a clock buffer control unit, responsive to a previous operation state, for generating an enable signal controlling the on/off switching of the clock buffer.02-12-2009
20100195413SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.08-05-2010
20100195409Fuse elemetns based on two-terminal re-writeable non-volatile memory - A margin restore fuse element is described, including a latch configured to store data, a first memory element coupled to the latch and configured to store a first resistive value, a second memory element coupled to the latch and configured to store a second resistive value, a restore circuit coupled to the latch, the first memory element, and the second memory element, the restore circuit being configured to perform a restore data operation to substantially restore the first and second memory elements to the first and second resistive values, respectively. The latch, restore circuit, and other circuitry can be formed FEOL on a substrate (e.g., a semiconductor wafer) as part of a microelectronics fabrication process and the fuse element and memory elements can be formed BEOL over the substrate as part of another microelectronics fabrication process. The fuse and memory elements can be included in a two-terminal non-volatile memory cell.08-05-2010
20100195410Semiconductor memory device having shift registers - A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in each of the n units of the shift registers. The signal processing units located on the odd-numbered positions counted from the input end side are connected to one another. The reversed signal processing units located on the even-numbered positions counted from the input end side are connected to one another. The signal processing units located on the end opposite to the input end side are connected to the reversed signal processing units located on the end opposite to the input end side. Each of the signal processing units includes the logic circuit unit and the flip-flop while each of the reversed signal processing units includes the reversed logic circuit unit and the reversed flip-flop.08-05-2010
20090073777SIGNAL TRANSFER APPARATUS AND METHODS - Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.03-19-2009
20090073778SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.03-19-2009
20080291749METHOD AND APPARATUS FOR TIMING ADJUSTMENT - A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.11-27-2008
20080291746Semiconductor Storage Device and Burst Operation Method - The present invention is a PSRAM in which a burst length can be increased without increasing consumed current, and a burst operation method therefor. In operation, column selection lines CSL11-27-2008
20080291748WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS - A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.11-27-2008
20120275239MEMORY APPARATUS AND REFRESH METHOD THEROF - A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.11-01-2012
20100302875SEMICONDUCTOR DEVICE HAVING NONVOLATILE MEMORY ELEMENT AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.12-02-2010
20100302874SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING THE SAME, AND CONTROLLER - To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.12-02-2010
20100302872BUFFER CONTROL SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - A buffer control signal generation circuit includes a burst start signal generator, a command decoder, a burst controller, and a burst column controller. The burst start signal generator shifts a write pulse into a first period to generate a first burst start signal and shifts the write pulse into a second period to generate a second burst start signal, such that the second period being shorter than the first period. The command decoder generates a burst period pulse and a column active pulse in response to the second burst start signal and a column control signal. The burst controller receives the column active pulse and buffers the burst period pulse to generate a burst end signal. The burst column controller generates the column control signal from the burst end signal and the column active pulse.12-02-2010
20110122710METHOD AND APPARATUS FOR GENERATING A SEQUENCE OF CLOCK SIGNALS - A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.05-26-2011
20110026332Semiconductor memory device and its operation method - Disclosed herein is a semiconductor memory device including: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to the bit line; a first switch for controlling connection of the sense line to the bit line; a data latch circuit having a second data holding node and a first data holding node connected to the sense line; and a second switch for controlling connection of the second data holding node of the data latch circuit to the bit line.02-03-2011
20100165751DATA OUTPUT DEVICE FOR SEMICONDUCTOR MEMORY APPARATUS - A data output device of a semiconductor memory apparatus includes detection means configured to detect a specified operation frequency range; pre-driving means configured to be inputted with signals; driving means configured to receive outputs of the pre-driving means and drive an output of data; and adjustment means configured to adjust a slew rate of the driving means under the control of an output signal of the detection means.07-01-2010
20100182848SEMICONDUCTOR DEVICE AND DATA PROCESSOR - To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.07-22-2010
20090067260Buffer control circuit of memory device - Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.03-12-2009
20110002175SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a repair node; a fuse one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; and a voltage drop unit coupled between the pull-up unit and the fuse and configured to lower a voltage level of the driving voltage.01-06-2011
20110110167INTEGRATED CIRCUIT - An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a test operation is activated.05-12-2011
20100172191Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage.07-08-2010
20110044116SYSTEM AND METHOD FOR CAPTURING DATA SIGNALS USING A DATA STROBE SIGNAL - A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.02-24-2011
20110116325COMPUTER APPARATUS AND MEMORY ERROR SIGNAL DETECTING SYSTEM - A memory error signal detecting system including a signal extracting circuit, a flip-flop, a latch circuit, and a light sign is provided. The signal extracting circuit receives a memory error signal to output a pulse signal when the memory error signal switches from a first level to a second level. When the preset end of the flip-flop receives the pulse signal, and the maintaining time of the pulse signal is maintained for a predetermine time, the flip-flop output end is set to a high voltage level. The latch circuit determines whether to output the state of the flip-flop output according to the reset signal. The light sign operates according to the state of an output end of the latch circuit. Furthermore, a computer apparatus including the memory error signal detecting system is also provided.05-19-2011
20090219765SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data to be programmed into a memory cell and changes the data held according to a verify result from the memory cell. Then, the data circuit selects one of the bit line application voltage terminals based on the data held therein and applies voltage of the selected bit line application voltage terminal to a bit line BLe or BLo.09-03-2009
20110211397PIPE LATCH CIRCUIT AND METHOD FOR OPERATING THE SAME - A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.09-01-2011
20100039871SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY - A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.02-18-2010
20110176372MEMORY INTERFACE - The memory interface includes: a first data latch unit that delays a strobe signal from a memory device, through a first variable delay unit and reads the strobe signal as a first data signal; and a second data latch unit that delays the same strobe signal through the second variable delay unit and reads the strobe signal as a second data signal. The memory interface uses the data read by the first data latch unit in a normal memory access operation, detects a boundary of the delay amount by comparing the data with the data read by the second data latch unit, and reflects the boundary on the delay amount of the first variable delay unit. Thereby, the delay amount can be corrected without suspending the normal memory access operation.07-21-2011
20090323435TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY - In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.12-31-2009
20090016120Synchronous semiconductor device and data processing system including the same - A synchronous semiconductor device includes: input buffers; a latch-signal generating circuit that generates a latch signal based on a clock signal; latch circuits that latch an address signal in response to the latch signal; delay circuits that supply the latch circuits with the address signal in synchronism with the latch signal; NOR gate circuits that inactivate the address signal in response to a chip select signal becoming inactive, the NOR gate circuits being arranged between the input buffers and the delay circuits. According to the present invention, without stopping an operation of the input buffers or an internal clock signal, consumed power generated between the input buffers and the latch circuits can be effectively reduced.01-15-2009
20100061157DATA OUTPUT CIRCUIT - A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.03-11-2010
20120243341SEMICONDUCTOR DEVICE HAVING PLURAL DATA BUSES AND PLURAL BUFFER CIRCUITS CONNECTED TO DATA BUSES - Disclosed herein is a device that includes a plurality of buffer circuits and data buses coupled to the buffer circuits. Each of the data buses includes first and second portions. The first portions of the data buses are arranged at a first pitch in the second direction, and the second portions of the data buses are arranged at a second pitch in the second direction, the second pitch being smaller than the first pitch.09-27-2012
20100054045Memory and Reading Method Thereof - A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.03-04-2010
20100054047SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.03-04-2010
20100054046DATA INPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device capable of reducing a whole area thereof includes a plurality of data input circuits configured to reflect inversion information on data inputted thereto, a plurality of global lines for transferring data outputted from the plurality of data input circuits, and a plurality of memory banks for storing data transferred from the plurality of global lines.03-04-2010
20090154256Integrated Circuit Memory Devices Including Delayed Clock Inputs for Input/Output Buffers and Related Systems and Methods - A memory system may include an integrated circuit memory device and a memory controller coupled to the integrated circuit memory device. The integrated circuit memory device may include a memory cell array having a plurality of memory cells, a clock generator configured to generate a clock signal, a plurality of data input/output buffers, and a delay circuit. The plurality of data input/output buffers may be coupled between respective data input/output pads and the memory cell array, and each of the data input/output buffers may be configured to communicate data with the memory cell array responsive to the clock signal with the clock signal being applied to a clock input of each of the input/output buffers. The delay circuit may be coupled between the clock generator and a first one of the data input/output buffers so that the clock signal is delayed by different amounts at clock inputs of the first data input/output buffer and a second one of the data input/output buffers. Moreover, the memory controller may be configured to perform data training. Related methods and memory devices are also discussed.06-18-2009
20100128539SEMICONDUCTOR MEMORY - A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.05-27-2010
20110249513TRANSMITTING/RECEIVING METHODS AND SYSTEMS WITH SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES - DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.10-13-2011
20110249512MEMORY CHIP AND MULTI-CHIP PACKAGE - A memory chip includes: 10-13-2011
20090027973NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with a high voltage; a sense node having its one end connected to each of the anti-fuse elements; a sense amplifier comparing the potential of the sense node with the reference potential and amplifying the difference therebetween, the sense amplifier being activated according to a sense-amplifier activation signal; an initialization circuit initializing the potential of the sense node according to an initialization signal; a control circuit outputting the initialization signal at a predetermined timing after input of an external signal input from the outside and outputting a first activation signal to activate the sense amplifier at a predetermined timing after input of the external signal; and a switching circuit outputting the first activation signal as the sense-amplifier activation signal when a normal data read operation is performed, and outputting an inverted version of the external signal as the sense-amplifier activation signal when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down.01-29-2009
20110069561SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS - The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.03-24-2011
20110069560DATA CAPTURE SYSTEM AND METHOD, AND MEMORY CONTROLLERS AND DEVICES - Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.03-24-2011
20120147678Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.06-14-2012
20100246278Accessing data within a memory formed of memory banks - A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located closer to an input and output of said memory than it is to at least one array located further from an input and output of said memory.09-30-2010
20100246281Sensing and latching circuit for memory arrays - According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.09-30-2010
20100246280SEMICONDUCTOR DEVICE HAVING RESET COMMAND - A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circuit is capable of holding selection information on circuits capable of being reset. The selection information is externally input. The reset control circuit outputs a reset signal on the basis of the selection information held in the latch circuit in response to a power-on reset signal and the first trigger signal output from the reset sequence circuit.09-30-2010
20100246279Pipe latch circuit and semiconductor memory device using the same - A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.09-30-2010
20100259998Non-volatile RAM, and solid state drive and computer system including the same - The non-volatile random access memory (RAM) includes a non-volatile RAM array, a buffer configured to buffer data to be programmed in the non-volatile RAM array and configured to buffer data read from the non-volatile RAM array, and a control block configured to read data from at least one of the non-volatile RAM array and the buffer based on whether the data to be read has been stored in the buffer, a temperature when the data was programmed, and a time lapse since the programming of the data.10-14-2010
20100259997Storage circuit and storage method - A storage circuit includes a first switching unit that receives data and is controlled to switch between an electrically connecting state and an electrically disconnecting state according to a clock signal input to a gate terminal of the first switching unit, an inverting unit that inverts the data and outputs the inverted data, a second switching unit that receives the inverted data and is controlled simultaneously with the first switching unit to switch between the electrically connecting state and the electrically disconnecting state according to the clock signal input to a gate terminal of the second switching unit and a latching unit that is connected to an output terminal of the first switching unit and an output terminal of the second switching unit, latches the data and the inverted data, and outputs the data and the inverted data simultaneously.10-14-2010
20100254200Buffer Control Circuit of Memory Device - Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.10-07-2010
20110176371MEMORY MODULE INCLUDING MEMORY BUFFER AND MEMORY SYSTEM HAVING THE SAME - A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.07-21-2011
20090147590APPARATUS FOR REDUCING LEAKAGE IN GLOBAL BIT-LINE ARCHITECTURES - A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.06-11-2009
20100097865DATA TRANSMISSION CIRCUIT AND A SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A data transmission circuit includes a data input unit configured to latch data in response to a data strobe signal and to output the data as input data, and a data input timing control unit configured to latch the input data in response to the data strobe signal delayed for a predetermined time interval and to output the input data to a bank group as delay data.04-22-2010
20100085816Flag signal generation circuit and semiconductor memory device - There is provided a flag signal generation circuit. The flag signal generation circuit includes a status register read (SRR) signal generating unit receiving an idle signal and an SRR command to generate an SRR signal; a pulse signal generating unit receiving an SRR signal to generate a pulse signal; and a flag signal generating unit receiving the pulse signal and a read signal for SRR to generate a flag signal.04-08-2010
20100039870MEMORY CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCORPORATING THE SAME - A memory control circuit includes a clock generation circuit that generates a clock signal and provides the clock signal to an external memory device, and at least one retention circuit that retains a data signal provided from the external memory device only under a significant state of a data strobe signal, which is provided together with the data signal. The memory control circuit controls data acquisition from the retention circuit in accordance with the clock signal. A data acquisition timing judgment unit, by monitoring the clock signal, judges whether or not a timing of the data acquisition has arrived. A data strobe signal correction unit maintains the significant state of the data strobe signal until it is judged that the data acquisition timing has arrived.02-18-2010
20120269008DATA INPUT DEVICE FOR SEMICONDUCTOR MEMORY DEVICE - A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing.10-25-2012
20120170385OUTPUT DRIVER AND ELECTRONIC SYSTEM COMPRISING SAME - An output driver comprises a pull-up circuit that pulls up an output node to a supply voltage in N successive intervals in response to N pull-up control signals having different phases and a pull-down circuit that pulls down the output node to a ground voltage in M successive intervals in response to M pull-down control signals having different phases.07-05-2012
20120170384INTEGRATED CIRCUIT, MEMORY SYSTEM, AND OPERATION METHOD THEREOF - An integrated circuit includes an input pad configured to receive a low-speed signal and a high-speed signal, a high-speed buffer coupled to the input pad, a low-speed buffer coupled to the input pad, a strobe input unit configured to receive a strobe signal for indicating an input of the high-speed signal to the input pad, and a buffer control unit configured to control an activation of the high-speed buffer in response to the strobe signal.07-05-2012
20080253198SEMICONDUCTOR MEMORY DEVICE WITH A NOISE FILTER AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit.10-16-2008
20120201085LOW POWER MEMORY CONTROL CIRCUITS AND METHODS - Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.08-09-2012
20110164460Semiconductor device and method of controlling the same - A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.07-07-2011
20100284228SEMICONDUCTOR DEVICE HAVING DATA INPUT/OUTPUT UNIT CONNECTED TO BUS LINE - To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.11-11-2010
20100329040DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.12-30-2010
20100329042MEMORY CHIP PACKAGE WITH EFFICIENT DATA I/O CONTROL - A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.12-30-2010
20100329041SEMICONDUCTOR MEMORY DEVICE HAVING POWER-SAVING EFFECT - A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.12-30-2010
20110134707BLOCK ISOLATION CONTROL CIRCUIT - A block isolation control circuit includes: a control signal generation unit configured to generate a control signal which is disabled when a defect occurs in a cell block and it is necessary to replace a defective cell block with a redundant cell block, or when the cell block is not selected in a test mode; and at least one switch element connected between the cell block and a bit line sense amplifier, wherein the switch element isolates the cell block from the bit line sense amplifier when the control signal is disabled.06-09-2011
20100165750DATA INPUT DEVICE OF SEMICONDUCTOR MEMORY APPARTUS AND CONTROL METHOD THEREOF - A data input device of a semiconductor memory apparatus includes input means configured to input data; precharge means configured to supply a precharge voltage for converting inputted data to a differential signal; enable means configured to enable the input means and the precharge means to operate; and control means configured to control a current amount of the enable means in a standby mode.07-01-2010
20100067311Non-Volatile Memory Device Having High Speed Serial Interface - A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit.03-18-2010
20100195408Non-Body Contacted Sense Amplifier with Negligible History Effect - In a method of mitigating hysteresis effect in a sense amplifier circuit, a data value is sensed from a data source with the sense amplifier during a first period. The data value is stored in a latch. The data valued stored in the latch is inverted, thereby generating an inverted data value. The data source is isolated from the sense amplifier and the inverted data value is read with the sense amplifier during a second period immediately following the first period.08-05-2010
20090175090Buffered DRAM - A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further coupled to receive address and command signals. If data access is directed to a second DRAM, the buffer buffers the data and strobe signals for access by the second DRAM. If data access is directed to the buffered DRAM the buffer buffers the data and strobe signals for access by the DRAM memory cell.07-09-2009
20090175091APPARATUS AND METHODS FOR AN INPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY APPARATUS - An input circuit for a semiconductor memory apparatus comprising a input unit configured to selectively latch a plurality of external signals and output the latched signal; and a control unit coupled to the input unit, the control unit configured to control the operations of the input unit according to an operation mode of the semiconductor memory apparatus is described herein.07-09-2009
20090175092Semiconductor Memory Devices for Controlling Latency - A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the second and third internal clock signals and the delayed signals, and a data output buffer that outputs the data in response to the latency signal and the third internal clock signal.07-09-2009
20100027354SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING SAME - A semiconductor memory device includes data input/output terminals (DQ02-04-2010
20110051531DATA OUTPUT CONTROL CIRCUIT OF A DOUBLE DATA RATE (DDR) SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE RESPONSIVE TO A DELAY LOCKED LOOP (DLL) CLOCK - A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock.03-03-2011
20110051530SEMICONDUCTOR MEMORY DEVICE AND METHOD OF UPDATING DATA STORED IN THE SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.03-03-2011
20110051529MEMORY DEVICE - Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The first pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate.03-03-2011
20100034030DOUBLE EDGE TRIGGERED FLIP-FLOP CIRCUIT - In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal. A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either one of rising edge and falling edge of the clock signal. At least one of the first latch circuit and the second latch circuit is configured by an SRAM (Static Random Access Memory) type.02-11-2010
20110305093DATA INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the data input/output buffer, in response to the first driving control signal. A second timing control unit controls an active timing of a second control signal to output a second driving control signal. A second data input/output unit transmits the write data from the global input/output line to a local input/output line or transmits the read data from the local input/output line to the global input/output line, in response to the second driving control signal.12-15-2011
20120099386SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.04-26-2012
20080247242Method Using a One-Time Programmable Memory Cell - A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states.10-09-2008
20110110165CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.05-12-2011
20120039134DATA OUTPUT CIRCUIT IN A SEMICONDUCTOR MEMORY APPARATUS - A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.02-16-2012
20120039133SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION - To provide a semiconductor device including a temperature detection circuit that detects a temperature of the semiconductor device and outputs temperature information, a counter circuit that takes a count of repeated inputs of a refresh command and outputs count information, a comparison circuit that activates a match signal when the temperature information matches the count information, and a refresh control circuit that controls whether to perform a refresh operation according to activation of the refresh command based on the match signal. According to the present invention, a refresh cycle can be finely adjusted because the repeated inputs of the refresh command are thinned out based on the temperature information. With this configuration, power consumption caused by the refresh operation can be reduced.02-16-2012
20090161443PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register.06-25-2009
20090097330Fuse latch circuit and fuse latch method - A fuse latch circuit starts a precharge operation for reading out a state of a fuse element when receiving an external command which is a command to reset an operation mode register (MRS reset command) after power-on, and reads out and latches the state of the fuse element after completion of the precharge operation.04-16-2009
20090154255Symmetrically operating single-ended input buffer devices and methods - Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor that charges and discharges the drain of the second transistor responsive to the input signal transitioning to mimic the second input node transitioning in the direction opposite to the transition of the input signal, while the reference signal at the second input node is maintained at a constant voltage level.06-18-2009
20110063925Semiconductor device and semiconductor package including the same - To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.03-17-2011
20110317496JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA - A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.12-29-2011
20110317497NON-VOLATILE MEMORY DEVICE - A non-volatile memory device for measuring a read current of a unit cell is disclosed. The non-volatile memory device includes a unit cell configured to read or write data, a column switching unit configured to select the unit cell in response to a column selection signal, a sense amplifier controlled by a sense-amplifier enable signal, configured to sense and amplify data that is received from the unit cell through the column switching unit, a first latch unit configured to latch the sense-amplifier enable signal for a predetermined time when a test code signal received from an external part is activated, a column controller configured to output a latch control signal in response to a combination of a column switch-off signal and a column control signal, and a second latch unit configured to control whether or not the column selection signal is latched in response to an activation state of the latch control signal.12-29-2011
20110158005Data Access Apparatus and Associated Method for Accessing Data Using Internally Generated Clocks - The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data at the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.06-30-2011
20120044773SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.02-23-2012
20120008423SETTING CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.01-12-2012
20120008426HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY - A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.01-12-2012
20120008424NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a plurality of latches for storing data, a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node, a transmission circuit for transferring the data of the common node to a first sense node, a bit line transmission circuit for transferring the data of the first sense node to a bit line, a sense circuit for transferring the data of the first sense node to a second sense node, and a discharge circuit for changing a voltage level of the common node based on the data of the second sense node.01-12-2012
20120008422SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a memory bank configured to output stored data in response to a column selection signal, a plurality of data latching units configured to latch the data outputted from the memory bank in response to an input control signal which is generated according to the column selection signal, and output the latched data in response to an output control signal, a time measurement unit configured to measure a time from an activation of the input control signal to an activation of the output control signal and generate a delay control signal, and an activation control unit configured to control an activation time of the column selection signal in response to the delay control signal.01-12-2012
20120008421DATA OUTPUTING METHOD OF MEMORY CIRCUIT AND MEMORY CIRCUIT AND LAYOUT THEREOF - A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9] via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], the batch of data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1], for n is an integer from 0 through 2, and from 4 through 6.01-12-2012
20090067261Multi-port memory device - A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.03-12-2009
20120057412MEMORY MACRO CONFIGURATION AND METHOD - A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments.03-08-2012
20120014189Semiconductor memory device and test method thereof - Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.01-19-2012
20120057413SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.03-08-2012
20120014190Refresh Signal Generating Circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.01-19-2012
20120300559SEMICONDUCTOR MEMORY INCLUDING PADS COUPLED TO EACH OTHER - A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.11-29-2012
20120300558METHOD AND APPARATUS FOR SYNCHRONIZING DATA FROM MEMORY ARRAYS - According to one embodiment, a device for synchronizing data output from two or more memory arrays that includes a plurality of sense circuits configured to be responsive to a clock signal. The device further includes a plurality of latches and a tracking circuit. The tracking circuit may be configured to produce a control signal responsive to the clock signal. The control signal may be operable to enable the plurality of latches. The tracking has an associated delay that is substantially the same as a delay associated with at least one of the plurality of sense circuits.11-29-2012
20120113729MEMORY INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE - There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access.05-10-2012
20120113728DATA INPUT CIRCUIT - A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.05-10-2012
20120300557SEMICONDUCTOR CELL AND SEMICONDUCTOR DEVICE - A technology is a semiconductor cell and a semiconductor device capable of reducing the coupling capacitance between adjacent bit lines by forming a bit line junction region in a separated island shape when forming a buried bit line, thereby improving characteristics of the semiconductor devices. The semiconductor cell includes a transistor including a gate and a gate junction region, a plurality of buried bit lines disposed to intersect the gate, and a plurality of bit line junction regions, each bit line junction region having an island shape formed between the buried bit lines and connected to the buried bit line.11-29-2012
20120300556DEVICES AND SYSTEMS INCLUDING ENABLING CIRCUITS - Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.11-29-2012
20100110800DATA OUTPUT CIRCUIT AND METHOD - A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same number of bits as that of the first parallel data signals in response to the first strobe signal and the first delayed strobe signal, a storing block configured to latch the second parallel data signals in response to a second strobe signal and a second delayed strobe signal, and a parallel-to-serial converting block configured to sequentially output the second parallel data signals latched in the storing block, wherein the first strobe signal is used to generate a data signal that is outputted first among the second parallel data signals.05-06-2010
20120026803DATA OUTPUT CIRCUIT AND METHOD - A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same number of bits as that of the first parallel data signals in response to the first strobe signal and the first delayed strobe signal, a storing block configured to latch the second parallel data signals in response to a second strobe signal and a second delayed strobe signal, and a parallel-to-serial converting block configured to sequentially output the second parallel data signals latched in the storing block, wherein the first strobe signal is used to generate a data signal that is outputted first among the second parallel data signals.02-02-2012
20120063242DATA RECEIVER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal03-15-2012
20100254197Latch Pulse Delay Control - A novel memory circuit includes a pulse line, a memory latch including an enable port, and a pulse delay element interposed between the pulse line and the enable port of the memory latch. In a particular embodiment, the pulse delay element includes a series of logic gates. In a more particular embodiment, the series of logic gates include a feedback line for disconnecting the enable port from the pulse line. In another particular embodiment, the enable ports of two different memory latches are connected to the same pulse line via two different latch pulse delay elements, each having different delay times. In a more particular embodiment, the data output port of the first latch is connected to the data input port of the second latch.10-07-2010
20100195411SEMICONDUCTOR MEMORY DEVICE AND FAIL BIT DETECTION METHOD IN SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes a plurality of pages. Each page of the plurality of pages is divided into a plurality of segments, and one segment is constituted of a plurality of bytes. A fail detection circuit receives signals of the plurality of fail bit detection signal lines, and the fail detection circuit collectively detects presence/absence of a fail bit in the memory cell array in units of segments.08-05-2010
20120206980BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.08-16-2012
20090135660Apparatus, memory device and method of improving redundancy - An apparatus includes a memory device. The memory device includes a first memory cell column which includes a plurality of first memory cells, a second memory cell column including a plurality of second memory cells, a detector which detects a delay of a memory cell signal outputted from at least one of the first memory cells, and a selector which selects the second memory cell column instead of the first memory cell column when the delay exceeds a predetermined criteria.05-28-2009
20120155190PAGE BUFFER CIRCUIT - A page buffer circuit includes: a main latch unit configured to have a main latch value which is dependent on a sub latch output signal, and output the main latch value to a first node; a sub latch unit configured to latch a voltage of a second node as a sub latch value in response to a storage enable signal, and generate the sub latch output signal according to the sub latch value when an output enable signal is activated; and a voltage determination unit connected between the first node and the second node, and configured to electrically connect or disconnect the first node to or from the second node in response to the storage enable signal, and determine a voltage level of the second node in response to the storage enable signal.06-21-2012
20100329039DATA BUFFER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A data buffer control circuit and a semiconductor memory apparatus including the same are presented. The data buffer control circuit may include an internal command signal generator and a buffer enable signal generator. The internal command signal generator is configured to generate an internal command signal that is activated if delayed command signals are conditioned in a predetermined state of level combination. The buffer enable signal generator is configured to generate a buffer enable signal, which enables a data buffer receiving data in a writing mode, from the internal command signal in sync with a falling edge of an internal clock signal.12-30-2010
20120155192SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING THE SAME - A semiconductor memory device and a method of testing the same are provided. The semiconductor memory device includes a memory cell array including a plurality of memory cells each of which stores at least one bit of data; an output terminal configured to transmit output data; and a data output circuit configured to be connected with the output terminal, to divide a cycle of a clock signal into at least two periods, to transmit the output data to the output terminal only during a particular period among the at least two periods, and to put the output terminal into a state of high impedance during the remaining periods other than the particular period among the at least two periods.06-21-2012
20120155193BURST TERMINATION CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME CROSS-REFERENCES TO RELATED APPLICATION - A semiconductor memory device includes a burst termination control unit and a data output control unit. The burst termination control unit generates a termination control signal, a read command, a write command and a mode resister read command. The data output control unit stops a data output operation in response to the termination control signal.06-21-2012
20120155191SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory configured to receive a first clock and including a first buffer configured to perform a data input operation and a data output operation, a second memory including a second buffer configured to perform a data input operation and a data output operation, and a data bus configured to connect the first buffer and the second buffer. The first memory transfers a second clock to the second memory using the first clock. The first buffer transfers data to the second memory in response to the first clock. The second buffer receives the data from the first buffer in response to the second clock.06-21-2012
20120106265SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal, a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time, and a data input block configured to load the data on the data transfer line in response to the write operation signal.05-03-2012
20110103157TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY - In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.05-05-2011
20110103156DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response to a chip selection signal, and outputs data to a connected rank or receives data from the connected rank. The data input/output section outputs the data transmitted from the rank selecting section through a data pad to an external device during a read operation, and outputs the data inputted to the data pad to the rank selecting section during a write operation.05-05-2011
20110032774Semiconductor Memory With Improved Memory Block Switching - A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.02-10-2011
20100091581Memory device and method of operating such a memory device - A memory device, and method of operation of such a device, are provided. The memory device comprises an array of memory cells arranged in a plurality of rows and a plurality of columns, at least one bit line being associated with each column. Column multiplexer circuitry is coupled to the plurality of columns, for inputting write data into a selected column during a write operation and for outputting an indication of read data sensed from a selected column during a read operation. The column multiplexer circuitry comprises a single pass gate transistor per bit line, and latch circuitry is then used to detect the read data from the indication of read data output by the column multiplexer circuitry during the read operation, and to store that detected read data. Such an approach provides a particularly area efficient construction for the column multiplexer circuitry whilst enabling correct evaluation of the read data held in the addressed memory cell.04-15-2010
20120120736Self Pre-Charging and Equalizing Bit Line Sense Amplifier - A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors.05-17-2012
20120120735SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSE AND CONTROL METHOD THEREOF - To provide a plurality of fuse elements, each of which is either in a programmed state or a non-programmed state, a plurality of fuse determination circuits, each of which outputs a determination result signal that corresponds to a programmed state or a non-programmed state of the fuse element, and a plurality of latch circuits that commonly receive a first timing signal, and each of which latches and outputs the determination result signal synchronously with the first timing signal.05-17-2012
20120120734DOUBLE LINE ACCESS TO A FIFO - An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in the second format and (ii) present the data in the second format. The read data buffer circuit may be configured to (i) receive data in the second format and (ii) present data in a third format. The memory may be configured to allow two reads or two writes during a single clock cycle of reference clock without encountering a data overflow condition.05-17-2012
20090185430Memory sensing and latching circuit - According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.07-23-2009
20110110166SEMICONDUCTOR DEVICE - The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.05-12-2011
20110116326Refresh Signal Generating Circuit - A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.05-19-2011
20100290294Signal margin improvement for read operations in a cross-point memory array - A configuration for biasing conductive array lines in a two-terminal cross-point memory array is disclosed. The configuration includes applying a read voltage to a selected X-conductive array line while applying an un-select voltage thru a biasing element to a remaining plurality of un-selected X-conductive array lines. A plurality of Y-conductive array lines are initially biased to some voltage (e.g., 0V) and then allowed to float unbiased after a predetermined amount of time has passed, some event has occurred, or both. As one example the event that triggers the floating of the plurality of Y-conductive array lines can be the read voltage reaching a predetermined magnitude. The array can be formed BEOL and include a plurality of two-terminal memory cells with each memory cell including a memory element and optionally a non-ohmic device (NOD) that are electrically in series with each other and with the two terminals of the memory cell.11-18-2010
20120314510SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.12-13-2012
20120314511SEMICONDUCTOR DEVICE - A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.12-13-2012
20120163100AUTO-PRECHARGE SIGNAL GENERATOR - An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.06-28-2012
20120127806MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR - A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor.05-24-2012
20120163099MODE-REGISTER READING CONTROLLER AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a mode-register reading controller and a mode register. The mode-register reading controller generates a control signal for loading data into an input/output line in response to an enable signal, during a mode-register reading operation. The control signal is generated in response to a mode-register read signal when there is a reset command is input. The mode register loads the data into the input/output line in response to the control signal.06-28-2012
20120163098SEMICONDUCTOR MEMORY DEVICE INCLUDING MODE REGISTER SET AND METHOD FOR OPERATING THE SAME - A semiconductor memory device and method for operating the same includes a controller configured to generate a data buffer control signal in a mode register set (MRS) mode, a data buffer configured to buffer and output a plurality of MRS codes inputted through a data pad in response to the data buffer control signal, and a plurality of MRS command generators configured to receive the MRS codes outputted from the data buffer through a data line and generate a plurality of MRS commands based on the received MRS codes.06-28-2012
20120213011SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal.08-23-2012
20120213010Asymmetric Sense Amplifier Design - A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.08-23-2012
20120213012STROBE APPARATUS, SYSTEMS, AND METHODS - A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.08-23-2012
20120134217SEMICONDUCTOR DEVICE HAVING PLURAL BANKS - A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.05-31-2012
20120250425SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY CONTROL METHOD - According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.10-04-2012
20120250424SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.10-04-2012
20110188324SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.08-04-2011
20120250423INPUT CIRCUIT - The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.10-04-2012
20080310240Semiconductor memory device having I/O unit - A semiconductor memory device is capable of reducing a test time upon the same condition of the actual operation thereof. The semiconductor memory device includes an output data select unit and a data output unit. The output data select unit selectively outputs valid data, which are loaded on a plurality of global lines, in response to an output control signal activated after a delay time corresponding to an additive latency from entry of a read operation in a test mode. The data output unit aligns data outputted from the output data select unit and outputs the aligned data through data pads.12-18-2008
20120176846Threshold Voltage Digitizer for Array of Programmable Threshold Transistors - A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as the ramp voltage is being applied, generating a respective control signal in response to sensing a predetermined threshold current along a respective bitline in the memory array, wherein each transistor in the memory array is in communication with a respective bitline in the memory array; and for each transistor in the memory array, latching a current value of the incrementing digital code in response to the respective control signal corresponding to the transistor being generated. The current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor.07-12-2012
20100008156SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a plurality of input units configured to receive a plurality of data, a plurality of latching units configured to latch output signals of the plurality of input units in response to a plurality of synchronization clock signals, and a synchronization clock generating unit configured to delay a source clock signal by a time corresponding to each of signal transmission times taken between the plurality of input units and the plurality of latching units, thereby generating the plurality of synchronization clock signals.01-14-2010
20120188828DATA CAPTURE SYSTEM AND METHOD, AND MEMORY CONTROLLERS AND DEVICES - Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.07-26-2012
20120257461METHOD OF TESTING A SEMICONDUCTOR MEMORY DEVICE - A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array.10-11-2012
20120262996DEVICE - Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.10-18-2012
20120262995SEMICONDUCTOR ELEMENT, MEMORY CIRCUIT, INTEGRATED CIRCUIT, AND DRIVING METHOD OF THE INTEGRATED CIRCUIT - A novel semiconductor element contributing to an increase in circuit scale is provided. In the semiconductor element, two different electrical switches are formed using a single oxide semiconductor layer. For example, in the semiconductor element, formation of a channel (a current path) in the vicinity of a bottom surface (a first surface) of the oxide semiconductor layer and formation of a channel in the vicinity of a top surface (a second surface) of the oxide semiconductor layer are independently controlled. Therefore, the circuit area can be reduced as compared to the case two electrical switches are separately provided (for example, the case where two transistors are separately provided). That is, a circuit is formed using the semiconductor element, whereby an increase in the circuit area due to an increase in circuit scale can be suppressed.10-18-2012
20120081973METHOD AND APPARATUS FOR TIMING ADJUSTMENT - A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.04-05-2012
20120081974INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY - An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.04-05-2012
20100309733NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory.12-09-2010
20120230125SEMICONDUCTOR MEMORY DEVICE AND METHODS THEREOF - According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.09-13-2012
20120230124LATCH SYSTEM APPLIED TO A PLURALITY OF BANKS OF A MEMORY CIRCUIT - A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.09-13-2012
20110122709Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit - A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.05-26-2011
20100008157SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DETECTING WRITE COMPLETION AT HIGH SPEED - A memory cell array has a plurality of memory cells arrayed in row and column directions. A plurality of sense amplifier units includes a plurality of sense amplifiers detecting write completion of each of the memory cells selected for each row. A plurality of detection units is arranged correspondingly to the sense amplifier units, and forms a transfer path for transferring potential in accordance with a detection output signal of each sense amplifier unit. The detection units detect a sense amplifier unit corresponding to a portion where the transfer path breaks off, as a sense amplifier unit including write incompletion bit.01-14-2010
20080298138Semiconductor device - Disclosed is a semiconductor device comprising: a signal selecting circuit for receiving, at first and second inputs thereof, respectively, a first signal output from a first initial-stage circuit that receives a data strobe signal from a first terminal, which is an input/output terminal, and a second signal output from a second initial-stage circuit that receives a data mask signal from a second terminal, which is an input terminal, and based upon a control signal that is supplied thereto, outputting the first and second signals from first and second outputs or interchanging the first and second signals and outputting the interchanged first and second signals from the second and first outputs; a buffer circuit for receiving an output signal from a third initial-stage circuit that receives a data signal from a data terminal; and a data latch circuit for latching a signal from the buffer circuit. The signal from the first output of the signal selecting circuit is supplied to the data latch circuit as a latch timing signal.12-04-2008
20120327723SEMICONDUCTOR DEVICE - A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.12-27-2012
20120269006SEMICONDUCTOR DEVICE - A semiconductor device is capable of reducing the coupling capacitance between adjacent bit lines by forming an air-gap at an opposite side of a one side contact when forming a buried bit line or increasing a thickness of an insulating layer, thereby improving characteristics of the semiconductor devices. The semiconductor device includes a plurality of line patterns including one side contacts, a bit line buried in a lower portion between the line patterns, a bit line junction region formed within each of the line patterns at one side of the bit line, and an air-gap formed between the other side of the bit line and each of the line patterns.10-25-2012
20120269005SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a plurality of first pads and a plurality of memory unit blocks. The plurality of first pads are configured to input/output data in a test mode. The plurality of memory unit blocks each include a plurality of second pads configured to input/output data in a normal mode, and a plurality of data path selection units configured to connect internal circuits of the corresponding memory unit block to the plurality of first pads or the plurality of second pads in response to a unit block selection flag signal, a write enable signal, a read enable signal, and a mode control signal.10-25-2012
20120269007SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING OUT THE SAME - A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.10-25-2012
20100226185SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM HAVING TERMINATION RESISTOR UNITS - A semiconductor memory module includes a memory module board having at least one semiconductor memory device, an advanced memory buffer (AMB) for receiving the data and the command/address signal from a host and providing the data and the command/address signal to the at least one semiconductor memory device, and a second termination resistor unit located on the memory module board and electrically connected to the AMB. The at least one semiconductor memory device includes a data input buffer for receiving data via a first input terminal and receiving a first reference voltage via a second input terminal, a command/address input buffer for receiving a command/address signal via a first input terminal and receiving a second reference voltage via a second input terminal, and a first termination resistor unit connected to the first input terminal of the data input buffer.09-09-2010
20100254198WRITE COMMAND AND WRITE DATA TIMING CIRCUIT AND METHODS FOR TIMING THE SAME - Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. The FF circuit latches the internal write command in response to an internal write command FF signal based on a write clock signal and generates an internal write enable signal in response to latching the internal write command. The write data register captures write data in response to the write clock signal and releases the captured write data in response to a delayed internal write enable signal.10-07-2010
20120275238MEMORY CIRCUIT AND CONTROL METHOD THEREOF - A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.11-01-2012
20110261627SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - In a semiconductor nonvolatile memory device, nonvolatile memory cells are plurally arranged in a memory array portion. An output circuit outputs setting information selected from plural sets of setting information to generate reference currents with different current values. A reference current circuit generates a reference current with a current value according to the setting information outputted from the output circuit. An amplifier circuit compares a cell current outputted from a selected memory cell of the memory array portion with the reference current generated by the reference current circuit.10-27-2011
20120287729SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array including a plurality of memory array basic units, a first bus for transfer of address/control signals, including a first buffer circuit operating as a pipeline register, a second bus for bidirectional transfer of write/read data, including a second buffer circuit operating as a pipeline register, a first control circuit sequentially sending the address/control signals on the first bus, and a second control circuit sequentially sending/receiving write/read data on the second bus (FIG. 11-15-2012
20100202219BURN-IN METHODS FOR STATIC RANDOM ACCESS MEMORIES AND CHIPS - A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.08-12-2010
20130010543MEMORY DEVICE HAVING SWITCH PROVIDING VOLTAGE TO BIT LINE - A memory device in which a circuit reads a cell condition. A terminal provides voltage to a bit line of the circuit via a switch. The circuit outputs and enables storage of a first logical value when the voltage provided from the terminal does not exceed a threshold value. The circuit outputs and enables storage of a second logical value when the voltage provided from the terminal exceeds the threshold value. The output and storage occurs in the absence of an electrical connection between the cell and circuit. The switch provides voltage supplied from the terminal to the bit line of the circuit. The voltage increases from a value which does not exceed the threshold to a value which exceeds the threshold.01-10-2013
20130010544LEAKAGE-AWARE KEEPER FOR SEMICONDUCTOR MEMORY - A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.01-10-2013
20130016572SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array block including a plurality of memory cells each including a data holding circuit configured to store data using a first and a second circuit elements and a transistor configured to connect the data holding circuit and a bit line together, sense amplifiers connected to bit lines directly or via switches, and a dummy memory cell array including a plurality of dummy memory cells each having the same circuit configuration as that of the memory cell with respect to the element size and the layout configuration. The plurality of dummy memory cells each include at least one inverter circuit configuration, and are connected together by the inverter circuits being connected together in series. An output signal of the inverter circuit of one in the final stage of the dummy memory cells is an activation signal for the sense amplifiers.01-17-2013
20130021852NONVOLATILE MEMORY AND METHOD OF CONTROLLING THEREOF - A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system. The controller is configured to control a sensing operation of the nonvolatile memory. An operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed.01-24-2013
20130021853SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - An embodiment of the present invention provides a semiconductor device, including cell string comprising a plurality of memory cells; page buffer comprising latch and switching element, wherein the switching element is coupled between the latch and the bit line which is coupled to the cell string; and a page buffer controller configured to apply a gradually rising turn-on voltage to the switching elements during a bit line setup operation of a program operation.01-24-2013
20130021851ANTI-FUSE CIRCUIT AND METHOD FOR ANTI-FUSE PROGRAMMING AND TEST THEREOF - An anti-fuse circuit including a plurality of programmable units and a test module is provided. The programmable units receive a stress voltage, a program data, and a write enable signal. During a programming period, the programmable units sequentially transmit the program data. When the write enable signal is enabled, the stress voltage stresses the programmable units according to the program data, and the programmable units output programming results for test. The test module is coupled to the programmable units and receives the program data and the programming results. During a test period, the test module compares the programming results with the program data and outputs different logic levels according to a result of the comparison of the first programming results and the program data. A method for anti-fuse programming and test adapted to the foregoing anti-fuse circuit is also provided.01-24-2013
20120243342SENSE AMPLIFICATION CIRCUITS, OUTPUT CIRCUITS, NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS, MEMORY CARDS HAVING THE SAME, AND DATA OUTPUTTING METHODS THEREOF - An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation.09-27-2012
20130170304MEMORY INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE - There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access.07-04-2013
20080225606DATA OUTPUT CIRCUIT AND METHOD IN DDR SYNCHRONOUS SEMICONDUCTOR DEVICE - Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.09-18-2008
20080225605LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME - A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.09-18-2008
20080225604SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory having a plurality of memory cells coupled to bit lines includes a bit line selecting circuit, a latch circuit, and a switching circuit. The bit line selecting circuit is disposed in a cell area where the memory cells are formed. The bit line selecting circuit is configured to select one of the bit lines in response to a first control signal. The latch circuit is disposed in a surrounding circuit area. The latch circuit is configured to perform a program operation or a read operation on the memory cells corresponding to the bit line selected by the bit line selecting circuit. The switching circuit is disposed in the surrounding circuit area, and is coupled between the bit line selecting circuit and the latch circuit. The switching circuit is configured to switch between the bit line selecting circuit and the latch circuit in response to a second control signal.09-18-2008
20080225603Circuit - An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.09-18-2008
20130141990MEMORY CONTROL DEVICE - A memory control device that can reduce a power consumption at the time of writing a memory. The memory control device includes a data output buffer circuit that burst-transfers data to a memory device through a data bus, and a mask signal output buffer circuit that outputs, to the memory device, a mask signal indicative of data that prohibits write into a memory cell within the memory device among the data. The data output buffer circuit puts an output node into a high impedance state when the mask signal is indicative of write prohibition.06-06-2013
20130176795Enhanced Power Savings for Memory Arrays - A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.07-11-2013
20130141988MEMORY WITH A SHARED I/O INCLUDING AN OUTPUT DATA LATCH HAVING AN INTEGRATED CLAMP - A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.06-06-2013
20130141989SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a plurality of memory banks, wherein each memory bank includes a bank control unit configured to reduce a voltage level of a first node to a ground voltage level when the memory bank is selected to perform a predetermined operation; an error control unit configured to supply an external voltage to the first node when the memory bank is not selected to perform the predetermined operation; and a signal generation unit configured to generate a bank operation signal in response to the voltage level of the first node.06-06-2013
20130135943MEMORY CIRCUIT AND MEMORY DEVICE - To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.05-30-2013
20130135942PIPE LATCH CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A pipe latch control circuit and a semiconductor integrated circuit using the same are provided. The pipe latch control circuit includes a read command control unit that receives a first signal and generates a read signal in response to a control signal. In the pipe latch control circuit, the read command control unit selects, in response to the control signal, the first signal or selects a second signal obtained by delaying the first signal according to an internal clock, and generates the selected first or second signal as the read signal.05-30-2013
20130114348SELF REFRESH PULSE GENERATION CIRCUIT - A self refresh pulse generation circuit includes a control signal generator configured to generate a control signal asserted for an initial period of a self refresh mode, and a self refresh pulse generator configured to generate a self refresh pulse having a period controlled in response to the control signal, in the self refresh mode.05-09-2013
20130094303Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory - Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.04-18-2013
20130094302INTEGRATED CIRCUIT CHIP AND SEMICONDUCTOR MEMORY DEVICE - An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.04-18-2013
20130114350SEMICONDUCTOR MEMORY DEVICE INCLUDING INITIALIZATION SIGNAL GENERATION CIRCUIT - An initialization signal generation circuit includes: an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as the auto refresh signal in response to the flag signal and an auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal, which is delayed by at least a pulse width of the refresh counting signal, after a time point where a combination of the counting signal becomes a preset combination.05-09-2013
20130114351SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF - A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of test data periodically in response to a data reference voltage whose voltage level is determined in response to a level test code during a test operation period defined by a test entry command and a test exit command, and generate a test result signal by comparing a logic level of the comparison data with the logic level of the test data; and a test operation sensing signal generation unit configured to generate a test operation sensing signal that is activated in response to the test entry command and inactivated in response to the test result signal.05-09-2013
20130100746METHODS AND APPARATUS OF STACKING DRAMS - Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.04-25-2013
20130114347SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM - A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.05-09-2013
20130114352SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.05-09-2013
20130114349SEMICONDUCTOR SYSTEM INCLUDING A CONTROLLER AND MEMORY - A semiconductor system includes three or more memory chips and a controller with first and second memory buffers configured to communicate with the three or more memory chips. The first and second memory buffers alternately transmit data to sequentially communicate with the three or more memory chips.05-09-2013
20130128675NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM AND CONTROLLER OPERATING METHOD - An operating method for a memory system provides a ready/busy signal from a nonvolatile memory device indicating an idle state or a busy state to a controller. The controller generates a next command but transfers the next command to the nonvolatile memory device in response to the ready/busy signal and the idle verse busy state of a target plane among multiple planes of the nonvolatile memory device.05-23-2013
20100277987SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - Systems and methods for programming data to a memory device (MD). The methods involve receiving the data at MD (11-04-2010
20110216606DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.09-08-2011
20080198671Enqueue Event First-In, First-Out Buffer (FIFO) - In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write control logic. The queue is configured to store a plurality of data items, wherein each data item has a type which is one of a plurality of types of data items that can be stored in the queue. The write control logic is configured to maintain write pointers that identify entries in the queue for each of the plurality of types. The write control logic is configured to update the write pointer corresponding to an input type for an input data item written to the queue. Additionally, the write control logic is configured to enqueue a write event in the FIFO to transport the enqueue event to a read clock domain different from the write clock domain.08-21-2008
20110235438TEMPORAL ALIGNMENT OF DATA UNIT GROUPS IN A SWITCH - Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available.09-29-2011
20120275240SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address.11-01-2012
20130155784SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.06-20-2013
20130155785MEMORY MACRO CONFIGURATION AND METHOD - A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments.06-20-2013
20130182511DIGITAL MEMORY SYSTEM THAT DYNAMICALLY ADJUSTS REFERENCE VOLTAGE AS A FUNCTION OF TRAFFIC INTENSITY - A digital memory system includes a memory controller having a driver configured for generating a digital signal. A memory module has a receiver in communication with the driver. The driver is configured for selectively directing the digital signal to the receiver of the memory module. A voltage control module is configured for determining a traffic intensity at which the digital signal is directed to the receiver and dynamically adjusting the reference voltage as a function of the traffic intensity at which the digital signal is directed to the receiver.07-18-2013
20130155782RANDOM ACCESS MEMORY AND REFRESH CONTROLLER THEREOF - A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result.06-20-2013
20130155783FAST-BYPASS MEMORY CIRCUIT - A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.06-20-2013
20130155779SEMICONDUCTOR STORAGE DEVICE, HOST CONTROLLING THE SAME, AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR STORAGE DEVICE AND THE HOST - According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data.06-20-2013
20130155780APPARATUSES AND METHODS FOR COMPARING A CURRENT REPRESENTATIVE OF A NUMBER OF FAILING MEMORY CELLS - Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.06-20-2013
20130155781FAST-BYPASS MEMORY CIRCUIT - A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.06-20-2013
20120281486SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY - A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.11-08-2012
20120281485DATA STORAGE SYSTEM, ELECTRONIC SYSTEM, AND TELECOMMUNICATIONS SYSTEM - A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should be written. The write pointer points at least one buffer ahead of the buffer to which the read pointer is pointing. An electronic system and a telecommunications system are further disclosed.11-08-2012
20110310677Semiconductor Memory Device Capable of Read Out Mode Register Information Through DQ Pads - A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a mode register read signal and generate a flag signal and at least one output information signal, and a global I/O line latch unit for transferring the output information signal to a global I/O line in response to the flag signal.12-22-2011
20130188428APPARATUSES, CIRCUITS, AND METHODS FOR REDUCING METASTABILITY IN LATCHES - Apparatuses, circuits, and methods are disclosed for reducing metastability in latches. In one such example apparatus, a circuit is configured to provide substantially complementary first and second signals and a latch stage is configured to latch the first and second signals. The latch stage includes a feedback circuit configured to provide positive feedback between the latched first and second signals.07-25-2013
20120008425SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array including a plurality of memory cells, circuits configured to receive program data when a program operation is performed and output a random signal in response to the program data, and a page buffer configured to logically combine the program data and the random signal and to store the logically combined data in the memory cells.01-12-2012
20130194877MEMORY AND METHOD OF OPERATING THE SAME - A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.08-01-2013
20130201767SEMICONDUCTOR MEMORY APPARATUS, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME - A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.08-08-2013
20130208548Method and Apparatus for Copying Data With A Memory Array Having Redundant Memory - A page copy operation such as copy back programming is performed between a source page of the memory array and a destination page of the memory array in different segments. The segments divide the columns of the main array and the set of redundant columns of the redundant array into, for example, sets of rows. The copy back programming transfers data from a part of the source page in the redundant array to a part of the destination page in the main array, and transfers data from a part of the source page in the main array to a part of the destination page in the redundant array.08-15-2013
20130208549PHASE INTERPOLATORS AND PUSH-PULL BUFFERS - Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.08-15-2013

Patent applications in class Having particular data buffer or latch