Entries |
Document | Title | Date |
20080219064 | Semiconductor memory apparatus with write training function - A semiconductor memory apparatus having a write training function includes a storage unit that stores write data or read data output from a memory cell block and outputs data according to an output control signal, and a control unit that controls the output control signal to be generated at different timings according to whether or not a write training signal is activated. | 09-11-2008 |
20080225612 | SEMICONDUCTOR MEMORY DEVICE - According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell by an operation to read a replica cell to which a replica bit line having a load equivalent to a bit line to be connected to the memory cell and a replica word line are connected, the semiconductor memory device comprising: a write control signal generating unit that includes logic gates coupled in multi stages for receiving an input of a replica word line activating signal generated in response to a driving signal for driving the replica word line, the write control signal generating unit generating a write control signal to determine a data write time required to write data in the memory cell based on the replica word line activating signal. | 09-18-2008 |
20080247245 | WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS - Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal. | 10-09-2008 |
20080253204 | Semiconductor memory apparatus including synchronous delay circuit unit - A semiconductor memory apparatus includes a write driver that receives data transmitted through an input/output line, and a synchronous delay circuit unit that generates an enable signal so as to allow the data transmitted through the input/output line to be supplied to the write driver. | 10-16-2008 |
20080253205 | WRITE CONTROL SIGNAL GENERATION CIRCUIT, SEMICONDUCTOR IC HAVING THE SAME AND METHOD OF DRIVING SEMICOUNDUCTOR IC - A write control signal generation circuit includes a delay/comparison/transmission block that outputs one of a delayed write command signal and a write command signal according to a test mode signal, and a control signal generation unit that generates a write control signal by delaying the output of the delay/comparison/transmission block corresponding to a variable amount of delay. | 10-16-2008 |
20080259699 | Memory Control With Selective Retention - The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines ( | 10-23-2008 |
20080285362 | Semiconductor memory device - A semiconductor memory device has a memory cell having a hierarchical bit line structure for large capacity even in a small cell size. The semiconductor memory device comprises a unit cell configured to read/write data, a cell data sensing unit configured to adjust a current amount of a main bit line depending on a sensing voltage of a sub bit line when data are sensed, and a write control unit configured to store data in the corresponding unit cell depending on a current level applied from the main bit line to the sub bit line. | 11-20-2008 |
20080304339 | Apparatus and Method of Operating an Integrated Circuit Technical Field - The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state. | 12-11-2008 |
20090010081 | OVERDRIVE WRITE METHOD, WRITE AMPLIFIER POWER GENERATING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage). | 01-08-2009 |
20090021994 | MEMORY AND METHOD FOR PROGRAMMING THE SAME - A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data. | 01-22-2009 |
20090021995 | Early Write Method and Apparatus - A write operation is performed in a memory device. During a first stage of the write operation, a signal is applied to gating circuitry at a first voltage level for coupling a data bus line to a bit line when the data bus line is unmasked and for decoupling the data bus line from the bit line when the data bus line is masked. During one or more subsequent stages of the write operation, the signal voltage level is changed for enabling completion of the write operation. | 01-22-2009 |
20090021996 | Memory Circuit, Memory Component, Data Processing System and Method of Testing a Memory Circuit - A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control circuit. The bit line control circuit is configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected. | 01-22-2009 |
20090034348 | WRITE DRIVER CIRCUIT OF AN UNMUXED BIT LINE SCHEME - A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver. | 02-05-2009 |
20090040841 | Method of Operating an Integrated Circuit Having at Least One Memory Cell - Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state. | 02-12-2009 |
20090040842 | Enhanced write abort mechanism for non-volatile memory - In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal. | 02-12-2009 |
20090040843 | Enhanced write abort mechanism for non-volatile memory - In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal. | 02-12-2009 |
20090046522 | METHOD FOR WRITING DATA IN A NON VOLATILE MEMORY UNIT - A method for writing data in a non volatile memory unit having memory pages includes a predetermined number of memory cells storing a memory word being a predetermined sequence of digital values. An erase operation erases the memory words in the memory page, setting the predetermined sequence of digital values to a sequence of complementary values. A program operation stores in the memory cell a word and sets a sequence of a word to be stored. For the memory cells of the memory page, the memory word is compared with the word to be stored. A positive check is returned if complementary values of the sequence correspond to complementary values of the predetermined sequence. If the check is negative, the erase operation is executed. The memory word is compared with the word to be stored and the program operation is executed if the word to be stored is different. | 02-19-2009 |
20090067266 | MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE - Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read. | 03-12-2009 |
20090086556 | Methods and apparatuses for operating memory - A low voltage memory apparatus is disclosed. The memory apparatus can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and a bit cell isolator to isolate at least a portion of the bit cell from a power return during a write cycle. Isolating a cross coupled flip flop in the bit cell during a write cycle can provide faster write times, increased write reliability and can reduce the effects of device variations on bit cell operation, particularly for low voltage applications. Other embodiments are also disclosed. | 04-02-2009 |
20090091991 | Apparatuses and methods for multi-bit programming - Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a number of bits having a second value. The input control unit is further configured to invert the first data to generate second data if the number of bits having a first value is greater than the number of bits having a second value and store the second data in the page buffer. The multi-bit programming apparatus further includes a page programming unit configured to program the second data stored in the page buffer in at least one multi-bit cell. | 04-09-2009 |
20090116310 | METHOD AND APPARATUS FOR WRITE ENABLE AND INHIBIT FOR HIGH DENSITY SPIN TORQUE THREE DIMENSIONAL (3D) MEMORY ARRAYS - A method and apparatus for write enable and write inhibit for high density spin torque three dimensional ( | 05-07-2009 |
20090129178 | Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time - An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core. | 05-21-2009 |
20090135663 | Memory device and method of operating such a memory device - A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply voltage line is associated with each column, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column. Threshold circuitry is connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage. Control circuitry is used during the write operation to disconnect the supply voltage line for the selected column from the first voltage source, and to connect the threshold circuitry to the supply voltage line for the selected column. As a result, the supply voltage to the addressed memory cell transitions to an intermediate voltage level determined by the threshold voltage of the threshold circuitry, thereby de-stabilising the addressed memory cell and assisting in the write operation. The technique of the present invention provides a particularly simple and power efficient technique for implementing a write assist mechanism. | 05-28-2009 |
20090141568 | No-Disturb Bit Line Write for Improving Speed of eDRAM - A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines. | 06-04-2009 |
20090141569 | SEMICONDUCTOR MEMORY DEVICE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented. | 06-04-2009 |
20090154263 | DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY, AND WRITE CIRCUIT - A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. | 06-18-2009 |
20090154264 | Integrated circuits, memory controller, and memory modules - In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level. | 06-18-2009 |
20090154265 | SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE - A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size. | 06-18-2009 |
20090161449 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has memory cells provided at intersections of word lines and bit lines, a precharge circuit connected to the bit lines, and a write circuit. The write circuit includes a column selection circuit controlled by a write control signal, a transistor for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential (e.g., 0 V), a capacitance element for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential (e.g., a negative potential) that is lower than the first potential, and a clamp circuit for clamping the second potential when a power supply voltage becomes high. | 06-25-2009 |
20090161450 | STORAGE DATA UNIT USING HOT CARRIER STRESSING - The memory comprises at least two data storage units using hot carrier stressing damage to store data. Each data storage unit comprises the first terminal, the second terminal and a third terminal. When the first cross voltage between the second and third terminals is higher than the first threshold voltage and the second cross voltage between the first and third terminals is higher than the second threshold voltage, the data storage unit is in the first writing operation. | 06-25-2009 |
20090185436 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING WRITE CONTROLLING CIRCUIT - A semiconductor integrated circuit includes a write controlling circuit configured to selectively provide a fixed pulse or a variable pulse according to a level of a test mode signal in a write operation mode, thereby adjusting a pulse width of an internal write pulse that is a current pulse driving an internal memory cell in response to the fixed pulse or the variable pulse. | 07-23-2009 |
20090231935 | MEMORY WITH WRITE PORT CONFIGURED FOR DOUBLE PUMP WRITE - A memory with a write port configured for double-pump writes. The memory includes a first and second memory locations each having one or more bit cells, and one or more bit lines each coupled to corresponding ones of the bit cells. A write port is coupled to each of the bit lines. Selection circuitry, responsive to a first clock edge, latches first data from a first data path through the write port, and responsive to a second clock edge, latches second data from a second data path through the write port. A first pulse is generated during a first phase of the clock signal to cause writing of the first data into the first memory location. A second pulse is generated during a second phase of the clock signal to cause writing of the second data into the second memory location. | 09-17-2009 |
20090268532 | Systems and Methods for Writing to a Memory - An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address. | 10-29-2009 |
20090285041 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF WRITING DATA THERETO - A non-volatile semiconductor storage device includes: a plurality of memory cells storing information based on a change in resistance value; and a plurality of first and second wirings connected to the plurality of memory cells and activated in reading data from and writing data to a certain one of the memory cells. Each of the memory cells includes: an irreversible storage element storing information based on a change in resistance value associated with breakdown of an insulation film; and a voltage booster circuit receiving an input of a voltage-boost clock performing clock operation in writing data to a certain one of the memory cells and applying a voltage-boosted signal boosted based on the voltage-boost clock to one end of the irreversible storage element. | 11-19-2009 |
20090323441 | Write Latency Tracking Using a Delay Lock Loop in a Synchronous DRAM - A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency. | 12-31-2009 |
20100008166 | CIRCUIT AND METHOD FOR CONTROLLING LOADING OF WRITE DATA IN SEMICONDUCTOR MEMORY DEVICE - A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length. | 01-14-2010 |
20100080072 | METHODS AND SYSTEMS TO WRITE TO SOFT ERROR UPSET TOLERANT LATCHES - Methods and systems to write to redundant storage latches, or storage cells, including soft error upset tolerant latches and feedback-interlocked redundant storage cells, including to write a logic value to one of a plurality of same sense storage nodes, and to write a complementary logic value to a selected one of a plurality of opposite sense storage nodes responsive to the logic value. Remaining storage nodes may be written to through circuitry within the storage cell. Logic values may be output substantially simultaneously with corresponding write operations. A system may include a multiple logic level write circuit to write to the first same sense storage node, and first and second single logic level write circuits to write to the first and second opposite sense storage nodes, respectively. | 04-01-2010 |
20100085821 | Operation method of non-volatile memory - Example embodiments provide a method of operating a non-volatile memory in which the non-volatile memory may only be changed from a first state to a second state and may not be changed from the second state to the first state during a programming operation. | 04-08-2010 |
20100085822 | CONTINUOUS PROGRAMMING OF NON-VOLATILE MEMORY - A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete. | 04-08-2010 |
20100118625 | CHARGE PUMP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A charge pump circuit includes a first charge pump unit that includes a first capacitor and a second capacitor connected in parallel and generates a first charge pump voltage in the second capacitor by pumping the first capacitor, and a second charge pump unit that includes a third capacitor connected to the second capacitor in series and generates a second charge pump voltage in the second capacitor by further pumping the first charge pump voltage charged in the second capacitor via the third capacitor. In this manner, by pumping the latter stage capacitor from among the capacitors connected in parallel by a parallel connection method, the voltage applied between the capacitor electrodes of the latter stage capacitor is lowered. | 05-13-2010 |
20100124129 | DATA WRITING APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A data writing apparatus includes a distributed transmission unit configured to transmit first data and second data, having been aligned to have the same timing, to data lines at mutually different timings, and a data writing unit configured to synchronize the first data and the second data having been transmitted through the data lines and to write the synchronized data in a memory area. | 05-20-2010 |
20100135088 | Operation method of semiconductor device - Provided is a method of operating a semiconductor device, in which timing for switching each of a drain voltage pulse signal and a gate voltage pulse signal from a first state to a second state is controlled in an erase mode and a write mode. | 06-03-2010 |
20100149887 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING POWER SOURCE - A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained. | 06-17-2010 |
20100157699 | WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURE - A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry. | 06-24-2010 |
20100165756 | METHODS AND SYSTEMS TO IMPROVE WRITE RESPONSE TIMES OF MEMORY CELLS - Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while preserving state-retention abilities of remaining ones of the plurality of memory cells. Weakening may include adjusting one or more resistances between one or more power supplies and the plurality of memory cells. Dynamic control may be selectively performed on portions of each of the memory cells in response to an input data logic state. Dynamic control may reduce a write contention within the subset of memory cells without disabling state-retention abilities of remaining ones of the plurality of memory cells, and may improve write response times of the memory cells. | 07-01-2010 |
20100165757 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor layer; a source layer and a drain layer in the semiconductor layer; an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data; a gate dielectric film on the body region; and a first gate electrode and a second gate electrode on one body region via the gate dielectric film, the first and the second gate electrodes separated from each other in a channel length direction of a memory cell comprising the drain layer, the source layer, and the body region. | 07-01-2010 |
20100172195 | ULTRA-LOW-POWER VARIATION-TOLERANT RADIATION-HARDENED CACHE DESIGN - A random access memory (RAM) cell provides a control section and a storage section coupled to the storage section. The storage section includes complementary metal-oxide semiconductor (CMOS) transistors and the storage section is read by precharging the control section to a virtual drain voltage. | 07-08-2010 |
20100177575 | Apparatus and method for controlling write access to a group of storage elements - An apparatus and method for controlling write access to a group of storage elements is provided. Each storage element within the group is identified by an n-bit address, and the total number of storage elements in the group is less than 2 | 07-15-2010 |
20100188909 | MEMORY HAVING NEGATIVE VOLTAGE WRITE ASSIST CIRCUIT AND METHOD THEREFOR - A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower than the logic high. The first potential is removed and a second potential is applied to the second bit line. The second potential is less than the first potential. The first potential may be ground, and the second potential may be a negative voltage. Reducing the write voltage for the bit line that is receiving a logic low improves its ability to be written. By first bringing the logic low to the first potential, which may be ground, and then further reducing the applied voltage, the requirements on the source of the second potential are reduced. | 07-29-2010 |
20100195418 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - Provided is a semiconductor memory device. The semiconductor memory device includes first and second memory chips and a control logic configured to execute an interleave program between the first and second memory chips. The control logic receives write data to be written into first and second memory blocks of the first memory chip. If the first and second memory blocks are normal blocks, the control logic simultaneously performs a program operation for the first and second memory blocks. If one memory block of the first and second memory blocks is a bad block, the control logic writes the received write data corresponding to the one memory block into a storage circuit. | 08-05-2010 |
20100208532 | MEMORY CIRCUIT - Provided is a memory circuit including: memory cells (A) arranged in columns and rows; memory cells (B) each provided for each of the rows for storing information indicative of whether writing into the memory cells (A) of the each of the rows has been completed or not; and a circuit for selecting one of the rows by utilizing the information stored in the memory cells (B). The memory circuit writes information into the memory cell (B) upon completion of writing into the memory cells (A) of a given one of the rows. By utilizing a change in the information stored in the memory cell (B), the given one of the rows is switched from a selected state to a non-selected state, and a next row is switched from the non-selected state to the selected state so that writing is enabled. The operation is repeated to thereby sequentially select a row to be written. | 08-19-2010 |
20100208533 | SYSTEMS AND METHODS FOR ISSUING ADDRESS AND DATA SIGNALS TO A MEMORY ARRAY - Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address. | 08-19-2010 |
20100214856 | Method to improve the write speed for memory products - A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip. | 08-26-2010 |
20100302881 | VOLTAGE GENERATION CIRCUIT AND NONVOLATILE MEMORY DEVICE USING THE SAME - A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit. | 12-02-2010 |
20100329044 | Assisting write operations to data storage cells - A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the higher voltage for a period determined by the pulse width and the high voltage level at other times; and pulse signal generation circuitry for generating said pulse signal. | 12-30-2010 |
20110032778 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell. | 02-10-2011 |
20110032779 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced. | 02-10-2011 |
20110038217 | MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE AND HIGH-POWER, LOW WRITE LATENCY MODE AND/OR INDEPENDENTLY SELECTABLE WRITE LATENCY - A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active. | 02-17-2011 |
20110051535 | Fin-Type Device System and Method - A fin-type device system and method is disclosed. In a particular embodiment, a method of fabricating a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer. | 03-03-2011 |
20110058431 | METHOD AND APPARATUS FOR COMPRESSION OF CONFIGURATION BITSTREAM OF FIELD PROGRAMMABLE LOGIC - A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value. For example, in some embodiments the mode value indicates one of four patterns, a normal pattern, a block checkerboard pattern, a bank checkerboard pattern, and an all banks pattern. | 03-10-2011 |
20110069566 | MEMORY CELL WRITE - Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed. | 03-24-2011 |
20110075493 | NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE WORDLINE VOLTAGE OF THE SAME - A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided. | 03-31-2011 |
20110090747 | INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE - The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals. | 04-21-2011 |
20110090748 | DEVICE FOR SUPPLYING A HIGH ERASE PROGRAM VOLTAGE TO AN INTEGRATED CIRCUIT - The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor. | 04-21-2011 |
20110103161 | METHOD OF REDUCING THE OCCURRENCE OF BURN-IN DUE TO NEGATIVE BIAS TEMPERATURE INSTABILITY - A method for alleviating burn-in effect and enabling performing a start-up process in respect of a device comprising a plurality of challengeable memory elements, wherein the memory elements are able to, upon start-up, generate a response pattern of start-up values useful for identification as the response pattern depends on physical characteristics of the memory elements, the method comprising the step of, after start-up of the memory elements, writing a data pattern to the memory elements which is inverse to a response pattern that was previously read from the same memory elements. Thus, degradation of the PMOS transistors due to NBTI can be alleviated. | 05-05-2011 |
20110110171 | POWERLESS EXTERNAL EVENT DETECTION DEVICE - The external event detection device comprises an electronic unit ( | 05-12-2011 |
20110110172 | Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith - At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer. | 05-12-2011 |
20110122714 | Control Method For Memory Cell - A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory cell includes providing a first controlling voltage to a gate of the transistor, providing a first setting voltage to the first node, and providing a second setting voltage to the second node. When it is determined that the memory cell has been successfully programmed, a specific action is executed. | 05-26-2011 |
20110141832 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 06-16-2011 |
20110141833 | LOW-WEAR WRITING IN A SOLID STATE MEMORY DEVICE - A method includes programming a non-volatile memory. The memory includes a plurality of cells, wherein each cell is configured to store a plurality of values, wherein each of value is represented by N digits where N is an integer greater than 1, wherein each of the plurality of cells is further configured to store electric charge representing a plurality of voltage levels, and wherein each of the plurality of voltage levels represents one of the plurality of values. Programming comprises providing the plurality of voltage levels into a first group of voltage levels and a second group of voltage levels in one of the plurality of cells, wherein a highest voltage level of the first group is less than or substantially equal to a lowest voltage level of the second group, and storing, in the first group of voltage levels, electric charge representing a value comprising, at most, N−1 digits. | 06-16-2011 |
20110149662 | MEMORY DEVICE AND METHOD OF WRITING DATA TO A MEMORY DEVICE - A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline. | 06-23-2011 |
20110188328 | Systems and Methods for Writing to Multiple Port Memory Circuits - A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell. | 08-04-2011 |
20110188329 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit ( | 08-04-2011 |
20110194364 | NVM OVERLAPPING WRITE METHOD - The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time. | 08-11-2011 |
20110199842 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 08-18-2011 |
20110205817 | METHOD AND APPARATUS FOR MANAGING OPEN BLOCKS IN NONVOLATILE MEMORY DEVICE - A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy. | 08-25-2011 |
20110211402 | LOW POWER FLOATING BODY MEMORY CELL BASED ON LOW-BANDGAP-MATERIAL QUANTUM WELL - Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell. | 09-01-2011 |
20110216610 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - Disclosed is a semiconductor device in which substantial enhancement of a write margin without degradation of a static noise can be achieved while obviating an increase in physical circuit size. There are disposed a plurality of power supply lines for feeding a power supply voltage to each column of static memory cells that use complementary bit lines in common; a plurality of power switches, each being disposed for each of the power supply lines; and a plurality of short-circuit switches, each being so arranged as to provide short-circuiting between output nodes of different power switches. When a complementary bit line select signal indicates an unselected level, the power switch corresponding thereto is put in an ON state so that, in a read operation, a power supply voltage is fed via the short-circuit switch concerned to a selected memory cell column from the power supply line corresponding to a memory cell being unselected, or in a write operation, a power supply voltage fed via the short-circuit switch concerned to a selected memory cell column is stopped. | 09-08-2011 |
20110235444 | SRAM WRITING SYSTEM AND RELATED APPARATUS - SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal. | 09-29-2011 |
20110267905 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal and output a generated programming voltage to the core region. | 11-03-2011 |
20110292745 | DATA TRANSMISSION DEVICE - A data transmission device in a semiconductor memory apparatus receives input data via a local data input/output line and output s the input data on a plurality of global data input/output lines. The data transmission device includes a write data generation block configured to receive the input data and test data and output one of input data and test data as write data in response to an activation of a test enable signal, and a loading block configured to apply the write data to one of the plurality of global data input/output lines in response to an enable signal. | 12-01-2011 |
20120002491 | TEST SIGNAL GENERATING DEVICE, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME AND MULTI-BIT TEST METHOD THEREOF - A semiconductor memory apparatus includes a multi-bit test signal generating device configured to receive an address signal and generate a multi-bit test signal based on the address signal when a multi-bit test write operation is performed. | 01-05-2012 |
20120008430 | SEMICONDUCTOR STORAGE DEVICE - According to the embodiments, a memory cell stores therein data, a dummy cell replicates an operation of the memory cell, a write control unit makes the dummy cell to perform writing in synchronization with write timing of the memory cell, and a row decoder performs opening and closing of a word line that performs a row selection of the memory cell based on a monitored result of a write condition of the dummy cell. | 01-12-2012 |
20120026810 | SEMICONDUCTOR MEMORY DEVICE AND ANTIFUSE PROGRAMMING METHOD - An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal. | 02-02-2012 |
20120039135 | MEMORY CELL WRITE - Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed. | 02-16-2012 |
20120057417 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CONTROLLING PROGRAMMING CURRENT PULSE - A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a magnitude corresponding to the code value of the write control code. | 03-08-2012 |
20120063245 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device according to an embodiment includes a write/erase unit, during data write or erase, the write/erase unit supplying a first electric pulse to a selected memory cell, the first electric pulse having an electric energy to an extent that an physical state of a memory element of the selected memory cell does not transition and accumulating charges in a rectifying element of the selected memory cell, after supplying the first electric pulse, and a certain pulse interval thereafter, and supplying a second electric pulse to the selected memory cell, the second electric pulse having larger electric energy than the first electric pulse, the second electric pulse causing the physical state of the memory element of the selected memory cell to transition. | 03-15-2012 |
20120075941 | Memory Programming Methods and Memory Programming Devices - Memory programming devices include a print head that moves across a substrate to deposit memory material on the substrate to form an array of memory cells and programming circuitry coupled to the print head so that the programming circuitry moves across the substrate along with the print head and that, for individual memory cells of the array, is positioned proximate the individual memory cell and writes data to the individual memory cell. Memory programming methods include depositing memory material above a first portion of an electrically conductive bitline printed on a substrate to form a memory cell and using programming circuitry positioned proximate the memory cell, storing data in the memory cell by altering a characteristic of the memory cell, the characteristic remaining altered after the programming circuitry is moved away from the memory cell. | 03-29-2012 |
20120081979 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first write control code generation unit configured to generate a first write control code which is updated with different cycles which have different periods, in response to a programming verification flag signal and a programming enable signal, and a data write unit configured to output a first programming current pulse with a magnitude corresponding to a code combination of the first write control code which is updated. | 04-05-2012 |
20120087194 | DATA WRITE TRAINING METHOD AND SEMICONDUCTOR DEVICE PERFORMING THE SAME - Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command. | 04-12-2012 |
20120140581 | Multiple Cycle Memory Write Completion - A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. | 06-07-2012 |
20120140582 | WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURES - A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry. | 06-07-2012 |
20120155198 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a read bit line is driven based on data read out from a memory cell. A read port drives the read bit line based on data stored in a storage node. A read word line performs row selection via the read port at a time of reading from the memory cell. A coupling driver assists a write operation to the memory cell by controlling a potential of the storage node via the read port. | 06-21-2012 |
20120163103 | MEMORY CELL USING BTI EFFECTS IN HIGH-K METAL GATE MOS - Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments. | 06-28-2012 |
20120170388 | SRAM INCLUDING WRITE ASSIST CIRCUIT AND METHOD OF OPERATING SAME - A static random access memory (SRAM) is described and includes; a bit cell connected with a word line, connected between a bit line and a complementary bit line, and receiving an internal voltage from a write assist circuit. The write assist circuit includes a power control circuit that charges/discharges an internal voltage line to provide the internal voltage in response to at least one control signal, and a compensation circuit that controls a level of the internal voltage. | 07-05-2012 |
20120182814 | PROGRAMMING CIRCUIT USING ANTIFUSE - A programming circuit using an antifuse includes a fuse signal generation unit including an antifuse which connects a node with a low voltage in response to a test address when the node is driven to a level of a high voltage, and configured to output a signal of the node as a fuse signal in response to a test mode signal; and a programming signal generation unit configured to buffer the fuse signal in response to a power-up signal and generate a programming signal. | 07-19-2012 |
20120206981 | METHOD AND DEVICE FOR WRITING DATA - Embodiments of the present invention provide a method and a device for writing data. The method includes: receiving a data block that is to be written in an EDRAM; obtaining, according to a status of a bank in the EDRAM, usable addresses corresponding to usable banks in the EDRAM; selecting an address from the usable addresses as a write-in address of the data block; and writing the data block in a bank corresponding to the write-in address. In the embodiments of the present invention, problems in the prior art that a conflict occurs when a data block is written in a bank and a conflict occurs when a data block is read from a bank can be avoided, and working efficiency of the EDRAM is improved. | 08-16-2012 |
20120206982 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device is provided with first and second main word lines, and a control circuit. The control circuit, in response to a command signal received from outside of the semiconductor device, activates the first main word line at a first timing, and activates the second main word line at a second timing different from the first timing, the first main word line maintaining an activation state at said second timing. | 08-16-2012 |
20120213014 | WRITE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage. | 08-23-2012 |
20120224439 | MASK-WRITE APPARATUS FOR A SRAM CELL - Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation. | 09-06-2012 |
20120224440 | MEMORY DEVICE AND METHOD OF WRITING DATA TO A MEMORY DEVICE - In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline. | 09-06-2012 |
20120230133 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD - A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part. | 09-13-2012 |
20120236663 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 09-20-2012 |
20120243348 | Method and Apparatus of Changing Device Identification Codes of a Memory Integrated Circuit Device - In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. | 09-27-2012 |
20120243349 | PROGRAM CYCLE SKIP - A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming. | 09-27-2012 |
20120250430 | CIRCUIT FOR PREVENTING A DUMMY READ IN A MEMORY - A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal. | 10-04-2012 |
20120269012 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit includes a first signal generator configured to generate a third active signal that is selectively enabled in a first duration in response to a first active signal enabled during the first duration and a second active signal enabled during at least one second duration within the first duration an internal circuit configured to cease operating in response to the third active signal, and a second signal generator configured to generate the second active signal in response to a mode determination signal and a strobe signal. | 10-25-2012 |
20120281487 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of memory cell units which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series, a voltage generator circuit which generates a voltage to be applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit. The control circuit, when writing data into the memory cell array, performs control so as to apply a first write pass voltage to unselected word lines in the memory cell units and, after a selected word line has reached a write voltage, further apply a voltage to the unselected word lines until a second write pass voltage higher than the first write pass voltage has been reached. | 11-08-2012 |
20120287733 | Memory circuitry with write boost and write assist - Memory circuitry | 11-15-2012 |
20120287734 | CONTINUOUS PROGRAMMING OF NON-VOLATILE MEMORY - A system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete. | 11-15-2012 |
20120327727 | MEMORY DEVICE AND RELATED CONTROL METHOD - A memory device includes: a first memory cell at least controlled by a first word line; a first auxiliary circuit coupled to an auxiliary bit line and controlled by the first word line, the first auxiliary circuit capable of storing a predetermined data value; and a control circuit capable of controlling a first word line voltage of the first word line according to a bit line voltage of the auxiliary bit line. | 12-27-2012 |
20130003472 | MEMORY WITH CORRELATED RESISTANCE - Methods, systems, and devices are disclosed, such as a system for sequentially writing to a data locations coupled to one another in series. In certain embodiments, the system includes a plurality of data locations and a controller. The controller is configured to sequentially write data values to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location. | 01-03-2013 |
20130039135 | MEMORY DEVICE FOR MANAGING TIMING PARAMETERS - A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types. | 02-14-2013 |
20130051164 | NONVOLATILE MEMORY DEVICES AND METHODS OF DRIVING THE SAME - A method of driving a nonvolatile memory device including applying a reset voltage to a unit memory cell, reading a reset current of the unit memory cell, confirming whether the reset current is within a first current range, if the reset current is not within the first current range, changing the reset voltage and applying a changed reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell, if the reset current is within the first current range, confirming whether a difference between the present reset current and an immediately previous set current is within a second current range, and, if the difference is not within the second current range, applying the reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell. | 02-28-2013 |
20130094306 | INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE - The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals. | 04-18-2013 |
20130107645 | Nonvolatile Memory And Writing Method Thereof, And Semiconductor Device | 05-02-2013 |
20130114355 | METHOD FOR ADJUSTING VOLTAGE CHARACTERISTICS OF SEMICONDUCTOR MEMORY ELEMENT, METHOD FOR ADJUSTING VOLTAGE CHARACTERISTICS OF SEMICONDUCTOR MEMORY DEVICE, CHARGE PUMP AND METHOD FOR ADJUSTING VOLTAGE OF CHARGE PUMP - Voltages are applied to supply voltage application points of memory cells of an SRAM, a semiconductor substrate, a word line and bit lines so that voltage Vdd takes value V | 05-09-2013 |
20130155791 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information. | 06-20-2013 |
20130188433 | MEMORY CIRCUIT AND METHOD OF WRITING DATUM TO MEMORY CIRCUIT - A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node. | 07-25-2013 |
20130188434 | LOW VOLTAGE WRITE SPEED BITCELL - In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an | 07-25-2013 |
20130223166 | GRAPHENE-BASED MEMORY DEVICES AND METHODS THEREFOR - Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack. The in-plane conductivity of the graphene stack of each memory cell is altered during programming of the memory cell to define a binary value of bits stored in the memory cell | 08-29-2013 |
20130229882 | PROGRAMMABLE/RE-PROGRAMMABLE DEVICE IN HIGH-K METAL GATE MOS - Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments. | 09-05-2013 |
20130301367 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in off-state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided. | 11-14-2013 |
20130308398 | MEMORY DEVICE HAVING CONTROL CIRCUITRY CONFIGURED FOR CLOCK-BASED WRITE SELF-TIME TRACKING - A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry comprises a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch. | 11-21-2013 |
20130308399 | WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY - A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell. | 11-21-2013 |
20130308400 | WRITE CONTROL DEVICE - A write control device includes a switching unit configured to selectively supply a write current in response to a driving control signal, a driving unit configured to supply a driving current to a memory cell corresponding to the write current applied through the switching unit, and an over-driving control unit coupled to an output node of the driving unit and configured to over-drive the output node in response to the driving control signal. | 11-21-2013 |
20130315013 | MEMORY DEVICE - A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array. | 11-28-2013 |
20130322190 | Memory Device Having Control Circuitry for Write Tracking Using Feedback-Based Controller - A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell. | 12-05-2013 |
20130322191 | SEMICONDUCTOR DEVICE CAPABLE OF BLOCK PROTECTION - A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal. | 12-05-2013 |
20130343137 | WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURES - A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry. | 12-26-2013 |
20140043922 | METHOD OF PROVIDING WRITE RECOVERY PROTECTION IN PSRAM AND RELATED DEVICE - A method of operating a PSRAM includes selecting a bit on a word line of the PSRAM, keeping the word line on for a first predetermined duration after selecting the bit, writing a data into the bit in response to a write command, and keeping the word line on for a second predetermined duration after the write command ends. | 02-13-2014 |
20140043923 | Memory Programming Methods and Memory Programming Devices - Memory programming devices include a print head that moves across a substrate to deposit memory material on the substrate to form an array of memory cells and programming circuitry coupled to the print head so that the programming circuitry moves across the substrate along with the print head and that, for individual memory cells of the array, is positioned proximate the individual memory cell and writes data to the individual memory cell. Memory programming methods include depositing memory material above a first portion of an electrically conductive bitline printed on a substrate to form a memory cell and using programming circuitry positioned proximate the memory cell, storing data in the memory cell by altering a characteristic of the memory cell, the characteristic remaining altered after the programming circuitry is moved away from the memory cell. | 02-13-2014 |
20140063988 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device. A semiconductor memory device in accordance with an embodiment of the present invention includes a write driver configured to provide voltage necessary for a write operation when the write operation is performed, a switch block connected to the write driver and configured to control the path of the write voltage, and a cell block connected to the switch block, wherein a constant voltage is supplied to a node leading to a cell selection path within the cell block using the write driver as a voltage source. | 03-06-2014 |
20140063989 | SEMICONDUCTOR MEMORY DEVICE INCLUDING WRITE DRIVER AND METHOD OF CONTROLLING THE SAME - Disclosed is a method of controlling a semiconductor memory device including a write driver. A method of controlling a phase change memory device includes turning on switches connected to a global bit line and a local bit line, respectively, enabling a write driver connected to the switches, enabling a word line, and enabling a memory cell to be accessed by the word line, wherein control is performed so that electric charges supplied from the write driver through the switches are charged when the write driver is enabled. | 03-06-2014 |
20140098620 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device. | 04-10-2014 |
20140133251 | SEMICONDUCTOR STORAGE APPARATUS - A semiconductor storage apparatus according to the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of pairs of bit lines, a plurality of sense amplifiers, a pair of common data lines, a data-to-be-written output circuit configured to, in writing data, set voltages of the common data lines forming the pair, a column selection signal output unit configured to output a plurality of column selection signals, and a plurality of column selection gates, in which in writing the data, the column selection signal output unit selectively turns on one of the column selection gates by setting each of voltages of the column selection signals to one of a level of a higher-potential power supply voltage and a level of a lower-potential power supply voltage, before activating the sense amplifiers. | 05-15-2014 |
20140160871 | SYSTEM AND METHOD FOR PERFORMING SRAM WRITE ASSIST - A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell. | 06-12-2014 |
20140160872 | VOLTAGE GENERATION CIRCUIT, AND WRITE DRIVER AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A voltage generation circuit includes a charge unit and a discharge unit. The charge unit is configured for raising a level of a ramp voltage to a predetermined level in response to a control signal. The discharge unit is configured for lowering the level of the ramp voltage in response to the control signal. The discharge unit uses a constant current source to lower the level of the ramp voltage. | 06-12-2014 |
20140177356 | PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE - Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell. | 06-26-2014 |
20140177357 | DATA WRITE CIRCUIT OF SEMICONDUCTOR APPARATUS - A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch the first delayed pattern signal in response to the second delayed pattern signal, and output a resultant signal; and a control block configured to generate the pattern signal, and vary a delay time of the data path according to a result of comparing phases of a latched signal of the data latch block and the pattern signal. | 06-26-2014 |
20140185394 | Memory with Bit Cell Header Transistor - A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal. | 07-03-2014 |
20140198591 | APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE - Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period. | 07-17-2014 |
20140211576 | Nonvolatile Logic Array with Built-In Test Drivers - A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits. | 07-31-2014 |
20140211577 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device is disclosed. The method may include receiving an access command, applying a first voltage to a selected word line of the semiconductor memory device for a period of time in response to receiving the access command, applying a second voltage to word lines adjacent to the selected word line before and after the period of time, and applying a third voltage to the word lines adjacent to the selected word line for the period of time, a voltage level of the third voltage greater than the second voltage. The applying the third voltage may occur when the semiconductor memory device is operated at a temperature below the predetermined temperature. | 07-31-2014 |
20140219039 | WRITE DRIVER FOR WRITE ASSISTANCE IN MEMORY DEVICE - A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddM | 08-07-2014 |
20140233330 | WRITE ASSIST CIRCUIT, MEMORY DEVICE AND METHOD - A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state. | 08-21-2014 |
20140233331 | WRITE CONTROL CIRCUITS AND WIRE CONTROL METHODS - According to various embodiments, a write control circuit configured to control writing to a memory cell by applying a writing current to the memory cell may be provided. The write control circuit may include: a current application circuit configured to apply the writing current to the memory cell; a determination circuit configured to determine whether writing to the memory cell is finished; and a stop writing circuit configured to cut off the writing current from the memory cell if it is determined that writing to the memory cell is finished. | 08-21-2014 |
20140254293 | HIGH-SPEED MEMORY WRITE DRIVER CIRCUIT WITH VOLTAGE LEVEL SHIFTING FEATURES - Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation. | 09-11-2014 |
20140269114 | CIRCUIT FOR MEMORY WRITE DATA OPERATION - A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage. | 09-18-2014 |
20140269115 | Integrated Write Mux and Driver Systems and Methods - An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals. | 09-18-2014 |
20150109868 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to the embodiment includes a memory cell array including memory cells; and a data write unit, the memory cells including a first selected memory cell defined for a memory cell targeted to data write, a second selected memory cell defined for a memory cell targeted to the data write next to the first selected memory cell, and non-selected memory cells defined for other memory cells, and the data write unit, at the time of write operation to the first selected memory cell, providing the second selected memory cell with a first non-selection electric pulse having electric energy within a range causing no change in the physical state of a memory element, and providing the non-selected memory cells with a second non-selection electric pulse having smaller electric energy than the first non-selection electric pulse. | 04-23-2015 |
20150131391 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal. | 05-14-2015 |
20150138901 | MEMORY CIRCUITRY USING WRITE ASSIST VOLTAGE BOOST - Within a memory | 05-21-2015 |
20150138902 | THREE-DIMENSIONAL (3-D) WRITE ASSIST SCHEME FOR MEMORY CELLS - An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells. | 05-21-2015 |
20150138903 | WRITING TO MULTI-PORT MEMORIES - A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port. | 05-21-2015 |
20150318028 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks. | 11-05-2015 |
20150318029 | Integrated Circuits with Asymmetric and Stacked Transistors - Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage. | 11-05-2015 |
20150318032 | APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE - Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period. | 11-05-2015 |
20150348600 | CONFIGURABLE VOLTAGE REDUCTION FOR REGISTER FILE - A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits. | 12-03-2015 |
20150364181 | OUTPUT SIGNAL GENERATING DEVICE, SEMICONDUCTOR DEVICE AND OUTPUT SIGNAL GENERATION METHOD - An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage. | 12-17-2015 |
20160005448 | Memory Circuitry Using Write Assist Voltage Boost - Within a memory | 01-07-2016 |
20160042775 | SEMICONDUCTOR MEMORY DEVICE FOR CONDUCTING MONITORING OPERATION TO VERIFY READ AND WRITE OPERATIONS - A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second data I/O block transmits the write internal signal to a second pad in response to a monitor enable signal. During a read operation, the first data I/O block supplies data from the first global I/O line to a first pad, and further generates a read internal signal. The second data I/O block transmits the read internal signal to the second pad in response to a monitor enable signal. | 02-11-2016 |
20160086654 | THERMAL AWARE DATA PLACEMENT AND COMPUTE DISPATCH IN A MEMORY SYSTEM - A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location. | 03-24-2016 |
20160125922 | THRESHOLD VOLTAGE GROUPING OF MEMORY CELLS IN SAME THRESHOLD VOLTAGE RANGE - A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell. | 05-05-2016 |