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Particular read circuit

Subclass of:

365 - Static information storage and retrieval

365189011 - READ/WRITE CIRCUIT

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DocumentTitleDate
20100142291Mobile system on chip (SoC) and mobile terminal using the mobile SoC, and method for refreshing a memory in the mobile SoC - A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.06-10-2010
20110188327SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.08-04-2011
20130028032SEMICONDUCTOR MEMORY DEVICE - A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.01-31-2013
20130077416Memory device and method of performing a read operation within a memory device - A memory device includes an array of memory cells arranged in rows and columns, each memory cell being configured to connect to separate write and read paths. The memory cells within each column form a plurality of memory cell groups and are coupled to the read data output circuitry by an associated read path. For each column, the associated read path comprises both a local path portion provided for each memory cell group and a global path portion shared by all memory cells within the column. The global path portion is then connected to the read data output circuitry. Each local path portion is coupled to an associated global path control circuit which is configured during the read operation to control a signal level of the associated global path portion in dependence on a signal level present on the associated local path portion.03-28-2013
20090154262SEMICONDUCTOR DEVICE AND METHOD FOR WRITING DATA INTO MEMORY - It is an object to provide memory and a semiconductor device in which falsification of data written thereinto is prevented. The memory includes a memory circuit, a writing circuit, and a reading circuit. The memory circuit has a memory cell array in which a plurality of memory cells where “0” and “1” of binary data can be written are arranged. The writing circuit includes a first writing circuit which writes one of “0” and “1” of binary data into one of the memory cells included in the memory circuit, and a second writing circuit which writes the other of “0” and “1” of binary data into one of the memory cells included in the memory circuit.06-18-2009
20130051163DATA TRANSMISSION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of the local bit line pairs and connect the selected local bit line pair to the global bit line pair; and a sense amplifier connected to the global bit line pair. The sense amplifier is controlled by a sense amplifier activation signal to which the outputs of the plurality of voltage change detection circuits are connected, whereby the voltage of a selected read data line pair is amplified using discharge of a non-selected read data line pair, to achieve high-speed read.02-28-2013
20120307575MEMORY CONTROLLER AND CONTROL METHOD - A memory controller includes: a first write circuit configured to write a first dummy pattern including a plurality of consecutive first dummy values at a first address of a memory; a second write circuit configured to write a first pattern including a plurality of types of consecutive values at a second address of the memory after a write operation of the first dummy pattern by the first write circuit; a third write circuit configured to write a second dummy pattern including a plurality of consecutive second dummy values at a third address of the memory after a write operation of the first pattern by the second write circuit; a read circuit configured to read the written first pattern based on the second address of the memory; and a timing adjustment circuit configured to adjust a timing at which data is written into the memory based on a read first pattern.12-06-2012
20110013466SEMICONDUCTOR APPARATUS AND DATA READING METHOD - A semiconductor device includes multiple memory cells, a first and second digit lines, where either of them is coupled to the memory cell to be read, a sense amplifier having a first and second sense nodes that are respectively connected to the first and second digit lines, a first switch between the first digit line and the first sense node, a second switch between the second digit line and the second sense node, and a control circuit that outputs a first and second control signals for controlling a conducive state of the first and second switches. When an activation of the sense amplifier is started, the control circuit makes the first and second switches conductive and disconnects the first or second switch corresponding to the digit line to which the memory cell to be read is not connected according to a potential difference between the first and second sense nodes.01-20-2011
20130064024SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING - A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.03-14-2013
20090238013SEMICONDUCTOR DEVICE - A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR09-24-2009
20090046521Memory structure, programming method and reading method therefor, and memory control circuit thereof - The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus each of the memory units of the memory structure of the present invention is sensed with its own appropriate set of reference currents correctly, and the improvement of sensing accuracy is therefore achieved.02-19-2009
20090046520SEMICONDUCTOR MEMORY DEVICE HAVING LOW POWER CONSUMPTION TYPE COLUMN DECODER AND READ OPERATION METHOD THEREOF - The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.02-19-2009
20090251976Method and apparatus for DQS postamble detection and drift compensation in a double data rate (DDR) physical interface - Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission.10-08-2009
20120236662WORD-LINE-POTENTIAL CONTROL CIRCUIT - According to one embodiment, in a memory cell array, a plurality of memory cells is arranged in an array. A read circuit reads out data from the memory cells. A word line driver drives a word line of the memory cells. A characteristic control unit controls a specific characteristic of the memory cells. A word-line-potential adjusting unit adjusts a potential of the word line based on a distribution of the characteristic when the specific characteristic of the memory cells is controlled.09-20-2012
20100014363SELFCALIBRATION METHOD AND CIRCUIT OF NONVOLATILE MEMORY AND NONVOLATILE MEMORY CIRCUIT - The present invention discloses a selfcalibration method of a reading circuit of a nonvolatile memory, by which trimming data having recorded a reference current are stored in a bit-pair form into the memory and regulate a sense amplifier, and a value of the reference current is obtained according to the trimming data when “0” and “1” in the outputted trimming data have the same quantities. The present invention further discloses a selfcalibration circuit of the nonvolatile memory, which includes a trimming data storage module, a sense amplifier module, a logic judgment module, and a scanning module. The present invention furthermore discloses a nonvolatile memory circuit, which includes a memory cell array and the selfcalibration circuit of the reading circuit of the nonvolatile memory. The present invention, not requiring an additional fuse or differential unit, can solve a deadlock problem securely and reliably without increasing circuit area and test cost, and be widely applied to OTP, MTP and EEPROM of various processes or various nonvolatile memories such as Flash EEPROM, MRAM, and FeRAM, improving reliability of the memory effectively.01-21-2010
20130163351DATA TRANSMISSION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A data transmission circuit includes first to fourth local lines, one or more first bit line sense amplifiers configured to correspond to the first local line, one or more second bit line sense amplifiers configured to correspond to the second local line, one or more third bit line sense amplifiers configured to correspond to the third local line, one or more fourth bit line sense amplifiers configured to correspond to the fourth local line, and a selection unit configured to select some first to fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to a first address in a first mode, and select some first and second bit line sense amplifiers or some third and fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to the first address and a second address in a second mode.06-27-2013
20090290439HIGH PERFORMANCE METAL GATE POLYGATE 8 TRANSISTOR SRAM CELL WITH REDUCED VARIABILITY - A static random access memory cell includes a metal hi-k layer; a poly-SiON gate stack over the metal hi-k layer; a plurality of inverters disposed within the poly-SiON gate stack; and a plurality of field effect transistors placed in the metal hi-k layer.11-26-2009
20110292743SEQUENTIAL ACCESS MEMORY ELEMENTS - Integrated circuits with sequential access memory cells are provided. A sequential access memory cell may include an inverter-like circuit, an inverter, a preset transistor, an access transistor, and a read circuit. The inverter-like circuit and the inverter are cross-coupled to form a bi-stable latch that is powered by a positive power supply line and that has first and second storage nodes. The preset transistor may be connected between the positive power supply line and the first storage node. The inverter-like circuit may include a transistor in its pull-down path. The preset transistor is enabled while the transistor is disabled to write a “1” at the first storage node. The access transistor may be used to write a “0” into the cell. The read circuit may be connected to the second storage node to read data from the cell without inducing a voltage rise at the second storage node.12-01-2011
20110292744NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A non-volatile memory device includes a plurality of input pads, a buffer configured to buffer data inputted through the plurality of the input pads in synchronization with a write enable signal, an even latch configured to store a first buffered data outputted from the buffer in response to an even write enable signal, an odd latch configured to store a second buffered data outputted from the buffer in response to an odd write enable signal, and a transfer unit configured to transfer stored data in the even latch and the odd latch to a selected bank of a plane in response to a bank selection signal.12-01-2011
20090003093FUSE READING CIRCUIT - Correction data is written in fuse circuits of q bits. A reading circuit sequentially reads information of the fuse circuits through a selector and writes the information in a storage circuit. Therefore, read data is output from the storage circuit in parallel.01-01-2009
20090257293SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the first main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs, a selector line for connecting a second main bit line connected to the sense amplifier with a sub-bit line to which the reference cell is connected, and a selector line for connecting the second main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs.10-15-2009
20110261634Differential Threshold Voltage Non-Volatile Memory and Related Methods - Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.10-27-2011
20120026809MULTI-BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.02-02-2012
20100091588MEMORY DEVICE AND MEMORY SYSTEM COMPRISING A MEMORY DEVICE AND A MEMORY CONTROL DEVICE - In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.04-15-2010
20130010550Nonvolatile Memory Devices Including Selective RWW and RMW Decoding - A nonvolatile memory device is provided, which includes a memory core including a plurality of nonvolatile memory cells, a first read circuit that reads a first codeword from the memory core during a Read While Write (RWW) operation, a second read circuit that reads a second codeword from the memory core during a Read Modification Write (RMW) operation, and a common decoder that is shared by the first read circuit and the second read circuit and selectively decodes the first codeword or the second codeword.01-10-2013
20090154261REFERENCE-FREE SAMPLED SENSING - Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component determines a logic state of each memory cell of the plurality of memory cells as a function of the sensed characteristic of each memory cell of the plurality of memory cells.06-18-2009
20120033510SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in of state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.02-09-2012
20090141566STRUCTURE FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATION CAPABILITY - A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.06-04-2009
20090285040Semiconductor Memory Device - A semiconductor memory device includes a memory cell array. The memory cell array includes a plurality of sub arrays. Each sub array includes a plurality of memory cells. The memory cell includes a pair of storage nodes that are complementary to each other. One storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a global bit-line. The other storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a local bit-line. The global bit-line is a bit-line connected in common to the plurality of the sub arrays. The local bit-line is provided for each of the sub arrays.11-19-2009
20110199841SEMICONDUCTOR MEMORY DEVICE HAVING LOW POWER CONSUMPTION TYPE COLUMN DECODER AND READ OPERATION METHOD THEREOF - The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.08-18-2011
20110170364CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME - A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.07-14-2011
20090279369DATA OUTPUT APPARATUS AND METHOD FOR OUTPUTTING DATA THEREOF - A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.11-12-2009
20110199840Semiconductor storage device - A device includes a memory cell array having a plurality of memory cells; sense amplifiers, which are arranged adjacent to the memory cell array, for amplifying signals that have been read out of corresponding ones of the memory cells; readout signal lines; a plurality of connection circuits for selectively connecting the sense amplifiers and the readout signal lines; a plurality of main amplifiers for amplifying and outputting signals that have been read out of the sense amplifiers via the readout signal lines by the connection circuits selected by selection signals; an enable signal line connected to the main amplifiers; and an enable signal generating circuit for outputting a main amplifier enable signal to the enable signal line. The enable signal generating circuit is placed in close proximity to the connection circuits.08-18-2011
20100110804METHOD FOR READING AND WRITING A BLOCK INTERLEAVER AND THE READING CIRCUIT THEREOF - A method for writing a memory of a block interleaver determines in a bit-wise manner whether to write data into the memory. A method for reading a memory of a block interleaver combines two adjacent columns of the memory into a temporary column and reads data from the temporary column.05-06-2010
20090034347HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY - A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.02-05-2009
20090034346Memory read control circuit - A DQS detection circuit 02-05-2009
20090168559METHOD OF AND APPARATUS FOR READING DATA - Provided are an apparatus and a method of capturing data by using a data transition of a data signal. The method includes detecting a data transition of a data signal input from an external source, generating a pulse signal corresponding to the detected data transition, and capturing the data signal by using the generated pulse signal as a trigger. Accordingly, stable capturing of data can be performed without changes in margins even when data bits of the read data enter a controller at different times due to skews.07-02-2009
20080285361Input/output line sense amplifier and semiconductor device having the same - An input/output (I/O) line sense amplifier includes a first sense amplifier configured to amplify a signal of an I/O line in response to a strobe signal, and a second sense amplifier configured to latch and amplify an output signal of the first sense amplifier in response to the strobe signal.11-20-2008
20080285360Semiconductor Memory Device and Method of Reading Data Therefrom - A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.11-20-2008
20080291755OUTPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE AND DATA OUTPUT METHOD - An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to a voltage level of a second power supply higher than a voltage level of the first power supply. In an active state, a voltage level of the gate terminal of the outputting PMOS transistor is changed to a voltage level of the first power supply in response to an active command or a read command, or in response to the state of a semiconductor memory device changing to the active state or a read state, and either the outputting PMOS transistor or the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell.11-27-2008
20110007580LOCAL SENSING AND FEEDBACK FOR AN SRAM ARRAY - An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells corresponding to accessed rows and columns of the SRAM array. The SRAM array also includes a separate, local sense and feedback circuit connected to a local column of the SRAM array, wherein a sensing portion indicates a memory state of an SRAM cell in an accessed row of the local column and a feedback portion rewrites the memory state back into the SRAM cell. Additionally, a method of operating an integrated circuit having an SRAM array includes providing an SRAM cell in an addressed condition of the SRAM array. The method also includes locally sensing a current memory state of the SRAM cell and locally feeding back to the SRAM cell to retain the memory state during the addressed condition.01-13-2011
20110007581Current Cancellation for Non-Volatile Memory - A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.01-13-2011
20110007582INFORMATION RECORDING APPARATUS AND INFORMATION RECORDING METHOD, INFORMATION REPRODUCING METHOD AND FADE-IN MEMORY - An information recording apparatus comprises a plurality of fine particles forming an array on a plane in close proximity of each other, each of the plural particles including a ferromagnetic metal, a light-emitting device for exciting a near-field light, and a photo-electric conversion element for detecting a near-field light traveled along the fine particles.01-13-2011
20080212382Crossbar waveform driver circuit - A driving waveform circuit includes a crossbar array having input columns and output rows wherein the crossbar array is configured to store data in the form of high or low resistance states, delay timing circuitry electrically connecting an input signal to the input columns of the crossbar array and configured to provide a relative delay timing between the input signal and each input column, and summation circuitry electrically connected to the output rows of the crossbar array for generating one or more output signals based on the stored resistance state data and the input signal. The driving waveform circuit is taught to be applied as inkjet printing drivers, micromirror drivers, robotic actuators, display device drivers, audio device drivers, computational device drivers, and counters.09-04-2008
20110267904HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY - A memory chip including a plurality of storage elements, a receiver and a program module. Each of the storage elements has a measurable parameter. The receiver receives N target values from a memory controller, where N is an integer greater than zero. The programming module adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values.11-03-2011
20090141567Semiconductor device having memory array, method of writing, and systems associated therewith - In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.06-04-2009
20110222358Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data To Account for Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift.09-15-2011
20110222357Process and Temperature Tolerant Non-Volatile Memory - A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.09-15-2011
20090080269SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.03-26-2009
20130215689HIGH PERFORMANCE TWO-PORT SRAM ARCHITECTURE USING 8T HIGH PERFORMANCE SINGLE-PORT BIT CELL - An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.08-22-2013
20110141831READ BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.06-16-2011
20090097337SEMICONDUCTOR STROAGE DEVICE - This disclosure concerns a memory including: memory cells having sources, drains, gates and floating bodies; word lines connected to gates of the memory cells and arranged in a first direction; first bit lines and second bit lines connected to sources or drains of the memory cells and arranged alternately in a second direction intersecting with the first direction; and first and second sense amplifiers provided in correspondence with the first and the second bit lines, wherein in a data reading operation, the first sense amplifier activates the first bit lines to sense data via the first bit lines in a state where voltage of the second bit lines is fixed, and after sensing of the data of the first bit line, the second sense amplifier activates the second bit lines to sense data via the second bit lines in a state where voltage of the first bit lines is fixed.04-16-2009
20090201749SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.08-13-2009
20090257291SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING PIPE-IN SIGNAL THEREOF - A semiconductor memory device includes a preliminary signal generator configured to output a preliminary pipe-in signal enabled when a read command is applied. A delay unit is configured to delay the preliminary pipe-in signal and output the delayed preliminary pipe-in signal to match the timing of output data. A pipe-in signal generator generates a pipe-in signals that are enabled between a predetermined enable point and a next enable point of the delayed preliminary pipe-in signal output.10-15-2009
20090244992INTEGRATED CIRCUIT AND METHOD FOR READING THE CONTENT OF A MEMORY CELL - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, a read circuit configured to read the memory cell, wherein the read circuit includes an output holding circuit configured to hold a memory cell content signal read from the memory cell, and an enable circuit configured to provide the memory cell content signal at an output of the read circuit only in case the memory cell fulfills a predefined criterion.10-01-2009
20090129177SENSING OF MEMORY CELLS IN A SOLID STATE MEMORY DEVICE BY FIXED DISCHARGE OF A BIT LINE - In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit line is sensed by sense amplifiers to determine the read voltage (i.e., threshold voltage) applied to a word line coupled to the target cell in order to turn on the target cell. The threshold voltage is indicative of the analog voltage stored on the target memory cell.05-21-2009
20100002529CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE OF DATA OUTPUT CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE - A data output circuit of a semiconductor memory device includes at least two data output pads disposed adjacent to each other, a driver unit configured to output a first data by driving a first pad among the data output pads, and a control unit configured to determine whether a phase of the first data is equal to a phase of adjacent data outputted through second pad adjacent to the first pad, and control a slew rate of the driver unit according to the determination result.01-07-2010
20100149886Semiconductor memory device and method for operating the same - In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation. Also, the controller is configured to restore data to the memory cell, which is storing a second data state, by applying a second source-line control voltage to the selected source line and applying a second word-line control voltage to the selected word line in a second period of the read operation.06-17-2010
20130215690MEMORY DEVICES HAVING SELECT GATES WITH P TYPE BODIES, MEMORY STRINGS HAVING SEPARATE SOURCE LINES AND METHODS - Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.08-22-2013
20110110169SENSE AMPLIFIER WITH REDUCED AREA OCCUPATION FOR SEMICONDUCTOR MEMORIES - A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.05-12-2011
20100246287STORAGE DEVICES WITH SOFT PROCESSING - A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.09-30-2010
20100238746READING CIRCUITRY IN MEMORY - A reading circuit in a memory, having a first memory cell coupled to a first bit line and a second bit line, a second memory cell coupled to the second bit line and a third bit line and a third memory cell coupled to the third bit line and a fourth bit line, is provided. The reading circuitry includes a sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line to the drain side bias circuit to receive the drain side bias in a read operation mode. The second selection circuit connects the first bit line and the fourth bit line to the sensing circuit in the read operation mode, so that the sensing circuit senses a current of the first memory cell.09-23-2010
20090116309SEMICONDUCTOR DEVICE - A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD05-07-2009
20120033511CONTROL CIRCUIT OF READ OPERATION FOR SEMICONDUCTOR MEMORY APPARATUS - A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver.02-09-2012
20090323440Data processing device and method of reading trimming data - A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random one of the plurality of memory regions.12-31-2009
20090109766EFFICIENT SENSE COMMAND GENERATION - In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator.04-30-2009
20100296350METHOD OF SETTING READ VOLTAGE MINIMIZING READ DATA ERRORS - A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.11-25-2010
20110116329SEMICONDUCTOR STORAGE DEVICE - A memory cell (05-19-2011
20100014362DATA READOUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A data readout circuit comprises: a 1st PMOS transistor configured to operate in a saturation region and including a source connected to a power supply, a drain connected to an input terminal connected to a memory cell of a data readout object, and a gate to which a 1st bias voltage is supplied; a 2nd PMOS transistor including a source connected to the drain of the 1st PMOS transistor, a drain connected to an output terminal, and a gate to which a 2nd bias voltage is supplied; a 1st NMOS transistor including a drain connected to the drain of the 2nd PMOS transistor, a source grounded, and a gate to which a 3rd bias voltage is supplied; and a bias voltage supply section causing the 2nd PMOS transistor to operate in a saturation region and supplying the 2nd bias voltage to the gate of the 2nd PMOS transistor, wherein the 2nd bias voltage is adjusted so as to keep a reference voltage of the input terminal at a junction point between the drain of the 1st PMOS transistor and the source of the 2nd PMOS transistor.01-21-2010
20100208531DATA READING CIRCUIT - There is provided a data reading circuit which is low in current consumption. In a read period, a signal (φ08-19-2010
20110249519DATA REPRODUCTION CIRCUIT - This is a data reproduction circuit for receiving data and reproducing the data and its clock which has an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.10-13-2011
20090027977Low read current architecture for memory - A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.01-29-2009
20100246288CIRCUIT AND METHOD FOR OUTPUTTING DATA IN SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to a common node from the pull-up and down signals. An assistant pre-driver generates an assistant drive signal, which is activated when the rising data disagrees with the falling data, in correspondence with inputs of the rising data, the falling data, the rising clock, the falling clock, and a pipe output control signal. An assistant main driver generates assistant last output data to the common node from the pull-up and down signals in accordance with a state of the assistant drive signal.09-30-2010
20100118624READ CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - Provided is a read circuit for a semiconductor memory device which may have a reduced circuit scale, and a semiconductor memory device. In a plurality of sense amplifiers of the read circuit of the semiconductor memory device, for serially reading data from a serial output terminal, if a number of byte selectors which may be selected to determine an address at a predetermined time before determination of the address is four, only four sense amplifiers are required in total, and hence the read circuit and the semiconductor memory device are reduced in circuit scale.05-13-2010
20100260000Low-Power Operation of Static Memory in a Read-Only Mode - A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be embedded within a large-scale integrated circuit, for example in combination with a microprocessor and associated circuitry. Upon system control circuitry determining that an SRAM array can be operated in a read-only mode, for example that a large number of read operations are likely to be performed prior to writing to the SRAM array, the power supply voltages applied to the SRAM array are reduced. The array power supply voltage and periphery power supply voltage can be at separate voltages and separately reduced from the read/write mode to the read-only mode. The read-only mode can be readily used for instruction cache memories, and for local instruction memories associated with an embedded microcontroller.10-14-2010
20120201086Signal Margin Improvement For Read Operations In A Cross-Point Memory Array - A configuration for biasing conductive array lines in a two-terminal cross-point memory array is disclosed. The configuration includes applying a read voltage to a selected X-conductive array line while applying an un-select voltage thru a biasing element to a remaining plurality of un-selected X-conductive array lines. A plurality of Y-conductive array lines are initially biased to some voltage (e.g., 0V) and then allowed to float unbiased after a predetermined amount of time has passed, some event has occurred, or both. As one example the event that triggers the floating of the plurality of Y-conductive array lines can be the read voltage reaching a predetermined magnitude. The array can be formed BEOL and include a plurality of two-terminal memory cells with each memory cell including a memory element and optionally a non-ohmic device (NOD) that are electrically in series with each other and with the two terminals of the memory cell.08-09-2012
20090257292Semiconductor device having resistance based memory array, method of reading, and writing, and systems associated therewith - One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.10-15-2009
20110158008SEMICONDUCTOR STORAGE DEVICE AND DATA READOUT METHOD - According to one embodiment, in a semiconductor storage device, a first internal bus, a second internal bus, and a third internal bus have bus widths decreasing stepwise from a memory cell array side to a data output circuit side. A first selection circuit and a second selection circuit divide the data, which is input via the first or second internal bus, according to a rate of a decrease in bus width in an input and an output, time-divide the divided data, and output the divided data to the second or third internal bus.06-30-2011
20080253203DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit that receives parallel data in response to the input control signal, arranges the parallel data in response to the selection signal, and sequentially outputs the arranged parallel data as serial data in synchronization with the output timing signal.10-16-2008
20110063930SUBTRACTION CIRCUITS AND DIGITAL-TO-ANALOG CONVERTERS FOR SEMICONDUCTOR DEVICES - A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combined (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.03-17-2011
20110075492MEMORY DEVICE BIT LINE SENSING SYSTEM AND METHOD THAT COMPENSATES FOR BIT LINE RESISTANCE VARIATIONS - Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.03-31-2011
20100214855METHODS OF QUANTIZING SIGNALS USING VARIABLE REFERENCE SIGNALS - Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.08-26-2010
20100165755SINGLE-ENDED BIT LINE BASED STORAGE SYSTEM - A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.07-01-2010
20100157698CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER - According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.06-24-2010
20100067314Memory Systems And Methods For Dynamically Phase Adjusting A Write Strobe And Data To Account For Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift.03-18-2010
20110261635Differential Threshold Voltage Non-Volatile Memory and Related Methods - Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.10-27-2011
20110261633Memory with improved data reliability - An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory cells, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means of the common word line signal, a read data value is determined in dependence on a voltage of the shared bit line, dependent on data values stored in the at least three memory cells. If, at a time of the read operation, one of the at least three memory cells holds a complement value of the written data value, the voltage of the shared bit line nonetheless has a value such that the read data value is determined with the same value as the written data value.10-27-2011
20090175099Single End Read Module for Register Files - A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.07-09-2009
20100020624READ ENHANCEMENT FOR MEMORY - An electronic circuitry is provided for reading out a memory element (ME). The electronic circuitry comprises a first electronic path (IP) being coupled to the memory element (ME), a second electronic path (RP) having predetermined electrical properties, and a basic detection element (BDE) being coupled to the first and second electronic paths (IP, RP) such that the information contained in the memory element (ME) can be determined by the basic detection element (BDE) based on the relation of a digital signal being propagated over the first path (IP) to a digital signal being propagated over the second path (RP).01-28-2010
20110216609Read Circuitry for an Integrated Circuit Having Memory Cells and/or a Memory Cell Array, and Method of Operating Same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation.09-08-2011
20090219769I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.09-03-2009
20120307576ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.12-06-2012
20100008165MEMORY CELL SENSING USING NEGATIVE VOLTAGE - Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.01-14-2010
20110110170Non-volatile memory systems and methods including page read and/or configuration features - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.05-12-2011
20110063929DELAY LINE THAT TRACKS SETUP TIME OF A LATCHING ELEMENT OVER PVT - A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).03-17-2011
20120300562METHOD AND CIRCUIT FOR TESTING A MULTI-CHIP PACKAGE - A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.11-29-2012
20120113731SEMICONDUCTOR SIGNAL PROCESSING DEVICE - A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.05-10-2012
20120155195OVERLAPPING INTERCONNECT SIGNAL LINES - Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.06-21-2012
20090231934Advanced Bit Line Tracking in High Performance Memory Compilers - A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior to enabling a real word line. A dummy bit line is matured in response to enabling of the dummy word line. The dummy bit line matures at a same rate that a real bit line matures. The method also includes disabling the dummy word line in response to determining a threshold voltage differential based on monitoring maturation of the dummy bit line. The real word line is enabled a predefined delay after enabling of the dummy word line. Similarly, the word line is disabled the predefined delay after disabling of the dummy word line. In response to disabling the dummy word line, a sense enable signal is generated.09-17-2009
20120155197SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times, and a control logic configured to determine the number of read operations and determine the read data of the memory cell based on the counted number.06-21-2012
20120155196Semiconductor memory and manufacturing method - A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.06-21-2012
20120075940MEMORY SYSTEM - A memory system according to the embodiment comprises a cell array including word lines and plural memory cells operative to store data in accordance with plural different physical levels when selected by the word lines; a register operative to hold first data input from external; and a data converter unit operative to convert the first data held in the register into second data and overwrite the second data in the area of the register for holding the first data, and further operative to convert the second data held in the register into third data to be recorded in the memory cells and overwrite the third data in the area of the register for holding the second data.03-29-2012
20120075939MEMORY CELLS HAVING A ROW-BASED READ AND/OR WRITE SUPPORT CIRCUITRY - A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path and at least one second current path. A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.03-29-2012
20120218838SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.08-30-2012
20120081978READ BOOST CIRCUIT FOR MEMORY DEVICE - A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.04-05-2012
20120230132DATA PROCESSING DEVICE AND METHOD OF READING TRIMMING DATA - A data processing device including a nonvolatile memory comprising a plurality of memory regions in which a same trimming data is stored, and a trimming data read control circuit configured to read the trimming data from a random memory region. The trimming data read control circuit comprises a region selection signal generation circuit configured to generate a region selection signal that specifies a random memory region among the memory regions, and a read circuit configured to read the trimming data from the random one memory region in response to the region selection signal. The region selection signal generation circuit comprises a clock counter configured to count a clock signal until a reset signal is input, and a signal generation circuit configured to generate the region selection signal based on a count value of the clock counter. The reset signal is input to the clock counter at a random timing.09-13-2012
20120230131SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of a current path, the other end, and a gate. The second transistor has one end, and the other end. The second transistor has one of a first and a second supply ability. The third transistor has one end, and the other end. The third transistor has one of a third and a fourth supply ability. The switch grounds the second and the third transistors. The sense amplifier turns off the first transistor after transferring the data to an outside, and supplies the second signal to the switch to set gates of the second transistor and third transistor to ground.09-13-2012
20110122713READ STROBE FEEDBACK IN A MEMORY SYSTEM - A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus.05-26-2011
20120320691CLAMPED BIT LINE READ CIRCUIT - One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.12-20-2012
20110038216METHOD FOR READING MEMORY CELL - Methods for reading a memory cell are provided. The method for reading a memory cell includes applying a first read pulse to a memory cell, heating the memory cell to a first temperature and obtaining a first read data. The first read data is converted to a first digital data. The first digital data is stored in a shift register. A second read pulse is applied to the memory cell, heating the memory cell to a second temperature and obtaining a second read data. The second read data is converted to a second digital data. The second digital data is stored in the shift register. A ratio of the first digital data and the second digital data is calculated, obtaining a quotient. The quotient is converted to an analog value. A log amplifier circuit takes the log of the analog value, representing an activation energy state.02-17-2011
20120275245SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A variation in threshold value of the memory cells is derived before data of a data buffer is written by using a writing circuit. Data in which the variation in threshold value is compensated with respect to the data of the data buffer is written to the memory cell.11-01-2012
20100232237HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY - A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.09-16-2010
20110305096CIRCUIT FOR READING NON-VOLATILE MEMORY CELLS AND MEMORY SYSTEM COMPRISING THE CIRCUIT - A circuit for reading memory cells includes: a sense node connectable to a memory cell; a sense device connected to the sense node and configured to be activated in a precharging step which precedes a cell reading step and to provide such an output signal to assume logic values dependant on an electric signal present at the sense node; a precharging circuit connected to said sense node and configured to be activated to make said sense node reach a precharging voltage and to be deactivated upon switching said output signal occurred in the precharging step.12-15-2011
20120092942TECHNIQUES FOR READING A MEMORY CELL WITH ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.04-19-2012
20120092941MEMORY CELL - Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.04-19-2012
20100202221METHOD OF READING MEMORY CELL - A method for reading a memory cell (08-12-2010
20120243347MEMORY CELLS HAVING A ROW-BASED READ AND/OR WRITE SUPPORT CIRCUITRY - A method of controlling a plurality of memory cells in a row. The method includes controlling a switching element using at least one write word line signal to raise a voltage of a node connected to the plurality of memory cells in the row when the plurality of memory cells in the row operate in a first mode. The method further includes controlling at least one transistor using the at least one write word line signal to connect the plurality of memory cells in the row to a reference voltage when the plurality of memory cells in the row operate in a second mode.09-27-2012
20080247244Reading circuitry in memory - A reading circuit in a memory having a first memory cell coupled to a first bit line and a second bit line and a second memory cell coupled to the second bit line and a third bit line, is provided. The reading circuitry comprises a source side sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line and the third bit line to the drain side bias circuit in a read operation mode. The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed.10-09-2008
20080232177NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - Disclosed is a nonvolatile memory device using a variable resistive element, and a data read circuit for use in variable resistive memory devices. More specifically, embodiments of the invention provide a data read circuit with one or more decoupling units to remove noise from one or more corresponding control signals. For instance, embodiments of the invention remove noise from a clamping control signal, a read bias control signal, and/or precharge signal. The disclosed decoupling units may be used alone or in any combination. Embodiments of the invention are beneficial because they can increase sensing margin and improve the reliability of read operations in memory devices with variable resistive elements.09-25-2008
20130141993INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY - An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.06-06-2013
20130170306MEMORY ARCHITECTURE AND DESIGN METHODOLOGY WITH ADAPTIVE READ - An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.07-04-2013
20110273944SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes first and second planes having a memory cell array that includes a plurality of memory cells coupled to bit lines, and page buffer groups that are coupled respectively to one or more of the bit lines and each include page buffers, and a common input/output circuit shared by the page buffer groups of the first and second planes for data input/output control, and coupled to data input/output pads.11-10-2011
20110273943System and Method to Read a Memory Cell with a Complementary Metal-Oxide-Semiconductor (CMOS) Read Transistor - A system and method to manage leakage of a complementary metal-oxide-semiconductor (CMOS) read transistor in a memory cell. In a particular embodiment, a memory cell is disclosed that includes a storage element and a complementary metal-oxide-semiconductor (CMOS) read transistor. The CMOS read transistor includes a first terminal coupled to a read word line, a second terminal coupled to a read bit line, and a third terminal coupled to the storage element. During a non-read operating time, the read word line and the read bit line are both maintained at substantially the same voltage level. During a read operation, the read word line is maintained at a particular voltage level until after a voltage representing data stored at the storage element is sensed by the CMOS read transistor.11-10-2011
20130148446SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first cell array including a plurality of memory cells that are connected to a first word line and each of which is connected to each member of a first pair of bit lines. The semiconductor storage device also includes a second cell array including a plurality of memory cells that are connected to a second word line and each of which is connected to each member of a second pair of bit lines. The semiconductor storage device further includes a redundant cell array including a plurality of memory cells that are connected to a word line different from the first and the second word lines and each of which is connected to one member of the first pair of bit lines and to one member of the second pair of bit lines.06-13-2013
20130148445LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter.06-13-2013
20130148444DATA READING DEVICE - There is disclosed a data reading device in which data of a nonvolatile storage element is reflected in a circuit to be regulated, with a minimum necessary delay width after turning a power on or after reset cancellation, and wrong writing due to a static electricity is prevented. A delay circuit is additionally disposed to output a delayed data reading signal after a signal of turning the power on or a signal of the reset cancellation is generated. A delay time T06-13-2013
20130148443MEMORY DEVICE AND A METHOD OF OPERATING SUCH A MEMORY DEVICE IN A SPECULATIVE READ MODE - A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.06-13-2013
20130182515DUAL-VOLTAGE DOMAIN MEMORY BUFFERS, AND RELATED SYSTEMS AND METHODS - Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.07-18-2013
20130121092SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED TO ONE ANOTHER - Disclosed herein is a device that includes a first semiconductor chip outputting a read command and a clock signal, a plurality of second semiconductor chips stacked to the first semiconductor chip, and a signal path electrically connected between the first and second semiconductor chips. Each of the second semiconductor chips performs a read operation to read out a data signal stored therein in response to the read command. Each of the second semiconductor chips includes a counter circuit performing a count operation in response to the clock signal to generate a count signal, and an output control circuit outputs the data signal to the signal path when the count signal indicates a predetermined value. The predetermined values of the second semiconductor chips are different from one another.05-16-2013
20130121093MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD - A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.05-16-2013
20130194880READING MEMORY DATA - A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line.08-01-2013
20120092940Memory Device and Read Operation Method Thereof - A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.04-19-2012
20130208552Method and Apparatus for Adjusting Drain Bias of A Memory Cell With Addressed and Neighbor Bits - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.08-15-2013

Patent applications in class Particular read circuit