Entries |
Document | Title | Date |
20080266984 | Programmable Heavy-Ion Sensing Device for Accelerated DRAM Soft Error Detection - Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode. | 10-30-2008 |
20080266985 | METHODS AND APPARATUS FOR TESTING INTEGRATED CIRCUITS - In some aspects, a method is provided for testing an integrated circuit (IC). The method includes the steps of selecting a bit from each of a plurality of memory arrays formed on an IC chip, selecting one of the plurality of memory arrays, and storing the selected bit from the selected memory array. Numerous other aspects are provided. | 10-30-2008 |
20080291745 | METHOD AND SYSTEM FOR SIMULTANEOUS READS OF MULTIPLE ARRAYS - A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set oft input selector signals. The method includes enabling each multiplexing circuit with a distinct combination of the set of input selector signals. The distinct combinations of the set of input selector signals cause each input selector signal to drive a comparable number of multiplexers. Each multiplexing circuit selects a memory location from the coupled indexed array. Further, the method includes reading the data at the selected memory locations through the output of each multiplexing circuit. | 11-27-2008 |
20080298137 | METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH - A domino read bit line structure ( | 12-04-2008 |
20080304330 | SYSTEMS, METHODS, AND APPARATUSES FOR TRANSMITTING DATA MASK BITS TO A MEMORY DEVICE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for transferring data mask bits to a memory device. In some embodiments, an integrated circuit includes logic to issue a partial write command to a memory device. In addition, the integrated circuit may include logic to transfer a write frame to the volatile memory device over an N bit wide data bus, wherein the write frame includes one or more data mask bits to be transferred over the N bit wide data bus. | 12-11-2008 |
20080304331 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application - The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem. | 12-11-2008 |
20080304332 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application - The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem. | 12-11-2008 |
20090016119 | Memory device performing write leveling operation - A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe latch unit latches the data outputted from the multiplexing unit and outputting the latched data. The output driver outputs the latched data outputted from the pipe latch unit. | 01-15-2009 |
20090040837 | System and method for reducing pin-count of memory devices, and memory device testers for same - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 02-12-2009 |
20090067258 | SEMICONDUCTOR MEMORY DEVICE HAVING A CURRENT CONSUMPTION REDUCTION IN A DATA WRITE PATH - The present invention describes a semiconductor memory device that can reduce current consumption occurring in a data write path. The semiconductor memory device includes a write path over which any one of general data and representative data corresponding to a particular mode is transferred in correspondence with a prescribed pad. A routing controller allows the representative data to be routed over a transfer path corresponding to any other pads in the particular mode and prevents the general data from being routed over the transfer path in modes other than the particular mode. The semiconductor memory device can reduce current consumption caused by unnecessary toggling of the data through utilization of the routing controller. | 03-12-2009 |
20090067259 | SEMICONDUCTOR MEMORY DEVICE CONFIGURED TO REDUCE CURRENT CONSUMPTION ASSOCIATED WITH CRITICAL EVALUATING OF DATA WRITE OPERATIONS - A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory device includes write pass corresponding to first pad which transfer any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific operational mode and upon deviating from the mode, interrupting the routing of the general data to the transfer pass. | 03-12-2009 |
20090086550 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks a plurality of banks stacked in a column direction, a global data line corresponding to the plurality of banks and a common global data line driving unit for multiplexing data on a plurality of local data lines corresponding to each of the banks to transmit the multiplexed result to the global data line. | 04-02-2009 |
20090091985 | INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROL METHOD OF THE SAME - An input circuit of a semiconductor memory apparatus includes a first frequency control unit which receives a first signal and a second frequency control unit which receives a second signal. The first frequency control unit outputs the first signal to the second frequency control unit in response to a test mode signal and generates a third signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals. Also, the second frequency control unit outputs the second signal to the first frequency control unit in response to the test mode signal and generates a fourth signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals. | 04-09-2009 |
20090097327 | SYSTEMS AND METHODS FOR READING DATA FROM A MEMORY ARRAY - One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal. | 04-16-2009 |
20090103372 | HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS - The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications. | 04-23-2009 |
20090103373 | HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS - The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications. | 04-23-2009 |
20090116297 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 05-07-2009 |
20090213663 | Circuits, devices, systems, and methods of operation for capturing data signals - Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit of the data signal responsive to a first edge of the write strobe signal and at least a second data digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each of the data digits of the data signal in substantially the same manner as the data capture circuit, and also generates a latch control signal indicative of when each data bits is latched. The latch control signal is provided to a write control circuit coupled to the feedback capture circuit and the data capture circuit. The write control circuit determines which of the data digits was latched first relative to an external timing, and generate a select control signal to drive the captured data digits onto the data bus in the order in which the data digits were received. | 08-27-2009 |
20090219764 | Semiconductor memory device for high-speed data input / output - Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data. | 09-03-2009 |
20090238009 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 09-24-2009 |
20090251974 | MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME - A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described. | 10-08-2009 |
20100008154 | INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING - An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs. | 01-14-2010 |
20100008155 | Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems - A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided. | 01-14-2010 |
20100034029 | STATIC RANDOM ACCESS MEMORY (SRAM) OF SELF-TRACKING DATA IN A READ OPERATION, AND METHOD THEREOF - The self-tracking data selection SRAM, comprising: a plurality of memory cell arrays, comprising: a plurality of memory cells each generating a first signal and outputting a first read data; a plurality of first buffers each receiving the first signal outputting a second signal; a first multiplexer receiving the plurality of first read data and the first signals; a plurality of second buffers each receiving the second signals and outputting a third signal; a second multiplexer receiving a plurality of second read data from the plurality of memory cell arrays and outputting a third signals. A method for self-tracking data in a read operation of a SRAM is disclosed. | 02-11-2010 |
20100074030 | ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE - An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node. | 03-25-2010 |
20100080070 | Method for Reducing Power Consumption in a Volatile Memory and Related Device - A method for reducing power consumption in a volatile memory includes switching off a bitline voltage provider according to a leakage control signal when a bitline array corresponding to the bitline voltage provider is dysfunctional due to a wordline to bitline short, controlling connections between a plurality of first bitline arrays corresponding to the bitline voltage provider and a plurality of sense amplifiers according to an access control signal, controlling connections between a plurality of second bitline arrays corresponding to the plurality of first bitline arrays and the plurality of sense amplifiers according to the access control signal, and providing power to the plurality of corresponding sense amplifiers according to the access control signal. | 04-01-2010 |
20100091580 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality of global lines. The first control unit controls the plurality of data transferring unit in response to a column select signal to select a column of a memory cell. The multiplexing unit multiplexes the data transferred to the plurality of global lines. The second control unit controls the multiplexing unit, wherein the second control unit synchronizes the column select signal with a column address signal having a column address information of the memory cell. | 04-15-2010 |
20100118614 | SEMICONDUCTOR APPARATUS, DATA WRITE CIRCUIT OF SEMICONDUCTOR APPARATUS, AND METHOD OF CONTROLLING DATA WRITE CIRCUIT - A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data input at relatively earlier timing among the plurality of data is latched at earlier timing than the other data by a portion of the plurality of latches. | 05-13-2010 |
20100118615 | Semiconductor memory device - A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line. | 05-13-2010 |
20100118616 | Semiconductor memory device - A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder. | 05-13-2010 |
20100165749 | Sense Amplifier Used in the Write Operations of SRAM - A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation. | 07-01-2010 |
20100202218 | System and Method for Level Shifter - In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component. | 08-12-2010 |
20100246275 | METHODS AND APPARATUS RELATED TO A SHARED MEMORY BUFFER FOR VARIABLE-SIZED CELLS - In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variable-sized cells. The write multiplexing module further configured to send each segment from the set of segments identified as a trailing segment to a portion of the shared memory mutually exclusive from the lead memory bank. | 09-30-2010 |
20100246276 | Semiconductor memory device having swap function for data output pads - A semiconductor memory device having a status register read function includes a plurality of data output pads electrically connected to corresponding package pin, and a swap controller connected between the plurality of data output pads and a plurality of output lines that output memory-related unique information in a specific operation mode. The swap controller controls a swap according to preset swap program information when a swap is needed to match the data output pads to the package pins. | 09-30-2010 |
20100309731 | KEEPERLESS FULLY COMPLEMENTARY STATIC SELECTION CIRCUIT - Selection circuitry for use in register files, multiplexers, and so forth is disclosed. The selection circuitry includes a plurality of local bit lines coupled to global bit line circuitry. Groups of cells or data inputs are coupled to each of the local bit lines. When a cell or data input of a given group is selected, a group select signal is provided to the global bit line circuitry. The global bit line circuitry drives a global bit line responsive to the group select signal and the data driven on (or provided to) the local bit line associated with the selected cell/input, thus providing a data output. When no cell of a given group is selected, the group select signal is de-asserted, causing the respective global bit line to be held in a predetermined state. | 12-09-2010 |
20100309732 | DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group. | 12-09-2010 |
20100315885 | CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING DATA SIGNALS - Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit of the data signal responsive to a first edge of the write strobe signal and at least a second data digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each of the data digits of the data signal in substantially the same manner as the data capture circuit, and also generates a latch control signal indicative of when each data bits is latched. The latch control signal is provided to a write control circuit coupled to the feedback capture circuit and the data capture circuit. The write control circuit determines which of the data digits was latched first relative to an external timing, and generate a select control signal to drive the captured data digits onto the data bus in the order in which the data digits were received. | 12-16-2010 |
20100315886 | DATA TRANSFER APPARATUS, AND METHOD, AND SEMICONDUCTOR CIRCUIT - Provided is a data transfer apparatus and method that enables fast data transfer, and has a simple circuit configuration and a small area; and a semiconductor circuit. The data transfer apparatus includes: a data pair generation circuit ( | 12-16-2010 |
20110085387 | SEMICONDUCTOR MEMORY APPARATUS WITH CLOCK AND DATA STROBE PHASE DETECTION - A semiconductor memory apparatus includes an internal tuning unit configured to tune a generation timing of a data input strobe signal according to a phase difference between an external clock signal and a data strobe clock signal, and a data input sense amplifier configured to transmit data bits to a global line in response to the data input strobe signal. | 04-14-2011 |
20110110164 | TRIM CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME - A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals. | 05-12-2011 |
20110128793 | PREAMBLE DETECTION AND POSTAMBLE CLOSURE FOR A MEMORY INTERFACE CONTROLLER - A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit. | 06-02-2011 |
20110134705 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A MULTIPLEXED COMMUNICATIONS INTERFACE - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions. | 06-09-2011 |
20110164459 | LIST STRUCTURE CONTROL CIRCUIT - A list structure control circuit includes memories each individually stores data, selection circuits arranged for each of the memories and series-connect the memories so that data stored in each memory has an order relation, and an update control circuit that adds a position selection signal which specifies a position for data insertion or data removal to a fixed value, or subtracts the position selection signal from the fixed value, generates an enable signal based on the calculation result, and controls data retention performed in the memories or data update performed in the memories using data of a memory in precedent stages based on the generated enable signal, wherein the selection circuits are controlled based on the position selection signal at the time of the data insertion, and data stored in a memory located at the position specified by the position specification signal is updated with data to be inserted. | 07-07-2011 |
20110194358 | SEMICONDUCTOR MEMORY DEVICE USING INTERNAL HIGH POWER SUPPLY VOLTAGE IN SELF-REFRESH OPERATION MODE AND RELATED METHOD OF OPERATION - A semiconductor memory device comprises a memory cell array comprising a plurality of memory banks. The semiconductor memory device performs refresh operations on the memory cell array using a normal refresh operation mode and a self-refresh operation mode. In the normal refresh operation mode, the semiconductor memory device performs refresh operations using an external high power supply voltage, and in the self-refresh operation mode, the semiconductor memory device performs refresh operations using an internal high power supply voltage. In the self-refresh operation mode, the refresh operations are performed in units of memory banks or memory bank groups. | 08-11-2011 |
20110199835 | No-Disturb Bit Line Write for Improving Speed of eDRAM - A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines. | 08-18-2011 |
20110216605 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICAL BIT LINES - Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The semiconductor memory device may also include a multiplexer coupled to the plurality of local bit lines and a global bit line coupled to the multiplexer. | 09-08-2011 |
20110242905 | SEMICONDUCTOR MODULE INCLUDING MODULE CONTROL CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal. | 10-06-2011 |
20110249510 | EMBEDDED STORAGE APPARATUS AND TEST METHOD THEREOF - An embedded storage apparatus including a control unit, a storage unit, and a signal processing and measurement unit is provided. The control unit outputs a plurality of signals, wherein the signals include a mode selection signal and a plurality of control signals. The storage unit is controlled by the control unit to read a data from a predetermined address. The storage unit has a plurality of output terminals. The signal processing and measurement unit has a plurality of input terminals and a plurality of output terminals, wherein the input terminals are connected to the output terminals of the storage unit. The signal processing and measurement unit reads the data from the output terminals and determines whether to perform a predetermined processing on the data according to the mode selection signal. After that, the signal processing and measurement unit outputs the data through the output terminals. | 10-13-2011 |
20110249511 | SEMICONDUCTOR DEVICE - A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of the external power supply voltage. | 10-13-2011 |
20110317494 | PIPE LATCH CIRCUIT OF MULTI-BIT PREFETCH-TYPE SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED STRUCTURE - Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprises a first multiplexer for selecting a certain input data from first group of the input data in response to a first selection control signal and a second multiplexer for selecting a certain input data from second group of the input data in response to a second selection control signal; a second multiplexing circuit for setting a sequence of output data from the first multiplexing circuit in response to a third selection control signal; and a second latch circuit comprises a third latch for latching a first output data from the second multiplexing circuit in response to a first output latch control signal and a fourth latch for latching a second output data from the second multiplexing circuit in response to a second output latch control signal. The invention cuts down the overall chip size and current consumption of the pipe latch circuit by reducing the number of multiplexers necessary for arranging the pre-fetched data in a predetermined output order. | 12-29-2011 |
20120008420 | Command Generation Circuit And Semiconductor Memory Device - There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command. | 01-12-2012 |
20120057411 | Latch Based Memory Device - A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach. | 03-08-2012 |
20120092934 | MULTIPLEXING CIRCUIT - A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line. | 04-19-2012 |
20120092936 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR CONTROLLING A SENSE AMPLIFIER - A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the internal read command signal in response to a test mode signal in a read mode. | 04-19-2012 |
20120099382 | READING MEMORY DATA - A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit. | 04-26-2012 |
20120099383 | DATA OUTPUT BUFFER AND MEMORY DEVICE - A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode. | 04-26-2012 |
20120106263 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME - A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. | 05-03-2012 |
20120106264 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 05-03-2012 |
20120120733 | SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME - Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit. | 05-17-2012 |
20120134216 | INTEGRATED CIRCUIT HAVING MEMORY ARRAY INCLUDING ECC AND COLUMN REDUNDANCY, AND METHOD OF OPERATING SAME - An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data. | 05-31-2012 |
20120140571 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 06-07-2012 |
20120155188 | REDUCED POWER CONSUMPTION MEMORY CIRCUITRY - In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input. | 06-21-2012 |
20120155189 | System and Method for Level Shifter - In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component. | 06-21-2012 |
20120218830 | METHOD AND SYSTEM FOR READING FROM MEMORY CELLS IN A MEMORY DEVICE - A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier. | 08-30-2012 |
20120224435 | MULTIPLE-PORT MEMORY DEVICE COMPRISING SINGLE-PORT MEMORY DEVICE WITH SUPPORTING CONTROL CIRCUITRY - A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into output signals that are supplied over the first and second ports of the multiple-port memory device. In an illustrative embodiment, the single-port memory device operates at a clock rate that is an integer multiple of a clock rate of first and second memory drivers that supply the input signals to and receive the output signals from the respective first and second ports of the multiple-port memory device. | 09-06-2012 |
20120230121 | DATA BUS POWER-REDUCED SEMICONDUCTOR STORAGE APPARATUS - In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system. | 09-13-2012 |
20120236659 | Staggered Mode Transitions in a Segmented Interface - A memory integrated circuit comprises first and second memory arrays and first and second interfaces. The first interface receives a signal for accessing a memory location in one of the first and the second memory arrays during a first time interval. The second interface receives a signal for accessing a memory location in one of the first and the second memory arrays during the first time interval. The first interface receives signals for accessing memory locations in the first and the second memory arrays, and the second interface is disabled from accessing the first and the second memory arrays during the second time interval. A signaling rate of a signal received by the second interface, a supply voltage of the second interface, an on-chip termination impedance of the second interface, or a voltage amplitude of a signal received by the second interface is adjusted during the second time interval. | 09-20-2012 |
20120257459 | MEMORY BUFFER FOR BUFFER-ON-BOARD APPLICATIONS - The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output command signal as its output. The apparatus further includes a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, the multiplexer being operable to route one of the first and second output command signals to its output in response to the control signal. | 10-11-2012 |
20120262994 | SYSTEM AND METHOD FOR MEMORY ARRAY DECODING - A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in the memory array. The read/write module is configured to control activation of at least two memory cells in the memory array during a read operation or a write operation, wherein the at least two memory cells activated by the read/write module are located on a different word line and a different bit line in the memory array, and wherein each memory cell coupled to a same bit line of the plurality of bit lines is configured to be written to or read from based on selection of the bit line. | 10-18-2012 |
20120275236 | Method and Apparatus for Power Domain Isolation during Power Down - An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. The circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain. | 11-01-2012 |
20120275237 | MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE - A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. | 11-01-2012 |
20120287725 | MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY - A DRAM controller component generates a timing signal and transmits, to a DRAM, (i) write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, (ii) a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and (iii) a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval. | 11-15-2012 |
20120287726 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 11-15-2012 |
20120294094 | METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE - A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells. | 11-22-2012 |
20130016571 | CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING DATA SIGNALS - Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received. | 01-17-2013 |
20130039131 | Systems And Methods Involving Multi-Bank, Dual- Or Multi-Pipe SRAMs - Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank. | 02-14-2013 |
20130044550 | Memory Array Having Word Lines with Folded Architecture - According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading. | 02-21-2013 |
20130064018 | MEMORY ACCESS CIRCUIT FOR DOUBLE DATA/SINGLE DATA RATE APPLICATIONS - A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data. | 03-14-2013 |
20130070533 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines. | 03-21-2013 |
20130094300 | READING DEVICES FOR MEMORY ARRAYS - A reading device for a memory array is provided. The memory array comprises memory cell columns. The reading device comprises first sensing amplifier groups, a second sensing amplifier group, and an output unit. Each first sensing amplifier groups selectively generates a first sensing output signal. The second sensing amplifier group generates a second sensing output signal. The output unit selectively outputs one of the second sensing output signal and the first sensing output signals according to a page address signal. In a reading operation period, the reading device reads data from a column group to the first sensing amplifier groups. In the reading operation period, when the page address signal indicates an initial input address, initial address data read from the specific column set corresponding to the initial input address among the column group is transmitted to the second sensing amplifier group to generate the second sensing output signal. | 04-18-2013 |
20130094301 | INTERFACES AND DIE PACKAGES, AND APPARTUSES INCLUDING THE SAME - A memory device includes a die package including a plurality of memory dies, an interface including an interface circuit, and a memory controller to control the interface with control data received from at least one die. The interface is to divide and multiplex an IO channel between the package and the controller into more than one channel using the data received from the at least one die. The interface includes a control input buffer to receive an enable signal through a control pad, a first input buffer to receive first data through a first IO pad in response to a first state of the enable signal, and a second input buffer to receive second data through a second IO pad in response to a second state of the enable signal. The interface further includes an input multiplexer to multiplex the first data and the second data to provide input data. | 04-18-2013 |
20130107636 | SEMICONDUCTOR MEMORY DEVICE | 05-02-2013 |
20130107637 | Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths | 05-02-2013 |
20130135941 | Enhanced Data Retention Mode for Dynamic Memories - A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells. | 05-30-2013 |
20130141986 | IMPLEMENTING COLUMN REDUNDANCY STEERING FOR MEMORIES WITH WORDLINE REPOWERING - A method and circuit for implementing column redundancy steering for memories with wordline repowering, and a design structure on which the subject circuit resides are provided. Each respective data column receives a precharge signal applied to an associated precharge function. An inverting multiplexer is provided in a precharge path after the wordline repowering having inputs coupled to the respective precharge functions before and after the wordline repowering. The inverting multiplexer passes the precharge signal from the precharge function before the wordline repowering or from the precharge function after the wordline repowering. The inverting multiplexer is controlled by the redundancy steering control signal that activates redundancy steering. | 06-06-2013 |
20130141987 | Latch Based Memory Device - A method of testing a latch based memory device is disclosed. The latch based memory device includes a number of latches, electrical connections and a circuit environment of the latches. A storage functionality of the latches can be tested during a first test phase while a functionality of the electrical connections and the circuit environment of the latches can be tested during a second test phase. | 06-06-2013 |
20130148438 | TRACKING CELL AND METHOD FOR SEMICONDUCTOR MEMORIES - A semiconductor memory includes a memory array having at least one bit line, a tracking bit line, and a global tracking circuit. The tracking bit line is configured to emulate a voltage transition of the at least one bit line. The global tracking circuit is configured to generate a timing signal for generating a negative voltage with respect to ground on the at least one bit line of the memory array. | 06-13-2013 |
20130194876 | BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT - A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship. | 08-01-2013 |
20130201765 | POWER MIXING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal. | 08-08-2013 |
20130201766 | Volatile Memory with a Decreased Consumption and an Improved Storage Capacity - A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines. | 08-08-2013 |
20130208546 | LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME - A latency control circuit is configured to delay a read information signal in response to a CAS latency signal and an internal clock signal to generate a delayed read information signal, and is further configured to generate a latency control signal based on the delayed read information signal in response to a plurality of sampling control signals and a plurality of transfer control signals. | 08-15-2013 |
20130223158 | MEMORY WITH BIT LINE CAPACITIVE LOADING - Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier. | 08-29-2013 |
20130223159 | MEMORY WITH VARIABLE STRENGTH SENSE AMPLIFIER - Embodiments of a memory are disclosed that may reduce the likelihood of a misread while reading a weak data storage cell. The memory column may include a number of data storage cells, a column multiplexer, and a sense amplifier. The sense amplifier may have two or more gain elements which can be individually selected to adjust the gain level of the sense amplifier. | 08-29-2013 |
20130223160 | DATA TRANSMISSION CIRCUITS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME - A semiconductor memory device including a first edge region for receiving a write command through a first pad portion to generate a column enable signal used in creation of a column selection signal; a second edge region including a data transmission control circuit capable of receiving an input data and a data strobe signal through a second pad portion and capable of receiving an address signal from the first pad portion to generate and output transmission data, the data transmission control circuit capable of outputting the column enable signal transmitted from the first edge region; and a core region including a column control portion that is capable of processing the transmission data in response to the column enable signal outputted from the second edge region to send the transmission data to bit lines electrically connected to memory cells. | 08-29-2013 |
20130229877 | MEMORY WITH BIT LINE CURRENT INJECTION - Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier. | 09-05-2013 |
20130229878 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 09-05-2013 |
20130229879 | METHOD OF USING MULTIPLEXING CIRCUIT FOR HIGH SPEED, LOW LEAKAGE, COLUMN-MULTIPLEXING MEMORY DEVICES - In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal. | 09-05-2013 |
20130235675 | OUTPUT DRIVING CIRCUIT CAPABLE OF DECREASING NOISE, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error. | 09-12-2013 |
20130242673 | TECHNIQUES FOR ACCESSING MEMORY CELLS - Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The apparatus may comprise a precharge switch coupled to a first voltage source node, a precharge capacitor coupled to the precharge switch, and a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell. The precharge switch may be configured to decouple the precharge capacitor from the first voltage source node, and the switch matrix may be configured to decouple the second voltage source node from the high impedance node of the memory cell and to couple the precharge capacitor to the high impedance node of the memory cell. | 09-19-2013 |
20130258786 | Victim Port-Based Design for Test Area Overhead Reduction in Multiport Latch-Based Memories - A multiport latch-based memory device includes a latch array, a plurality of first multiplexers, and a second multiplexer. The latch array is responsive to output data from an input data register in a functional mode associated with the latch-based memory device. The plurality of first multiplexers is responsive to output data from the latch array in the functional mode. The plurality of first multiplexers is responsive to output data from the input data register in a test mode associated with the latch-based memory device. The second multiplexer selectively provides output data from the plurality of first multiplexers to the input data register in the test mode, thereby providing a data path bypassing the latch array in the test mode. Embodiments of a corresponding method and computer-readable medium are also provided. | 10-03-2013 |
20130272072 | BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN TEST VALUES - Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed. | 10-17-2013 |
20130279269 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes two or more memory chips electrically coupled. Each of the memory chips includes global lines, a MUX unit, a selection unit, and an output unit. The global lines transmit data stored in memory cells. The MUX unit receives the data loaded onto the global lines to output a test data. The selection unit is inserted into two or more of the global lines and configured to output the test data instead of the data loaded onto the two or more global lines, in a test mode. The output unit is coupled to the global lines and is configured to output the data in a normal mode, and output the test data received from any one of the two or more global lines connected to the selection unit to an I/O pad based on information about the memory chip in a test mode. | 10-24-2013 |
20130286749 | System and Method for Memory Array Decoding - A memory array includes a plurality of sense amplifiers and a first switch module. The plurality of sense amplifiers is connected respectively to a plurality of global bit lines. The plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array. The memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines. The first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines. The first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines. | 10-31-2013 |
20130294174 | MEMORY DEVICE FOR PERFORMING MULTI-CORE ACCESS TO BANK GROUPS - A memory device has a burst length “b”, performs “k” core accesses per command, and receives a command, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”. The memory device includes a memory cell array comprising a plurality of bank groups, a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group, and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units. Data items comprised in output data of the multiplexer have a same time space. | 11-07-2013 |
20130308392 | MEMORY DEVICE AND METHOD FOR DRIVING MEMORY DEVICE - A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell. | 11-21-2013 |
20130315004 | SEMICONDUCTOR DEVICE, A METHOD FOR MANUFACTURING THE SAME, AND A SYSTEM HAVING THE SAME - A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other. | 11-28-2013 |
20140003160 | High-Speed Sensing Scheme for Memory | 01-02-2014 |
20140003161 | SEMICONDUCTOR APPARATUS AND TEST CIRCUIT THEREOF | 01-02-2014 |
20140022850 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING - A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively. | 01-23-2014 |
20140022851 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING - A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell. | 01-23-2014 |
20140043918 | AUTOMATED CONTROL OF OPENING AND CLOSING OF SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY ROWS - An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be configured to directly control when to open and close rows of a synchronous dynamic random access memory (SDRAM) during double data rate (DDR) operations. | 02-13-2014 |
20140050033 | MEMORY CELL ASSEMBLY INCLUDING AN AVOID DISTURB CELL - A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM cells are arranged in rows and columns, wherein each column is coupled to an avoid-disturb cell, a sense amplifier, and a write driver. The avoid-disturb cell receives a select signal capable of assuming first or second states. An output of the sense amplifier is coupled to an input of the write driver when the select signal is in the first state. A data-in bus is coupled to the input of the write driver if the select signal is in the second state. The write driver then sends the output signal to the SRAM cell. | 02-20-2014 |
20140071770 | Burst Sequence Control And Multi-Valued Fuse Scheme In Memory Device - A decoder circuit, responsive to a burst sequence control signal, for accessing a memory location in a memory array. The decoder circuit receives an address signal and outputs a plurality of first select lines. Logic circuitry receives these first select lines and a burst sequence control signal and outputs a plurality of second select lines. When the bust sequence control signal is unasserted, the logic circuitry passes through to the plurality of second select lines the signals received on the plurality of first select lines. When the burst sequence control signal is asserted, the logic circuitry performs a logical operation on the signals received on the plurality of first select lines and outputs the result on the plurality of second select lines. | 03-13-2014 |
20140078833 | INCREASING MEMORY OPERATING FREQUENCY - A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates. | 03-20-2014 |
20140092690 | Variable Rate Parallel to Serial Shift Register - A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to I conversion, data is received from an (N×m)-wide parallel data bus in an N by in wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent. | 04-03-2014 |
20140092691 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line. | 04-03-2014 |
20140098617 | PACKAGE - A package includes a first die and a second die. An interface connects the first die and the second die. At least one of the first and second dies includes a memory. The interface is configured to transport both control signals and memory transactions. A multiplexing circuit multiplexes the control signals and the memory transactions onto the interface such that connections of the interface are shared by the control signals and the memory transactions. | 04-10-2014 |
20140119130 | MEMORY DEVICE WITH CONTROL CIRCUITRY FOR GENERATING A RESET SIGNAL IN READ AND WRITE MODES OF OPERATION - A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation. | 05-01-2014 |
20140119131 | MEMORY DEVICE REDUNDANCY MANAGEMENT SYSTEM - A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device. | 05-01-2014 |
20140133246 | CONFIGURABLE EMBEDDED MEMORY SYSTEM - An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data. | 05-15-2014 |
20140140143 | MEMORY CIRCUIT AND METHOD OF OPERATING THE MEMORY CIRCUIT - A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage. | 05-22-2014 |
20140140144 | SENSE AMPLIFIER CIRCUIT - A sense amplifier circuit includes first and second signal lines and first and second inverters. Each inverter includes an input terminal, an output terminal, and a power source terminal. A second signal line potential is supplied to the first inverter input terminal. The second inverter input terminal is connected to the first inverter output terminal, and the second inverter output terminal is connected to the first inverter input terminal. A first signal line potential is supplied to the second inverter input terminal. A first switch transistor is connected to the first inverter power source terminal and has a gate connected to the second signal line. A switch second transistor is connected to the second inverter power source terminal and has a gate connected to the first signal line. | 05-22-2014 |
20140146618 | CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT - A circuit arrangement, having a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and at least one second access line; an access controller configured to control an access to at least one electronic component of the plurality of electronic components via the at least one first access line and the at least one second access line; a bias circuit configured to provide a defined potential to at least one of the first access lines, wherein the bias circuit is configured, during an access to an electronic component via one selected first access line of the plurality of first access lines, to provide the defined potential to one or two first access lines of the plurality of first access lines, wherein the one or two first access lines are arranged adjacent to the selected first access line, and, wherein during the access to the electronic component, the potentials of the first access lines of the plurality of first access lines other than the selected first access line and the one or two first access lines arranged adjacent to the selected first access line are floating. | 05-29-2014 |
20140146619 | MEMORY WRITE ASSIST - A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell. | 05-29-2014 |
20140160861 | MEMORY DEVICE AND METHOD FOR DRIVING MEMORY ARRAY THEREOF - A memory array includes a plurality of columns of memory cells and each column of memory cells of the memory array is coupled to a local voltage source, a bit line, and a bit line bar. Provide a working voltage to pre-charge the bit line and the bit line bar of the column of memory cells when a memory cell of the column of memory cells is selected to be read, and meanwhile use local voltage sources coupled to remaining columns of memory cells of the memory array to provide high voltages lower than the working voltage to pre-charge bit lines and bit line bars of the remaining columns of memory cells. | 06-12-2014 |
20140169106 | NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME - A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver. | 06-19-2014 |
20140177343 | MEMORY DEVICE WITH HIGH-SPEED READING FUNCTION AND METHOD THEREOF - A method includes steps of: providing a first memory cell array including a plurality of first word lines, wherein a plurality of first data are stored in the first memory cell array; providing a second memory cell array including a plurality of second word lines, wherein the second memory cell array is separated from the first memory cell array, and a plurality of second data are stored in the second memory cell array; selecting one of the first word lines and one of the second word lines at a same time or an overlapping time; alternately selecting a first address of the first memory cell array and a second address of the second memory cell array to alternately read a first corresponding portion of the first data and a second corresponding portion of the second data from the first memory cell array and the second memory cell array. | 06-26-2014 |
20140177344 | METHOD AND APPARATUS FOR CLOCK POWER SAVING IN MULTIPORT LATCH ARRAYS - An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line. | 06-26-2014 |
20140204682 | METHOD AND APPARATUS FOR SIMULTANEOUSLY ACCESSING A PLURALITY OF MEMORY CELLS IN A MEMORY ARRAY TO PERFORM A READ OPERATION AND/OR A WRITE OPERATION - A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells. Each of the memory cells is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of a first bit line of the bit lines and a first word line of the word lines. The second memory cell is located at the intersection of a second bit line of the bit lines and a second word line of the word lines. The read/write module is configured to concurrently activate the first memory cell and the second memory cell to simultaneously access both the first memory cell and the second memory cell. | 07-24-2014 |
20140219036 | EQUALIZER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal. | 08-07-2014 |
20140233324 | DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA - Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal. | 08-21-2014 |
20140241070 | REFERENCE AND SENSING WITH BIT LINE STEPPING METHOD OF MEMORY - A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory. | 08-28-2014 |
20140247672 | READING MEMORY DATA - A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point. | 09-04-2014 |
20140247673 | ROW SHIFTING SHIFTABLE MEMORY - A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row. | 09-04-2014 |
20140269104 | Sense Amplifier Column Redundancy - A memory includes a redundant sense amplifier and a plurality of sense amplifier pairs. Each sense amplifier pair includes a first sense amplifier and a second sense amplifier. Each sense amplifier pair drives a common load line. The memory is configured to implement column redundancy using a single redundant sense amplifier without requiring local read lines for each sense amplifier. | 09-18-2014 |
20140269105 | CIRCUIT FOR GENERATING NEGATIVE BITLINE VOLTAGE - An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme. | 09-18-2014 |
20140293710 | Data Transmission Using Delayed Timing Signals - An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit. | 10-02-2014 |
20140307512 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 10-16-2014 |
20140321217 | APPARATUS AND METHOD FOR READING DATA FROM MULTI-BANK MEMORY CIRCUITS - The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal. The apparatus also includes a second multiplexer configured to generate data at a second output from a second selected one of a second set of bit lines of a second memory bank based on the select signal. Additionally, the apparatus includes a gating device configured to gate the data from either the first and second multiplexer outputs based on an enable signal. And, the apparatus includes an interface circuit configured to produce the gated data on a global bit line. | 10-30-2014 |
20140321218 | TECHNIQUES FOR ACCESSING MEMORY CELLS - Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The apparatus may comprise a precharge switch coupled to a first voltage source node, a precharge capacitor coupled to the precharge switch, and a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell. The precharge switch may be configured to decouple the precharge capacitor from the first voltage source node, and the switch matrix may be configured to decouple the second voltage source node from the high impedance node of the memory cell and to couple the precharge capacitor to the high impedance node of the memory cell. | 10-30-2014 |
20140340968 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal. | 11-20-2014 |
20140347938 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an input buffer configured to buffer data inputted through a data input/output pad; a data input control unit configured to transfer an output of the input buffer to a data input/output line in response to a write clock; a test loop control unit configured to output one of a signal of the data input/output line and test latch data in response to a test mode signal; a data output control unit configured to output an output of the test loop control unit in response to a read clock; an output inversion select unit configured to output an output signal of the data output control unit by inverting or non-inverting it; and an output buffer configured to buffer an output signal of the output inversion select unit and output a resultant signal to a node which is coupled with the data input/output pad and input buffer. | 11-27-2014 |
20140355358 | Circuits and Methods for Efficient Execution of A Read or A Write Operation - A system for efficient execution of a read or a write is described. The system includes a memory array including a way. The system further includes a read and compare circuit. The read and compare circuit compares data stored within lower address memory cells of the way with information received from a storage device to generate a result of comparison. Moreover, the read and compare circuit compares data stored within higher address memory cells of the way with the information to generate a result of comparison. The system further includes a merge and multiplex circuit coupled to the read and compare circuit. The merge and multiplex circuit merges the result of comparison generated based on the comparison with the lower address memory cells and the result of comparison generated based on the comparison with the higher address memory cells to create a merged outcome of comparison. | 12-04-2014 |
20140355359 | CONTINUOUS TUNING OF PREAMBLE RELEASE TIMING IN A DOUBLE DATA-RATE MEMORY DEVICE INTERFACE - Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison. | 12-04-2014 |
20140376316 | PROGRAMMABLE MEMORY CELL AND DATA READ METHOD THEREOF - A programmable memory cell includes a non-volatile memory unit, a reference current generator and a readout unit. The non-volatile memory unit is configured to be performed by a program operation, a read operation or an erase operation. The reference current generator is configured to generate a reference current; wherein a value of the reference current is dynamically modulated according to a count number of the program and erase operations performed on the non-volatile memory unit. The readout unit, electrically coupled to the non-volatile memory unit and the reference current generator, is configured to read a data stored in the non-volatile memory cell according to the reference current. A data read method applied to the aforementioned programmable memory cell is also provided. | 12-25-2014 |
20150016193 | CIRCUIT CONFIGURATION AND OPERATING METHOD FOR SAME - A circuit configuration is described including a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as a function of the control signal, into a first register unit optionally at least a part of the first set of input data or of the second set of digital input data and to write into a second register unit optionally at least a part of the first set of input data or of the second set of input data. | 01-15-2015 |
20150029794 | DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY - A circuit for a differential current sensing scheme includes first and second cell segments, first and second reference cells, and first and second current sense amplifiers. The first and second reference cells are configured to store opposite logic values. The first and second current sense amplifiers are each configured with a first node and a second node for currents therethrough to be compared with each other. A cell of the first cell segment and a cell of the second cell segment are coupled to the first nodes of the first and second current sense amplifiers, respectively, and the first and second reference cells are coupled to both the second nodes of the first and second current sense amplifiers. | 01-29-2015 |
20150043285 | INTERFACES AND DIE PACKAGES, AND APPARTUSES INCLUDING THE SAME - A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an IO channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. The interface device for a memory device includes a control input buffer configured to receive an enable signal through a control pad, a first input buffer configured to receive a first data through a first IO pad in response to a first state of the enable signal, and a second input buffer configured to receive a second data through a second IO pad in response to a second state of the enable signal. The interface device further includes an input multiplexer configured to multiplex the first data and the second data to provide an input data. | 02-12-2015 |
20150055420 | APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES - Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells. | 02-26-2015 |
20150063039 | REDUNDANCY IN STACKED MEMORY STRUCTURE - A circuit includes stacked memory arrays and a control circuit. The stacked memory arrays includes a first layer and a second layer. The control circuit is configured to receive a first address in the first layer; cause the second layer to be enabled for accessing; and provide a second row address for accessing the second layer. | 03-05-2015 |
20150078101 | METHODS AND APPARATUSES FOR ALTERNATE CLOCK SELECTION - Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode. | 03-19-2015 |
20150085586 | MEMORY DEVICE AND METHOD OF OPERATION OF SUCH A MEMORY DEVICE - A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells. | 03-26-2015 |
20150085587 | PING-PONG BUFFER USING SINGLE-PORT MEMORY - A method of controlling a ping-pong buffer includes selectively providing one of a ping gated write clock signal and a ping gated read clock signal to a single-port ping buffer, and selectively providing a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A controller of a ping-pong buffer includes a ping multiplexer and a pong multiplexer. The ping multiplexer selectively provides a ping gated write clock signal or a ping gated read clock signal to a single-port ping buffer. The pong multiplexer selectively provides a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A ping-pong buffer system includes a ping buffer, a pong buffer, a ping multiplexer, and a pong multiplexer. The ping buffer and pong buffer each include a single-port memory. | 03-26-2015 |
20150098277 | Data Strobe Generation - In an embodiment, a method of generating strobe signals includes generating a first strobe signal in a first mode by operating a multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to a control signal. In a second mode, the method includes generating a second strobe signal by operating the multiplexer with the clock signal to select between the first input signal and the second input signal, the first input signal corresponding to the control signal inverted and delayed and the second input signal having a static second signal level. | 04-09-2015 |
20150109865 | HIGH FREQUENCY PSEUDO DUAL PORT MEMORY - A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced. | 04-23-2015 |
20150109866 | DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA - Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal. | 04-23-2015 |
20150117119 | MEMORY CIRCUITRY WITH WRITE ASSIST - Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage. | 04-30-2015 |
20150117120 | GATED-FEEDBACK SENSE AMPLIFIER FOR SINGLE-ENDED LOCAL BIT-LINE MEMORIES - A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal. | 04-30-2015 |
20150131388 | HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT - The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations. | 05-14-2015 |
20150138895 | HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT - The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations. | 05-21-2015 |
20150146491 | IN-MEMORY COMPUTATIONAL DEVICE - A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each column of the memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0. The computing device additionally includes at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from the first section and a decoder to activate a word line connected to a cell in the column in the second section to write the bit line voltage into the cell. | 05-28-2015 |
20150294700 | MEMORY TIMING CIRCUIT - A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit. | 10-15-2015 |
20150325314 | At-Speed Test of Memory Arrays Using Scan - A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC. | 11-12-2015 |
20150340071 | MEMORY DEVICE WITH VARIABLE STROBE INTERFACE - A memory device includes a variable strobe interface configured to select one of a data queue strobe signal or a system clock signal to signal initiation of data receipt at the memory device. | 11-26-2015 |
20150364170 | DISTRIBUTED CLOCK SYNCHRONIZATION - A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe. | 12-17-2015 |
20150364172 | SEMICONDUCTOR APPARATUS CONFIGURED TO MANAGE AN OPERATION TIMING MARGIN - A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals. | 12-17-2015 |
20150364173 | STORAGE DEVICE INCLUDING NONVOLATILE MEMORY AND MEMORY CONTROLLER AND OPERATING METHOD OF RETIMING CIRCUIT INTERFACING COMMUNICATION BETWEEN NONVOLATILE MEMORY AND MEMORY CONTROLLER - A storage device includes a nonvolatile memory, and a memory controller adapted to control the nonvolatile memory and to transmit a first timing signal to the nonvolatile memory at a read operation. The nonvolatile memory includes a nonvolatile memory device adapted to output read data and a second timing signal in response to the first timing signal, and a retiming circuit adapted to detect a locking delay according to the first timing signal, to produce a third timing signal from the second timing signal using the detected locking delay, to retime the read data by latching the read data in synchronization with the third timing signal and to output the third timing signal and the retimed read data to the memory controller. | 12-17-2015 |
20150380075 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a first die and a second die disposed adjacent to the first die. The semiconductor package may include a plurality of pads configured for receiving and outputting data mask addresses. The semiconductor package may include mapping blocks configured to map data mask signals among the first die, the second die, and the plurality of pads in response to a received address. | 12-31-2015 |
20160005453 | SEMICONDUCTOR DEVICE - A semiconductor device may include pad blocks configured for receiving and outputting data. The semiconductor device may also include input/output driving blocks configured to transfer data received from global input/output lines to the pad blocks in response to a read operation, and transfer data from the pad blocks to the global input/output lines in response to a write operation. The input/output driving blocks are disposed in a peripheral region and control a width of the data. | 01-07-2016 |
20160005455 | MEMORY CONTROLLER AND MEMORY DEVICE COMMAND PROTOCOL - Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers. | 01-07-2016 |
20160012877 | SEMICONDUCTOR MEMORY APPARATUS | 01-14-2016 |
20160042777 | DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA - Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal. | 02-11-2016 |
20160055922 | SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE - Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs. | 02-25-2016 |
20160064054 | Double Pumped Memory Techniques - A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal. | 03-03-2016 |
20160064101 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device. The second semiconductor device may include a selective transfer unit configured to electrically couple the third pad group to the first pad group or to an interface unit electrically coupled to the first pad group, in response to a test mode enable signal. | 03-03-2016 |
20160093343 | LOW POWER COMPUTATION ARCHITECTURE - An embodiment includes a system, comprising a first memory; a plurality of first circuits, wherein each first circuit is coupled to the memory; and includes a second circuit configured to generate a first output value in response to an input value received from the first memory; and an accumulator configured to receive the first output value and generate a second output value; and a controller coupled to the memory and the first circuits, and configured to determine the input values to be transmitted from the memory to the first circuits. | 03-31-2016 |
20160111139 | DYNAMIC SELECTION OF OUTPUT DELAY IN A MEMORY CONTROL DEVICE - In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions. | 04-21-2016 |
20160118140 | SEMICONDUCTOR DEVICE - A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair. | 04-28-2016 |
20160118984 | CALIBRATION DEVICE AND MEMORY SYSTEM HAVING THE SAME - A calibration device for use in a memory system includes a bias circuit providing bias current, and a calibration unit generating a control signal for calibration. The bias circuit includes an internal resistor and measures a second bias current generated by mirroring a first bias current through the internal resistor, and adjusts the second bias current to generate the second bias current in a predetermined range as a third bias current. The calibration unit generates the control signal based on a comparison result between a reference voltage and a voltage generated based on the third bias current through an adjustable resistor. | 04-28-2016 |
20160133305 | CALIBRATION IN A CONTROL DEVICE RECEIVING FROM A SOURCE SYNCHRONOUS INTERFACE - In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path. | 05-12-2016 |
20160133314 | SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME, AND METHODS OF OPERATING MEMORY SYSTEMS - A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode. | 05-12-2016 |
20160141012 | MANAGING SKEW IN DATA SIGNALS - An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory. | 05-19-2016 |
20160148658 | ELECTRONIC DEVICE AND DATA TRANSMISSION METHOD THEREOF - An electronic device and a data transmission method thereof are provided. The electronic device includes a counter, a multiplexer, and a buffer. The counter counts the number of read times that the host device reads the electronic device, and produces a read time header corresponding to the number of read times. The multiplexer selects a piece of transmission data in a plurality of data to be transmitted according to the read time header. Each of the plurality of data to be transmitted corresponds to a different read time header related to the varied number of read times. The buffer buffers the read time header and outputs the read time header and the transmission data to the host device after receiving the transmission data. The host device decodes the read time header and the transmission data to obtain the selected data to be transmitted. | 05-26-2016 |
20160148662 | MEMORY TIMING CIRCUIT - A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit. | 05-26-2016 |
20160180896 | MEMORY WITH MULTIPLE WRITE PORTS | 06-23-2016 |
20160196857 | STACKED MEMORY DEVICE AND SYSTEM | 07-07-2016 |
20180025757 | METHOD AND APPARATUS FOR SERIAL DATA OUTPUT IN MEMORY DEVICE | 01-25-2018 |
20180025760 | APPARATUSES AND METHODS INCLUDING NESTED MODE REGISTERS | 01-25-2018 |