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Magnetic thin film

Subclass of:

365 - Static information storage and retrieval

365129000 - SYSTEMS USING PARTICULAR ELEMENT

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Class / Patent application numberDescriptionNumber of patent applications / Date published
365173000 Multiple magnetic storage layers 54
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DocumentTitleDate
20080259679Programming method of magnetic random access memory - A programming method of a magnetic random access memory (MRAM) is provided. The magnetic random access memory includes a first magnetic pinned layer, a second magnetic pinned layer and a magnetic free layer. The first magnetic pinned layer is pinned at a first magnetic direction. The second magnetic pinned layer is pinned at a second magnetic direction. The magnetic free layer is magnetized into the first magnetic direction or the second magnetic direction. The programming method includes the following the steps. In the step (a), an additional magnetic field is applied onto the magnetic free layer. In the step (b), a first electron current is emitted through the magnetic free layer to magnetize the magnetic free layer into the first magnetic direction or the second magnetic direction.10-23-2008
20100014347DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT - A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.01-21-2010
20110194343STRAM WITH COMPENSATION ELEMENT AND METHOD OF MAKING THE SAME - Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit; a reference magnetic element having a magnetization orientation that is pinned in a reference direction; an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the magnetic reference element; and a compensation element adjacent to the free magnetic layer. The compensation element applies a bias field on the magnetization orientation of the free magnetic layer. The bias field is formed of a first vector component parallel to the easy axis of the free magnetic layer and a second vector component orthogonal to the easy axis of the free magnetic layer. The bias field reduces a write current magnitude required to switch the direction of the magnetization orientation of the free magnetic layer.08-11-2011
20110194342NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS - Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.08-11-2011
20110194341SPIN-TORQUE BASED MEMORY DEVICE WITH READ AND WRITE CURRENT PATHS MODULATED WITH A NON-LINEAR SHUNT RESISTOR - A spin-torque based memory device includes a write portion including a fixed ferromagnetic spin-polarizing layer, a spin-transport layer having a spin accumulation region formed above the fixed ferromagnetic spin-polarizing layer. The memory device further includes a read portion in electrical contact with the spin-transport layer. The read portion includes a free layer magnet, a read non-magnetic layer, and a reference layer. The memory device further includes a metal contact region formed overlying the read portion and a nonlinear resistor formed between an upper surface of the spin transport layer and the metal contact region and modulating write and read current paths depending on an applied voltage, thereby creating different current paths for write and read processes.08-11-2011
20100074003Single conductor magnetoresistance random access memory cell - The single conductor magnetoresistance random access memory consists of memory cells which are made up of a flat thin film conductor, covered on both flat surfaces with thin magnetic films. Their coercive forces have different values. A current flowing through the conductor produces a magnetic field which circles the conductor. For high currents, which lead to magnetic fields larger than the coercive force of each of the magnetic films, the two magnetic films will be magnetized antiparallel to each other. Current values which produce magnetic fields between the values of the coercive field values of both films, will only modify the magnetization direction of the film with the low coercive field. It can be lined up parallel- or anti-parallel to the magnetization of the high coercive force film without changing the magnetization direction of the high coercive film. For materials which show the giant magnetoresistance effect, the resistance of the conducting film for parallel line-up of the magnetoresistance direction will differ noticeably from the resistance for a antiparallel line-up. Currents so low that the magnetic field generated around the conducting film is below the coercive fields will not change the magnetization direction even in the film with the low coercive field. Such a current can be used to measure the resistance of the memory element without destroying the information. It leads to a non-destructive read out.03-25-2010
20090296462HIGH SPEED LOW POWER MAGNETIC DEVICES BASED ON CURRENT INDUCED SPIN-MOMENTUM TRANSFER - A high speed and low power method to control and switch the magnetization direction and/or helicity of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a reference magnetic layer with a fixed magnetic helicity and/or magnetization direction and a free magnetic layer with a changeable magnetic helicity and/or magnetization direction. The fixed magnetic layer and the free magnetic layer are preferably separated by a non-magnetic layer. The fixed and free magnetic layers may have magnetization directions at a substantially non-zero angle relative to the layer normal. A current can be applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information. The resistance, which depends on the magnetic state of the device, is measured to read out the information stored in the device.12-03-2009
20130033931STORAGE ELEMENT AND STORAGE DEVICE - Provided is a storage element including a storage layer that holds information according to a magnetization state of a magnetic body, a magnetization fixing layer that has magnetization serving as a reference of the information stored in the storage layer, and an insulation layer that is formed of a non-magnetic body disposed between the storage layer and the magnetization fixing layer. The information is stored by reversing the magnetization of the storage layer using spin torque magnetization reversal occurring with a current flowing in a lamination direction of a layer configuration of the storage layer, the insulation layer, and the magnetization fixing layer, and a size of the storage layer is less than a size in which a direction of the magnetization is simultaneously changed.02-07-2013
20100046288MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - An MRAM according to the present invention has a pinned layer 02-25-2010
20130077395MAGNETIC MEMORY DEVICE - A magnetic memory device comprises a magnetic wire extending in a first direction, a pair of first electrodes operable to pass a current through the magnetic wire in the first direction or in an opposite direction to the first direction, a first insulating layer provided on the magnetic wire in a second direction being substantially perpendicular to the first direction, a plurality of second electrodes provided on the first insulating layer and provided at specified interval in the second direction, and a third electrode electrically connected to the plurality of second electrodes.03-28-2013
20130083595MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - A magnetic memory includes a first magnetic line, an electrode, a write-in portion, a second magnetic line, and a spin-wave generator. The first magnetic line has a plurality of magnetic domains and domain walls, the domain wall separating the magnetic domain. The electrode is provided to both ends of the first magnetic line. The write-in portion is provided adjacent to the first magnetic line. The second magnetic line is provided so that the second magnetic line intersects with the first magnetic line. The spin-wave generator provided to one end of the second magnetic line. The spin-wave detector provided to the other end of the second magnetic line.04-04-2013
20100110785Memory Cell With Proportional Current Self-Reference Sensing - Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.05-06-2010
20100110783SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING - A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell.05-06-2010
20130044541MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.02-21-2013
20090154230MAGNETIC MEMORY DEVICE AND METHOD - An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction. Methods of operating and manufacturing these magnetic random access memories are also disclosed.06-18-2009
20100091563MAGNETIC MEMORY WITH PHONON GLASS ELECTRON CRYSTAL MATERIAL - A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.04-15-2010
20120182796STORAGE ELEMENT AND MEMORY DEVICE - A storage element includes a storage layer which has magnetization vertical to the film surface and of which the direction of magnetization changes, a magnetization fixed layer which has magnetization vertical to the film surface serving as a reference of information, and an insulating layer, and the direction of magnetization of the storage layer changes by injecting spin-polarized electrons in the laminated direction of the layer structure so as to perform information recording, the size of an effective demagnetizing field that the storage layer receives is configured to be smaller than a saturated magnetization amount of the storage layer, and a ferromagnetic layer material constituting the storage layer has CoFeB as the base material and an anti-corrosive element is added to the base material.07-19-2012
20120182795EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.07-19-2012
20130088915NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.04-11-2013
20130088914NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.04-11-2013
20090268515Twin-Cell Semiconductor Memory Devices - Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.10-29-2009
20090067231MAGNETIC MEMORY CELL BASED ON A MAGNETIC TUNNEL JUNCTION(MTJ) WITH INDEPENDENT STORAGE AND READ LAYERS - Embodiments of the invention magnetic memory device, comprising: a magnetic tunnel junction (MTJ) which includes a first free layer optimized for reading; and a second free layer separate from the MTJ and optimized for writing.03-12-2009
20130064010MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.03-14-2013
20090237989MAGNETIC MEMORY DEVICE - A width and a thickness of a bit line are represented as W09-24-2009
20090237987Crossbar diode-switched magnetoresistive random access memory system - A magnetic memory or MRAM memory system comprising an M×N crossbar array of MRAM cells. Each memory cell stores binary data bits with switchable magnetoresistive tunnel junctions (MJT) where the electrical conductance changes as the magnetic moment of one electrode (the storage layer) in the MJT switches direction. The switching of the magnetic moment is assisted by a phase transition interlayer that transitions from antiferromagnetic to ferromagnetic at a well defined, above ambient temperature.09-24-2009
20090237988MAGNETIC MEMORY DEVICE - A magnetic memory device includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read current source which supplies a read current to the MRAM cells in a read mode, a sense amplifier which detects terminal voltages of the MRAM cells generated by the read current to generate a detection output signal, a latch circuit which latches the detection output signal to output read data, and a data write circuit which supplies a write current to the MRAM cells depending on write data in a write mode to perform writing and which supplies the write current to the MRAM cells depending on the read data in the read mode to perform rewriting.09-24-2009
20110026321MAGNETIC MEMORY WITH POROUS NON-CONDUCTIVE CURRENT CONFINEMENT LAYER - A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.02-03-2011
20110280065Write Energy Conservation In Memory - A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the first write signal is generated, and then compares the stored data with the received bits of data to determine whether each of the received bits of data was written to the memory. In response to a second write signal, received bits of data determined not to have been written during the first write signal, are written.11-17-2011
20090207653MEMORY STORAGE DEVICE WITH HEATING ELEMENT - A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.08-20-2009
20110286264MAGNETIC RANDOM ACCESS MEMORY AND INITIALIZING METHOD - A magnetic random access memory which includes a magnetic record layer which is ferromagnetic; a ferromagnetic magnetization fixed layer whose magnetization is fixed; and a non-magnetic spacer layer provided between the magnetic record layer and the magnetization fixed layer. The magnetic record layer includes a magnetization invertible region whose magnetization is invertible and which is connected to the magnetization fixed layer through the spacer layer; a first magnetization region which has a magnetization in a first direction and which is provided in parallel to the magnetization invertible region; a second magnetization region which has a magnetization in a second direction and which is provided in parallel to the magnetization invertible region; a first inclined region connected to the magnetization invertible region and the first magnetization region at a predetermined inclination angle; and a second inclined region connected to the magnetization invertible region and the second magnetization region at the inclination angle.11-24-2011
20090279354Stacked Magnetic Devices - Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying lines in common and positioned therebetween. The magnetic device is configured such that at least one of the adjacent magnetic toggling devices toggles mutually exclusively of another of the adjacent magnetic toggling devices. In an exemplary embodiment, the magnetic device comprises a plurality of levels with each of the adjacent stacked magnetic toggling devices residing in a different level.11-12-2009
20110299330PSEUDO PAGE MODE MEMORY ARCHITECTURE AND METHOD - A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.12-08-2011
20110141803Magnetic tunnel junction devices, electronic devices including a magnetic tunneling junction device and methods of fabricating the same - Perpendicular magnetic tunnel junction (MTJ) devices, methods of fabricating a perpendicular MTJ device, electronic devices including a perpendicular MTJ device and methods of fabricating the electronic device are provided, the perpendicular MTJ devices include a pinned layer, a tunneling layer and a free layer. At least one of the pinned layer and the free layer includes a multi-layered structure including an amorphous perpendicular magnetic anisotropy (PMA) material.06-16-2011
20100054034READ CIRCUIT AND READ METHOD - In a read circuit, a write circuit writes a data to be stored and/or a test data to the memory cell. A control circuit controls the write circuit to write the test data to the memory cell in a first phase, and to write the test data which is same as the first phase to the memory cell in a second phase. An integrator integrates voltages at one terminal of the memory cell during the first phase to obtain a first integrated voltage, and integrates voltages at one terminal of the memory cell during the second phase to obtain a second integrated voltage. A buffer stores the first integrated voltage. A comparator compares the first integrated voltage from the buffer with the second integrated voltage from the integrator to obtain the data.03-04-2010
20100080053STATIC SOURCE PLANE IN STRAM - The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.04-01-2010
20080310218Semiconductor memory device and its data reading method - Disclosed herein is a semiconductor memory device including a plurality of magnetic memory elements, a control line group and a read driving circuit.12-18-2008
20100054033MAGNETIC THIN LINE AND MEMORY DEVICE - A magnetic thin line includes a first magnetic film having in-plane magnetic anisotropy and a second magnetic film that is magnetically coupled to the first magnetic film and has perpendicular magnetic anisotropy. With the coupling of the first magnetic film and the second magnetic film, magnetic wall width of the first magnetic film is lower than a case where the first magnetic film is not magnetically coupled to the second magnetic film.03-04-2010
20100008135Information storage devices using magnetic domain wall movement and methods of operating the same - An information storage device includes a storage node, a write unit configured to write information to a first magnetic domain region of the storage node, and a read unit configured to read information from a second magnetic domain region of the storage node. The information storage device further includes a temporary storage unit configured to temporarily store information read by the read unit, and a write control unit electrically connected to the temporary storage unit and configured to control current supplied to the write unit. The information read from the second magnetic domain region is stored in the temporary storage unit and written to the first magnetic domain region.01-14-2010
20100034017OSCILLATING CURRENT ASSISTED SPIN TORQUE MAGNETIC MEMORY - A memory unit having a spin torque memory cell with a ferromagnetic free layer, a ferromagnetic pinned layer and a spacer layer therebetween, with the free layer having a switchable magnetization orientation with a switching threshold. A DC current source is electrically connected to the spin torque memory cell to cause spin transfer torque in the free layer. An AC current source is electrically connected to the spin torque memory cell to produce an oscillatory polarized current capable of spin transfer torque via resonant coupling with the free layer.02-11-2010
20090262575THIN FILM MAGNETIC MEMORY DEVICE CAPABLE OF CONDUCTING STABLE DATA READ AND WRITE OPERATIONS - A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.10-22-2009
20090251957SYSTEM AND METHOD FOR WRITING DATA TO MAGNETORESISTIVE RANDOM ACCESS MEMORY CELLS - Magnetic random access memory (MRAM) cell with a thermally assisted switching writing procedure and methods for manufacturing and using same. The MRAM cell includes a magnetic tunnel junction that has at least a first magnetic layer, a second magnetic layer, and an insulating layer disposed between the first and a second magnetic layers. The MRAM cell further includes a select transistor and a current line electrically connected to the junction. The current line advantageously can support a plurality of MRAM operational functions. The current line can fulfill a first function for passing a first portion of current for heating the junction and a second function for passing a second portion of current in order to switch the magnetization of the first magnetic layer.10-08-2009
20100091562TEMPERATURE DEPENDENT SYSTEM FOR READING ST-RAM - A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.04-15-2010
20100091564MAGNETIC STACK HAVING REDUCED SWITCHING CURRENT - A magnetic stack having a ferromagnetic free layer, a ferromagnetic pinned reference layer, a non-magnetic spacer layer between the free layer and the reference layer, and a variable layer proximate the free layer. The variable layer is antiferromagnetic at a first temperature and paramagnetic at a second temperature higher than the first temperature. During a writing process, the variable layer is paramagnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the variable layer provides reduced switching currents.04-15-2010
20090154229SENSING AND WRITING TO MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.06-18-2009
20110170342ELECTRONIC DEVICES UTILIZING SPIN TORQUE TRANSFER TO FLIP MAGNETIC ORIENTATION - Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.07-14-2011
20100277975SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.11-04-2010
20100118603DEVICE AND METHOD OF PROGRAMMING A MAGNETIC MEMORY ELEMENT - The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction. The first and second currents cause the non-fixed magnetization of the second magnetic element to toggle between substantially parallel to the fixed magnetization of the first magnetic element and between substantially antiparallel to the fixed magnetization of the first magnetic element.05-13-2010
20100128520NON VOLATILE MEMORY INCLUDING STABILIZING STRUCTURES - An apparatus that includes a magnetic structure including a reference layer; and a free layer; an exchange coupling spacer layer; and a stabilizing layer, wherein the exchange coupling spacer layer is between the magnetic structure and the stabilizing layer and exchange couples the free layer of the magnetic structure to the stabilizing layer.05-27-2010
20100118602DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF - A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line.05-13-2010
20120033490Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction - A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.02-09-2012
20100080054NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS READING METHOD - A reading method includes: selecting the memory cell; performing a read operation on the selected memory cell to supply the read voltage, amplifying a first voltage read out from the selected memory element, outputting a second voltage obtained by amplifying the first voltage, and storing the second voltage as a first read state; performing a write operation on the selected memory cell to supply one of the first and second write voltages, regarding a third voltage appearing on the second line during the write operation as a second read state, comparing the first read state with the second read state, and deciding a state stored in the memory element before the read operation, as a read logic state on the basis of a result of the comparison; and writing the decided read logic state into the memory element if a logic state written in the write operation is different from the decided read logic state.04-01-2010
20120294077SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack.11-22-2012
20090168506CLOSE SHAPED MAGNETIC MULTI-LAYER FILM COMPRISING OR NOT COMPRISING A METAL CORE AND THE MANUFACTURE METHOD AND THE APPLICATION OF THE SAME - Each layer in the magnetic multilayer film is a closed ring or oval ring and the magnetic moment or flux of the ferromagnetic film in the magnetic unit is in close state either clockwise or counterclockwise. A metal core is put in the geometry center position in the close-shaped magnetic multilayer film. The cross section of the metal core is a corresponding circular or oval. A MRAM is made of the closed magnetic multilayer film with or without a metal core. The close-shaped magnetic multilayer film is formed by micro process method. The close-shaped magnetic multilayer film can be used broadly in a great variety of device that uses a magnetic multilayer film as the core, such as MRAM, magnetic bead in computer, magnetic sensitive sensor, magnetic logic device and spin transistor.07-02-2009
20090161423MAGNETIC RANDOM ACCESS MEMORY - An MRAM having a first cell array group (06-25-2009
20110170340READ DIRECTION FOR SPIN-TORQUE BASED MEMORY DEVICE - A spin-torque based memory device includes a plurality of magnetic storage cells in an array, each magnetic storage cell includes at least one magnetic tunnel junction (MTJ) element, and at least one bit line and at least one bit complement line corresponding to the plurality of magnetic storage cells. Each respective MTJ element is written by driving a write current in a first or second direction to program the respective MTJ element in a low resistance state or a high resistance state and each respective MTJ element is read by driving a read current through the respective MTJ element in a direction that tends to disturb the respective MTJ element into the high resistance state.07-14-2011
20110170341METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTIONS USABLE IN SPIN TRANSFER TORQUE MAGNETIC MEMORIES - A method and system for providing a magnetic junction are described. The method and system include providing a free layer, a symmetry filter, and a pinned layer. The free layer has a first magnetic moment switchable between stable states when a write current is passed through the magnetic junction. The symmetry filter transmits charge carriers having a first symmetry with higher probability than charge carriers having another symmetry. The pinned layer has a second magnetic moment pinned in a direction. The symmetry filter resides between the free layer and the pinned layer. At least one of the free layer and the pinned layer lies in a plane, has the charge carriers of the first symmetry in a spin channel at a Fermi level, lacks the charge carriers of the first symmetry at the Fermi level in another spin channel, and has a nonzero magnetic moment component perpendicular to the plane.07-14-2011
20090296461Memory Devices and Related Data Storage Devices and Systems Including the Same - Memory devices that include a semiconductor substrate defining a data storage area and a peripheral circuit area. A first magnetic memory device is provided in the peripheral area of the semiconductor substrate and is configured to exchange data signals externally. A second magnetic memory device is provided in the data storage area of the semiconductor substrate and is configured to exchange the data signals with the first magnetic memory device. Each portion of the first magnetic memory device and a portion of the second magnetic memory device include a magnetic tunnel junction structure having at least one magnetic layer. Related data storage devices and systems are also provided.12-03-2009
20090285017MEMORY DEVICE AND MEMORY - A memory device is provided. The memory device includes a memory layer and a fixed-magnetization layer. The memory layer retains information based on a magnetization state of a magnetic material. The fixed-magnetization layer is formed on the memory layer through an intermediate layer made of an insulating material. The information is recorded on the memory layer with a change in a magnetization direction of the memory layer caused by injecting a spin-polarized electron in a stacked direction. A level of effective demagnetizing field, which is received by the memory layer, is smaller than a saturation-magnetization level of magnetization of the memory layer.11-19-2009
20110199818METHOD OF INITIALIZING MAGNETIC MEMORY ELEMENT - An initialization method is provided for a magnetic memory element including: a data recording layer having perpendicular magnetic anisotropy which includes: a first magnetization fixed region, a second magnetization fixed region, and a magnetization free region coupled to the first magnetization fixed region and the second magnetization fixed region, the data recording layer being structure so that the coercive force of the first magnetization fixed region being different from that of the second magnetization fixed region. The initialization method includes steps of: directing the magnetizations of the first magnetization fixed region, the second magnetization fixed region and the magnetization free region in the same direction; and applying a magnetic field having both components perpendicular to and parallel to the magnetic anisotropy of the data recording layer to the data recording layer.08-18-2011
20090290413Magnetic Random Access Memory with an Elliptical magnetic tunnel junction - A magnetic tunnel junction (MTJ)-based magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure and methods for manufacturing and using same. The TAS MTJ-based MRAM cell includes a magnetic tunnel junction that is formed with an anisotropic shape and that comprises a ferromagnetic storage layer, a reference layer, and an intermediate insulating layer. The ferromagnetic storage layer has a magnetization that is adjustable above a high temperature threshold; whereas, the reference layer has a fixed magnetization. The ferromagnetic storage layer is provided with a magnetocrystalline anisotropy that is oriented essentially perpendicular to a long axis of the anisotropic shape of the magnetic tunnel junction. The TAS MTJ-based MRAM cell advantageously limits the effects of dispersion in the magnetic tunnel junction shape anisotropy coming from the fabrication process and features a lower power consumption when compared with conventional MTJ-based MRAM and TAS MTJ-based MRAM cells.11-26-2009
20090296460SEMICONDUCTOR MEMORY DEVICE - The present invention provides a semiconductor memory device capable of preventing erroneous writing of a data signal. In DL drivers of an MRAM, transistors corresponding to a selected digit line group are made conductive to charge 16 digit lines to power supply voltage and charge a node to a predetermined voltage VP12-03-2009
20120294078BIPOLAR SPIN-TRANSFER SWITCHING - Orthogonal spin-transfer magnetic random access memory (OST-MRAM) uses a spin-polarizing layer magnetized perpendicularly to the free layer to achieve large spin-transfer torques and ultra-fast energy efficient switching. OST-MRAM devices that incorporate a perpendicularly magnetized spin-polarizing layer and a magnetic tunnel junction, which consists of an in-plane magnetized free layer and synthetic antiferromagnetic reference layer, exhibit improved performance over prior art devices. The switching is bipolar, occurring for positive and negative polarity pulses, consistent with a precessional reversal mechanism, and requires an energy less than 450 fJ and may be reliably observed at room temperature with 0.7 V amplitude pulses of 500 ps duration.11-22-2012
20080212364Magnetic Memory Cell and Method of Fabricating Same - A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media.09-04-2008
20100110784STRAM with Self-Reference Read Scheme - Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.05-06-2010
20100103727ST-RAM EMPLOYING A MAGNETIC RESONANT TUNNELING DIODE AS A SPACER LAYER - A memory cell that includes a first magnetic layer, the magnetization of which is free to rotate under the influence of spin torque; a tunneling layer comprising a magnetic resonant tunneling diode (MRTD); and a second magnetic layer, wherein the magnetization of the second magnetic layer is pinned, wherein the tunneling layer is between the first magnetic layer and the second magnetic layer.04-29-2010
20100103729SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ AND WRITE ASSIST METHODS - A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and the bit line read voltage is stored and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a magnetic field to the MTJ and then writing the desired resistance state are also disclosed.04-29-2010
20100103728SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ AND WRITE ASSIST METHODS - A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell, the magnetic field rotates the magnetization orientation of the free magnetic layer without switching a resistance state of the magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and the bit line read voltage is stored and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a destabilizing magnetic field to the MTJ and then writing the desired resistance state are also disclosed.04-29-2010
20100277974Single bit line SMT MRAM array architecture and the programming method - An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.11-04-2010
20110267878Josephson Magnetic Random Access Memory System and Method - One aspect of the present invention includes a Josephson magnetic random access memory (JMRAM) system. The system includes an array of memory cells arranged in rows and columns. Each of the memory cells includes an HMJJD that is configured to store a digital state corresponding to one of a binary logic-1 state and a binary logic-0 state in response to a word-write current that is provided on a word-write line and a bit-write current that is provided on a bit-write line. The HMJJD is also configured to output the respective digital state in response to a word-read current that is provided on a word-read line and a bit-read current that is provided on a bit-read line.11-03-2011
20080273380METHOD AND SYSTEM FOR PROVIDING FIELD BIASED MAGNETIC MEMORY DEVICES - A method and system for providing a magnetic memory is disclosed. The method and system include providing a plurality of magnetic storage cells in an array, a plurality of bit lines, and at least one bias structure. Each of the plurality of magnetic storage cells includes at least one magnetic element having an easy axis and being programmable by at least one write current driven through the magnetic element. The plurality of bit lines corresponds to the plurality of magnetic storage cells. The at least one bias structure is magnetically coupled with the at least one magnetic element in each of the plurality of magnetic storage cells. The at least one bias structure provides a bias field in a direction greater than zero degrees and less than one hundred eighty degrees from the easy axis.11-06-2008
20100128518Novel spin momentum transfer MRAM design - We describe the structure and method of formation of a STT MTJ or GMR MRAM cell element that utilizes transfer of spin torque as a mechanism for changing the magnetization direction of a free layer. The critical current is reduced by constructing the free layer as a lamination comprising two ferromagnetic layers sandwiching a coupling valve layer. When the Curie temperature of the coupling valve layer is above the temperature of the cell, the two ferromagnetic layers are exchange coupled in parallel directions of their magnetization. When the coupling valve layer is above its Curie temperature, it no longer exchange couples the layers and they are magnetostatically coupled. In the exchange coupled configuration, the free layer serves to store data and the cell can be read. In its magnetostatically coupled configuration, the cell can be more easily written upon because one of the layers can assist the spin torque transfer by its magnetostatic coupling. If the free layer is formed as a multi-layered lamination of N periodically repeating combinations of a ferromagnetic layer and a coupling valve layer, the critical current can be reduced by a factor of N.05-27-2010
20080205129NON-VOLATILE MAGNETIC MEMORY DEVICE - A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line. The multiple magnetic elements are arranged such that remnant magnetic field stored in them can be cumulatively sensed. In another embodiment, the magnetic element is arranged to be magnetized in a single general direction, but is shaped such that magnetic flux lines emanate from it in different directions. The different directions are arranged to direct flux lines through the sensing region of a sensor, which measures their cumulative effect.08-28-2008
20080278998Data Storage Device and Method - A serial magnetic mass storage device and associated data storage method is provided based on magnetic nanowires that support single magnetic domains separated by domain walls. Each data-storing nanowire has a plurality of crossing nanowires along its length, forming cross junctions that constitute domain wall pinning sites. Data is fed through each data-storing nanowire by moving the magnetic domains under the action of a field that alternates between alignment and anti-alignment with the crossing nanowires. The data is encoded in the chirality of the domain walls, with up and down chirality transverse domain walls being used to encode 0's and 1's. Data is clocked into each nanowire with suitable nucleation generators capable of nucleating domains with domain walls of pre-defined chirality. Data is clocked out of each nanowire with suitable magnetic field sensors that sense the chirality.11-13-2008
20110007561SELF-REFERENCED MAGNETIC RANDOM ACCESS MEMORY CELLS - The present disclosure concerns a magnetic random access memory cell containing a magnetic tunnel junction formed from an insulating layer comprised between a sense layer and a storage layer. The present disclosure also concerns a method for writing and reading the memory cell comprising, during a write operation, switching a magnetization direction of said storage layer to write data to said storage layer and, during a read operation, aligning magnetization direction of said sense layer in a first aligned direction and comparing said write data with said first aligned direction by measuring a first resistance value of said magnetic tunnel junction. The disclosed memory cell and method allow for performing the write and read operations with low power consumption and an increased speed.01-13-2011
20110007559NANOWIRE AND MEMORY DEVICE USING IT AS A MEDIUM FOR CURRENT-INDUCED WALL DISPLACEMENT - Disclosed herein are a nanowire and a current-induced domain wall displacement-type memory device using the same. The nanowire has perpendicular magnetic anisotropy and is configured in a manner that when a parameter Q, calculated by a saturation magnetization per unit area, a domain wall thickness and a spin polarizability of a ferromagnet that is a constituent material of the nanowire, has a value of (formula 1 should be inserted here) a domain wall thickness, a width “*′” and a thickness −* of the nanowire satisfy the relationship of (formula 2 should be inserted here) The present invention can be designed such that a current density capable of driving a memory device utilizing the current-driven domain wall displacement has a value of less than (formula 3 should be inserted here), through the determination of the optimal nanowire width and thickness satisfying a value of a critical current density, Jc for the domain wall displacement below a certain value required for commercialization, for a given material in the nanowire with perpendicular anisotropy. According to such a configuration of the present invention, the current density required for the domain wall displacement can be at least 10 times or further lowered than the current density in currently available nano wires. Therefore, the present invention is capable of solving the problems associated with high power consumption and malfunction of the device due to generation of Joule heat and is also capable of achieving low-cost production of memory devices.01-13-2011
20080266943Spin-torque MRAM: spin-RAM, array - A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.10-30-2008
20090279353MAGNETIC TUNNEL JUNCTION TRANSISTOR - A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material.11-12-2009
20100142265MAGNETIC STRUCTURE WITH MULTIPLE-BIT STORAGE CAPABILITIES - A magnetic structure (06-10-2010
20090161424THERMALLY ASSISTED MAGNETIC WRITE MEMORY - A thermally assisted magnetic write memory including of memory points or memory cells, each of which includes a double magnetic tunnel junction separated from one another by a layer made from an antiferromagnetic material, and whereof the stacking order of the layers constituting them is reversed with regard to one another. Each of the magnetic tunnel junctions includes a reference layer, a storage layer, an insulating layer inserted between the reference and storage layers, constituting the tunnel barrier of the magnetic tunnel junction concerned. The blocking temperature of the layer is lower than the blocking temperature of the reference layer of the corresponding magnetic tunnel junction. The product RA resistance x area of the two tunnel barriers is different. Each memory point a way to heat the storage layers to a temperature above the blocking temperature of the layers.06-25-2009
20090161422Magnetic Tunnel Junction Device with Separate Read and Write Paths - In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path.06-25-2009
20120069649NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.03-22-2012
20120069648SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are positioned between a first electrode and a second electrode.03-22-2012
20120069646SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode.03-22-2012
20090052237MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY APPARATUS - A magnetic memory element includes a laminated construction of a first electrode, a first pinned layer, a first intermediate layer, a memory layer, a second intermediate layer, a second pinned layer and a second electrode, and a third electrode coupled to the first intermediate layer and not directly coupled to the memory layer. The magnetization directions of the first pinned layer, the second pinned layer, and the memory layer are parallel or antiparallel to each other. The magnetization direction of the memory layer takes a first direction when the current is passed with a first polarity so that the current flowing through the first pinned layer exceeds a first threshold. The magnetization direction of the memory layer takes a second direction when the current is passed with a second polarity so that the current flowing through the first pinned layer exceeds a second threshold.02-26-2009
20110141802METHOD AND SYSTEM FOR PROVIDING A HIGH DENSITY MEMORY CELL FOR SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include providing a plurality of magnetic storage cells, a plurality of bit lines corresponding to the magnetic storage cells, a plurality of word lines corresponding to the magnetic storage cells, and a common voltage plane coupled with the magnetic storage cells. Each of the magnetic storage cells includes at least one magnetic element and at least one selection device coupled with the magnetic element(s). The magnetic element(s) are programmable using at least one write current driven through the magnetic element(s). The common voltage plane is coupled with the memory cells. The write current(s) flow between the common voltage plane, the magnetic element(s), and at least one of the bit lines.06-16-2011
20090219757MAGNETIC STORAGE DEVICE - A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.09-03-2009
20090251955MRAM AND DATA READ/WRITE METHOD FOR MRAM - An MRAM according to the present invention is provided with a magnetic recording layer being a ferromagnetic layer and a pinned layer connected to the magnetic recording layer through a nonmagnetic layer. The magnetic recording layer includes a magnetization switching region, a first magnetization fixed region and a second magnetization fixed region. The magnetization switching region has reversible magnetization and overlaps with the pinned layer. The first magnetization fixed region and the second magnetization fixed region are both connected to the same one end of the magnetization switching region. Also, the first magnetization fixed region and the second magnetization fixed region respectively have first fixed magnetization and second fixed magnetization whose directions are fixed. One of the first fixed magnetization and the second fixed magnetization is fixed in a direction toward the above-mentioned one end, and the other is fixed in a direction away from the above-mentioned one end.10-08-2009
20100149863Magnetic tracks, information storage devices including magnetic tracks, and methods of operating information storage devices - A magnetic track includes first and second magnetic domain regions having different lengths and different magnetic domain wall movement speeds. A longer of the first and second magnetic domain regions serves as an information read/write region. An information storage device includes a magnetic track. The magnetic track includes a plurality of magnetic domain regions and a magnetic domain wall region formed between neighboring magnetic domain regions. The plurality of magnetic domain regions includes a first magnetic domain region and at least one second magnetic domain region having a smaller length than the first magnetic domain region. The information storage device further includes a first unit configured to perform at least one of an information recording operation and an information reproducing operation on the first magnetic domain region, and a magnetic domain wall movement unit configured to move a magnetic domain wall of the magnetic domain wall region.06-17-2010
20100177561MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.07-15-2010
20100149862MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory comprises a magnetic recording layer equipped with a magnetization reversal region having a reversible magnetization and through which a write current is made to flow in the in-plane direction, a magnetization fixed layer having a fixed magnetization, a nonmagnetic layer provided between the magnetization reversal region and the magnetization fixed layer, and a heat absorbing structure provided opposing to the magnetic recording layer and having a function of receiving heat generated in the magnetic recording layer and of radiating the heat. Such magnetic random access memory can radiate heat generated in the magnetic recording layer by using the heat absorbing structure and prevent temperature rising caused by the write current flowing in the in-plane direction.06-17-2010
20100002501MRAM Device Structure Employing Thermally-Assisted Write Operations and Thermally-Unassisted Self-Referencing Operations - A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature T01-07-2010
20100177562COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES - Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.07-15-2010
20100259976Shared Transistor in a Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Cell - A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.10-14-2010
20100188894IN-SITU RESISTANCE MEASUREMENT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.07-29-2010
20100188893Heat assisted switching and separated read-write MRAM - A MRAM structure is described that has a dedicated data storage layer formed between first and second electrodes and a dedicated data sensing layer between second and third electrodes to enable separate read and write functions. A diode between the storage layer and first electrode allows a heating current to flow between first and second electrodes to switch the data storage layer while a field is applied. A second diode between the sensing layer and third electrode enables a sensing current to flow only between second and third electrodes during a read process. Data storage and sensing layers and the three electrodes may be arranged in a vertical stack or the sensing layer, second diode, and third electrode may be shifted between adjacent stacks each containing first and second electrodes, a storage layer, and first diode. Second electrode and the sensing layer may be continuous elements through multiple MRAMs.07-29-2010
20090316475Information storage devices and methods of operating the same - Provided are an information storage device and a method of operating the same. The information storage device includes: a magnetic layer having a plurality of magnetic domain regions and a magnetic domain wall interposed between the magnetic domain regions; a first unit disposed on a first region which is one of the plurality of magnetic domain regions for recording information to the first region; a second unit connected to the first unit for inducing a magnetic field so as to record information to the first region.12-24-2009
20100188895STAGGERED STRAM CELL - Spin-transfer torque memory having a free magnetic layer having a thickness extending in a out-of-plane direction and extending in a lateral direction in an in-plane direction between a first end portion and an opposing second end portion. A tunneling barrier separates a reference magnetic layer from the first end portion and forms a magnetic tunnel junction. A first electrode is in electrical communication with the reference magnetic layer and a second electrode is in electrical communication with the free magnetic layer second end portion such that current flows from the first electrode to the second electrode and passes through the free magnetic layer in the lateral direction to switch the magnetic tunnel junction between a high resistance state and a low resistance state.07-29-2010
20100226169STRAM WITH COMPENSATION ELEMENT AND METHOD OF MAKING THE SAME - Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit; a reference magnetic element having a magnetization orientation that is pinned in a reference direction; an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the magnetic reference element; and a compensation element adjacent to the free magnetic layer. The compensation element applies a bias field on the magnetization orientation of the free magnetic layer. The bias field is formed of a first vector component parallel to the easy axis of the free magnetic layer and a second vector component orthogonal to the easy axis of the free magnetic layer. The bias field reduces a write current magnitude required to switch the direction of the magnetization orientation of the free magnetic layer.09-09-2010
20100238721Stuck-At Defect Condition Repair for a Non-Volatile Memory Cell - A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.09-23-2010
20100142264MAGNETIC MEMORY CELL, MAGNETIC RANDOM ACCESS MEMORY, AND DATA READ/WRITE METHOD FOR MAGNETIC RANDOM ACCESS MEMORY - The present invention provides a new data writing method for an MRAM which can suppress deterioration of a tunnel barrier layer.06-10-2010
20120069647SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more SIT memory cell structures comprise a STT stack including; a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material positioned between a ferromagnetic storage material and the pinned ferromagnetic material; a multiferroic material in contact with the ferromagnetic storage material; and a first electrode and a second electrode, wherein the antiferromagnetic material, the pinned ferromagnetic material, and the ferromagnetic storage material are located between the first electrode and the second electrode. The STT memory cell structure can include a third electrode and a fourth electrode, wherein at least a first portion of the multiferroic material is located between the third and the fourth electrode.03-22-2012
20100085805MAGNETIC RANDOM ACCESS MEMORY (MRAM) UTILIZING MAGNETIC FLIP-FLOP STRUCTURES - Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing layer; and a first stabilizing layer, wherein the first tunnel barrier structure is between the magnetization controllable structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the first tunnel barrier structure, wherein the magnetic flip-flop device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization so that the device reaches one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current; a second tunnel barrier structure and a reference layer, wherein the second tunnel barrier structure is between the magnetic flip-flop device and the reference layer. MRAM cells that include such devices and arrays including such cells are also disclosed.04-08-2010
20090251956Magnetic random access memory devices, methods of driving the same and data writing and reading methods for the same - A magnetic memory device includes a lower structure or an antiferromagnetic layer, a pinned layer, an information storage layer, and a free layer formed on the lower structure or the antiferromagnetic layer. In a method of operating a magnetic memory device, information from the storage information layer is read or stored after setting the magnetization of the free layer in a first magnetization direction. The information is stored when the first magnetization direction is opposite to a magnetization direction of the pinned layer, but is read when the first magnetization direction is the same as the magnetization direction of the pinned layer.10-08-2009
20090073756Boosted gate voltage programming for spin-torque MRAM array - A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.03-19-2009
20090323410System and Method to Fabricate Magnetic Random Access Memory - A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, a method of aligning a magnetic film during deposition is disclosed. The method includes applying a first magnetic field along a first direction in a region in which a substrate resides during a deposition of a first magnetic material onto the substrate. The method further includes applying a second magnetic field along a second direction in the region during the deposition of the first magnetic material onto the substrate.12-31-2009
20110032755VOLTAGE BOOSTING IN MRAM CURRENT DRIVERS - Disclosed is a current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor M02-10-2011
20090109739LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.04-30-2009
20090109740Semiconductor device using magnetic domain wall movement - Provided may be a semiconductor device using magnetic domain wall movement. The semiconductor device may include a magnetic track having a plurality of magnetic domains and a thermal conductive insulating layer configured to contact the magnetic track. The thermal conductive insulating layer may prevent or reduce the magnetic track from being heated due to a current supplied to the magnetic track.04-30-2009
20080273381Method for Switching Random Access Memory Elements and Magnetic Element Structures - A method for storing data in a magnetic memory element of an array of elements which avoids inadvertent switching of other elements. First and second magnetic fields are applied to a selected magnetic element for a first time interval to switch the element into an intermediate state where minor domains are created. A second value of magnetic fields are then applied large enough to switch the magnetization of the minor domains, but not large enough to switch the magnetization of an adjacent memory cell. Once the minor domain is switched, the magnetization of the magnetic element assumes the state where the major domain has a magnetization direction representing the value of the stored data bit.11-06-2008
20100302843Spin Transfer Torque - Magnetic Tunnel Junction Device and Method of Operation - A method is disclosed that includes controlling current flow direction for current sent over a source line or a bit line of a magnetic memory device. A current generated magnetic field assists switching of a direction of a magnetic field of a free layer of a magnetic element within a spin transfer torque magnetic tunnel junction (STT-MTJ) device.12-02-2010
20100321994MEMORY SELF-REFERENCE READ AND WRITE ASSIST METHODS - A magnetic tunnel junction memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a magnetic tunnel junction memory unit includes applying a first read current through a magnetic tunnel junction data cell to form a first bit line read voltage, then applying a first magnetic field through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell, and then applying a second read current thorough the magnetic field modified magnetic tunnel junction data cell to form a second bit line read voltage. The first read current being less than the second read current. Then comparing the first bit line read voltage with the second bit line read voltage to determine whether the magnetic tunnel junction data cell was in a high resistance state or a low resistance state. Methods of applying a magnetic field to the MTJ and then writing the desired resistance state are also disclosed.12-23-2010
20100321993Methods of forming spin torque devices and structures formed thereby - Methods of forming spin torque microelectronic devices are described. Those methods may include forming a free FM layer on a substrate, forming a non-magnetic layer on the free FM layer, forming at least three input pillars on the non-magnetic layer, and forming an output pillar on the non-magnetic layer to form a majority gate device.12-23-2010
20110002162Gate drive voltage boost schemes for memory array - This invention describes a circuit and method to limit the stress caused by gate voltages required to write a one or zero in magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, which require high programming currents. The circuit and method selects one cell at a time for writing a one or a zero, different voltages to write a one or a zero, and a precharge circuit to limit the stress on non selected cells.01-06-2011
20110026320STAGGERED MAGNETIC TUNNEL JUNCTION - A staggered magnetic tunnel junction includes a free magnetic layer extending in a lateral direction between a first end portion and an opposing second end portion and a tunneling barrier disposed between a reference magnetic layer and the first end portion and forming a magnetic tunnel junction. Current flows through the free magnetic layer in the lateral direction to switch the magnetic tunnel junction between a high resistance state and a low resistance state.02-03-2011
20110026322RECORDING METHOD FOR MAGNETIC MEMORY DEVICE - [Object] To provide a recording method for a magnetic memory device including a recording layer that is capable of changing a magnetization direction and holds information as a magnetization direction of a magnetic body and a magnetization reference layer that is provided with respect to the recording layer with an insulation layer interposed therebetween and becomes a reference of the magnetization direction, the magnetic memory device being recorded with information by a current flowing between the recording layer and the magnetization reference layer via the insulation layer, the recording method being capable of maintaining, even when a write pulse considerably higher than an inversion threshold value is applied, a write error rate of 1002-03-2011
20090067232Multiple Magneto-Resistance Devices Based on Doped Magnesium Oxide - The present invention provides a low resistance high magnetoresistance (MR) device comprised of a junction of two magnetic elements separated by a magnesium oxide (MgO) layer doped with such metals as Al and Li. Such device can be used as a sensor of magnetic field in magnetic recording or as a storage element in magnetic random access memory (MRAM). The invention provides a high-MR device possessing a diode function, comprised of a double junction of two outer magnetic elements separated by two MgO insulating layer and a center MgO layer doped with such metals as Al and Li. Such device provides design advantages when used as a storage element in MRAM. The invention with MR wherein a gate electrode is placed in electrical or physical contact to the center layer of the double tunnel junction.03-12-2009
20110044099HEAT ASSISTED MAGNETIC WRITE ELEMENT - This magnetic element for writing by magnetic field or heat assisted spin transfer comprises a stack consisting of: 02-24-2011
20090034326METHODS AND APPARATUS FOR THERMALLY ASSISTED PROGRAMMING OF A MAGNETIC MEMORY DEVICE - A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic memory device can be configured so that a first current flows through the thermal plate heating the thermal plate. The magnetic behavior of the free layer can be altered due to the heating caused by the first current, making it easier to switch the orientation and magnetization of the free layer. A second current can then flow through a bit line near the free layer generating a magnetic field sufficient to switch the orientation of magnetization of the free layer.02-05-2009
20100220524MAGNETIC BOOSTER FOR MAGNETIC RANDOM ACCESS MEMORY - Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost a magnetic field generated by current flowing therein.09-02-2010
20100014346UNIPOLAR SPIN-TRANSFER SWITCHING MEMORY UNIT - A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state.01-21-2010
20110149646TRANSIENT HEAT ASSISTED STTRAM CELL FOR LOWER PROGRAMMING CURRENT - A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the cell. The heat transferred from the heating region increases the temperature of the free region, which decreases the magnetization and the critical switching current density of the free region. In some embodiments, the heating region may also provide a current path to the free region, and the magnetization of the free region may be switched according to the spin polarity of the programming current, programming the memory cell to a high resistance state or a low resistance state.06-23-2011
20110149648PROGRAMMABLE DEVICE - A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is in immediate contact with the multiferroic material. Magnetization of the ferromagnetic material is switchable by a transition between the first switching state and the second switching state of the multiferroic material by an exchange coupling between electronic states of the multiferroic material and the ferromagnetic material. The programmable device also includes means for determining a direction of the magnetization of the ferromagnetic material. A spin valve effect is used for causing an electrical resistance between the source and the drain electrode.06-23-2011
20100135072Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirectional Write Current - Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.06-03-2010
20100128519NON VOLATILE MEMORY HAVING INCREASED SENSING MARGIN - A non volatile memory assembly that includes a reference element having: a reference component; and a reference transistor, wherein the reference component is electrically connected to the reference transistor, and the reference transistor controls the passage of current across the reference component; and at least one non volatile memory element having: a non volatile memory cell, having at least a low and a high resistance state; and an output that electrically connects the reference element with the at least one non volatile memory element, wherein the reference transistor and the memory transistor are activated by a reference gate voltage and a memory gate voltage respectively, and the reference gate voltage and the memory gate voltage are not the same.05-27-2010
20110249491METHOD AND APPARATUS FOR PROGRAMMING A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.10-13-2011
20110249490Asymmetric Write Scheme for Magnetic Bit Cell Elements - Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.10-13-2011
20100124106MAGNETIC MEMORY WITH MAGNETIC TUNNEL JUNCTION CELL SETS - A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set.05-20-2010
20110069541FERROMAGNETIC THIN WIRE ELEMENT - The present invention uses a ferromagnetic thin wire having a domain wall inside, with the magnetic moment at the center thereof being perpendicular to the longitudinal axis of the thin wire. With the domain wall being fixed by a domain wall fixation device (e.g. antiferromagnetic thin wires) so that the domain wall is prevented from moving in the ferromagnetic thin wire, when a direct current is supplied, the magnetic moment rotates in the immobilized domain wall. This rotation of the moment can be detected by a TMR element or the like. This configuration of the ferromagnetic thin wire element can be directly used to create a microwave oscillator or magnetic memory.03-24-2011
20100309718SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.12-09-2010
20100284215MAGNETIC MEMORY WITH A THERMALLY ASSISTED WRITING PROCEDURE AND REDUCED WRITING FIELD - A magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure, comprising a magnetic tunnel junction formed from a ferromagnetic storage layer having a first magnetization adjustable at a high temperature threshold, a ferromagnetic reference layer having a fixed second magnetization direction, and an insulating layer, said insulating layer being disposed between the ferromagnetic storage and reference layers; a select transistor being electrically connected to said magnetic tunnel junction and controllable via a word line; a current line electrically connected to said magnetic tunnel junction; characterized in that the magnetocrystalline anisotropy of the ferromagnetic storage layer is essentially orthogonal with the magnetocrystalline anisotropy of the ferromagnetic reference layer. The TAS-MRAM cell of the invention can be written with a smaller magnetic field than the one used in conventional TAS-MRAM cells and has low power consumption.11-11-2010
20100284216INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME - An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data.11-11-2010
20100329001Methods of operating semiconductor memory devices including magnetic films having electrochemical potential difference therebetween - Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic film, and an upper magnetic film formed on the tunneling film, wherein the lower and upper magnetic films are ferromagnetic films forming an electrochemical potential difference therebetween when the lower and upper magnetic films have opposite magnetization directions.12-30-2010
20100328999MEMORY AND DATA PROCESSING METHOD - A memory includes: memory devices that each store data of one bit; and a read unit that, by using one predetermined memory device of the memory devices that are included in a memory block having a predetermined unit number of the memory devices as an inversion flag device, reads out data of (the predetermined unit number −1) bits that is written in the other memory devices with the bits being inverted in a case where the data of one bit written in the inversion flag device is a first value representing any one of “0” and “1” and directly reads out the data of (the predetermined unit number −1) bits that is written in the other memory devices in a case where the data of one bit written in the inversion flag device is a second value other than the first value.12-30-2010
20100328998MEMORY AND WRITE CONTROL METHOD - A memory includes: a memory device that has a memory layer storing data as a magnetization state of a magnetic body and a magnetization fixed layer whose direction of magnetization is fixed through a nonmagnetic layer interposed between the memory layer and the magnetization fixed layer and stores the data in the memory layer by changing a magnetization direction of the memory layer when a write current flowing in a stacked direction of the memory layer and the magnetization fixed layer is applied; and a voltage control unit that supplies the write current configured by independent pulse trains of two or more to the memory device by using a write voltage that is configured by independent pulse trains of two or more.12-30-2010
20110080782WRITE CURRENT COMPENSATION USING WORD LINE BOOSTING CIRCUITRY - Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.04-07-2011
20100097852MRAM DIODE ARRAY AND ACCESS METHOD - A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.04-22-2010
20110176360MAGNETIC RANDOM ACCESS MEMORY (MRAM) UTILIZING MAGNETIC FLIP-FLOP STRUCTURES - Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing layer; and a first stabilizing layer, wherein the first tunnel barrier structure is between the magnetization controllable structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the first tunnel barrier structure, wherein the magnetic flip-flop device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization so that the device reaches one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current; a second tunnel barrier structure and a reference layer, wherein the second tunnel barrier structure is between the magnetic flip-flop device and the reference layer. MRAM cells that include such devices and arrays including such cells are also disclosed.07-21-2011
20100214834THIN FILM MAGNETIC MEMORY DEVICE INCLUDING MEMORY CELLS HAVING A MAGNETIC TUNNEL JUNCTION - In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, and therefore, the data read speed can be increased.08-26-2010
20100195381SWITCHABLE ELEMENT - A switchable element. The element includes a source electrode, a drain electrode, a conducting channel between the source electrode and the drain electrode, and a gate with multiferroic material being switchable, by application of an electrical signal to the gate, between a first switching state with a first spontaneous polarization direction and a second switching state with a second spontaneous polarization direction. The conducting channel is magnetoresistive, and a magnetic field strength at the conducting channel in the first switching state is different than a magnetic field strength in the second switching state, whereby a current-voltage characteristic of the conducting channel is dependent on the switching state of the multiferroic material.08-05-2010
20100329000NON-VOLATILE MEMORY - Non-volatile memories can have data retention problems at high temperatures reducing the reliability of such devices. A non-volatile memory cell is described having a magnet, a ferromagnetic switching element and heating means. The non-volatile memory cell has a set position having a low resistance state and a reset position having a high resistance state. The non-volatile memory is set by applying a magnetic field to the switching element causing it to move to the set position. The non-volatile memory cell is reset by the heating means which causes the switching element to return to the reset position. The switching element is formed from a ferromagnetic material or a ferromagnetic shape memory alloy. This structure can have improved reliability at higher temperatures than previously described non-volatile memories.12-30-2010
20100067292Semiconductor Integrated Circuit - A semiconductor integrated circuit is provided that can prevent an internal voltage from the voltage generating circuit from varying during a long term. The semiconductor integrated circuit of the present invention includes a voltage generating circuit configured to generate a reference voltage; a function circuit configured to operate by using the reference voltage; a first capacitance connected to a first node between the voltage generating circuit and the function circuit; and a switch provided between the voltage generating circuit and the first node. The switch is in a turned-off state at least for a period during which the function circuit is in an activated state.03-18-2010
20100195379System and Method of Pulse Generation - In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.08-05-2010
20100195382THIN FILM MAGNETIC MEMORY DEVICE CAPABLE OF CONDUCTING STABLE DATA READ AND WRITE OPERATIONS - A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.08-05-2010
20100195380Non-Volatile Memory Cell with Precessional Switching - A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.08-05-2010
20110188306Increased Magnetic Damping for Toggle MRAM - Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer.08-04-2011
20110188305Read disturb free SMT MRAM reference cell circuit - An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.08-04-2011
20110141804METHOD AND SYSTEM FOR PROVIDING DUAL MAGNETIC TUNNELING JUNCTIONS USABLE IN SPIN TRANSFER TORQUE MAGNETIC MEMORIES - A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The pinned layers are nonmagnetic layer-free and self-pinned. In some aspects, the magnetic junction is configured to allow the free and second pinned layers to be switched between stable magnetic states when write currents are passed therethrough. The magnetic junction has greater than two stable states. In other aspects, the magnetic junction includes at least third and fourth spacer layers, a second free layer therebetween, and a third pinned layer having a pinned layer magnetic moment, being nonmagnetic layer-free, and being coupled to the second pinned layer. The magnetic junction is configured to allow the free layers to be switched between stable magnetic states when write currents are passed therethrough.06-16-2011
20110149647Perpendicular magnetic tunnel junctions, magnetic devices including the same and method of manufacturing a perpendicular magnetic tunnel junction - Provided are a perpendicular magnetic tunnel junction (MTJ), a magnetic device including the same, and a method of manufacturing the MTJ, the perpendicular MTJ includes a lower magnetic layer; a tunnelling layer on the lower magnetic layer; and an upper magnetic layer on the tunnelling layer. One of the upper and lower magnetic layers includes a free magnetic layer that exhibits perpendicular magnetic anisotropy, wherein the magnetizing direction of the free magnetic layer is changed by a spin polarization current. A polarization enhancing layer (PEL) and an exchange blocking layer (EBL) are stacked between the tunnelling layer and the free magnetic layer.06-23-2011
20110051509System and Method to Manufacture Magnetic Random Access Memory - A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device.03-03-2011
20110007560SPIN POLARISED MAGNETIC DEVICE - A magnetic device includes a magnetic reference layer with a fixed magnetisation direction located either in the plane of the layer or perpendicular to the plane of the layer, a magnetic storage layer with a variable magnetisation direction, a non-magnetic spacer separating the reference layer and the storage layer and a magnetic spin polarising layer with a magnetisation perpendicular to that of the reference layer, and located out of the plane of the spin polarising layer if the magnetisation of the reference layer is directed in the plane of the reference layer or in the plane of the spin polarising layer if the magnetisation of the reference layer is directed perpendicular to the plane of the reference layer. The spin transfer coefficient between the reference layer and the storage layer is higher than the spin transfer coefficient between the spin polarising layer and the storage layer.01-13-2011
20120307556MAGNETIC DEVICE WITH EXCHANGE BIAS - A magnetic device includes a magnetic layer having a variable direction of magnetisation, and a first antiferromagnetic layer in contact with the magnetic layer, the first antiferromagnetic layer being able to trap the direction of magnetisation of the magnetic layer. The magnetic device also includes a layer made of a ferromagnetic material in contact with the first antiferromagnetic layer through its face opposite to the magnetic layer, the directions of magnetisation of the magnetic and ferromagnetic layers being substantially perpendicular. A first layer among the magnetic and ferromagnetic layers has a magnetisation, the direction of which is oriented in the plane of the first layer whereas the second of the two layers among the magnetic and ferromagnetic layers has a magnetisation, the direction of which is oriented outside of the plane of the second layer.12-06-2012
20110134689MAGNETIC RECORDING ELEMENT, MAGNETIC MEMORY CELL, AND MAGNETIC RANDOM ACCESS MEMORY - A low-power consumption non-volatile memory employing an electric field write magnetic recording element is provided. A multiferroic layer 06-09-2011
20110134688Asymmetric Write Current Compensation - An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.06-09-2011
20110305077MEMORY DEVICE - Disclosed herein is a memory device, including: a memory element including a memory layer for holding therein information in accordance with a magnetization state of a magnetic material, a fixed magnetization layer which is provided on the memory layer through a non-magnetic layer and whose direction of a magnetization is fixed to a direction parallel with a film surface, and a magnetic layer which is provided on a side opposite to the fixed magnetization layer relative to the memory layer through a non-magnetic layer and whose direction of a magnetization is a direction vertical to the film surface; and a wiring through which a current is caused to flow through the memory element in a direction of lamination of the layers of the memory element.12-15-2011
20110305078LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.12-15-2011
20090073755MRAM read bit with askew fixed layer - A new read scheme is provided for an MRAM bit having a reference layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. The reference layer has a magnetization direction that is tilted with respect to an easy axis of the storage layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer.03-19-2009
20120039119METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING A BIAXIAL ANISOTROPY - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic anisotropy, at least a portion of which is a biaxial anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.02-16-2012
20090046501LOW-COST NON-VOLATILE FLASH-RAM MEMORY - A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die.02-19-2009
20120155164Multibit Cell of Magnetic Random Access Memory With Perpendicular Magnetization - A multi-bit cell of magnetic random access memory comprises a magnetic tunnel junction element including a first and second free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state and a switching current, a first and second tunnel barrier layer, and a pinned layer comprising a fixed magnetization oriented substantially perpendicular to a layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers, a selection transistor electrically connected to a word line, and a bit line intersecting the word line. The magnetic tunnel junction element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.06-21-2012
20120044755System and Method of Reference Cell Testing - In a particular embodiment, a method of testing a reference cell in a memory array includes coupling a first reference cell of a first reference cell pair of the memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array.02-23-2012
20120044754Spin-Torque Transfer Magneto-Resistive Memory Architecture - A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT02-23-2012
20120002466STORAGE APPARATUS - Disclosed herein is a storage apparatus including a cell array configured to include storage devices arranged to form an array. Each of the storage device has: a storage layer for storing information as the state of magnetization of a magnetic substance; a fixed-magnetization layer having a fixed magnetization direction; and a tunnel insulation layer sandwiched between the storage layer and the fixed-magnetization layer. In an operation to write information on the storage layer, a write current is generated to flow in the layer-stacking direction of the storage layer and the fixed-magnetization layer in order to change the direction of the magnetization of the storage layer. The cell array is divided into a plurality of cell blocks. The thermal stability of the storage layer of any particular one of the storage devices has a value peculiar to the cell block including the particular storage device.01-05-2012
20100008134TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT - A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.01-14-2010
20120063218SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR MAGNETIC ANISOTROPY MULTILAYERS - A spin-torque transfer memory random access memory (STTMRAM) element includes a composite fixed layer formed on top of a substrate and a tunnel layer formed upon the fixed layer and a composite free layer formed upon the tunnel barrier layer, the magnetization direction of each of the composite free layer and fixed layer being substantially perpendicular to the plane of the substrate. The composite layers are made of multiple repeats of a bi-layer unit which consists of a non-magnetic insulating layer and magnetic layer with thicknesses adjusted in a range that makes the magnetization have a preferred direction perpendicular to film plane.03-15-2012
20120063219MAGNETIC VORTEX STORAGE DEVICE - A magnetic storage device includes a network of planar magnetic cells in a vortex state, each cell's vortex core having a magnetization with either a first and second equilibrium position in opposite direction and perpendicular to the cellular plane, each of the two positions representing binary information. The device includes means for writing binary information stored in the cells, including means for selectively applying, in the vicinity of each cell, a first bias static magnetic field roughly perpendicular to the cellular plane and a linearly polarized radio frequency magnetic field roughly parallel to the device. The described device also includes means for reading preferably resonantly the polarity using a selective transport measurement between two intersecting electrodes by guiding the current lines through the region around the vortex core by means of a point contact.03-15-2012
20120057403MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element including a memory layer that maintains information through the magnetization state of a magnetic material, a magnetization-fixed layer with a magnetization that is a reference of information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. The storing of the information is performed by inverting the magnetization of the memory layer by using a spin torque magnetization inversion occurring according to a current flowing in the lamination direction of a layered structure having the memory layer, the intermediate layer, and the magnetization-fixed layer, the memory layer includes an alloy region containing at least one of Fe and Co, and a magnitude of an effective diamagnetic field which the memory layer receives during magnetization inversion thereof is smaller than the saturated magnetization amount of the memory layer.03-08-2012
20120206959MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory cell 08-16-2012
20120206958MAGNETIC RANDOM ACCESS MEMORY WITH FIELD COMPENSATING LAYER AND MULTI-LEVEL CELL - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.08-16-2012
20120300543MAGNETIC TUNNEL JUNCTIONS WITH PERPENDICULAR MAGNETIZATION AND MAGNETIC RANDOM ACCESS MEMORY - In magnetic tunnel junctions manufactured with use of a ferromagnetic material having perpendicular magnetic anisotropy, a difference in record retention time depending on stored information due to an imbalance in thermal stability between a parallel state and an anti-parallel state of magnetization, which correspond to bit information, is alleviated. A reference layer and a recording layer which constitute a magnetic tunnel junction are made different in area from each other so as to correct the difference in record retention time corresponding to stored information.11-29-2012
20120300542STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes a storage layer which has magnetization perpendicular to its film surface and which retains information by a magnetization state of a magnetic substance, a magnetization pinned layer having magnetization perpendicular to its film surface which is used as the basis of the information stored in the storage layer, an interlayer of a non-magnetic substance provided between the storage layer and the magnetization pinned layer, and a cap layer which is provided adjacent to the storage layer at a side opposite to the interlayer and which includes at least two oxide layers. The storage element is configured to store information by reversing the magnetization of the storage layer using spin torque magnetization reversal generated by a current passing in a laminate direction of a layer structure including the storage layer, the interlayer, and the magnetization pinned layer.11-29-2012
20120300541STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes: a storage layer which retains information by a magnetization state of a magnetic substance; a magnetization pinned layer having magnetization which is used as the basis of the information stored in the storage layer; and an interlayer of a non-magnetic substance provided between the storage layer and the magnetization pinned layer. The storage element is configured to store information by reversing magnetization of the storage layer using spin torque magnetization reversal generated by a current passing in a laminate direction of a layer structure including the storage layer, the interlayer, and the magnetization pinned layer, and when the saturation magnetization of the storage layer and the thickness thereof are represented by Ms (emu/cc) and t (nm), respectively, (1489/Ms)−0.59311-29-2012
20100277976MAGNETIC MEMORY DEVICES INCLUDING MAGNETIC LAYERS HAVING DIFFERENT PRODUCTS OF SATURATED MAGNETIZATION AND THICKNESS AND RELATED METHODS - A magnetic memory device may include a tunnel barrier, a reference layer on a first side of the tunnel barrier, and a free layer on a second side of the tunnel barrier so that the tunnel barrier is between the reference and free layers. The free layer may include a first magnetic layer adjacent the tunnel barrier, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer. More particularly, the nonmagnetic layer may be between the first and second magnetic layers, and the first magnetic layer may be between the tunnel barrier and the second magnetic layer. A product of a saturated magnetization of the first magnetic layer and a thickness of the first magnetic layer may be less than a product of a saturated magnetization of the second magnetic layer and a thickness of the second magnetic layer. Related methods are also discussed.11-04-2010
20110103143LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.05-05-2011
20120250404MAGNETIC TUNNEL JUNCTION WITH FREE LAYER HAVING EXCHANGE COUPLED MAGNETIC ELEMENTS - A magnetic tunnel junction device includes a reference magnetic layer and a magnetic free layer including first and second magnetic elements that are magnetically exchange coupled. The magnetic exchange coupling between the first and second magnetic elements is configured to achieve a switching current distribution less than about 200% and a long term thermal stability criterion of greater than about 60 k10-04-2012
20120250405MAGNETIC FIELD ASSISTED STRAM CELLS - Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations.10-04-2012
20100290281METHOD FOR RECORDING OF INFORMATION IN MAGNETIC RECORDING ELEMENT AND METHOD FOR RECORDING OF INFORMATION IN MAGNETIC RANDOM ACCESS MEMORY - Provided are a method for recording information in a magnetic recording element and a method for recording information in a magnetic random access memory. The method for recording information in a magnetic recording element includes preparing the magnetic recording element having a magnetic free layer in which a magnetic vortex is formed. A current or a magnetic field whose direction varies with time is applied to the magnetic free layer to switch a core orientation of a magnetic vortex formed in the magnetic free layer to an upward direction or downward direction from a top surface of the magnetic free layer “0” or “1” is assigned according to the direction of the core orientation of the magnetic vortex formed in the magnetic free layer. According to the method for recording information in a magnetic recording element of the present invention, the core orientation of the magnetic vortex formed in the magnetic free layer of the magnetic recording element can be selectively switched by applying a current or magnetic field whose direction varies with time to the magnetic recording element, so that information can be easily and correctly recorded, lower power is consumed in recording information, and the switching for recording information can be performed very rapidly.11-18-2010
20100290280SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.11-18-2010
20100290279Semiconductor Memory Device and Method for Operating the Same - A semiconductor memory device includes a plurality of memory cells configured to store data having a polarity corresponding to a direction of current flowing through a source line and a bit line; and a precharge driving unit configured to precharge the bit line to a voltage corresponding to the data in response to a precharging signal before the data are stored in the memory cells.11-18-2010
20120314494SEMICONDUCTOR STORAGE DEVICE - In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of the cell transistors. Second bit lines each of which is electrically connected to a second end of one of the MTJ elements. Word lines each of which is electrically connected to a gate of one of the cell transistors or functions as a gate of one of the cell transistors. A plurality of the second bit lines correspond to one of the first bit lines. A plurality of the MTJ elements share the same word line and the same active area. The active area is continuously formed in an extending direction of the first and second bit lines.12-13-2012
20100246250Pipeline Sensing Using Voltage Storage Elements to Read Non-Volatile Memory Cells - Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.09-30-2010
20100246254MAGNETIC MEMORY WITH A THERMALLY ASSISTED WRITING PROCEDURE - A magnetic memory device of MRAM type with a thermally-assisted writing procedure, the magnetic memory device being formed from a plurality of memory cells, each memory cell comprising a magnetic tunnel junction, the magnetic tunnel junction comprising a magnetic storage layer in which data can be written in a writing process; a reference layer, having a magnetization being always substantially in the same direction at any time of the writing process; an insulating layer between the reference layer and the storage layer; wherein the magnetic tunnel junction further comprises a writing layer made of a ferrimagnetic 09-30-2010
20100246252NONVOLATILE SOLID STATE MAGNETIC MEMORY AND RECORDING METHOD THEREOF - A nonvolatile solid state magnetic memory with a ultra-low power consumption and a recording method thereof, the memory including a magnetic material having a magnetic anisotropy that can be changed by increasing or decreasing a carrier concentration, wherein a direction of an easy axis of magnetization, in which the magnetization is oriented easily, is controlled by increasing or decreasing the carrier concentration. The nonvolatile solid state magnetic memory including a recording layer of a magnetic material, and a recording method thereof, in which a carrier (electron or hole) concentration in the recording layer is increased and/or decreased, whereby the magnetization is rotated or reversed and the recording operation is performed.09-30-2010
20100246251Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells - A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.09-30-2010
20100246253MAGNETIC MEMORY DEVICE, AND MANUFACTURING METHOD THEREOF - To provide a magnetic memory device that can suppress the reduction of function of a magnetic memory element, and a manufacturing method thereof. A magnetic memory device includes a magnetic memory element capable of holding data based on a magnetized state thereof, and a digit line and a bit line which are capable of changing the magnetized state of the magnetic memory element by a magnetic field generated. The magnetic memory element is disposed above the digit line and the bit line at an intersection part of the digit line and the bit line. The digit line has a first width at the intersection part, and the bit line has a second width at the intersection part. The first width is larger than a third width of the magnetic memory element, and the second width is smaller than a fourth width of the magnetic memory element.09-30-2010
20100208515MAGNETIC RANDOM ACCESS MEMORY - The spin torque transfer magnetic random access memory includes a magnetic tunnel junction element including a pinned layer, a free layer, and a tunnel insulating film formed between the pinned layer and the free layer, and a memory cell select transistor having one diffused region electrically connected to a side of the fee layer of the magnetic tunnel junction element.08-19-2010
20100208516ACTIVE STRAP MAGNETIC RANDOM ACCESS MEMORY CELLS - A magnetic random access memory (MRAM) cell with a thermally assisted writing procedure comprising a magnetic tunnel junction formed from a magnetic storage layer, a reference layer, and an insulating layer inserted between the reference layer and the storage layer; and a first strap portion laterally connecting one end of the magnetic tunnel junction to a first selection transistor; wherein the cell further comprises a second strap portion extending opposite to the first strap portion and connecting laterally said one end of the magnetic tunnel junction to a second selection transistor, and in that said first and second strap portions being adapted for passing a portion of current via the first and second selection transistors. The disclosed cell has lower power consumption than conventional MRAM cells.08-19-2010
20100208514Magnetic Memory Cell and Method of Fabricating Same - A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media.08-19-2010
20100067293Programmable and Redundant Circuitry Based On Magnetic Tunnel Junction (MTJ) - Techniques, apparatus and circuits based on magnetic or magnetoresistive tunnel junctions (MTJs). In one aspect, a programmable circuit device can include a magnetic tunnel junction (MTJ); a MTJ control circuit coupled to the MTJ to control the MTJ to cause a breakdown in the MTJ in programming the MTJ; and a sensing circuit coupled to the MTJ to sense a voltage under a breakdown condition of the MTJ.03-18-2010
20090059659SPIN TRANSISTOR AND MAGNETIC MEMORY - A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on the substrate to extend in the first direction, and sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a plurality of channel regions respectively provided in the projecting semiconductor layers, and a gate electrode provided on the channel regions.03-05-2009
20120170361LOW-COST NON-VOLATILE FLASH-RAM MEMORY - A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.07-05-2012
20100271870MAGNETIC STACK HAVING ASSIST LAYER - A magnetic memory cell having a ferromagnetic free layer and a ferromagnetic pinned reference layer, each having an out-of-plane magnetic anisotropy and an out-of-plane magnetization orientation and switchable by spin torque. The cell includes a ferromagnetic assist layer proximate the free layer, the assist layer having a low magnetic anisotropy less than about 500 Oe. The assist layer may have in-plane or out-of-plane anisotropy.10-28-2010
20120218815Magnetic Random Access Memory (MRAM) Read With Reduced Disburb Failure - Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ.08-30-2012
20120188818Low-crystallization temperature MTJ for Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) - A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.07-26-2012
20120188817Read Sensing Circuit and Method with Equalization Timing - A Magnetic Random Access Memory (MRAM) includes read sensing circuitry having an equalizer device configured between a bit cell output node and a reference node of the bit cell. The equalizer is turned on to couple the output node to the reference node during an initial portion of a read operation and to decouple the output node from the reference node after an equalization delay period. A sense amplifier is enabled to provide a data output from the bit cell only after the delay period and decoupling of the output node from the reference node to provide balanced sensing speed of data represented by parallel and antiparallel state magnetic tunnel junctions (MTJs).07-26-2012
20120188816Row-Decoder Circuit and Method with Dual Power Systems - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.07-26-2012
20120257448Multi-Cell Per Memory-Bit Circuit and Method - A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.10-11-2012
20120230101METHOD AND APPARATUS FOR WRITING TO A MAGNETIC TUNNEL JUNCTION (MTJ) BY APPLYING INCREMENTALLY INCREASING VOLTAGE LEVEL - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.09-13-2012
20110038200Gate drive voltage boost schemes for memory array II - Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row.02-17-2011
20100232220ELECTRONIC DEVICES FORMED OF TWO OR MORE SUBSTRATES BONDED TOGETHER, ELECTRONIC SYSTEMS COMPRISING ELECTRONIC DEVICES AND METHODS OF MAKING ELECTRONIC DEVICES - Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads are positioned on a surface of the first substrate and comprise a width extending over at least two of the plurality of conductive traces. A plurality of vias extend from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems.09-16-2010
20100232219Micromagnetic Elements, Logic Devices And Related Methods - Micromagnetic elements, logic devices and methods of fabricating and using them to store data and perform logic operations are disclosed. Micromagnetic elements for data storage, as well as those providing output from a logic device, are at least partially covered with an optical coating that facilitates determination of the magnetic state. The disclosed logic devices perform one or more of AND, OR, NAND and NOR operations.09-16-2010
20120087185MAGNETIC LATCH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A spin-transfer torque magnetic random access memory (STTMRAM) element is configured to store a state when electrical current is applied thereto. The STTMRAM element includes first and second free layers, each of which having an associated direction of magnetization defining the state of the STTMRAM element. Prior to the application of electrical current to the STTMRAM element, the direction of the magnetization of the first and second free layers each is in-plane and after the application of electrical current to the STTMRAM element, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.04-12-2012
20120287709NON VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a non volatile semiconductor memory device includes a substrate, a first electrode, a functional film, and a second electrode. The first electrode is provided on the substrate. The functional film is located on the first electrode and serves as a storage medium. The second electrode is provided on the functional film or in the functional film, and has a convex curved upper surface.11-15-2012
20120287708SELECTION DEVICE FOR A SPIN-TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY - A spin-torque transfer magnetic random access memory (STT-MRAM) that includes a magnetic bit coupled between a first conductor line and a selection device. The selection device includes at least two transistors. The selection device is operative to (a) select the magnetic bit for a spin-torque transfer (STT) write operation when the at least two transistors are in a first state and (b) select the magnetic bit for a read operation when the at least two transistors are in a second state. The selection device may be implemented in silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology, and the transistors may include body ties. The selection device may also be radiation hardened.11-15-2012
20110157971Magnetic random access memories and methods of operating the same - A spin transfer torque magnetic random access memory (STT-MRAM) and includes: a memory cell and a reference cell configured to operate as a reference when data stored in the memory cell is read. The memory cell includes: a first magnetic tunneling junction (MTJ) element and a first transistor connected to the first MTJ element. The reference cell includes: second and third MTJ elements connected in parallel; and second and third transistors that are connected to the second and third MTJ elements, respectively. The STT-MRAM further includes a control circuit having a write circuit configured to supply write currents having opposite directions to the second and third MTJ elements.06-30-2011
20080253178MRAM with enhanced programming margin - An MRAM that is not subject to accidental writing of half-selected memory elements is described, together with a method for its manufacture. The key features of this MRAM are a C-shaped memory element used in conjunction with a segmented bit line architecture.10-16-2008
20080239800MAGNETIC MEMORY ARRAYS - A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field.10-02-2008
20080225582Thin film magnetic memory device capable of conducting stable data read and write operations - A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.09-18-2008
20080225581MEMORY DEVICE AND MEMORY - A memory device is provided. The memory device includes a memory layer and a fixed-magnetization layer. The memory layer retains information based on a magnetization state of a magnetic material. The fixed-magnetization layer is formed on the memory layer through an intermediate layer made of an insulating material. The information is recorded on the memory layer with a change in a magnetization direction of the memory layer caused by injecting a spin-polarized electron in a stacked direction. A level of effective demagnetizing field, which is received by the memory layer, is smaller than a saturation-magnetization level of magnetization of the memory layer.09-18-2008
20130114336THREE PORT MTJ STRUCTURE AND INTEGRATION - A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.05-09-2013
20110267879MAGNETIC MEMORY ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory cell includes: a magnetization recording layer; and a magnetic tunneling junction section. The magnetization recording layer includes a ferromagnetic layer with perpendicular magnetic anisotropy. The magnetic tunneling junction section is used for reading information in the magnetization recording layer. The magnetization recording layer includes two domain wall moving areas.11-03-2011
20110273929SEMICONDUCTOR MAGNETIC MEMORY INTEGRATING A MAGNETIC TUNNELING JUNCTION ABOVE A FLOATING-GATE MEMORY CELL - A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.11-10-2011
20110273928METHOD AND SYSTEM FOR PROVIDING A MAGNETIC MAGNETIC FIELD ALIGNED SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive write current(s) through selected storage cell(s) of the magnetic storage cells to write to the selected storage cell(s). The preset lines drive preset current(s) in proximity to but not through the selected storage cell(s). The preset current(s) generate magnetic field(s) to orient the magnetic element(s) of the selected storage cell(s) in a direction. The word lines enable the selected storage cell(s) for writing. Either the bit lines reside between the preset lines and the storage cells or the preset lines reside between the storage cells and on a storage cell side of the bit lines.11-10-2011
20080198648WRITING METHOD FOR MAGNETIC MEMORY CELL AND MAGNETIC MEMORY ARRAY STRUCTURE - A writing method for a magnetic memory cell which has a magnetic free stack layer with a bi-directional easy axis. A magnetic X axis and a magnetic Y axis are taken as reference directions, and the bi-directional easy axis is substantially on the magnetic X axis. The method includes applying a first magnetic field in a first direction of the magnetic Y axis. Then, a second magnetic field added onto the first magnetic field is applied in a first direction of the magnetic X axis. Next, the application of the first magnetic field is terminated. Thereafter, a third magnetic field is applied on the magnetic Y axis in a second direction opposite to the first direction. The second magnetic field is terminated and the third magnetic field is terminated.08-21-2008
20080198647METHOD AND APPARATUS FOR BITLINE AND CONTACT VIA INTEGRATION IN MAGNETIC RANDOM ACCESS MEMORY ARRAYS - In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction on at least three sides.08-21-2008
20120257449High Density Magnetic Random Access Memory - A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel barrier layer disposed between the pinned and free layers, a first electrical circuit for applying a first current to a first conductor electrically coupled to the free layer to produce a bias magnetic field along a hard axis of the free layer, a second electrical circuit for applying a second current to a second conductor electrically coupled to the pinned layer to cause a spin momentum transfer in the free layer, wherein magnitudes of the bias magnetic field and spin momentum transfer in combination exceed a threshold and thus reverse the magnetization direction of the free layer.10-11-2012
20100315870METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.12-16-2010
20100315869Spin torque transfer MRAM design with low switching current - The invention discloses a method to store digital information through use of spin torque transfer in a device that has a very low critical current. This is achieved by adding a spin filtering layer whose direction of magnetization is fixed to be parallel to the device's pinned layer.12-16-2010
20120281467MAGNONIC MAGNETIC RANDOM ACCESS MEMORY DEVICE - A mechanism is provided for bidirectional writing. A structure includes a reference layer on top of a tunnel barrier, a free layer underneath the tunnel barrier, a metal spacer underneath the free layer, an insulating magnet underneath the metal spacer, and a high resistance layer underneath the insulating layer. The high resistance layer acts as a heater in which the heater heats the insulating magnet to generate spin polarized electrons. A magnetization of the free layer is destabilized by the spin polarized electrons generated from the insulating magnet. A voltage is applied to change the magnetization of the free layer when the magnetization is destabilized. A polarity of the voltage determines when the magnetization of the free layer is parallel and antiparallel to a magnetization of the reference layer.11-08-2012
20120020152Writable Magnetic Memory Element - The invention relates to a writable magnetic element comprising a stack of layers presenting a write magnetic layer, wherein the stack has a central layer of at least one magnetic material presenting a direction of magnetization that is parallel or perpendicular to the plane of the central layer, said central layer being sandwiched between first and second outer layers of non-magnetic materials, the first outer layer comprising a first non-magnetic material and the second outer layer comprising a second non-magnetic material that is different from the first non-magnetic material, at least the second non-magnetic material being electrically conductive, wherein it includes a device for causing current to flow through the second outer layer and the central layer in a current flow direction parallel to the plane of the central layer, and a device for applying a magnetic field having a component along a magnetic field direction that is either parallel or perpendicular to the plane of the central layer and the current flow direction, and wherein the magnetization direction and the magnetic field direction are mutually perpendicular.01-26-2012
20130201757MULTI-FREE LAYER MTJ AND MULTI-TERMINAL READ CIRCUIT WITH CONCURRENT AND DIFFERENTIAL SENSING - A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer.08-08-2013
20120087184Magnetic Random Access Memory (MRAM) Layout with Uniform Pattern - A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.04-12-2012

Patent applications in class Magnetic thin film

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