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Amorphous (electrical)

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365 - Static information storage and retrieval

365129000 - SYSTEMS USING PARTICULAR ELEMENT

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DocumentTitleDate
20130044540PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL - An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.02-21-2013
20130044539APPARATUSES, DEVICES AND METHODS FOR SENSING A SNAPBACK EVENT IN A CIRCUIT - Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.02-21-2013
20100020594DEVICE FOR PROGRAMMING A PCM CELL WITH DISCHARGE OF CAPACITANCE AND METHOD FOR PROGRAMMING A PCM CELL - A device for programming PCM cells includes a pulse-generator circuit for supplying programming current pulses. The pulse-generator circuit includes: at least one first capacitive element; a charging circuit, connectable to the first capacitive element in a first operating condition, for bringing a reference voltage on the first capacitive element to a reset value; a discharge-current generator, selectively connectable to the first capacitive element in a second operating condition, for discharging the first capacitive element through a controlled discharge current; a logic unit, configured to control connection and disconnection of the first capacitive element), of the charging circuit, and of the discharge-current generator; and a voltage-to-current converter, for converting the reference voltage into current.01-28-2010
20090196096Memory Cells, Methods Of Forming Memory Cells, And Methods Of Forming Programmed Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.08-06-2009
20090196095MULTIPLE MEMORY CELLS AND METHOD - Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.08-06-2009
20090196094INTEGRATED CIRCUIT INCLUDING ELECTRODE HAVING RECESSED PORTION - An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.08-06-2009
20090196093STACKED DIE MEMORY - A memory includes a first die including a first array of phase change memory cells and a second die including a second array of phase change memory cells. The second die is stacked above the first die. The memory includes lines configured to access the first die and the second die. The first die and the second die are enclosed in a single package.08-06-2009
20090196092Programming bit alterable memories - Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust.08-06-2009
20090196091Self-aligned phase change memory - A self-aligned phase change memory may be formed by blanket depositing a number of layers and then using patterning techniques to define the individual cells. In one embodiment, a layer of phase change material may be blanket deposited over a lower electrode material. The structure may then be patterned and etched to form a plurality of spaced, parallel elongate first strips. Those strips may then be covered with a filler material, planarized, and then patterned again in a transverse direction to form a plurality of transverse, spaced, parallel second strips. The resulting structure then has singulated phase change material with connections in at least one of the row or column direction. The singulated the phase change material is self-aligned to underlying and overlying electrodes.08-06-2009
20110188304MULTIPLE LEVEL CELL PHASE-CHANGE MEMORY DEVICES HAVING PRE-READING OPERATION RESISTANCE DRIFT RECOVERY, MEMORY SYSTEMS EMPLOYING SUCH DEVICES AND METHODS OF READING MEMORY DEVICES - A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.08-04-2011
20080259678Method for initializing resistance-variable material, memory device containing a resistance-variable material, and method for initializing nonvolatile memory circuit including variable resistor - An initialization method of the present invention is a method for initializing a material (variable-resistance material) (10-23-2008
20080259676Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Computer Program Product - According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell.10-23-2008
20110194340Phase Change Device with Offset Contact - A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.08-11-2011
20110194339MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME - A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.08-11-2011
20090122599WRITING SYSTEM AND METHOD FOR PHASE CHANGE MOMORY - An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.05-14-2009
20090122602SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.05-14-2009
20090122601POWER SUPPLYING CIRCUIT AND PHASE-CHANGE RANDOM ACCESS MEMORY INCLUDING THE SAME - Embodiments of the invention provide a power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks.05-14-2009
20090109738PHASE-CHANGE MEMORY DEVICE WITH ERROR CORRECTION CAPABILITY - A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.04-30-2009
20100074000Analog Access Circuit for Validating Chalcogenide Memory Cells - An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.03-25-2010
20100074001INFORMATION RECORDING/REPRODUCING DEVICE - The information recording/reproducing device includes a stacked structure which is comprised of an electrode layer and a recording layer, a buffer layer which contacts with the recording layer and a recording circuit which records data to the recording layer by generating a phase change in the recording layer. The recording layer is comprised of a complex compound having two cations, and one of the cations is a transition element having “d” orbit where electrons are incompletely filled. The recording layer is comprised of Cu03-25-2010
20100073999SEMICONDUCTOR INTEGRATED CIRCUIT - In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN03-25-2010
20130077394MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY - A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode.03-28-2013
20130077393TIMING VIOLATION HANDLING IN A SYNCHRONOUS INTERFACE MEMORY - A Phase-Change Memory (PCM) that allows an Activate command to start and all following Activate commands are ignored until a time tRC has elapsed.03-28-2013
20130077392SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.03-28-2013
20130039123NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.02-14-2013
20130039124PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND RELATED METHODS OF OPERATION - A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.02-14-2013
20130033929WRITE SCHEME IN A PHASE CHANGE MEMORY - In a phase change memory, an input data corresponding to a plurality of memory cells is received and a previous data is read from the plurality of memory cells. The input data is compared with the previous data. In the case where the input data is different from the previous data for one or more of the plurality of memory cells and a write count is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the write count is updated or incremented. Such operations of data comparison and update of the write count are repeated. If the write count reaches the maximum value, it will be determined that the writing is failed.02-07-2013
20130033930SUPPLY VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.02-07-2013
20100046287SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY INCLUDING RESISTANCE CHANGE MATERIAL AND METHOD OF OPERATING - Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.02-25-2010
20100046286RESISTIVE MEMORY DEVICES USING ASSYMETRICAL BITLINE CHARGING AND DISCHARGING - A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.02-25-2010
20100046285MULTIPLE PHASE CHANGE MATERIALS IN AN INTEGRATED CIRCUIT FOR SYSTEM ON A CHIP APPLICATION - Integrated circuits are described along with methods for manufacturing. An integrated circuit as described herein includes a plurality of memory cells on a substrate. The plurality of memory cells comprise a first set of memory cells comprising a first memory material, and a second set of memory cells comprising a second memory material. The first and second memory materials have different properties such that the first and second sets of memory cells have different operational memory characteristics.02-25-2010
20100103724Variable Resistance memory device - The variable resistance memory device may include a memory cell array including a plurality of memory blocks, a bit line selection circuit including a plurality of bit lines connected to the plurality of memory blocks, at least one readout Y-pass driver configured to control a connection of the bit line selection circuit when a readout operation is performed, and a write Y-pass driver configured to control a connection of the bit line selection circuit when a write operation is performed. The write Y-pass driver is configured to control at least two of the plurality of bit lines connections.04-29-2010
20090161421PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.06-25-2009
20130083594MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY - A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode.04-04-2013
20130028014REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS - Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.01-31-2013
20090080243DEVICE CONTROLLING PHASE CHANGE STORAGE ELEMENT AND METHOD THEREOF - Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.03-26-2009
20100067290Method of programming of phase-change memory and associated devices and materials - A method of programming a phase-change memory (PCM) device to the high resistance reset state by means of pressure-induced amorphization. A train of few short pulses is applied to the PCM device produces high pressure on phase-change alloy (PCA). PCM device contains a PCA with easily deformed atomic structure by external pressure and materials mechanically contacted PCA. These materials have lower coefficients of thermal expansion and compressibility as well as higher coefficient of hardness than the corresponding coefficients of the PCA.03-18-2010
20100328996PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES - A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.12-30-2010
20120182794Multi-Terminal Phase Change Devices - Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.07-19-2012
20130051137TILE-LEVEL SNAPBACK DETECTION THROUGH COUPLING CAPACITOR IN A CROSS POINT ARRAY - Embodiments of the present disclosure describe methods, apparatus, and system configurations for tile-level snapback detection through a coupling capacitor in a phase-change memory array. Other embodiments may be described and claimed.02-28-2013
20130051136METHODS, APPARATUSES, AND CIRCUITS FOR PROGRAMMING A MEMORY DEVICE - Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.02-28-2013
20130051138PHASE CHANGE MEMORY - A phase change memory device including a voltage generator that generates an operating voltage by generating at least one modified clock signal, a pulse width of which is maintained constant for at least one clock cycle in response to a pump enable signal being enabled, from at least one reference clock signal, and performing a pump operation on a power supply voltage according to the at least one modified clock signal; and a memory cell array that includes a plurality of phase change memory cells connected between word lines and bit lines. The operating voltage is applied to the memory cell array so as to perform a data access operation.02-28-2013
20090303786SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS - The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided.12-10-2009
20090303785PHASE CHANGE MEMORY DEVICES AND READ METHODS USING ELAPSED TIME-BASED READ VOLTAGES - A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods are also described.12-10-2009
20090303783Thin film input/output - Input/Output circuitry employs thin-film switching devices to drive output signals from an integrated circuit to an external device and to receive input signals from an external device. Three terminal ovonic threshold switches (3T OTS) may be employed to drive input and output signals.12-10-2009
20090303782Standalone thin film memory - A standalone memory device includes thin-film peripheral circuitry, including decoding circuitry. The standalone thin film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass. The memory is configured for operation with an external memory controller.12-10-2009
20090303780INTEGRATED CIRCUIT INCLUDING AN ARRAY OF DIODES COUPLED TO A LAYER OF RESISTANCE CHANGING MATERIAL - An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.12-10-2009
20090040820Phase Change Memory - A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units, is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least, one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result.02-12-2009
20090040817METHOD FOR EFFICIENTLY DRIVING A PHASE CHANGE MEMORY DEVICE - A method for efficiently driving a phase change memory device is presented that includes the operational procedures of writing, reading, comparing and changing. The phase change memory device has a resistor configured to sense a crystallization state changed by currents so as to store data corresponding to the crystallization state. The writing operation writes data having a first state in a corresponding unit cell of the phase change memory device. The reading operation reads a cell data stored in the unit cell. The comparing operation compares the data having the first state with the cell data read from the unit cell to verify whether or not the data having the first state is the same as the cell data. The changing operation changes a write condition when the data having a first state is different from that of the cell data.02-12-2009
20090091971Semiconductor phase change memory using multiple phase change layers - In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.04-09-2009
20130058158METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT - Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. A storage cell may further comprise a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.03-07-2013
20130058160PHASE CHANGE MEMORY DEVICE AND COMPUTING SYSTEM HAVING THE SAME - A phase change memory device includes a memory cell array, a register unit and a control unit. The memory cell array includes a plurality of phase change memory cells. The register unit includes a circular queue. The control unit receives a write address and a write data in a write mode, programs the write data in a phase change memory cell corresponding to the write address among the plurality of phase change memory cells, provides the write address and the write data to the register unit, and outputs a write complete signal before a phase of the phase change memory cell is stabilized or after the phase of the phase change memory cell is stabilized based on a logic level of a first result signal received from the register unit. The phase change memory device increases a programming speed.03-07-2013
20130058159METHOD OF OPERATING PHASE-CHANGE MEMORY - One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.03-07-2013
20110013446REFRESH CIRCUITRY FOR PHASE CHANGE MEMORY - A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.01-20-2011
20100128517PHASE-CHANGE MEMORY DEVICE WITH DISCHARGE OF LEAKAGE CURRENTS IN DESELECTED BITLINES AND METHOD FOR DISCHARGING LEAKAGE CURRENTS IN DESELECTED BITLINES OF A PHASE-CHANGE MEMORY DEVICE - A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents in the bitlines. The bitline discharge unit has a voltage regulation unit and a plurality of bitline discharge switches coupled between the voltage regulation unit and a respective bitline. The bitline discharge switches are controlled to connect the deselected bitlines to the voltage regulation unit and to disconnect the selected bitline from the voltage regulation unit. The voltage regulation unit comprises a PMOS transistor coupled between a regulated voltage bus and a reference potential line. The regulated voltage bus is connected to the bitline discharge switches and the control terminal of the PMOS transistor is biased to a constant voltage.05-27-2010
20090268514Semiconductor memory device and control method thereof - A semiconductor memory device includes: a plurality of word lines; a plurality of bit lines; plurality of memory cells arranged at intersections of the word lines and the bit lines; a word driver that selects any one of the word lines; a plurality of sense amplifiers connectable to any of the bit lines; a sense-amplifier starting circuit that sequentially starts the sense amplifiers in response to a request of consecutive read operations to the memory cells connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver; and an address determining circuit that temporarily stops an operation of the sense-amplifier starting circuit in response to a request of consecutive read operations to a same memory cell connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver.10-29-2009
20090268513MEMORY DEVICE WITH DIFFERENT TYPES OF PHASE CHANGE MEMORY - A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device.10-29-2009
20090073753SEMICONDUCTOR DEVICE - At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.03-19-2009
20090067226INTEGRATED CIRCUIT WITH PHASE-CHANGE MEMORY CELLS AND METHOD FOR ADDRESSING PHASE-CHANGE MEMORY CELLS - The present invention relates to integrated circuit comprising a plurality of bitlines (b03-12-2009
20130163323SEMICONDUCTOR MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT OR PHASE-CHANGE ELEMENT AS MEMORY DEVICE - A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element.06-27-2013
20090251953Variable resistance memory device - A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word line decoders includes a first transistor having a gate connected to the global word line. A voltage greater than an operation voltage of one or more of the plurality of local word line decoders is applied to a selected one of the plurality of global word lines.10-08-2009
20090251952STATE MACHINE SENSING OF MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell can be programmed with the first sensing reference. The method also includes generating a second sensing reference according to a second output of the state machine. The method further includes determining a programmed level of the memory cell with the second generated sensing reference.10-08-2009
20090237986NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.09-24-2009
20090237985SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD - An electrically rewritable non-volatile memory device is configured by the EEPROM 09-24-2009
20090237984MEMORY CELL - Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.09-24-2009
20090237983INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT DOPED WITH DIELECTRIC MATERIAL - An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.09-24-2009
20090231913SEMICONDUCTOR DEVICE - There is provided a technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.09-17-2009
20090231912PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated.09-17-2009
20090046500APPARATUS AND METHOD OF NONVOLATILE MEMORY DEVICE HAVING THREE-LEVEL NONVOLATILE MEMORY CELLS - An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.02-19-2009
20090046499INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ - An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.02-19-2009
20090046498INTEGRATED CIRCUIT INCLUDING MEMORY HAVING REDUCED CROSS TALK - An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.02-19-2009
20090010051Reading a phase change memory - A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.01-08-2009
20090010050Calibration system for writing and reading multiple states into phase change memory - A memory system includes phase change memory cells. A control module causes one of the phase change memory cells to be written using a write parameter, causes a resistance value of the one of the phase change memory cells to be read back, adjusts the write parameter, and causes the writing, reading and adjusting to be repeated until the resistance value is within a predetermined range of a target resistance value.01-08-2009
20090010049Phase change memory device - A phase change memory device is constituted of a plurality of memory cells including a plurality of phase change memory elements, which are arranged at intersecting points formed between a plurality of word lines and a plurality of bit lines. A write circuit which operates based on a write voltage source (Vwrite) is controlled by control signals (e.g. WE, RDIS, SDIS, and DIN) output from a control circuit which operates based on a voltage source (VDD), where Vwrite>VDD. All the control signals based on VDD are applied to the gates of N-channel MOS transistors included in the write circuit. This allows adequately high write currents to be supplied to phase change memory elements; and this eliminates the necessity of arranging a potential switch circuit in the write circuit, thus reducing the scale of the phase change memory device.01-08-2009
20090010048MEMORY DEVICE INCLUDING A PROGRAMMABLE RESISTANCE ELEMENT - Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.01-08-2009
20090010047WRITING CIRCUIT FOR A PHASE CHANGE MEMORY - A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.01-08-2009
20120113711Using A Bit Specific Reference Level To Read A Memory - A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments,05-10-2012
20130163320ENERGY-EFFICIENT ROW DRIVER FOR PROGRAMMING PHASE CHANGE MEMORY - A drive circuit and method for parallel programming a plurality of phase change memory (PCM) cells includes a first signal generator device for generating a slow ramping signal; an adiabatic computing element receives the slow ramping signal and responsively generates an output slow ramping signal in adiabatic fashion, the output slow ramping signal applied to the single wordline conductor associated with each PCM cell of the plurality of cells being programmed in a time interval. Each PCM cell of the plurality being programmed is connected to a respective bitline conductor. A second signal generator generates, during the time interval, one or more bitline signals for input to a respective bitline conductor of a respective PCM cell. A state of the applied slow ramping output signal and the one or more bitline signals during the time interval governs a programmed state of the PCM cell.06-27-2013
20130163321DRIFT MITIGATION FOR MULTI-BITS PHASE CHANGE MEMORY - An RC-based sensing scheme to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing scheme ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing scheme is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing scheme is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift.06-27-2013
20130163322PARALLEL PROGRAMMING SCHEME IN MULTI-BIT PHASE CHANGE MEMORY - A system, a method for parallel programming multiple bits of a phase change memory array for high bandwidth. The system and method includes parallel programming scheme wherein a common wordline (WL) is driven with a first pulse of one of: gradually increasing (RESET) or decreasing (SET) amplitudes which control current flow through one or more phase change memory cells associated with the WL. Simultaneously therewith, one or more bitlines (BLs) are driven with one or more second pulses, each second pulse more narrow than that of the first pulse applied to the WL. The starting time of the one or more second pulses may vary with each bitline driven at a time later than, but within the window of the wordline pulse to achieve a programming current suitable for achieving the corresponding memory cell state.06-27-2013
20110032754PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated.02-10-2011
20090122600NONVOLATILE MEMORY USING RESISTANCE MATERIAL - A nonvolatile memory using a resistance material includes first and second memory-cell blocks having different block address information and each including a plurality of nonvolatile memory cells; a global bitline common to the first and second memory-cell blocks; first and second local bitlines corresponding to the first and second memory-cell blocks, respectively, and coupled to each other; and a common bitline selection circuit interposed between the first and second memory-cell blocks and coupled between the first and second local bitlines and the global bitline.05-14-2009
20120099370PHASE CHANGE MEMORY DEVICE - A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.04-26-2012
20090175071PHASE CHANGE MEMORY DYNAMIC RESISTANCE TEST AND MANUFACTURING METHODS - A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.07-09-2009
20130021844PHASE CHANGE MEMORY WITH DOUBLE WRITE DRIVERS - A Phase Change Memory (PCM) having double write drivers. A PCM apparatus includes a memory array having a bitline with a first end and a second end for accessing a PCM cell coupled to the bitline between the first end and the second end of the bitline, a first write driver and a second write driver coupled to the first end of the bitline and the second end of the bitline respectively for simultaneously supplying current to the PCM cell when writing to the PCM cell, and a sense amplifier coupled to the second end of the bitline for sensing a resistance of the PCM cell when reading from the PCM cell. Embodiments of the present invention provide apparatuses, methods, and systems having reduced writing current requirements.01-24-2013
20110019467VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION - A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.01-27-2011
20090310403NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device includes multiple memory blocks divided into multiple memory block groups. Each memory block group includes at least two memory blocks of the multiple memory blocks. The nonvolatile memory device also includes a main word line common to the memory blocks, and multiple sub-word lines corresponding to the memory blocks. Sub-word lines of the multiple sub-word lines located within the same memory block group are electrically connected to each other, and sub-word lines of the multiple sub-word lines located in different memory block are electrically isolated from each other.12-17-2009
20120081954PHASE CHANGE MEMORY APPARATUS HAVING ROW CONTROL CELL - A semiconductor integrated circuit includes a phase change memory apparatus includes a plurality of row control cells and a plurality of phase change memory cells formed on the row control cells while being electrically connected to the row control cells. The plurality of row control cells and the plurality of phase change memory cells are vertically stacked in a cell array area.04-05-2012
20110128780SEMICONDUCTOR DEVICE - At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.06-02-2011
20110128779MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL - Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.06-02-2011
20090040811PHASE CHANGE MEMORY DEVICE HAVING MULTIPLE RESET SIGNALS AND OPERATING METHOD THEREOF - A phase change memory device includes a cell array unit having a phase change resistance cell positioned at an intersection of a word line and a bit line. A write driving unit is configured to generate a single write voltage to the cell array unit when data to be written is a first data and is configured to generate a plurality of write voltages selectively when the data is a second data.02-12-2009
20110299328Memory Arrays - Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F12-08-2011
20120099371METHOD OF OPERATING A PHASE-CHANGE MEMORY DEVICE - A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.04-26-2012
20110299329BOTTOM ELECTRODE GEOMETRY FOR PHASE CHANGE MEMORY - A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. The bottom electrode can also be tapered to have a smaller cross-sectional area at the top of the bottom electrode than at the bottom of the bottom electrode.12-08-2011
20100309716SUPPLY VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE HAVING SAME - A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.12-09-2010
20090201721Phase change memory device and write method thereof - A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.08-13-2009
20110292722SEMICONDUCTOR DEVICE - A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogcnidc material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.12-01-2011
20110292719PHASE-CHANGE MEMORY DEVICE - A phase-change memory device includes: a cell array including at least one unit cell; a current sensing unit sensing data stored in the at least one unit cell; and a power generation circuit supplying a power source voltage to the current sensing unit, in which the power generation circuit is activated while the current sensing unit is performing a sensing operation.12-01-2011
20100259975PHASE CHANGE MONEY DEVICE - A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.10-14-2010
20110292721Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.12-01-2011
20110292720PHASE-CHANGE MEMORY DEVICE - A phase-change memory device includes: a unit cell including a phase-change resistor; a sense amplifier applying a sensing current to the phase-change resistor; and a switching unit operating in a standby mode or a read mode according to a global line signal and controlling passing presence of the sensing current passing through the phase-change resistor according to an active signal in the standby mode.12-01-2011
20090290411WRITE VERIFY METHOD FOR RESISTIVE RANDOM ACCESS MEMORY - Write verify methods for resistance random access memory (RRAM) are disclosed. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and setting a counter to zero. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value and adding one to the counter. This step is repeated until either the counter reaches a predetermined number or until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value and adding one to the counter. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until either the counter reaches a predetermined number or until all the high resistance state resistance value is less than the upper resistance limit value.11-26-2009
20100110782Page Mode Access for Non-volatile Memory Arrays - An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.05-06-2010
20100103725Resistance Variable Memory Device for Protecting Coupling Noise - The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to,a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.04-29-2010
20080310217WRITING CIRCUIT FOR A PHASE CHANGE MEMORY - A writing circuit for a phase change memory is provided. The writing circuit comprises a driving current generating circuit, a first switch device, a first memory cell and a second switch device. The driving current generating circuit provides a writing current to the first memory cell. The first switch device is coupled to the driving current generating circuit. The first memory cell is coupled between the first switch device and the second switch device. The second switch device is coupled between the first memory cell and a ground, wherein when the driving current generating circuit outputs the writing current to the first memory cell, the second switch device is turned on after the first switch device has been turned on for a first predetermined time period.12-18-2008
20100034016PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays.02-11-2010
20100091559Programmable resistance memory with feedback control - A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.04-15-2010
20100091560Multi-terminal phase change devices - Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.04-15-2010
20100091561Programmable Matrix Array with Chalcogenide Material - A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device.04-15-2010
20130010533DESCENDING SET VERIFY FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.01-10-2013
20100265761NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT FOR GENERATING WRITE VOLTAGE - A non-volatile semiconductor memory circuit for generating a write voltage is presented. The non-volatile semiconductor memory circuit includes a memory cell and a voltage generator. The voltage generator provides a write voltage at a given target level that varies in accordance with an amount of current detected by the memory cell array by using a reference voltage.10-21-2010
20090154227INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS - The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.06-18-2009
20090154226INTEGRATED CIRCUIT INCLUDING QUENCH DEVICES - An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.06-18-2009
20090147564PHASE CHANGE MEMORY CELL HAVING INTERFACE STRUCTURES WITH ESSENTIALLY EQUAL THERMAL IMPEDANCES AND MANUFACTURING METHODS - A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a bit line structure and has a second thermal impedance therebetween. The first and second thermal impedances are essentially equal such that applying a reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures.06-11-2009
20090147566Phase Change Memory And Control Method Thereof - A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein.06-11-2009
20090147565Method and apparatus for accessing a phase-change memory - Fixed-voltage programming pulses are employed to program a phase change memory cell. A burst of incrementally widening fixed-voltage programming pulses may be employed to program a phase change memory to a target threshold voltage.06-11-2009
20100128516Nonvolatile Memory Devices Having Bit Line Discharge Control Circuits Therein that Provide Equivalent Bit Line Discharge Control - A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.05-27-2010
20080239798Compensation circuit and memory with the same - One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal.10-02-2008
20080266940Air Cell Thermal Isolation for a Memory Array Formed of a Programmable Resistive Material - A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.10-30-2008
20100124105VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.05-20-2010
20100124104Memory device and writing method thereof - A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.05-20-2010
20100124103Resistance-change random access memory device - A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.05-20-2010
20110261613PHASE CHANGE MEMORY ARRAY BLOCKS WITH ALTERNATE SELECTION - A phase change memory is disclosed. The phase change memory has a plurality of block units. The block units are alternately selected. The alternate block unit selection suppresses peak current ground bouncing on sub-wordline and connected ground line through sub-wordline driver transistor. An alternate bitline selection avoids adjacent cell heating interference in the selected block unit.10-27-2011
20110261612SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR GENERATING PROGRAMMING CURRENT PULSE - A semiconductor apparatus includes a first write control code generation unit configured to generate first write control codes which have fixed value for a first time and are cyclically updated after the first time, a second write control code generation unit configured to generate a second write control code, and a data write unit configured to output a first programming current pulse in response to the first write control codes, or a second programming current pulse in response to the second write control code.10-27-2011
20110261610NONVOLATILE MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A nonvolatile memory device includes a cell array including a plurality of phase change memory cells, a switching unit configured to select any one of the plurality of phase change memory cells, a clamping unit coupled between the switching unit and a sensing line and configured to adjust an amount of a clamping current flowing through the sensing line, a program switching unit configured to couple the switching unit to the sensing line during a program operation, a voltage driving unit configured to supply the sensing line with a write voltage corresponding to data to be written during the program operation, and supply the sensing line with a constant read voltage during a data sensing operation, and a sense amplifier configured to compare and amplify a voltage of the sensing line and a preset read reference voltage.10-27-2011
20090316474Phase change memory - The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.12-24-2009
20090244963Programming multilevel cell phase change memories - A multilevel phase change memory cell may have a plurality of intermediate levels between a set and a reset or a crystalline and amorphous states. These intermediate levels between set and reset may be differentiated not only by programming current, but also by different programming pulse widths. As a result, the intermediate states may be positioned, on the programming current versus programming pulse width curve, in regions of common resistance with a relatively large range of programming current.10-01-2009
20090310402Method and apparatus for decoding memory - A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.12-17-2009
20120033489MEMORY DEVICE, PRECHARGE CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME - A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array.02-09-2012
20100085804SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area.04-08-2010
20090040819NONVOLATILE MEMORY DEVICE USING RESISTIVE ELEMENTS AND AN ASSOCIATED DRIVING METHOD - A nonvolatile memory device is configured to increase the reliability of a write operation by providing a sufficiently high write current while reducing current consumption in a read operation. The nonvolatile memory device includes a memory cell array having a plurality of nonvolatile memory cells. A global bit line and a local bit line coupled to a plurality of the nonvolatile memory cells. The local bit line has first and second nodes. First and second bit line selection circuits are included where the first bit line selection circuit is coupled to the first node of the local bit line and the second bit line selection circuit is coupled to the second node of the local bit line. The first and second bit line selection circuits operate during a first period to electrically connect the local bit line to the global bit line, and only one of the first and second bit line selection circuits operates during a second period to electrically connect the local bit line to the global bit line.02-12-2009
20090080242Programming a multilevel phase change memory cell - Multilevel phase change memory cells may be programmed forming amorphous regions of amorphous phase change material in a storage region of the phase change memory cell. Crystalline paths of crystalline phase change material are formed through the amorphous regions of amorphous phase change material. Lengths of the crystalline paths are controlled so that at least a first crystalline path has a first length in a first programming state and a second crystalline path has a second length, different from the first length, in a second programming state.03-26-2009
20090080241Programming a phase change memory - A programming circuit of a phase change memory cell includes a controllable current generator to supply a programming pulse and an internal control unit coupled to the controllable current generator for stepwise modifying the programming pulse. The internal control unit, in turn, includes a control signal generator to provide the controllable current generator with a plurality of control signals. An oscillator provides a time reference signal and a driving module drives the control signal generator based on the time reference signal. As a result, a programming pulse with stepwise adjustable slope can be produced, including such a pulse with different leading and trailing edges.03-26-2009
20120294076Forming Sublithographic Heaters for Phase Change Memories - A phase change memory with a heater with sublithographic dimensions may be achieved, in some embodiments, with lower thermal budget. The phase change memory may use a controlled etching process to reduce the lateral dimension of the heater.11-22-2012
20120294073METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE - A method of driving phase change memory device which reduces or prevents unwanted heat disturbances from interfering with memory states in adjacent memory cells is presented. The phase change memory cells are disposed at word and bit line intersections. The method includes collectively erasing all of the memory cells as a unit in the bit line into a reset state. The method then includes individually programming only selected memory cells of the memory cells into set states.11-22-2012
20120268983RANDOM-ACCESS MEMORY WITH DYNAMICALLY ADJUSTABLE ENDURANCE AND RETENTION - A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality.10-25-2012
20100080051BIT-ERASING ARCHITECTURE FOR SEEK-SCAN PROBE (SSP) MEMORY STORAGE - An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.04-01-2010
20090052231SEMICONDUCTOR DEVICE - A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other.02-26-2009
20090279350BIPOLAR SWITCHING OF PHASE CHANGE DEVICE - Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse. The method further includes applying a set bias arrangement to the memory cell to change the resistance state from the higher resistance state to the lower resistance state. The set bias arrangement comprises a second voltage pulse, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.11-12-2009
20110267876NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.11-03-2011
20100124101PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE - Provided is a phase-change random access memory device. The phase-change random access memory device includes a phase-change memory cell array having multiple phase-change memory cells, a sensing unit and a discharge unit. The sensing unit detects data, stored in a phase-change memory cell to be sensed of the multiple phase-change memory cells, during a sensing period. The discharge unit discharges at least one node of multiple nodes positioned on a sensing path between the phase-change memory cell array and the sensing unit during a period other than the sensing period.05-20-2010
20090273968METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATION FOR PCRAM DEVICES - A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line associated with a selected phase change element (PCE) to be read; comparing a first voltage on a node of the bit line with a second voltage on a delay node, wherein the second voltage represents a delayed voltage with respect to the first voltage due to a resistance/capacitance time constant associated therewith; and determining whether, during the read operation, the first voltage drops below the value of the second voltage; wherein in the event the first voltage drops below the value of the second voltage during the read operation, the PCE is determined to be programmed to an amorphous state and in the event the first voltage does not drop below the value of the second voltage, the PCE is determined to be programmed to a crystalline state.11-05-2009
20120106244PHASE-CHANGE MEMORY DEVICE - A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.05-03-2012
20120106243CURRENT CONTROL APPARATUS AND PHASE CHANGE MEMORY HAVING THE SAME - A current control apparatus of a phase change memory includes a temperature sensing block having an output voltage level which varies depending on temperature of an internal circuit and a write driver configured to control an amount of program current provided to a memory cell in response to the output voltage level of the temperature sensing block.05-03-2012
20120106242MEMORY APPARATUS HAVING STORAGE MEDIUM DEPENDENT ON TEMPERATURE AND METHOD FOR DRIVING THE SAME - A memory apparatus includes a temperature detection block configured to detect temperature of an internal circuit and output a temperature detection signal, a current control block configured to receive the temperature detection signal and generate a pulse control signal, and a write driver configured to provide a program pulse having a compensated level and width to a memory cell in response to the pulse control signal.05-03-2012
20090279352Storage nodes, phase change memories including a doped phase change layer, and methods of operating and fabricating the same - Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change layer includes indium with a concentration ranging from about 5 at % to about 15 at %. The phase change layer may be a GST layer that includes indium. The phase change layer may be a GST layer that includes gallium.11-12-2009
20090279349PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE - Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.11-12-2009
20090262574SEMICONDUCTOR DEVICE - A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.10-22-2009
20090262573MULTILEVEL NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE - A multilevel nonvolatile memory device using a resistance material is provided. The multilevel nonvolatile memory device includes at least one multilevel memory cell and a read circuit. The at least one multilevel memory cell has a level of resistance that varies according to data stored therein. The read circuit first reads first bit data from the multilevel memory cell by providing a first read bias to the multilevel memory cell and secondarily reads second bit data from the multilevel memory cell by providing a second read bias to the multilevel memory cell. The second read bias varies according to a result of the first reading.10-22-2009
20090262572MULTILAYER STORAGE CLASS MEMORY USING EXTERNALLY HEATED PHASE CHANGE MATERIAL - A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity to the PCM element and configured to program the PCM element to one of a low resistance crystalline state and a high resistance amorphous state, and a second diode serving a sense diode for a current path used in reading the state of the PCM element; the base substrate further including decoding, programming and sensing circuitry formed therein, with each of the plurality of semiconductor layers spaced by an insulating layer; and intralayer wiring for communication between the base substrate circuitry and the array of memory cells in each of the semiconductor layers.10-22-2009
20090290412Memory Devices, Memory Device Constructions, Constructions, Memory Device Forming Methods, Current Conducting Devices, and Memory Cell Programming Methods - Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.11-26-2009
20090273969CAPACITIVE DIVIDER SENSING OF MEMORY CELLS - The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.11-05-2009
20090296457Phase change random access memory and methods of manufacturing and operating same - A phase change memory device includes a switching device, a phase change storage node connected to the switching device, and a gate electrode which is spaced apart from the phase change storage node and increases an electrical resistance of the storage node during a reset programming operation. The gate electrode may be disposed around the phase change storage node, and may be used for applying an electric field to the phase change storage node.12-03-2009
20090285016Circuit for Reading Memory Cells - A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.11-19-2009
20090296459Nonvolatile Memory Device Using Variable Resistive Element - A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.12-03-2009
20090168504Phase change memory apparatus having an improved cycling endurance and programing method therefor - A phase change memory apparatus includes a phase change memory array in which a plurality of phase change memory devices are arranged, and a pulse generator that supplies a writing current pulse, an erasure current pulse, and a reverse repair current pulse to the phase change memory devices in the phase change memory array. The reverse repair current pulse has opposite direction to the writing current pulse and the erasure current pulse of the phase change memory devices, and is of such a size that resultant Joule heat and electromigration move the elements of the reverse repair current pulse. The reverse repair current pulse has a width equal to or more than a smaller one of duration of a normal writing operation and duration of a normal erasure operation.07-02-2009
20120294075PHASE-CHANGE MEMORY DEVICE - A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.11-22-2012
20120294072Phase-Change Memory and a Method of Programming the Same - According to embodiments of the present invention, a phase-change memory for storing data is provided. The phase-change memory includes a first dielectric material; a second dielectric material; and a phase-change material sandwiched between the first dielectric material and the second dielectric material, at least one of the first or second dielectric materials being a composite dielectric material having a structure of layers of two or more component materials, wherein the first dielectric material has a lower thermal conductivity than the second dielectric material. Further embodiments relate to a method of programming the phase-change memory.11-22-2012
20100110781Phase change memory device generating program current and method thereof - A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.05-06-2010
20100110780Programmable resistance memory - A minimal-duration current pulse is employed to program a programmable resistance memory to a high-resistance, RESET state. Although the duration and magnitude of RESET programming pulses in accordance with the principles of the present invention may vary depending, for example, upon the composition and structure of a cell, a method and apparatus in accordance with the principles of the present invention employs the briefest pulse practicable for a given cell or array of cells.05-06-2010
20100110779MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.05-06-2010
20100110778PHASE CHANGE MEMORY PROGRAM METHOD WITHOUT OVER-RESET - Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a fixed sequence of voltage pulses across the memory cell of increasing pulse height to change the resistance state from the lower resistance state to the higher resistance state. The fixed sequence of voltage pulses cause increasing current through the phase change memory element until change to the higher resistance state occurs, and after the change the voltage pulses in the fixed sequence causing a voltage across the phase change memory element less than the threshold voltage.05-06-2010
20100103721Heater and memory cell, memory device and recording head including the heater - A heater includes at least two leads, and a heating element which is formed between the at least two leads, a material of the heating element being different from a material of the at least two leads such that a location of a hot spot in the heater is controllable based on a polarity of current in the heater.04-29-2010
20100103723NONVOLATILE MEMORY APPARATUS - Provided are a plurality of memory cell arrays 04-29-2010
20100103726PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.04-29-2010
20100103722METHOD OF PROGRAMMING RESISTIVITY CHANGING MEMORY - A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing the resistance value to a threshold value, selecting, based on the comparison, a cell reset process to be employed for programming the at least one resistivity-changing memory cell to the high-resistance state. The selecting includes selecting a predetermined reset process as the cell reset process when the resistance value is less than the threshold value, and adjusting the predetermined process and selecting the adjusted predetermined reset process as the cell reset process when the resistance value is at least equal to the threshold value.04-29-2010
20110267875SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes a memory cell array configured to include a plurality of memory cells, a plurality of bit lines respectively coupled to the plurality of memory cells, a first power-supply voltage supplying circuit configured to provide a first power-supply voltage to the memory cell array through the plurality of bit lines, a second power-supply voltage supplying circuit configured to provide a second power-supply voltage to the memory cell array through the plurality of bit lines, a first address selection circuit configured to couple a bit line selected by a first selection address to the first power-supply voltage supplying circuit, and a second address selection circuit configured to couple a bit line selected by a second selection address to the second power-supply voltage supplying circuit.11-03-2011
20080239799NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE/WRITE METHOD THEREOF - A nonvolatile semiconductor memory device includes a memory cell array which includes a memory cell string including a plurality of memory cells each having a variable resistor element and a switching element having a current path with one end and the other end, between which the variable resistor element is connected, the plurality of memory cells having current paths thereof being connected in series, the memory cell array further including a first select element connected to one end of a current path of the memory cell string, and a second select element connected to the other end of the current path of the memory cell string, a bit line which is electrically connected to one end of a current path of the first select element, and a source line which is electrically connected to one end of a current path of the second select element.10-02-2008
20090003048NONVOLATILE MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT AND ASSOCIATED OPERATING METHOD - A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.01-01-2009
20090003047RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a semiconductor substrate; a cell array so formed on the substrate as to have resistance-change memory cells three-dimensionally stacked and arranged; and a sense amplifier array formed on the substrate under the cell array, wherein the cell array includes first and second cell array blocks arranged in a bit line direction, and first and second bit lines are selected from the first and second cell array blocks, respectively, to constitute a pair and coupled to differential input nodes in the sense amplifier array.01-01-2009
20100142263Semiconductor Switching Device - A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided that has a collector, a base and an emitter. The body region of the MOS transistor serves as the base of the bipolar transistor and the drain region of the MOS transistor serves as the collector of the bipolar transistor. Activation of the MOS transistor causes the bipolar transistor to turn on. The MOS transistor is activated to turn on the bipolar transistor and the bipolar transistor delivers current to the source region.06-10-2010
20090097305METHOD OF FORMING PHASE CHANGE MATERIAL LAYER USING GE(II) SOURCE, AND METHOD OF FABRICATING PHASE CHANGE MEMORY DEVICE - In one aspect, a method of forming a phase change material layer is provided. The method includes supplying a reaction gas including the composition of Formula 1 into a reaction chamber, supplying a first source which includes Ge(II) into the reaction chamber, and supplying a second source into the reaction chamber. Formula 1 is NR04-16-2009
20090168505SEMICONDUCTOR DEVICE - A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.07-02-2009
20090168503Phase change memory with bipolar junction transistor select device - A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory.07-02-2009
20080232161RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF - A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.09-25-2008
20090052232METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL - A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone02-26-2009
20080273379Programming a normally single phase chalcogenide material for use as a memory of FPLA - A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.11-06-2008
20120039118Providing a Ready-Busy Signal From a Non-Volatile Memory Device to a Memory Controller - A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to.02-16-2012
20080278997SEMICONDUCTOR MEMORY DEVICE AND WRITE CONTROL METHOD THEREOF - A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write data, a write driver supplying a write current to the bit line, a write control circuit controlling operations of the write driver, and a timing signal generation circuit supplying a timing signal to the write control circuit. The timing signal has a waveform including a pulse indicating a time of starting supplying the write current when a first logical level is to be written, a pulse indicating a time of ending supplying the write current if the first logical level is to be written, and a pulse indicating one of a time of starting supplying the write current and a time of ending supplying the write current when a second logical level is to be written.11-13-2008
20080291719Streaming mode programming in phase change memories - A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.11-27-2008
20100277973Metallic-Glass-Based Phase-Change Memory - A phase-change material for use in a phase-change memory device is provided. The phase-change material includes at least one metal and is reversibly phase-changeable, switchable, to a detectable metallic glass state or to a detectable crystalline state thereof. There is also provided a phase-change memory, that includes at least one phase change memory cell comprising the phase change material whereby the phase-change material and thereby the phase-change memory cell is reversibly programmable to one of these states. A method of fabricating the phase-change memory is also provided.11-04-2010
20090003046MEMORY WITH DYNAMIC REDUNDANCY CONFIGURATION - One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed.01-01-2009
20110205791TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.08-25-2011
20120294074PHASE CHANGE MEMORY PROGRAMMING METHOD AND PHASE CHANGE MEMORY - Disclosed is a method of programming a phase change memory (11-22-2012
20100290275PHASE CHANGE MEMORY APPARATUS - A phase change memory apparatus is presented. The phase change memory apparatus includes a phase change memory cell, a sense amplifier, and a voltage selecting unit. The sense amplifier is configured to differentially amplify a current that through the memory cell and a comparison voltage. The voltage selecting unit is configured to provide a reference voltage as the comparison voltage when performing a normal read function and to selectively provide either a first voltage level or a second voltage level as the comparison voltage in accordance with data when performing a verify read function.11-18-2010
20100142262INFORMATION RECORDING AND REPRODUCING APPARATUS - An information recording and reproducing apparatus, includes: a recording layer including a first layer including a first compound, the first compound being a conjugated compound including at least two types of cation elements, at least one selected from the cation elements being a transition element having a d orbit incompletely filled by electrons, a shortest distance between adjacent cation elements being not more than 0.32 nm; a voltage application unit that applies a voltage to the recording layer, produces a phase change in the recording layer, and records information; an electrode layer that applies a voltage to the recording layer; and an orientation control layer provided between the recording layer and the electrode layer to control an orientation of the recording layer.06-10-2010
20100142261INFORMATION RECORDING AND REPRODUCING APPARATUS - An information recording and reproducing apparatus, includes: a stacked structure including an electrode layer and a recording layer; a buffer layer added to the electrode layer; and a voltage application unit configured to apply a voltage to the recording layer, produce a phase change in the recording layer, and record information. The recording layer includes a first layer including a first compound having an ilmenite structure represented by A06-10-2010
20080266942Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices - A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.10-30-2008
200802669418/9 AND 8/10-BIT ENCODING TO REDUCE PEAK SURGE CURRENTS WHEN WRITING PHASE-CHANGE MEMORY - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are uninverted. Peak currents are thus reduced by encoding to reduce reset data bits.10-30-2008
20110205790PHASE-CHANGE MEMORY DEVICE - A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.08-25-2011
20110205789Semiconductor memory apparatus - A semiconductor memory apparatus includes a plurality of unit cell arrays having a plurality of word lines which are disposed in a row direction and a plurality of global bit lines which are disposed in a column direction; a row decoder configured to activate at least two word lines among the plurality of word lines in response to a row address which designates one word line; a global column switch block configured to select two different global bit lines among the plurality of global bit lines in response to column control signals; and a column decoder configured to generate the column control signals in response to a column address.08-25-2011
20090303784Asymetric threshold three terminal switching device - An asymmetric-threshold three-terminal electronic switching device includes three terminals coupled to a threshold-switching material. A signal applied across first and second terminals affects an electrical characteristic between the second and third electrodes to a greater extent than the same signal applied across the first and third electrodes. The affected electrical characteristic may be a threshold voltage or conductivity, for example.12-10-2009
20090303781Method and apparatus for thin film memory - A multi-layer thin-film device includes thin film memory and thin film logic. The thin film memory may be programmable resistance memory, such as phase change memory, for example. The thin film logic may be complementary logic.12-10-2009
20090086534APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES - A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.04-02-2009
20100271869PHASE CHANGE MEMORY DEVICE HAVING DECENTRALIZED DRIVING UNITS - A phase change memory device includes a plurality of intersecting bit lines and word lines. A cell array including a plurality of unit phase change resistance cells is formed at intersections of the plurality of bit lines and the plurality of word lines. A plurality of sub word line driving units are configured to drive the word lines in response to a plurality of sub word line signals. A plurality of main word line driving units are configured to drive the sub word line driving units in response to a main word line signal. A precharge unit is configured to precharge the word lines. In the phase change memory device, the driving units are is decentralized.10-28-2010
20090161415INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION - An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.06-25-2009
20110267877SEMICONDUCTOR DEVICE - A semiconductor device includes first and second phase-change memory elements (GST11-03-2011
20090161416OPTIMIZED PHASE CHANGE WRITE METHOD - A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.06-25-2009
20120140555MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.06-07-2012
20090027956RESISTANCE VARIABLE MEMORY DEVICE REDUCING WORD LINE VOLTAGE - A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.01-29-2009
20090027954PHASE CHANGE MEMORY DEVICE WITH BIT LINE DISCHARGE PATH - A phase change memory device includes a cell array. The cell array includes a phase change resistance cell formed at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a bit line discharge signal in a precharge mode. A column switching unit is configured to selectively control a connection between the bit line and a global bit line in response to a column selecting signal.01-29-2009
20090027951Reading phase change memories with select devices - A phase change memory including a threshold device, such as an ovonic threshold switch, and a storage device may be read. Reading the cell may involve applying a first voltage to a selected cell and then a second voltage, lower than the first voltage. The first voltage may be sufficient to threshold the ovonic threshold switch if the storage device is in the set state.01-29-2009
20090161418PHASE CHANGE MEMORY DEVICE HAVING DECENTRALIZED DRIVING UNITS - A phase change memory device includes a plurality of intersecting bit lines and word lines. A cell array including a plurality of unit phase change resistance cells is formed at intersections of the plurality of bit lines and the plurality of word lines. A plurality of sub word line driving units are configured to drive the word lines in response to a plurality of sub word line signals. A plurality of main word line driving units are configured to drive the sub word line driving units in response to a main word line signal. A precharge unit is configured to precharge the word lines. In the phase change memory device, the driving units are decentralized.06-25-2009
20090161419NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING - Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.06-25-2009
20090161417Two cell per bit phase change memory - A phase change memory array may have a plurality of cells in which a bit is determined by a single cell. In addition, a portion of the array may include a plurality of cells which are combined so that two cells form one bit of memory. One of the combined cells is programmed to the complementary state of the other of the combined cells. Thus, the bit is determined by reading the indicator bit which is correctly programmed and comparing it to the complement cell. As a result, the bit may be very reliable because the read window is twice as wide as that used in a conventional phase change memory which compares the selected bit current to a reference current that is midway between the programmed and unprogrammed states.06-25-2009
20090185412PHASE-CHANGE MATERIAL, MEMORY UNIT AND METHOD FOR ELECTRICALLY STORING/READING DATA - A phase-change material and a memory unit using the phase-change material are provided. The phase-change material is in a single crystalline state and includes a compound of a metal oxide or nitroxide, wherein the metal is at least one selected from a group consisting of indium, gallium and germanium. The memory unit includes a substrate; at least a first contact electrode formed on the substrate; a dielectric layer disposed on the substrate and formed with an opening for a layer of the phase-change material to be formed therein; and at least a second contact electrode disposed on the dielectric layer. As the phase-change material is in a single crystalline state and of a great discrepancy between high and low resistance states, the memory unit using the phase-changed material can achieve a phase-change characteristic rapidly by pulse voltage and avert any incomplete reset while with a low critical power.07-23-2009
20090129144PHASE CHANGE MEMORY AND METHOD DISCHARGING BITLINE - Disclosed are a phase change memory device in which an active time is reduced and a method of discharging a bitline in the phase change memory device. In the phase change memory device having the reduced active time and the method of discharging the bitline in the phase change memory device, the bitline is either always discharged when the phase change memory device is in standby, is discharged after the active operation of the phase change memory device, or is discharged prior to and after the active operation of the phase change memory device.05-21-2009
20090034323PHASE CHANGE MEMORY WITH DUAL WORD LINES AND SOURCE LINES AND METHOD OF OPERATING SAME - A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.02-05-2009
20080316807Semiconductor memory device having metal-insulator transition film resistor - A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.12-25-2008
20120069645MULTIPLE BIT PHASE CHANGE MEMORY CELL - A phase change memory cell has more than one memory region (03-22-2012
20120069644Replaceable, precise-tracking reference lines for memory products - Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts.03-22-2012
20090185411INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS - The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.07-23-2009
20090141548MEMORY AND METHOD FOR DISSIPATION CAUSED BY CURRENT LEAKAGE - Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.06-04-2009
20090141547Non-volatile memory devices and methods of fabricating and using the same - Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.06-04-2009
20090141546Method of operating a phase-change memory device - A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.06-04-2009
20090141545Planar third dimensional memory with multi-port access - Embodiments of the invention relate generally to a planar third dimensional memory with multi-port access, the planar third dimensional memory including memory planes composed of a plurality of memory layers. The memory layers can include non-volatile memory elements. The planar third dimensional memory can also include insulation layers, each being formed to separate a memory layer from another memory layer, and a logic plane configured to control access to the plurality of memory planes. In some cases, the memory planes can be formed vertically above the logic plane. The logic plane can be formed in a substrate, such as a semiconductor wafer, for example. The planar third dimensional memory can include a multi-port interface that can be configured to provide access between a plurality of ports and the plurality of memory planes.06-04-2009
20090003045CMOS-PROCESS-COMPATIBLE PROGRAMMABLE VIA DEVICE - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer.01-01-2009
20090003044PROGRAM METHOD WITH LOCALLY OPTIMIZED WRITE PARAMETERS - A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.01-01-2009
20090027950Block Erase for Phase Change Memory - An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.01-29-2009
20090273970MEMORY DEVICE INCLUDING A PROGRAMMABLE RESISTANCE ELEMENT - Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.11-05-2009
20130121069INTERNAL VOLTAGE GENERATING CIRCUIT OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD THEREOF - An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.05-16-2013
20110141800PHASE-CHANGE MEMORY DEVICE - A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal, and a data write unit configured to output a program current in response to the write control signals and control a level of the program current according to a code combination of the write control codes.06-16-2011
20090052235Resistance variable memory device and programming method thereof - Provided is a method of programming a resistance variable memory device. The resistance variable memory device includes a memory cell having multi states and a write driver outputting a program pulse for programming the memory cell into one of the multi states. The method of programming the resistance variable memory device includes applying a first program pulse to the resistance variable memory device and applying a second program pulse to a memory cell when the memory cell is programmed into an intermediate state. When the first program pulse is a reset pulse, the reset pulse is an over program pulse, that is, an over reset pulse. Therefore, the resistance variable memory device can secure a sufficient read margin as well as improve a resistance drift margin.02-26-2009
20090052234Phase-change random access memory device and semiconductor memory device - A semiconductor memory device includes: first and second wiring layers extending in substantially parallel to each other in a first direction; a first semiconductor region formed in a part of a portion between the first and second wiring layers; a second semiconductor region formed on an opposite side to the first semiconductor region with respect to the second wiring layer and making a pair with the first semiconductor region; a third semiconductor region formed in another part of the portion between the first and second wiring layers; a fourth semiconductor region formed on an opposite side to the third semiconductor region with respect to the first wiring layer and making a pair with the third semiconductor region; a third wiring layer extending in a second direction that crosses the first direction and having an electrical contact with the first semiconductor region; a fourth wiring layer extending in the second direction and having an electrical contact with the fourth semiconductor region; a fifth wiring layer extending in the first direction to cross over the first and third semiconductor regions; a sixth wiring layer extending in the first direction in substantially parallel to the fifth wiring layer to cross over the second semiconductor region; seventh wiring layers extending in the second direction in substantially parallel to one another, each of the seventh wiring layers intersecting each of the fifth and sixth wiring layers; first memory elements each disposed at an intersection of an associated one of the seventh wiring layers and the fifth wiring layer; and second memory elements each disposed at an intersection of an associated one of the seventh wiring layers and the sixth wiring layer.02-26-2009
20090052236Resistance variable memory device and operating method thereof - Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.02-26-2009
20090097307Phase-change random access memory device, system having the same, and associated methods - A phase-change random access memory (PRAM) device includes a PRAM cell array having a first bank that includes first to m04-16-2009
20090097306Phase-change random access memory device, system having the same, and associated methods - A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality of global bit line discharge units coupled to the first global bit line, the first plurality of global bit line discharge units configured to discharge the first global bit line in response to a first global discharge signal.04-16-2009
20130215677PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE - A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance.08-22-2013
20110228600MEMORY PROGRAMMING - Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.09-22-2011
20110141799REVERSING A POTENTIAL POLARITY FOR READING PHASE-CHANGE CELLS TO SHORTEN A RECOVERY DELAY AFTER PROGRAMMING - A potential supplied to selected cells in a Phase Change Memory (PCM) is reversed in polarity following a program operation to suppress a recovery time and provide device stabilization for a read operation.06-16-2011
20110141798Amorphous Semiconductor Threshold Switch Volatile Memory Cell - A voltage memory switch may be formed of an amorphous semiconductor threshold switch and a select device. The amorphous threshold switch may be latched into one of two different current conducting levels. Then, in some embodiments, a relatively dense memory array can be achieved by maintaining an appropriate bias on the cell to prevent it from losing the programmed state.06-16-2011
20090097304NONVOLATILE MEMORY USING RESISTANCE MATERIAL - Provided is a nonvolatile memory using a resistance material. In embodiments of the invention, a PRAM is configured to apply a step-down voltage to wordlines during a standby mode. Aspects of the present invention thus provide a nonvolatile memory with reduced standby current. Additionally, embodiments of the invention allow for faster transition from a standby state to an active state.04-16-2009
20090231911PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE - Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the first and second electrodes. The memory element may include a programmable portion having a material configured to change between multiple phases. The programmable portion may be isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element.09-17-2009
20090231910NON-VOLATILE MEMORY WITH RESISTIVE ACCESS COMPONENT - Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.09-17-2009
20110228599Non-Volatile Memory Cell with Programmable Unipolar Switching Element - A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.09-22-2011
20080316806Phase change memory device - A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.12-25-2008
20080316803SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device.12-25-2008
20090207652SEMICONDUCTOR DEVICE INCLUDING RESISTANCE STORAGE ELEMENT - A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.08-20-2009
20090219756Apparatus and Method for Determining a Memory State of a Resistive N-Level Memory Cell and Memory Device - A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n−1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values.09-03-2009
20090219755INTEGRATED CIRCUIT INCLUDING AN ELECTRODE HAVING AN OUTER PORTION WITH GREATER RESISTIVITY - An integrated circuit includes a first electrode including an inner portion and an outer portion laterally surrounding the inner portion. The outer portion has a greater resistivity than the inner portion. The integrated circuit includes a second electrode and resistivity changing material contacting the first electrode and coupled to the second electrode.09-03-2009
20100165713METHOD FOR LOW POWER ACCESSING A PHASE CHANGE MEMORY DEVICE - A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.07-01-2010
20090244964Reducing temporal changes in phase change memories - A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.10-01-2009
20090244962Immunity of phase change material to disturb in the amorphous phase - Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.10-01-2009
20090244961PHASE CHANGE MEMORY - The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.10-01-2009
20100265762Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include anon-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.10-21-2010
20100149858Providing a Ready-Busy Signal From a Non-Volatile Memory Device to a Memory Controller - A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to.06-17-2010
20080259677Memory including bipolar junction transistor select devices - An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.10-23-2008
20120195113PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS - A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal.08-02-2012
20090257275Seasoning phase change memories - A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory.10-15-2009
20100149859PHASE-CHANGE MEMORY DEVICE - A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal, and a data write unit configured to output a program current in response to the write control signals and control a level of the program current according to a code combination of the write control codes.06-17-2010
20100014345NONVOLATILE MEMORY DEVICE WITH TEMPERATURE CONTROLLED COLUMN SELECTION SIGNAL LEVELS - A nonvolatile memory device includes a memory cell array with a matrix of nonvolatile memory cells. The nonvolatile memory cells may store data using variable resistive elements. A plurality of bitlines are coupled to a plurality of nonvolatile memory cell arrays in the memory cell array. A column selection circuit selects among the bitlines in response to a column selection signal. A controller regulates a level of the column selection signal in response to a temperature signal from a temperature sensor. The temperature sensor may be configured to measure temperature outside the nonvolatile memory device to generate the temperature signal.01-21-2010
20100002500Read Reference Circuit for a Sense Amplifier Within a Chalcogenide Memory Device - A read reference circuit for a sense amplifier within a chalcogenide memory device is disclosed. The read reference circuit provides a reference voltage level to the sense amplifier for distinguishing between a logical “0” state and a logical “1” state within a chalcogenide memory cell. In conjunction with a precharge circuit, the read reference circuit generates a selectable read reference current to the sense amplifier in order to detect the logical state of the chalcogenide memory cell. The precharge circuit precharges the bitlines of the chalcogenide memory cell before the sense amplifier detects the logical state of the chalcogenide memory cell.01-07-2010
20100165728PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE - Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.07-01-2010
20100149856Writing Memory Cells Exhibiting Threshold Switch Behavior - A memory cell exhibiting threshold switch behavior, such as a phase change memory, can be programmed in a way that eliminates the need for a separate post-programming verification cycle. In particular, a circuit can be used to apply the programming pulse to a cell in a way that determines whether the cell has reached the desired threshold voltage. If the cell has not reached the desired threshold voltage, it receives another programming pulse. If it has, it does not receive another programming pulse. Thus, by applying a voltage across the cell that never exceeds the threshold voltage of the cell, the need for a separate verification cycle can be eliminated in some embodiments.06-17-2010
20100177559METHOD FOR SETTING PCRAM DEVICES - Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a bias arrangement to a memory cell to change the resistance state from a higher resistance state to a lower resistance state. The bias arrangement comprises a first voltage pulse and a second voltage pulse across the phase change memory element, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.07-15-2010
20100157666METHOD FOR READING SEMICONDUCTOR MEMORIES AND SEMICONDUCTOR MEMORY - A phase change memory cells including a memory element or a threshold device is read using a read current which does not threshold either the memory element or the threshold device in the case of both a set and a reset memory element. As a result, higher currents may be avoided, increasing read endurance. A sensing circuit includes a charging rate detector coupled to a selected address line and sensing a rate of change of a voltage on the selected address line.06-24-2010
20100182826Reduction of Drift in Phase-Change Memory via Thermally-Managed Programming - A method of programming a phase-change material. The method includes providing a transformation pulse to the phase-change material, where the transformation pulse includes a programming waveform and a conditioning waveform. The programming waveform provides sufficient energy to alter the structural state of the phase-change material. In one embodiment, the programming waveform alters the volume fractions of crystalline and amorphous phase regions within the phase-change material. The conditioning waveform provides sufficient energy to heat the phase-change material to a temperature above the ambient temperature but below the crystallization temperature of the phase-change material. The method programs the phase-change material to a state that exhibits a reduced time variation of resistance.07-22-2010
20100002498INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY CELL - An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion.01-07-2010
20100165720VERIFICATION CIRCUITS AND METHODS FOR PHASE CHANGE MEMORY ARRAY - A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state07-01-2010
20100165727PHASE CHANGE MATERIAL MEMORY HAVING NO ERASE CYCLE - An information storage array includes a programmable material at one or more storage locations and pulse generation circuitry for generating at least two pulses—in particular, a write pulse that writes a value into the programmable material an erase pulse that erases a value from the programmable material. In general, the erase pulse is greater in duration than the write pulse. Either the write pulse or the erase pulse is selected based at least in part on a state of a data bit to be stored in the programmable material.07-01-2010
20100165729NONVOLATILE MEMORY DEVICE AND RELATED METHODS OF OPERATION - In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.07-01-2010
20100165725RELIABLE SET OPERATION FOR PHASE-CHANGE MEMORY CELL - A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed.07-01-2010
20090147563INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT - An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance.06-11-2009
20100182828SEMICONDUCTOR STORAGE DEVICE - There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.07-22-2010
20100182827High Margin Multilevel Phase-Change Memory via Pulse Width Programming - An electronic device and method of programming for binary and multilevel memory operation. The active material of the device is a phase-change material. The method includes utilization of the pulse duration of electrical pulses as a programming variable to program a phase-change device to two or more memory states that differ in the relative proportion and/or spatial arrangement of crystalline and amorphous phase regions. Pulse width programming, in conjunction with a device electrical contact having a resistivity within a particular range, enables fine control over the crystalline-amorphous phase-change process by facilitating control over the spatial distribution of thermal energy produced by Joule heating. The degree of control over the phase-change process enables reliable multilevel memory operation by providing for reproducible programming of memory states that are well-resolved in both resistance and programming variable.07-22-2010
20100182825Programmable resistance memory - A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.07-22-2010
20100259974NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT - Disclosed is a non-volatile semiconductor memory circuit. The non-volatile semiconductor memory circuit a memory cell array, and a verification sense amplifier controller configured to control switching devices, which receive external input data, depending on a level of the input data such that distribution voltage is changed when controlling a write operation by comparing the input data with cell data written in the memory cell array so as to provide cell data.10-14-2010
20100188892ELECTRIC DEVICE COMPRISING PHASE CHANGE MATERIAL AND HEATING ELEMENT - An electric device has a resistor including a phase change material changeable between a first phase and a second phase within a switching zone. The resistor has a first resistance when the phase change material is in the first phase and a different second resistance, when the phase change material is in the second phase. The resistor may conduct a first current. The device has a heating element that may conduct a second current for enabling a transition of the phase change material from the first to the second phase. At the position of the switching zone, the resistor is arranged as a first line and the heating element is arranged as a second line. The first and second line may conduct the first current and the second current respectively, wherein the first line and the second line cross at the position of the switching zone.07-29-2010
20090316473INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.12-24-2009
20080205128PHASE CHANGE MEMORY DEVICE - A phase change memory device has a memory cell that uses a phase change film as a storage element, and includes: a first phase change region formed on a side of one face of the phase change film; and a second phase change region formed on a side of another face of the phase change film in a position that corresponds to the first phase change region, wherein the phase change memory stores two-bit data using combinations of a high resistance state due to amorphization and a low resistance state due to crystallization in the first phase change region with the high resistance state and the low resistance state in the second phase change region, the resistance value of the low resistance state being lower than that of the high resistance state.08-28-2008
20130215676SUPPLY VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal.08-22-2013
20080212362Control of set/reset pulse in response to peripheral temperature in pram device - A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.09-04-2008
20100157665MEMORY CELL DEVICE AND PROGRAMMING METHODS - A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value.06-24-2010
20080232159PHASE-CHANGE TaN RESISTOR BASED TRIPLE-STATE/MULTI-STATE READ ONLY MEMORY - The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.09-25-2008
20100149857Reading Threshold Switching Memory Cells - Using the voltage across a threshold switching cell to sense the state of the cell, rather than sensing current through the cell, may result in a faster read. In some embodiments, current consumption during reading of conductive states may be reduced by using a capacitor coupled across the cell.06-17-2010
20100226168Programming methods for phase-change memory - Set pulses with finite rise time that heat up phase change alloy between about nucleation temperature and about average of crystallization and melting temperatures are proposed for programming phase change memory from reset to set state in order to minimize energy during this transition and to achieve uniform set state distribution. Non-square reset pulses with finite rise time that heat up phase change alloy at or above melting temperature are proposed for programming phase change memory from set to reset state in order to improve cell endurance.09-09-2010
20100238720Electronic Device, And Method of Operating An Electronic Device - An electronic device (09-23-2010
20110058410SEMICONDUCTOR MEMORY DEVICE - A random-access non-volatile semiconductor memory device, which does not use individual gate terminals of transistors of memory cells in order to select individual memory cells for read/write operations performed on the device. The gate terminals of the memory cells are all biased to the same voltage during a read or write operation. For example, the gate terminals of the memory cells in the array are electrically connected together. By appropriate control of source and drain voltages during a read or write operation, discrimination can be achieved between selected and non-selected memory cells of the array.03-10-2011
20090310401INTEGRATED CIRCUIT INCLUDING A MEMORY ELEMENT PROGRAMMED USING A SEED PULSE - An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse.12-17-2009
20090116281Reading Phase Change Memories - A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.05-07-2009
20090116280Accessing a phase change memory - A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient charge for an ensuing access. When a memory cell is accessed, charge stored on the capacitor is discharged through the phase change memory, supplying a current to the phase change memory cell that is sufficient for the intended access operation and greater than that provided directly by the current source.05-07-2009
20090285014INTEGRATED CIRCUIT AND METHOD FOR SWITCHING A RESISTIVELY SWITCHING MEMORY CELL - An integrated circuit and method for switching a resistively switching memory cell. One embodiment provides an initial pulse and at least one escalated pulse in case the memory cell did not switch.11-19-2009
20090279351SEMICONDUCTOR MEMORY DEVICES AND METHODS HAVING CORE STRUCTURES FOR MULTI-WRITING - A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line. In a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, so that data writing time is reduced under the same conditions as a normal write mode.11-12-2009
20080316802MEMORY DEVICE HAVING DRIFT COMPENSATED READ OPERATION AND ASSOCIATED METHOD - A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels.12-25-2008
20090040816METHOD FOR DRIVING A PHASE CHANGE MEMORY DEVICE USING VARIOUS WRITE CONDITIONS - A phase change memory device includes a phase change resistor configured to sense a change in crystallization state due to current flow in order to store data that corresponds to the crystallization state. The phase change memory device is driven by reading cell data of a selected unit cell using a reference current. The cell data is compared to write data and then it is determined whether the write data is set data or reset data if the cell data is different from the write data. The set or reset state is written to the cell and verified during a write and verification operation under various conditions to stably write the data.02-12-2009
20090040814METHOD FOR DRIVING MULTI-LEVEL DATA TO A PHASE CHANGE MEMORY DEVICE - A phase change memory device including a phase change resistor senses a crystallization state that is changed according to supplied currents to store data corresponding to the crystallization state. The phase change memory device may receive and store multi-level data. The multi-level data is driven to the phase change memory device by reading cell data of a selected cell. The cell data is compared to multi-level data to be written to the cell. A high resistance reset state is written to the phase change resistor by applying a write voltage that corresponds to a threshold voltage when the cell data is different from the multi-level data. The multi-level data is then written to the phase change resistor by writing and verifying a set state that corresponds to the multi-level data.02-12-2009
20090323407Memory device, an information storage process, a process, and a structured material - A memory device, including a plurality of nanoscale memory cells (12-31-2009
20090073752Adaptive wordline programming bias of a phase change memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.03-19-2009
20090073754Multi-level phase change memory device, program method thereof, and method and system including the same - In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set to be longer than a falling time of the program signal.03-19-2009
20090073751Interleaved array architecture - A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.03-19-2009
20120243306METHOD AND APPARATUS TO RESET A PHASE CHANGE MEMORY AND SWITCH (PCMS) MEMORY CELL - The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, the non-volatile memory of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a process for resetting the PCMS memory utilizing a “look-up” table to calculate a current required to place a bit above a reference level to maximum threshold voltage.09-27-2012
20110032753MEMORY CELLS INCLUDING RESISTANCE VARIABLE MATERIAL PATTERNS OF DIFFERENT COMPOSITIONS - A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.02-10-2011
20100220519Sensing Characteristic Evaluating Apparatus for Semiconductor Device and Method Thereof - A sensing characteristic evaluating apparatus for a semiconductor device includes a test current supply unit configured to supply a test current to an input/output line during a test mode for evaluating a sensing characteristic, and a sensing amplifying circuit configured to receive the test current from the input/output line, to compare and amplify a sensing input voltage corresponding to the test current with a reference voltage, and to output an amplified voltage as a sensing output voltage.09-02-2010
20090161420FIELD-EMITTER-BASED MEMORY ARRAY WITH PHASE-CHANGE STORAGE DEVICES - Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other embodiments, the field-emitter devices include a volume-change material, capable of changing a measurable electrical property of the devices, and/or three-dimensional memory arrays of the same.06-25-2009
20090109737Method of restoring variable resistance memory device - Methods of programming a phase-change memory device that remedy device failure. The methods includes applying a sequence of two or more electrical energy pulses to the device, where the sequence of pulses includes positive polarity pulses and negative polarity pulses. In one method, two or more pulses of an initial polarity are applied and are followed by one or more pulses having opposite polarity. In another method, pulses of an initial polarity are repeatedly applied until the device fails and one or more pulses of opposite polarity are subsequently applied to restore the device to its initial performance. The pulses may be set pulses, reset pulses, or pulses that produce programmed states having a resistance intermediate between the set resistance and reset resistance of the device.04-30-2009
20100220521PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND RELATED METHODS OF OPERATION - A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.09-02-2010
20100296338NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.11-25-2010
20100302842SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF, DATA PROCESSING SYSTEM, AND DATA PROCESSING DEVICE - A semiconductor memory device includes: first and second impurity diffusion layers that form a part of a semiconductor substrate, each of the impurity diffusion layers function as one and the other of an anode and a cathode, respectively of a pn-junction diode; a recording layer connected to the second impurity diffusion layer; and a cylindrical sidewall insulation film provided on the first impurity diffusion layer. At least a part of the second diffusion layer and at least a part of the recording layer are formed in a region surrounded by a sidewall insulation film. According to the present invention, because a pillar-shaped pn-junction diode and the recording layer are formed in a self-aligned manner, the degree of integration of a semiconductor memory device can be increased. Further, because a silicon pillar is a part of the semiconductor substrate, a leakage current attributable to a crystal defect can be reduced.12-02-2010
20130135924PROGRAMMING OF PHASE-CHANGE MEMORY CELLS - Methods and apparatus are provided for programming a phase-change memory cell having s>2 programmable cell states. At least one control signal is applied to produce a programming pulse for programming the cell. At least one control signal is varied during the programming pulse to shape the programming pulse in dependence on the cell state to be programmed and produce a selected one of a plurality of programming pulse waveforms corresponding to respective programming trajectories for programming the cell states. The selected programming pulse waveform corresponds to a programming trajectory containing the cell state to be programmed.05-30-2013
20100309714METHODS, STRUCTURES, AND DEVICES FOR REDUCING OPERATIONAL ENERGY IN PHASE CHANGE MEMORY - Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.12-09-2010
20110122685MULTI-LEVEL PHASE-CHANGE MEMORY DEVICE AND METHOD OF OPERATING SAME - A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages.05-26-2011
20110122683Resetting Phase Change Memory Bits - After determining that a reset pulse has reached its programmed threshold voltage level, a lower voltage verify can be conducted. This can be followed by another program step to increase the programmed threshold voltage. By avoiding the need for subsequent verification after the cell has reached its desired threshold level, read disturbs may be reduced in some embodiments. In some embodiments, by using lower voltages, it is not necessary to apply higher bias voltages to de-selected cells which may result in current leakage.05-26-2011
20100321992PHASE CHANGE MEMORY ELEMENTS USING ENERGY CONVERSION LAYERS, MEMORY ARRAYS AND SYSTEMS INCLUDING SAME, AND METHODS OF MAKING AND USING SAME - A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.12-23-2010
20100321990Memory Including Vertical Bipolar Select Device and Resistive Memory Element - A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.12-23-2010
20100321991Chalcogenide Devices Exhibiting Stable Operation from the As-Fabricated State - A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge12-23-2010
20100321989FUSION MEMORY DEVICE EMBODIED WITH PHASE CHANGE MEMORY DEVICES HAVING DIFFERENT RESISTANCE DISTRIBUTIONS AND DATA PROCESSING SYSTEM USING THE SAME - A fusion memory device having phase change memory devices that have different resistance distributions and a corresponding data processing system is presented. The fusion memory device includes a first and a second phase change memory group arranged on the same chip. Because the second phase change memory group exhibits a resistance distribution different from that of the first phase change memory group, then the fusion memory device can be configured to simultaneously function as both a DRAM device and as a flash memory device. Because the first and second phase change memory groups can be composed of similar PRAM components, the corresponding manufacturing and driving circuitry is markedly simplified as compared to other fusion memory devices that have dissimilar DRAM and flash memory components.12-23-2010
20100321987MEMORY DEVICE AND METHOD FOR SENSING AND FIXING MARGIN CELLS - A programmable resistance memory device with a margin cell detection and refresh resources. Margin cell detection and refresh can comprise reading a selected cell, measuring a time interval which correlates with resistance of the selected cell during said reading, and enabling a refresh process if the measured time falls within a pre-specified range. The refresh process includes determining a data value stored in the selected cell, using for example a destructive read process, and refreshing the data value in the selected cell. The time interval can be measured by detecting timing within the sensing interval of a transition of voltage or current on a bit line across a threshold.12-23-2010
20110002161PHASE CHANGE MEMORY CELL WITH SELECTING ELEMENT - A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array.01-06-2011
20110242887Programmable Resistance Memory with Feedback Control - A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.10-06-2011
20110013447SEMICONDUCTOR DEVICE - A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.01-20-2011
20090003049PHASE CHANGE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.01-01-2009
20100182829SEMICONDUCTOR MEMORY DEVICE - To provide a plurality of write amplifiers that perform a data write operation upon memory cells and a write control circuit that controls a timing of a data write operation performed by the write amplifiers. When a data write operation using another write amplifier is requested while a data write operation using a predetermined write amplifier is performed, the write control circuit suspends the data write operation using the predetermined write amplifier. The suspended data write operation is performed again simultaneously with the data write operation using the other write amplifier. Accordingly, random column access like that of a DRAM can be realized by simple control.07-22-2010
20090067230Multi-level memory devices and methods of operating the same - The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.03-12-2009
20090067228PHASE CHANGE MEMORY DEVICE, MANUFACTURING METHOD THEREOF AND OPERATING METHOD THEREOF - A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM device without the need for an additional insulation layer. The PCM device has a phase change resistor PCR that has one terminal connected to a word line and the other terminal connected in common to the N-terminals of two PN diodes in which the P-terminals are connected in common to the bit line. As a result, a current flowing through the phase change resistor PCR is doubled which results in doubling the cell driving capacity.03-12-2009
20090067227PHASE CHANGE MEMORY DEVICE HAVING A PLURALITY OF REFERENCE CURRENTS AND OPERATING METHOD THEREOF - A phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A plurality of sense amplifiers sense and amplify data of the phase change resistance cell selected using a plurality of reference currents. A plurality of comparing units compare an output signal of the corresponding sense amplifier with that of the neighboring sense amplifier so as to output a flag enable signal.03-12-2009
20110110148MEMORY ARRAYS AND ASSOCIATED METHODS OF MANUFACTURING - Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit.05-12-2011
20110026319NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT AND METHOD OF CONTROLLING THE SAME - A non-volatile semiconductor memory circuit for use in compensating for time dependent resistive changes in phase change memory cells is presented. The non-volatile semiconductor memory circuit includes a control signal generation unit and a sensing block. The control signal generation unit is configured to provide a control signal having a voltage level corresponding to a read command or a write command. The sensing block is configured to selectively provide a first sensing reference voltage substantially equal to a reference voltage. The sensing block is also configured to selectively provide a second sensing reference voltage which is lower than the reference voltage. The first and second sensing reference voltages are selectively provided as a function of the voltage level of the control signal in which the first and second sensing reference voltages are used to read data of the memory cell array.02-03-2011
20110026318ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS - Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.02-03-2011
20100177560NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES - A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.07-15-2010
20120134203Semiconductor Device and Data Processing System - In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.05-31-2012
20090034325Programmable matrix array with chalcogenide material - A chalcogenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.02-05-2009
20110044097PHASE CHANGE MEMORY AND OPERATION METHOD OF THE SAME - An operation method of phase change memory (PCM) is provided. The operation method includes applying a RESET pulse to a phase change material of the PCM, wherein the RESET pulse has a profile with a first tail such that a plurality of seeds are formed in the phase change material. Due to the design of the RESET pulse in the operation method, it can speed up the crystal process.02-24-2011
20090040818TIME EFFICIENT PHASE CHANGE MEMORY DATA STORAGE DEVICE - A phase change memory device is presented that includes a phase change resistance cell array and a cache register. The phase change resistance cell array includes a phase change resistor configured to sense crystallization changed depending on currents so as to store data corresponding to resistance change. The cache register is configured to store a plurality of data applied externally depending on a register write command and to simultaneously output the plurality of data to the phase change resistance cell array depending on a cell write command.02-12-2009
20110044098Nonvolatile Memory Cells Having Phase Changeable Patterns Therein for Data Storage - A nonvolatile memory cell includes a substrate and a phase changeable pattern configured to retain a state of the memory cell, on the substrate. An electrically insulating layer is provided, which contains a first electrode therein in contact with the phase changeable pattern. The first electrode has at least one of an L-shape when viewed in cross section and an arcuate shape when viewed from a plan perspective. A lower portion of the first electrode may be ring-shaped when viewed from the plan perspective. The lower portion of the first electrode may also have a U-shaped cross-section. An upper portion of the first electrode may also have an arcuate shape that spans more than 180° of a circular arc.02-24-2011
20110116307PHASE CHANGE MEMORY DEVICE SUITABLE FOR HIGH TEMPERATURE OPERATION - A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.05-19-2011
20110116309Refresh Circuitry for Phase Change Memory - A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.05-19-2011
20110116308MULTIPLE PHASE CHANGE MATERIALS IN AN INTEGRATED CIRCUIT FOR SYSTEM ON A CHIP APPLICATION - An integrated circuit includes a plurality of memory cells on a substrate, in which a first set of memory cells uses a first memory material, and a second set of memory cells uses a second memory material. The first and second memory materials have different properties such that the first and second sets of memory cells have different operational memory characteristics, such as switching speeds, retention and endurance.05-19-2011
20090052230INTEGRATED CIRCUIT INCLUDING SILICIDE REGION TO INHIBIT PARASITIC CURRENTS - An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.02-26-2009
20090190393PHASE CHANGE MEMORY DEVICE WITH DUMMY CELL ARRAY - A phase change memory device includes a cell array having a phase change resistance cell arranged at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a first bit line discharge signal. A column switching unit selectively controls a connection between the bit line and a global bit line in response to a column selecting signal. The dummy cell disconnects a discharging path in response to the first bit line discharge signal in a precharge mode, and discharges the bit line in response to the first bit line discharge signal in an active mode.07-30-2009
20090323409METHODS FOR HIGH SPEED READING OPERATION OF PHASE CHANGE MEMORY AND DEVICE EMPLOYING SAME - Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.12-31-2009
20110080781PHASE CHANGE MEMORY DEVICE AND CONTROL METHOD - The present invention relates to a phase change memory device comprising a plurality of phase change memory cells, each cell comprising a phase change material (04-07-2011
20110242886Apparatus and Systems Using Phase Change Memories - Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.10-06-2011
20110242884Programming at Least One Multi-Level Phase Change Memory Cell - A method of applying at least one programming pulse to the a PCM cell for programming the PCM cell to have a respective definite cell state, the definite cell state being defined by a definite resistance level using an annealing pulse or a melting pulse. The respective definite cell state represents two information entities, a step of applying a first reading pulse to the respective programmed PCM cell to provide a first resistance value, a step of applying at least a second reading pulse to the respective programmed PCM cell to provide a second resistance value, the first reading pulse and the second reading pulse being different pulses; and a step of determining the respective definite cell state of the respective programmed PCM cell dependent on the respective provided first resistance value and the respective provided second resistance value.10-06-2011
20100220522PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING READ OPERATION THEREOF - A phase change random access memory is provided which includes a memory array including a plurality of phase change memory cells, and wordlines respectively connected to the phase change memory cells, where, in a read operation, a voltage of a wordline connected to a selected phase change memory cell is transitioned between at least two voltage stages having different voltage levels.09-02-2010
20100220520Multi-bit phase change memory devices - A multi-bit phase change memory device including a phase change material having a plurality of crystalline phases. A non-volatile multi-bit phase change memory device may include a phase change material in a storage node, wherein the phase change material includes a binary or ternary compound sequentially having at least three crystalline phases having different resistance values according to an increase of temperature of the phase change material.09-02-2010
20110080779SEMICONDUCTOR DEVICE INCLUDING RESISTANCE STORAGE ELEMENT - A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.04-07-2011
20110211390SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.09-01-2011
20110242885THREE-DIMENSIONAL PHASE CHANGE MEMORY - A memory device includes a stack of semiconductor layers. A circuit is on a layer of the stack of semiconductor layers. A primary memory array is on another layer of the stack of semiconductor layers different from the layer comprising the circuit. A plurality of electrical communication paths are between the circuit and the primary memory array. The circuit controls the operation of the primary memory array over the electrical communication paths.10-06-2011
20110085376Shunted Phase Change Memory - By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.04-14-2011
20090040815PHASE CHANGE MEMORY DEVICE USING A MULTIPLE LEVEL WRITE VOLTAGE - A phase change memory device using a multiple level write voltage is described. The phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A voltage selection adjusting unit is configured to select one of a plurality of multiple voltages in response to a voltage adjusting signal to output a driving voltage. A write driving unit is also configured to finely adjust the voltage level of the driving voltage in response to a voltage fine-adjusting signal to supply the driving voltage to the cell array unit.02-12-2009
20090040812PHASE CHANGE MEMORY DEVICE HAVING WRITE DRIVING CONTROL SIGNAL CORRESPONDING TO SET/RESET WRITE TIME - A phase change memory device includes a phase change resistance cell configured to sense a crystallization state that changes in response to a current so that data corresponding to the crystallization state can be stored in the phase change resistance cell. A write driving control signal generating unit outputs a write enable signal and a precharge enable signal in response to a write control signal that corresponds to a heating period and a quenching period of the write data. A write driving unit is configured to supply a driving voltage corresponding to the write data to the phase change resistance cell in response to the write enable signal and the precharge enable signal.02-12-2009
20100039857Write Circuit for Providing Distinctive Write Currents to a Chalcogenide Memory Cell - A write circuit for providing distinctive write currents to a chalcogenide memory cell is disclosed. The write circuit includes a current amplitude trim module, a current amplification and distribution module, and a write current shaping module. The current amplitude trim module provides a well-compensated current across a predetermined range of temperatures, voltage supplies and process corners intended for programming a chalcogenide memory cell. The current amplification and distribution module amplifies the well-compensated current in order to meet a programming requirement of the chalcogenide memory cell. The write current shaping module supplies an appropriate amount of write “0” current or write “1” current, based on the amplified current, to program the chalcogenide memory cell accordingly.02-18-2010
20090323408METHODS FOR DETERMINING RESISTANCE OF PHASE CHANGE MEMORY ELEMENTS - Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.12-31-2009
20110176358Reading Phase Change Memories - A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.07-21-2011
20100054031COLUMN DECODER FOR NON-VOLATILE MEMORY DEVICES, IN PARTICULAR OF THE PHASE-CHANGE TYPE - A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.03-04-2010
20090016099Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices - In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.01-15-2009
20090016100Multi-level phase change memory device and related methods - Provided are a phase change memory device and a reading method thereof. An example embodiment of a phase change memory device may include main cells programmed to have any one of a plurality of resistance states respectively corresponding to multi-bit data, reference cells programmed to have at least two respectively different resistance states among the resistance states each time the main cells are programmed, and a reference voltage generation circuit sensing the reference cells to generate reference voltages for identifying each of the resistance states.01-15-2009
20100039856PROGRAMMABLE PHASE-CHANGE MEMORY AND METHOD THEREFOR - A non-volatile memory is disclosed. A contiguous layer of phase change material (02-18-2010
20100054032ROW DECODER FOR NON-VOLATILE MEMORY DEVICES, IN PARTICULAR OF THE PHASE-CHANGE TYPE - A hierarchical row decoder is for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines and array bitlines. The row decoder has a global decoder that addresses first and a second global wordlines according to first address signals; and a local decoder, which is operatively coupled to the global decoder and addresses a respective array wordline according to the value the first and second global wordline and second address signals. The local decoder has a first circuit branch providing, when the first global wordline is addressed, a first current path between the array wordline and a first biasing source during a reading operation; and a second circuit branch providing, when the second global wordline is addressed, a second current path, distinct from the first current path, between the array wordline and a second biasing source during a programming operation.03-04-2010
20100054030Programmable resistance memory - A memory includes a programmable resistance array and unipolar MOS peripheral circuitry. The peripheral circuitry includes address decoding circuitry. Because unipolar MOS circuitry is employed, the number of mask steps and, concomitantly, the cost of the programmable resistance memory may be minimized.03-04-2010
20120230098PROGRAMMING OF PHASE-CHANGE MEMORY CELLS - A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V09-13-2012
20120230097DETERMINING CELL-STATE IN PHASE-CHANGE MEMORY - A method, an apparatus, and a device for determining the state of a phase-change memory cell. The method includes the steps of: biasing a cell with a time-varying read voltage (V09-13-2012
20120230096DEVICES AND METHODS TO PROGRAM A MEMORY CELL - Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.09-13-2012
20100061145Phase Change Memory Cell with MOSFET Driven Bipolar Access Device - Embodiments are directed to memory devices comprising a bipolar junction transistor having an emitter, a base and a collector; a first side of a resistance changing memory element coupled to the emitter of the bipolar junction transistor; and a MOSFET coupled to the base of the bipolar junction transistor.03-11-2010
20100061146Nonvolatile Memory Devices Including Variable Resistive Elements - A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.03-11-2010
20100135071MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME - A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.06-03-2010
20100135070Adjustable Write Pulse Generator Within a Chalcogenide Memory Device - An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell. The programmable ring oscillator generates a first set of continuous write “0” and write “1” pulse signals based on the well-compensated current. The frequency divider then divides the first set of continuous write “0” and write “1” pulse signals into a second set of continuous write “0” and write “1” pulse signals. The single pulse generator subsequently converts the second set of continuous write “0” and write “1” pulse signals into a single write “0” pulse signal or a single write “1” pulse signal when programming the chalcogenide memory cell.06-03-2010
20110075474PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND WRITE CONTROL METHOD FOR THE SAME - The disclosed phase change random access memory apparatus is configured to program a predetermined phase change memory cell in the phase change memory apparatus in response to a plurality of write instructions applied at independent points of time.03-31-2011
20090027953PHASE CHANGE MEMORY DEVICE - A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.01-29-2009
20090213645Method and apparatus for accessing a multi-mode programmable resistance memory - A memory is configurable among a plurality of operational modes and types of interfaces. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix. Individual operational modes may be matched to individual interfaces, operated one at a time or in parallel.08-27-2009
20090213647Phase-change random access memory capable of reducing word line resistance - A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.08-27-2009
20090213646Phase-change random access memories capable of suppressing coupling noise during read-while-write operation - A semiconductor memory device includes at least one write global bit line connected to a plurality of local bit lines and at least one read global bit line connected to the local bit lines. The phase-change memory device having the write global bit line and the read global bit line suppress coupling noise generated during a read-while-write operation.08-27-2009
20090213644Method and apparatus for accessing a multi-mode programmable resistance memory - A memory is configurable among a plurality of operational modes. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix.08-27-2009
20090213643Integrated Circuit and Method of Improved Determining a Memory State of a Memory Cell - According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first potential. The method further includes setting the second electrode to a second potential being different from the first potential, thereby generating a memory state sensing current flowing through the resistivity changing memory cell; controlling the strength of the second potential in dependence on the strength of the memory state sensing current such that the strength of the memory state sensing current is kept constant.08-27-2009
20110075475SET ALGORITHM FOR PHASE CHANGE MEMORY CELL - Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.03-31-2011
20120134204CONCENTRIC PHASE CHANGE MEMORY ELEMENT - The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.05-31-2012
20120134202VERIFY OR READ PULSE FOR PHASE CHANGE MEMORY AND SWITCH - Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices.05-31-2012
20110069540Method of a phase-change memory programming - A method of programming a phase-change memory (PCM) device to the high resistance reset state by means of pressure-induced amorphization. A train of few short bipolar current pulses is applied to the PCM device in order to stress phase-change alloy (PCA) under high pressure, and current in each pulse is almost equal to set current. An atomic structure of phase-change alloy is easily deformable by external pressure due to weak chemical bonds. Some materials mechanically contacted PCA in PCM have lower coefficients of thermal expansion and compressibility as well as higher coefficient of hardness than the corresponding coefficients of the PCA.03-24-2011
20110069538MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE - A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.03-24-2011
20110069539PROGRAMMING MULTI-LEVEL PHASE CHANGE MEMORY CELLS - A method and a feedback controller for programming at least one multi-level phase-change memory cell with a programming signal. The method and feedback controller include a sequence of write pulses applied to the multi-level phase change memory cell, wherein the feedback controller adjusts in real time at least one parameter of each write pulse as a function of a determined resistance error of the phase-change memory cell with respect to a desired reference resistance level.03-24-2011
20110058411PHASE CHANGE MEMORY SYSTEM HAVING WRITE DRIVER - A phase change memory system capable of gradually reducing current at the time of writing set data by using a small number of control circuits while occupying a small dimension is disclosed. The phase change memory system includes a memory cell array including a plurality of memory cells, each including a phase change material which is changed into a set or reset state depending on the amount of current, and a write driver supplying current corresponding to a set or reset state to a selected memory cell of the memory cell array. The write driver includes a slow quenching unit including an analog circuit supplying current slowly decreased in the memory cell array.03-10-2011
20110149644VOLTAGE CONTROL CIRCUIT FOR PHASE CHANGE MEMORY - The present invention relates to a voltage control circuit, semiconductor memory device, and method of controlling a voltage in a phase-change memory, wherein the voltage control circuit generates a controlled voltage which can be above the logic supply voltage. This voltage can limit the bit line voltage in a phase-change memory to allow the use of smaller transistors in the memory cells and in the program current part of the circuit. This results in smaller memory cells and modules.06-23-2011
20100309715STABLE CURRENT SUPPLY CIRCUIT IRRESPECTIVE OF PVT VARIATIONS AND SEMICONDUCTOR HAVING SAME - A current supply circuit comprises a reference voltage generator generating a reference voltage that varies with temperature, a current circuit generating a constant reference current irrespective of the temperature based on the reference voltage, and a current source generating a mirror current by mirroring a base current as a replica current of the reference current.12-09-2010
20100302840PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS FOR CONTROLLING DATA TRANSMISSION - A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat.12-02-2010
20100265763Memory Device Including an Electrode Having an Outer Portion With Greater Resistivity - A memory cell includes a first electrode having a first region and a second region, a second electrode and a phase change material. The phase change material is interposed between the first electrode and the second electrode with the first region of the first electrode arranged closer to the phase change material than the second region. The first region of the first electrode includes an inner portion laterally surrounded by an outer portion. The outer portion has a greater resistivity than the inner portion. The second region of the first electrode has the same resistivity as the inner portion of the first region.10-21-2010
20100302841PHASE CHANGE MEMORY APPARATUS AND TEST CIRCUIT THEREFOR - A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal.12-02-2010
20100118601PHASE CHANGE RANDOM ACCESS MEMORY DEVICE - In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.05-13-2010
20100254184SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes a control circuit that performs control of reading data from and writing data into each memory cell. The control circuit includes a flip-flop circuit that stores the data read from the memory cell and stores the data to be written into the memory cell and a dynamic type holding circuit connected to the flip-flop circuit through a switch. The dynamic-type holding circuit temporarily stores the data read from the memory cell. When the data read from the memory cell and then held in the holding circuit is different from the data in the flip-flop circuit to be written, supplied from an outside at a time of writing into the memory cell, control is performed so that the data in the flip-flop circuit is written into the memory cell.10-07-2010
20080316805Electronic Circuit With a Memory Matrix - An electronic circuit comprises a memory matrix (12-25-2008
20100097851METHOD FOR PROGRAMMING A MULTILEVEL PHASE CHANGE MEMORY DEVICE - A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.04-22-2010
20090296458RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF WRITING DATA - A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current12-03-2009
20090251954VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.10-08-2009
20080247227SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA10-09-2008
20080247226Memory devices having electrodes comprising nanowires, systems including same and methods of forming same - Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.10-09-2008
20080247225Variable resistance memory with lattice array using enclosing transistors - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.10-09-2008
20080247224Phase Change Memory Bridge Cell with Diode Isolation Device - Memory cells are described along with arrays and methods for manufacturing. An embodiment of a memory cell as described herein includes a second doped semiconductor region on a first doped semiconductor region and defining a pn junction therebetween. A first electrode on the second doped semiconductor region. An insulating member between the first electrode and a second electrode, the insulating member having a thickness between the first and second electrodes. A bridge of memory material across the insulating member, the bridge having a bottom surface and contacting the first and second electrodes on the bottom surface, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.10-09-2008
20080285333Electric Device Comprising Phase Change Material - The electric device (11-20-2008
20080285334LOCAL BANK WRITE BUFFERS FOR ACCELERATING A PHASE-CHANGE MEMORY - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data. The very long write-1 time may require wait states. To eliminate wait states for sequential accesses, the PCM cells are divided into 16 banks. Each bank has its own bank write latch that stores data locally at the bank while the bank is being written. Data lines to the banks are freed up to transfer data to other banks once the data is written into the local bank write latch, allowing the long set-current pulse to be applied locally to slowly grow crystals in the alloy resistors. External host data are buffered and applied to the data lines by an array data mux.11-20-2008
20080285336SEMICONDUCTOR DEVICE - To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.11-20-2008
20080285335PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES USING EXTERNALLY HEATED PHASE CHANGE MATERIAL - A programmable phase change material (PCM) structure includes a heater element formed at a transistor gate level of a semiconductor device, the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes, the heater element configured to receive programming current passed therethrough, a layer of phase change material disposed on top of a portion of the thin wire structure, and sensing circuitry configured to sense the resistance of the phase change material.11-20-2008
20080273378MULTI-LEVEL RESISTIVE MEMORY CELL USING DIFFERENT CRYSTALLIZATION SPEEDS - An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds.11-06-2008
20090052233SEMICONDUCTOR MEMORY DEVICE AND WRITING CONTROL METHOD THEREOF - A semiconductor memory device includes: a plurality of write control circuits; a plurality of memory cells grouped in the write control circuits; a plurality of write drivers that write data to a corresponding memory cell when the write control circuit is activated; and a main control circuit that causes the write control circuits to become active in response to presence of a data writing request to the memory cells belonging to a predetermined group and subsequent absence of the data writing request to the memory cells belonging to the same group within a predetermined period.02-26-2009
20120170359Phase Change Memory With Fast Write Characteristics - A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.07-05-2012
20100309717NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.12-09-2010
20080205127PHASE CHANGE STORAGE CELLS FOR MEMORY DEVICES - Storage cells for a semiconductor device can include a first layer of phase change material on a substrate and a second layer of phase change material being in contact with the first layer, the second layer of phase change material having a higher resistance than the first layer.08-28-2008
20080285332Bit-Alterable, Non-Volatile Memory Management - Methods and apparatuses for storage of data in bit-alterable, non-volatile memories. In some embodiments, an array of memory locations implemented as bit-alterable, non-volatile memory configured as a plurality of blocks of memory locations; and control circuitry coupled with the array of memory locations to cause a block of data to be stored in the array of memory spanning a boundary between a first block of memory locations and a second block of memory locations. One or more processors access system data during initialization of an electronic system by retrieving data from a pre-selected location in a bit-alterable, non-volatile memory without scanning multiple memory locations to locate the system data.11-20-2008
20100284213Method of cross-point memory programming and related devices - A reverse recovery current of a diode is used for programming a cross-point memory. Programming of a crossbar memory device, comprising a diode with preferably short charge carriers lifetime and a storage element by keeping the device at one polarity for a period of time and then switching it from first polarity to second polarity (e.g., forward to reverse polarity of the diode). Programming occurs due to diode's reverse recovery current. The value and duration of the recovery current pulse are selected to program the storage element into one of plurality of electrically distinguish states by variation of the level of current flowing through the device in the first polarity of applied bias voltage, by variation of the speed for changing the bias voltage from first polarity to second polarity, and by steady state value of the second polarity voltage applied to the device in one or more embodiments.11-11-2010
20100284214ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.11-11-2010
20100284212METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE CELLS USING ADAPTIVE RESET PULSES - A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity.11-11-2010
20100284211Multilevel Nonvolatile Memory via Dual Polarity Programming - A programming scheme and method of programming a non-volatile memory device for multilevel operation. The scheme includes defining two or more memory states, where at least one of the memory states is programmed with a positive polarity electrical pulse and at least one of the memory states is programmed with a negative polarity electrical pulse. The method includes programming with two or more pulses, where at least one pulse has positive polarity and one pulse has negative polarity. The non-volatile memory material may be a phase-change material and the two or more memory states may be distinguishable on the basis of electrical resistance.11-11-2010
20110085375METHODS FOR DETERMINING RESISTANCE OF PHASE CHANGE MEMORY ELEMENTS - Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.04-14-2011
20100328997PHASE-CHANGE MEMORY ELEMENT, PHASE-CHANGE MEMORY CELL, VACUUM PROCESSING APPARATUS, AND PHASE-CHANGE MEMORY ELEMENT MANUFACTURING METHOD - A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when supplied with an electric current via the perovskite layer.12-30-2010
20100328995METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY - Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.12-30-2010
20100328994PHASE CHANGE MEMORY WITH FINITE ANNULAR CONDUCTIVE PATH - A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.12-30-2010
20110080778PHASE CHANGE MEMORY DEVICE - A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.04-07-2011
20110080777Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.04-07-2011
20110080775NONVOLATILE MEMORY DEVICE, STORAGE SYSTEM HAVING THE SAME, AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.04-07-2011
20110080774SEMICONDUCTOR DEVICE - Objects of the present invention are to improve the manufacturing yield of semiconductor devices, reduce manufacturing cost of the semiconductor device, and reduce the circuit area of an integrated circuit included in the semiconductor device. A memory layer of a memory element and a resistive layer of a resistor included in the semiconductor device are formed of the same material. Therefore, the memory layer and the resistive layer are formed in the same step, whereby the number of manufacturing steps of the semiconductor device can be reduced. As a result, the manufacturing yield of the semiconductor devices can be improved and the manufacturing cost can be reduced. In addition, the semiconductor device includes a resistor having a resistive component which has high resistance value. Consequently, the area of the integrated circuit included in the semiconductor device can be reduced.04-07-2011
20110255333PHASE CHANGE MEMORY DEVICE WITH IMPROVED PERFORMANCE THAT MINIMIZES CELL DEGRADATION - A phase change memory device having an improved performance that minimizes cell degradation is presented. The phase change memory device includes: a cell array, a sense amplifier, a write driving unit, and a reference level selecting unit. The cell array has a phase change resistor is configured to read/write data. The sense amplifier is configured to compare a reference voltage with a sensing voltage received from the cell array. The write driving unit is configured to supply a driving voltage corresponding to write data to the cell array. The reference level selecting unit is configured to select a read reference voltage in a read mode so as to output the reference voltage, and to select a reference voltage corresponding to input data in a write verifying mode so as to output the reference voltage.10-20-2011
20120147668Diode and Memory Device Having a Diode - A diode and a memory device having a diode are provided. The diode includes a semiconductor layer and phase change material layer. The semiconductor layer and the phase change material layer have different energy bandgaps and different carrier concentrations such that an isotype heterojunction is formed at a boundary interface between the semiconductor layer and the phase change material layer.06-14-2012
20120147666PHASE CHANGE MATERIAL CELL WITH STRESS INDUCER LINER - An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.06-14-2012
20100149861PHASE CHANGE MEMORY DEVICE - A phase change memory device includes a plurality of programming current driving blocks each of which is configured to provide a corresponding phase change memory cell with a programming current corresponding to input data and a programming current adjusting block commonly connected to the plurality of programming current driving blocks and configured to generate a control voltage to adjust the programming current.06-17-2010
20110134686SEMICONDUCTOR DEVICES INCLUDING SENSE AMPLIFIER CONNECTED TO WORD LINE - A semiconductor device includes a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, respectively, and a sense amplifier block for sensing and amplifying a signal of a word line among the plurality of word lines.06-09-2011
20110134685Energy-efficient set write of phase change memory with switch - Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed.06-09-2011
20110075473CIRCUIT AND METHOD FOR GENERATING REFERENCE VOLTAGE, PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND READ METHOD USING THE SAME - A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference cell sense amplifier reads out the data stored in the reference cell on the basis of a predetermined reference voltage. A voltage compensation unit outputs a compensation reference voltage by controlling the reference voltage in accordance with the output value of the sense amplifier.03-31-2011
20110096595SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - Disclosed is a resistance change type nonvolatile memory that has an insulation film structure, is advantageous for the implementation of high integration, and achieves a stable switching characteristic, and a manufacturing method therefor. The memory includes at least an MIM (Metal/Insulator/Metal) structure including an insulation film (04-28-2011
20110096594MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION - Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.04-28-2011
20100214832PHASE-CHANGE RANDOM ACCESS MEMORY - A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.08-26-2010
20100214831Memory device, memory system having the same, and programming method of a memory cell - A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data.08-26-2010
20100214830MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION - Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.08-26-2010
20100214827Integrated Circuit with Memory Cells Comprising a Programmable Resistor and Method for Addressing Memory Cells Comprising a Programmable Resistor - A module comprises a bus invert encoder (08-26-2010
20100214833SEMICONDUCTOR DEVICE - For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.08-26-2010
20100214829MEMORY PROGRAMMING - Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.08-26-2010
20100165714METHOD OF STORING AN INDICATION OF WHETHER A MEMORY LOCATION IN PHASE CHANGE MEMORY NEEDS PROGRAMMING - A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed.07-01-2010
20100165722Phase Change Memory - A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.07-01-2010
20100165719PHASE CHANGE MEMORY DEVICE - A phase change memory device with memory cells (07-01-2010
20100165723PHASE CHANGE MEMORY - A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.07-01-2010
20100165716NONVOLATILE MEMORY WITH OVONIC THRESHOLD SWITCHES - A memory device including a plurality of memory cells being arranged in a matrix having a plurality of rows and a plurality of columns. Each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The memory device further including a plurality of row lines each one for selecting the memory cells of a corresponding row and a plurality of column lines each one for selecting the memory cells of a corresponding column. The memory device further includes for each line among the row lines and/or the column lines a respective set of local lines each one for selecting a group of memory cells of the corresponding line, and a respective set of selection elements each one for selecting a corresponding local line of the set in response to the selection of the respective line.07-01-2010
20100165721INTERNAL VOLTAGE GENERATING CIRCUIT OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD THEREOF - An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.07-01-2010
20100165718APPARATUS AND METHOD FOR SENSING MULTI-LEVEL CELL DATA - A multi-level sensing apparatus of the non-volatile memory includes a first sense amplifier configured to compare a first reference voltage with a read data of a bit line and amplify a comparison result to generate a first output; a reference voltage selector configured to select one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output; a second sense amplifier configured to compare the fourth reference voltage with the read data of the bit line and amplify a comparison result to generate a second output; and a decoder configured to decode the first and second outputs to output a sensing data.07-01-2010
20100165712METHOD FOR LOW-STRESS MULTILEVEL READING OF PHASE CHANGE MEMORY CELLS AND MULTILEVEL PHASE CHANGE MEMORY - According to a method for multilevel reading of a phase change memory cell a bit line (07-01-2010
20100165715PROTECTION REGISTER FOR A PHASE-CHANGE MEMORY - A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array.07-01-2010
20100165717WRITE DRIVER CIRCUIT OF PRAM - A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver circuit of the PRAM includes a normal driver configured to provide a write current for set or reset of a phase change cell connected to a bit line, a test driver configured to share a node with the normal driver, and provide an additional current for a test to the write current through the shared node in response to a test mode control signal, and a mode control unit configured to control an operation according to the test mode by providing the test mode control signal to the test driver.07-01-2010
20100165711SET ALGORITHM FOR PHASE CHANGE MEMORY CELL - Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.07-01-2010
20100067289SEMICONDUCTOR DEVICE - A semiconductor device includes first and second phase-change memory elements (GST03-18-2010
20100067285NOVEL SENSING CIRCUIT FOR PCRAM APPLICATIONS - A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias different from the first bias. The method includes determining a data value stored in the memory cell based on a difference between the first and second responses and a predetermined reference.03-18-2010
20100067288MEMORY DEVICE STRUCTURES INCLUDING PHASE-CHANGE STORAGE CELLS - A conductive write line of a memory device includes a resistive heating portion for setting and resetting a phase-change material (PCM) storage cell of the device. A dielectric interface extends between the resistive heating portion of the write line and a side of the storage cell, and provides electrical insulation while allowing for thermal coupling between the resistive heating portion and the storage cell. A width of the resistive heating portion of the write line may be less than a width of the storage cell and/or may be less than a width of adjacent portions of the write line, between which the resistive heating portion extends. The side of the storage cell may define a channel of the storage cell through which the write line passes, such that the resistive heating portion is located within the channel.03-18-2010
20100067286MEMORY SENSING DEVICES, METHODS, AND SYSTEMS - The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents.03-18-2010
20100067287TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.03-18-2010
20100195378Phase Change Memory With Dual Word Lines and Source Lines and Method of Operating Same - A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.08-05-2010
20100195377SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF TESTING THE SAME - A semiconductor memory apparatus includes a sense amplifier coupled to a plurality of bit lines, a switching unit configured to cause the plurality of bit lines to be coupled to a first node in response to a switching signal, a mode selecting unit configured to selectively couple the first node to a pad or a ground terminal in response to a mode selection signal and a testing unit configured to supply current to the pad during a test mode.08-05-2010
20110188302METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE - A method of driving phase change memory device which reduces or prevents unwanted heat disturbances from interfering with memory states in adjacent memory cells is presented. The phase change memory cells are disposed at word and bit line intersections. The method includes collectively erasing all of the memory cells as a unit in the bit line into a reset state. The method then includes individually programming only selected memory cells of the memory cells into set states.08-04-2011
20110149643PHASE CHANGE MEMORY APPARATUS HAVING GLOBAL BIT LINE AND METHOD FOR DRIVING THE SAME - A phase change memory apparatus includes a global bit line and an internal power generation circuit. The global bit line is configured to integratedly control a plurality of bit lines. The internal power generation circuit is configured to supply an internal voltage while the global bit line is discharged and configured to control the internal voltage after the global bit line is discharged, when a deep power down mode signal is enabled.06-23-2011
20110149645MULTI-LEVEL PROGRAMMABLE PCRAM MEMORY - A series of phase change material layers sandwiched between a bottom electrode and a top electrode may have different phase change temperatures selected to provide a memory device having three or more discrete resistance levels, and thus three or more discrete logic levels. The non-volatile memory may form part of a logic device and/or a memory array device, as well as other devices and systems. The phase change material layers may be formed using physical deposition methods, chemical deposition methods, or using atomic layer deposition. Atomic layer deposition may reduce the overall device thermal exposure and provide improved layer thickness uniformity and sharp material boundaries at the interface of different phase change materials, thus providing improved resistance level accuracy.06-23-2011
20090175072PHASE-CHANGE RANDOM ACCESS MEMORY DEVICES AND RELATED METHODS OF OPERATION - A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed.07-09-2009
20110188303Phase change memory device generating program current and mehtod thereof - A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.08-04-2011
20100027328Multilevel Variable Resistance Memory Cell Utilizing Crystalline Programming States - A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values of the different states are stable with time and exhibit little or no drift. As a result, the programming scheme is particularly suited to multilevel memory applications. The crystalline programming states may be achieved by stabilizing crystalline phases that adopt different crystallographic structures or by stabilizing crystalline phases that include mixtures of two or more distinct crystallographic structures that vary in the relative proportions of the different crystallographic structures. The programming scheme incorporates at least two crystalline programming states and further includes at least a third programming state that may be a crystalline, amorphous or mixed crystalline-amorphous state.02-04-2010
20100027326Memory device, memory system having the same, and programming method of a memory cell - A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit.02-04-2010
20100027325INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD - An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.02-04-2010
20100027329Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.02-04-2010
20100027327Nonvolatile Memory Devices Having Variable-Resistance Memory Cells and Methods of Programming the Same - Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.02-04-2010
20100020595Accessing a Phase Change Memory - A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient charge for an ensuing access. When a memory cell is accessed, charge stored on the capacitor is discharged through the phase change memory, supplying a current to the phase change memory cell that is sufficient for the intended access operation and greater than that provided directly by the current source.01-28-2010
20100020593Vertical string phase change random access memory device - A phase change random access memory device is disclosed including a first electrode, a second electrode, a phase change material layer between the first and second electrode, a plurality of gate layers formed along the phase change material layer, an insulating film between the phase change material layer and the plurality of gate layers, and a plurality of interlayer insulating layers between the plurality of gate layers and between the first and second electrode and the plurality of gate layers, in which multiple bits of information may be stored in a single memory cell corresponding to the positions of the plurality of gate layers.01-28-2010
20110216583SEMICONDUCTOR DEVICE - A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.09-08-2011
20110216582INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a recording layer and a driving unit. The recording layer includes a first layer containing a first compound. The first compound includes a first positive ion element. The first positive ion element is made of a transition metal element and serves as a first positive ion. The second positive ion element serves as a second positive ion. The driving unit is configured to generate a phase change in the recording layer and to record information by at least one of application of a voltage and application of a current to the recording layer. The coordination number of the first positive ion element at a position of a second coordination of the second positive ion element is 80% or more and less than 100% of the coordination number when the first compound is assumed to be a perfect crystal.09-08-2011
20110051508MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY - A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode.03-03-2011
20110051507MAINTENANCE PROCESS TO ENHANCE MEMORY ENDURANCE - Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory.03-03-2011
20110051506FLEXIBLE MULTI-PULSE SET OPERATION FOR PHASE-CHANGE MEMORIES - Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the plurality of memory cells. The plurality of sets of program pulse tuning instructions may be different from one another in at least one respect.03-03-2011
20110051505REDUCING PROGRAMMING TIME OF A MEMORY CELL - The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.03-03-2011
20110051504CREATING SHORT PROGRAM PULSES IN ASYMMETRIC MEMORY ARRAYS - The present invention provides methods and apparatus for adjusting voltages of bit and word lines to create short programming pulses to program a memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, switching the first line from the first voltage to a second voltage, and switching the first line from the second voltage to the first voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results. The switching operations together may create a first pulse.03-03-2011
20080212363METHOD FOR PROGRAMMING PHASE-CHANGE MEMORY AND METHOD FOR READING DATE FROM THE SAME - When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat.09-04-2008
20090285015PHASE-CHANGE MEMORY DEVICE INCLUDING BIASING CIRCUIT - A memory cell device is provided which includes a substrate, a plurality of unit memory cells connected between a word line and respective bit lines, where each memory cell including a resistance variable element, such a phase-change element, and a diode connected in series between the word line and the respective bit line, and a biasing circuit which applies a biasing voltage to the substrate to decrease a current flow in the word line.11-19-2009
20100165724WORD-LINE DRIVER INCLUDING PULL-UP RESISTOR AND PULL-DOWN TRANSISTOR - Embodiments include but are not limited to apparatuses and systems including a plurality of memory cells, each memory cell including a selector and a storage element coupled to the selector. A word-line may be coupled to the memory cells and may have a word-line driver including a pull-up resistor coupled to the selectors for the memory cells to access respective storage elements of the memory cells. Other embodiments may be described and claimed.07-01-2010
20100054029CONCENTRIC PHASE CHANGE MEMORY ELEMENT - The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.03-04-2010
20120307555PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure includes forming an insulator material on a first conductive element and on a dielectric material of a phase change memory cell, forming a heater self-aligned with the first conductive element, forming a phase change material on the heater and at least a portion of the insulator material formed on the dielectric material, and forming a second conductive element of the phase change memory cell on the phase change material.12-06-2012
20120307554DETERMINING CELL-STATE IN PHASE-CHANGE MEMORY - A method, an apparatus, and a device for determining the state of a phase-change memory cell. The method includes the steps of: biasing a cell with a time-varying read voltage (V12-06-2012
20120307553Circuitry for Reading Phase Change Memory Cells Having a Clamping Circuit - A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.12-06-2012
20120307552Process of producing a resistivity-change memory cell intended to function in a high-temperature environment - A process of producing a resistivity-change memory cell is described. The process includes a deposition at room temperature, in amorphous state, of a layer of a nitrogen (N)-doped alloy of germanium (Ge) and tellurium (Te) to constitute the resistivity-change material of the memory cell. An annealing is then performed such as to limit the type of re-crystallisation by nucleation starting from the amorphous state of the phase-change material. The material used and the process permit the data retention at high temperature to be significantly improved.12-06-2012
20090154228Random Access Memory Employing Read Before Write for Resistance Stabilization - An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has that data state, such matching data states are identified and writing to those bits is precluded during the write command. In one embodiment, both the incoming data to be written to a bit and the data currently present at that bit address are latched. These latched data are then compared (e.g., with an XOR gate) to determine which bits have a matching data state. The results of this comparison are used as an enable signal to the write (column) driver in the PCRAM memory array, with the effect that only data bits having different data state are written, while data bits having a matching data state are not needlessly re-written. Because matching data states are ignored, reliability problems associated with such redundant writing are alleviated, and power is saved.06-18-2009
20110134687RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF WRITING DATA - A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current06-09-2011
20110305075Programmable Resistance Memory - A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.12-15-2011
20110305076PHASE CHANGE MEMORY DEVICE - A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.12-15-2011
20110305074SELF-ALIGNED BIT LINE UNDER WORD LINE MEMORY ARRAY - A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.12-15-2011
20110141801USE OF SYMMETRIC RESISTIVE MEMORY MATERIAL AS A DIODE TO DRIVE SYMMETRIC OR ASYMMETRIC RESISTIVE MEMORY - A crosspoint array is made up of a plurality of bitlines and wordlines and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline, and each crossbar element comprising at least a phase change material used as a rectifier in series with a solid electrolyte used as an asymmetric resistive memory element. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the phase change material in the crossbar elements from an OFF state to an ON state; a second set of voltages to read or program the solid electrolyte, and a third set of voltages to transition the phase change material from an ON state to an OFF state.06-16-2011
20110080780Method for Programming a Multilevel Phase Change Memory Device - A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.04-07-2011
20110110150SEMICONDUCTOR DEVICE - A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.05-12-2011
20120039117DESTRUCTION OF DATA STORED IN PHASE CHANGE MEMORY - A mechanism and means by which the data information pattern stored in Phase Change Memory PCM (02-16-2012
20120039116PHASE CHANGE MEMORY DEVICE COMPRISING BISMUTH-TELLURIUM NANOWIRES - The present invention relates to a phase change memory device comprising bismuth-tellurium nanowires. More specifically, the bismuth-tellurium nanowires having PRAM characteristics may be prepared by using a porous nano template without any high temperature process and said nanowires may be used in the phase change memory device by using their phase change characteristics to identify memory characteristics.02-16-2012
20120147667VARIABLE RESISTANCE MEMORY PROGRAMMING - Some embodiments include a device having memory elements and methods of storing information into the memory elements. Such methods can include increasing a temperature of a portion of a memory element for a time interval during an operation to change a resistance state of the memory element. After the time interval, the methods can include decreasing the temperature of the portion of the memory element. Decreasing the temperature can be performed using a signal having a first negative slope and a second negative slope. Other embodiments are described.06-14-2012
20100165726DISCHARGE PHASE CHANGE MATERIAL MEMORY - An information storage array includes a programmable material at a storage location and a capacitor set. A switching network charges the capacitor set to a first voltage and discharges the capacitor set at a second voltage. The second voltage is greater than the first voltage and it or a waveform derived therefrom is applied to the storage location to thereby change a state of the programmable material.07-01-2010
20100097850APPARATUS AND SYSTEMS USING PHASE CHANGE MEMORIES - Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.04-22-2010
20100097849VARIABLE RESISTANCE MEMORY DEVICE PERFORMING PROGRAM AND VERIFICATION OPERATION - A variable resistance memory device includes; a memory cell array comprising a plurality of memory cells, a pulse shifter shifting a plurality of program pulses to generate a plurality of shifted program pulses, a write and verification driver receiving the plurality of shifted program pulses to provide a program current that varies with the plurality of shifted program pulses to the plurality of memory cells, and control logic providing the plurality of program pulses to the pulse shifter and the write and verification driver during a program/verification operation, such at least two write data bits are programmed to the memory cell array in parallel during the program/verification operation.04-22-2010
20120120722PIPELINE ARCHITECTURE FOR SCALABLE PERFORMANCE ON MEMORY - An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.05-17-2012
20110063904PHASE CHANGE MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD - A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells. A number of applications for the at least one verification pulse and the intervals between respective applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.03-17-2011
20110063903NONVOLATILE MEMORY DEVICES, SYSTEMS HAVING THE SAME, AND WRITE CURRENT CONTROL METHODS THEREOF - Provided is a nonvolatile memory device, a memory system having the same, and a write current control method thereof. The memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device has a plurality of write modes. The memory controller includes a sensor configured to sense environment information of the memory system. The memory controller is configured to select one of the write modes according to the sensed environment information and control the nonvolatile memory device according to the selected write mode. Accordingly, the nonvolatile memory device provides a write current for appropriate current consumption in a write operation.03-17-2011
201100639022T2R-1T1R MIX MODE PHASE CHANGE MEMORY ARRAY - A memory device as described herein includes an array of programmable resistance memory cells. The memory device further includes sense circuitry having a dual memory cell (2T-2R) mode to read a data value stored in a pair of memory cells in the array based on a difference in resistance between a first memory cell in the pair and a second memory cell in the pair. The sense circuitry also has a single memory cell (1T-1R) mode to read a data value in a particular memory cell in the array based on the resistance of the particular memory cell.03-17-2011
20120155163REDUCING PROGRAMMING TIME OF A MEMORY CELL - The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.06-21-2012
20120155162SEMICONDUCTOR STORAGE APPARATUS OR SEMICONDUCTOR MEMORY MODULE - A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.06-21-2012
20120155161THREE-TERMINAL OVONIC THRESHOLD SWITCH AS A CURRENT DRIVER IN A PHASE CHANGE MEMORY - A three-terminal Ovonic Threshold Switch (OTS) is used to provide current to a Phase Change Memory Switch (PCMS) cross point array. The current is started by sending a small current into the second terminal of the three-terminal OTS allowing a larger current to flow from the first terminal to the third terminal of the three-terminal OTS. A method of making the three-terminal OTS is also presented.06-21-2012
20110317480PHASE CHANGE MEMORY CODING - An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.12-29-2011
20110317484RESISTIVE MEMORY DEVICES USING ASSYMETRICAL BITLINE CHARGING AND DISCHARGING - A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.12-29-2011
20110317483Data Programming Circuits and Memory Programming Methods - A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.12-29-2011
20110317482PHASE CHANGE MEMORY WORD LINE DRIVER - A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.12-29-2011
20120044753PROGRAMMABLY REVERSIBLE RESISTIVE DEVICE CELLS USING CMOS LOGIC PROCESSES - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.02-23-2012
20120002465METHODS, STRUCTURES, AND DEVICES FOR REDUCING OPERATIONAL ENERGY IN PHASE CHANGE MEMORY - Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.01-05-2012
20120002464SEMICONDUCTOR DEVICE EQUIPPED WITH A PLURALITY OF MEMORY BANKS AND TEST METHOD OF THE SEMICONDUCTOR DEVICE - A write circuit writes a first data signal that is an input data signal that indicates a first logic level to each memory bank in sequence and writes a second data signal that is an input data signal that indicates a second logic level to each memory bank simultaneously.01-05-2012
20120057401PHASE CHANGE MEMORY CYCLE TIMER AND METHOD - A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.03-08-2012
20120014177SEMICONDUCTOR SWITCHING DEVICE - A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided that has a collector, a base and an emitter. The body region of the MOS transistor serves as the base of the bipolar transistor and the drain region of the MOS transistor serves as the collector of the bipolar transistor. Activation of the MOS transistor causes the bipolar transistor to turn on. The MOS transistor is activated to turn on the bipolar transistor and the bipolar transistor delivers current to the source region.01-19-2012
20100002499PHASE CHANGE MEMORY PROGRAMMING METHOD WITHOUT RESET OVER-WRITE - A method for programming a phase change memory device that avoids RESET overwrite. The method partially comprised of applying a reset write current pulse through the phase change memory element such that the reset write current pulse produces a voltage drop across the phase change memory element less than a reset threshold voltage and greater than a set threshold voltage. The reset write current pulse writing a RESET state to the phase change memory cell. The method additionally comprised of applying a set write current pulse through the phase change memory element such that the set write current pulse produces a voltage drop across the phase change memory element that is equal to or greater than the reset threshold voltage. The set write current pulse writing a SET state to the phase change memory cell.01-07-2010
20120113710NON-VOLATILE MEMORY ARRAY AND EVICE USING ERASE MARKERS - A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to the data unit and indicating whether the data unit is in an erased state or a not-erased state.05-10-2012
20120026787SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A transistor includes first and second control gates, and a storage gate. The storage gate is made to be a conductor, supplied with a specific potential, and then made to be an insulator, thereby holding the potential. Data is written by making the storage gate a conductor, supplying a potential of data to be stored, and making the storage gate an insulator. Data is read by making the storage gate an insulator, supplying a potential to a read signal line connected to one of a source and a drain of the transistor, supplying a potential for reading data to the first control gate, and then detecting a potential of a bit line connected to the other of the source and the drain.02-02-2012
20120026786WRITE OPERATION FOR PHASE CHANGE MEMORY - Embodiments disclosed herein may relate to controlling a discharge of a capacitive element coupled to a phase change memory cell to produce a specified state in the phase change memory cell.02-02-2012
20120057402WRITE DRIVER, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME AND PROGRAMMING METHOD - A write driver, a semiconductor memory apparatus using the same, and a programming method. The write driver includes a reset control unit configured to output a first current pulse for a first period of time and subsequently output a second current pulse having a higher current level than the first current pulse for a second period of time to a memory cell array in response to a reset program command.03-08-2012
20090135645Data Programming Circuits And Memory Programming Methods - A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.05-28-2009
20110080776SEMICONDUCTOR MEMORY DEVICE HAVING DIODE CELL STRUCTURE - A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.04-07-2011
20090141549Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith - At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.06-04-2009
20100172174SEMICONDUCTOR DEVICE HAVING ARCHITECTURE FOR REDUCING AREA AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.07-08-2010
20110103142SEMICONDUCTOR DEVICE - In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.05-05-2011
20110103140DATA READ CIRCUIT FOR PHASE CHANGE MEMORY DEVICE AND APPARATUSES INCLUDING THE SAME - The data read circuit includes a variable current generation circuit and a data sensing circuit. The variable current generation circuit is configured to generate a variable current that varies in response to an external temperature. The data sensing circuit is configured to sense and amplify data on a bit line connected to a non-volatile memory cell according to the variable current and to configured to output the sensed and amplified data. The data sensing circuit controls a margin for sensing the data according to the variable current.05-05-2011
20110103139Double-pulse write for phase change memory - The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower current than the first step; verifying a parameter of the phase change material wherein if the parameter is higher than a target for a SET state, then repeating the writing with the first step, the writing with the second step, and the verifying until the parameter is lower than the target wherein a current for the first step is decreased by a decrement with each iteration without becoming lower than a current for the second step.05-05-2011
20110103141Reading a Phase Change Memory - A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.05-05-2011
20100091558Dielectric-Sandwiched Pillar Memory Device - A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element.04-15-2010
20120120723Dynamic Pulse Operation for Phase Change Memory - The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.05-17-2012
20120250402SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.10-04-2012
20120120724PHASE CHANGE MEMORY DEVICE - A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.05-17-2012
20110110149STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING - A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.05-12-2011
20100290278SEMICONDUCTOR MEMORY DEVICE REWRITING DATA AFTER EXECUTION OF MULTIPLE READ OPERATIONS - Provided is a semiconductor memory device including a memory cell; a writing driver providing a program current to the memory cell to write data in the memory cell; a sense amplifier processing a read operation reading data written in the memory cell; and a controller providing a rewriting signal for rewriting data read from the sense amplifier in the memory cell to the writing driver after the sense amplifier repeatedly applies a read operation more than a predetermined number of times.11-18-2010
20100290277RESISTIVE MEMORY CELL ACCESSED USING TWO BIT LINES - An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.11-18-2010
20100290276Semiconductor memory using resistance material - A semiconductor memory includes a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each bit line connected to a corresponding column of the memory cells; a column selection circuit configured to select at least one bit line in response to a column select signal; and a read circuit configured to precharge the selected bit line in response to a precharge signal, to apply a read bias to the precharged bit line in response to a read bias provision signal, and to read data from the memory cells. A resistance level of each of the memory cells varies according to data stored therein, and the read circuit reads data from a first memory cell of the plurality of memory cells in response to the precharge signal having a first pulse width and reads data from a second memory cell of the plurality of memory cells in response to the precharge signal having a second pulse width.11-18-2010
20100290274NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.11-18-2010
20100290273Nonvolatile Memory Device - A nonvolatile memory device includes a plurality of programming current driving units configured to supply memory cells with a programming current corresponding to a write data, a common programming current controlling unit configured to generate a common control voltage for controlling the programming current and a switching unit configured to transfer the common control voltage to the programming current driving unit selected among the plurality of programming current driving units by a plurality of driving selection signals.11-18-2010
20100290272Phase Change Memory Device - A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.11-18-2010
20100290271ONE-TRANSISTOR, ONE-RESISTOR, ONE-CAPACITOR PHASE CHANGE MEMORY - Memory devices and methods for operating such devices are described herein. A memory cell as described herein comprises a transistor electrically coupled to first and second access lines. A programmable resistance memory element is arranged along a current path between the first and second access lines. A capacitor is electrically coupled to the current path between the first and second access lines.11-18-2010
20100246247Phase-change random access memories, memory devices, memory systems, methods of operating and methods of manufacturing the same - A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.09-30-2010
20100246248MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE - A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.09-30-2010
20100246246Memory device, memory system having the same, and programming method of a memory cell - A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell.09-30-2010
20100246249CHARGE CARRIER STREAM GENERATING ELECTRONIC DEVICE AND METHOD - The present invention discloses an electronic device comprising a generator for generating a stream (09-30-2010
20120127790ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES - Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.05-24-2012
20120127789STORAGE NODE, PHASE CHANGE MEMORY DEVICE AND METHODS OF OPERATING AND FABRICATING THE SAME - A storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper electrode may be composed of thermoelectric materials having a melting point higher than that of the phase change layer, and having different conductivity types. An upper surface of the lower electrode may have a recessed shape, and a lower electrode contact layer may be provided between the lower electrode and the phase change layer.05-24-2012
20100149860PHASE-CHANGE MEMORY DEVICE - A phase-change memory device performs a buffer program operation in response to a buffer program command sequence. The phase-change memory device includes a page buffer unit configured to store a plurality of input data corresponding to a word count value of a buffer program command sequence and selectively output the stored input data in response to a selection signal, and a page buffer control unit configured to generate the selection signal determined by counting a value representing the word count value.06-17-2010
20110182115METHOD FOR FABRICATING INDIUM (In)-ANTIMONY (Sb)-TELLURIUM (Te) NANOWIRES AND PHASE-CHANGE MEMORY DEVICE COMPRISING THE NANOWIRES - Disclosed herein is a method for manufacturing (In)—(Sb)—(Te) (IST) nanowires and a phase-change memory device comprising the nanowires. The method comprises providing a substrate and vapors of In, Sb and Te precursors in a chamber and allowing the vapors to react with each other on the substrate in the chamber at a temperature of 230-300° C. and a pressure of 7-15 Torr. With the method, IST nanowires can be fabricated cost-effectively.07-28-2011
20110182114SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A semiconductor memory device substantially prevents a faulty operation from being generated in a read operation, and increases the operation reliability. The semiconductor memory device includes a cell array configured to include a memory element having a different resistance value in response to data, a sense-amp configured to sense and amplify the data, a global bit line configured to couple the sense-amp to a cell array, and a discharge unit configured to discharge the global bit line prior to execution of a read operation.07-28-2011
20110182113SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device prevents a faulty operation of a program operation, and increases the reliability of operation. The semiconductor memory device includes a unit cell including a memory element configured to have a different resistance value in response to data, and a write driver configured to output a program current and voltage for programming the unit cell in response to a test signal.07-28-2011
20120314491SET PULSE FOR PHASE CHANGE MEMORY PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to a single pulse algorithm for programming a phase change memory.12-13-2012
20120314493PHASE CHANGE MEMORY AND METHOD FOR FABRICATING PHASE CHANGE MEMORY - A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.12-13-2012
20120212999Methods Of Forming Programmed Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.08-23-2012
20100067291METHOD FOR PROGRAMMING PHASE-CHANGE MEMORY AND METHOD FOR READING DATE FROM THE SAME - When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat.03-18-2010
20090021977Phase change material containing carbon, memory device including the phase change material, and method of operating the memory device - Provided are a phase change material containing carbon (C), a memory device including the phase change material, and a method of operating the memory device. The phase change material contains a main compound and an additive, wherein the main compound is In—Sb—Te and the additive includes carbon (C). A content a of the carbon (C) may be 0.005≦a≦0.30 atomic (at) %. The additive may further contain nitrogen (N), oxygen (O), boron (B), or a transition metal. The additive may include carbide instead of the carbon (C).01-22-2009
20120230099PHASE CHANGE MEMORY - A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.09-13-2012
20090059658MEMORY SYSTEM, MEMORY DEVICE AND APPARATUS INCLUDING WRITING DRIVER CIRCUIT FOR A VARIABLE RESISTIVE MEMORY - An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.03-05-2009
20090059657CMOS STORAGE DEVICES CONFIGURABLE IN HIGH PERFORMANCE MODE OR RADIATION TOLERANT MODE - A radiation tolerant circuit, structure of the circuit and method of autonomic radiation event device protection. The circuit includes a charge storage node connected to a resistor, the resistor comprising a material having an amorphous state and a crystalline state, the amorphous state having a higher resistance than the crystalline state, the material reversibly convertible between the amorphous state and the crystalline state by application of heat; an optional resistive heating element proximate to the resistor; and means for writing data to the charge storage node and means for reading data from the charge storage node.03-05-2009
20120170360SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is disclosed. The semiconductor memory device converts a sequentially-changing step voltage into a current so as to provide a write current, and minimizes the influence of a threshold voltage variation caused by fabrication deviation, such that it can be stably operated. The semiconductor memory device includes a current driver. The current driver includes a step voltage provider configured to provide a step control voltage sequentially changing in response to a pulse control signal, a control current provider configured to provide a control current in response to the step control voltage, and a write driver configured to provide a write current capable of writing data in a memory cell in response to the control current.07-05-2012
20120075926SEMICONDUCTOR DEVICE - A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.03-29-2012
20120075925PCRAM With Current Flowing Laterally Relative to Axis Defined By Electrodes - An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.03-29-2012
20120075924METHOD, APPARATUS AND SYSTEM TO DETERMINE ACCESS INFORMATION FOR A PHASE CHANGE MEMORY - Techniques for determining access information describing an accessing of a phase change memory (PCM) device. In an embodiment, an initial read time for a PCM cell is determined based on a final read time for the PCM cell, set threshold voltage information and a reset threshold voltage drift, wherein the final read time and the initial read time define a time window for reading the PCM cell. In another embodiment, a time window extension is determined based on a reset threshold voltage drift.03-29-2012
20120075923PHASE CHANGE MEMORY STATE DETERMINATION USING THRESHOLD EDGE DETECTION - Subject matter disclosed herein relates to techniques to read a memory cell that involve a threshold edge phenomenon of a reset state of phase change memory.03-29-2012
20100271868Phase change memory devices and memory systems including the same - A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a resistance level of a selected phase change memory cell. The clamping circuit controls an amount of clamping current flowing into a bit line connected with the selected phase change memory cell. The CCSGC provides the clamping control signal to the clamping circuit and adjusts a level of the clamping control signal.10-28-2010
20100271867Variable resistive memory device compensating bit line resistance - Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.10-28-2010
20100008133PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A method of writing data in a phase change memory includes; receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.01-14-2010
20100008132RESISTANCE MEMORY ELEMENT, PHASE CHANGE MEMORY ELEMENT, RESISTANCE RANDOM ACCESS MEMORY DEVICE, INFORMATION READING METHOD THEREOF, PHASE CHANGE RANDOM ACCESS MEMORY DEVICE, AND INFORMATION READING METHOD THEREOF - A resistance memory element, a phase change memory element, a resistance random access memory device, an information reading method thereof, a phase change random access memory device, and an information reading method thereof are provided. The resistance random access memory device includes an array of resistance memory element arranged in a matrix. Each resistance memory element includes a substrate in which a source region and a drain region are formed along the column direction and a channel region is formed between the source region and the drain region, a bit line formed on the channel region out of a conductive material to have a shape extending along the arrangement direction of the columns, a resistance switching layer formed on the bit line out of a material of which electrical resistance is switched by an electrical signal, and a word line formed on the resistance switching layer out of a conductive material to have a shape extending along the row direction.01-14-2010
20090067229SEMICONDUCTOR MEMORY DEVICE FOR WRITING DATA TO MULTIPLE CELLS SIMULTANEOUSLY AND REFRESH METHOD THEREOF - A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.03-12-2009
20120218814WRITE BANDWIDTH IN A MEMORY CHARACTERIZED BY A VARIABLE WRITE TIME - A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.08-30-2012
20120314492NON-VOLATILE MEMORY DEVICE HAVING PHASE-CHANGE MATERIAL AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks.12-13-2012
20090040813PHASE CHANGE MEMORY DEVICE AND OPERATING METHOD THEREOF - A phase change memory device and operation is described where the phase change memory device includes a phase change resistance cell storing data corresponding to a sensed crystallization state. The phase change memory device operates by reading data of a selected phase change resistance cell when in a write mode. The data to be written is compared to the read data. If the read data is different from the data to be written, it is determined whether the data to be written is a first data. An operation writing and verifying the first data in the cell under a first operating condition when the is data to be written is the first data is then performed. After performing verification, if the read data is different from the first data, the first data is written and verified in the selected phase change resistance cell under a second operating condition.02-12-2009
20120262984Reducing Temporal Changes in Phase Change Memories - A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.10-18-2012
20090027955NON-VOLATILE MEMORY DEVICES INCLUDING STACKED NAND-TYPE RESISTIVE MEMORY CELL STRINGS AND METHODS OF FABRICATING THE SAME - A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.01-29-2009
20120081956SEMICONDUCTOR PHAST CHANGE MEMORY USING MULTIPLE PHASE CHANGE LAYERS - In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.04-05-2012
20120081955PHASE CHANGE RANDOM ACCESS MEMORY DEVICE - A phase change random access memory device includes: a sense amplifier driving unit configured to compare an input voltage applied through an input signal line with a reference voltage and amplify an output signal in response to the comparison result; an input unit configured to receive an input signal from the input signal line and transmit the received signal to the sense amplifier driving unit; and a coupling prevention unit including a plurality of MOS transistors sharing a bulk bias, coupled between the sense amplifier driving unit and the input unit, and configured to control a sensing margin in response to a level of the input signal.04-05-2012
20120081953SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a first write control code generation unit configured to generate first write control codes which are updated with different cycles in a plurality of respective periods, in response to a programming verification flag signal and a programming enable signal, the first write control code generation unit determining the number of the plurality of periods depending upon a code value of the repetition times setting codes and an update cycle of the first write control codes in an initial period among the plurality of periods depending upon a code value of initial setting codes; and a data write unit configured to output a first programming current pulse with a magnitude corresponding to a code combination of the first write control codes which are updated.04-05-2012
20120230100PROGRAMMABLE PHASE-CHANGE MEMORY AND METHOD THEREFOR - A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region.09-13-2012
20110122684VOLTAGE COMPENSATION CIRCUIT, MULTI-LEVEL MEMORY DEVICE WITH THE SAME, AND VOLTAGE COMPENSATION METHOD FOR READING THE MULTI-LEVEL MEMORY DEVICE - A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.05-26-2011
20110122682High Density Low Power Nanowire Phase Change Material Memory Device - A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.05-26-2011
20100321988CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY - Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.12-23-2010
20080298122Biasing a phase change memory device - A phase change memory device includes a plurality of cells connected to bitlines and including respective phase change memory elements and cell select devices and an addressing circuit for selectively addressing at least one bitline and one cell connected thereto. A reading column bias circuit supplies a bitline voltage to the addressed bitline and cell. The bitline voltage includes the sum of a safe voltage and a reference select device voltage, wherein the reference voltage is equal to a select device voltage on the select device when a cell current flowing through the phase change memory element and the cell select device is equal to a safe current. The safe voltage and the safe current are such that phase transition of the phase change memory element is prevented in any bias condition including a cell voltage lower than the safe voltage and in any bias condition including the cell current lower than the safe current.12-04-2008
20080298121METHOD OF OPERATING PHASE-CHANGE MEMORY - A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction.12-04-2008
20080298120Peripheral Devices Using Phase-Change Memory - Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller accesses PCM mass storage devices containing PCM memory chips that form a mass-storage device that is block-addressable rather than randomly-addressable. SATA, IDE, or MMC/SD transactions from a host bus are read by a bus transceiver on the peripheral PCM controller. Various routines that execute on a CPU in the peripheral PCM controller are activated in response to commands in the host-bus transactions. A PCM controller in the peripheral controller transfers data from the bus transceiver to the PCM mass storage devices for storage.12-04-2008
20120320670FAST VERIFY FOR PHASE CHANGE MEMORY WITH SWITCH - A phase change memory with switch (PCMS) compensates for threshold voltage drift by utilizing a lower demarcation voltage for a verify operation after programming than for a read operation occurring at least a predetermined period of time after the programming operation.12-20-2012
20120320669MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.12-20-2012
20110032752Multi-Level Memory Device Using Resistance Material - A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC.02-10-2011
20110038199MEASUREMENT METHOD FOR READING MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A memory system includes a memory cell configured to represent at least two binary values, a bit line coupled to the memory cell, and first and second comparators coupled to the bit line that, respectively, compare a first and second reference value to a value of a parameter of the bit-line. The system also includes a first and second timers configured to measures a time for the parameter of the bit line to decay. The system also includes a logic unit coupled to the first and second timers that selects the time for the parameter of the bit line to decay from to a first value or a second value.02-17-2011
20120268984Adaptive Wordline Programming Bias of a Phase Change Memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.10-25-2012
20090034324NONVOLATILE MEMORY DEVICES THAT INCLUDE A WRITE CIRCUIT THAT WRITES DATA OVER MULTIPLE WRITE PERIODS USING PULSES WHOSE PEAKS DO NOT COINCIDE WITH EACH OTHER - Nonvolatile memory devices include a plurality of nonvolatile memory cells and a write circuit that is operable to write data to the nonvolatile memory cells over a plurality of consecutive division write periods by generating a plurality of write pulses whose peaks do not coincide with one another to the nonvolatile memory cells.02-05-2009
20110235409SEMICONDUCTOR MEMORY DEVICE FOR WRITING DATA TO MULTIPLE CELLS SIMULTANEOUSLY AND REFRESH METHOD THEREOF - A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.09-29-2011
20110235408SEMICONDUCTOR MEMORY DEVICE - For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.09-29-2011
20100232218METHOD OF TESTING PRAM DEVICE - A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.09-16-2010
20100232217METHOD FOR EFFICIENTLY DRIVING A PHASE CHANGE MEMORY DEVICE - A method for efficiently driving a phase change memory device is presented that includes the operational procedures of writing, reading, comparing and changing. The phase change memory device has a resistor configured to sense a crystallization state changed by currents so as to store data corresponding to the crystallization state. The writing operation writes data having a first state in a corresponding unit cell of the phase change memory device. The reading operation reads a cell data stored in the unit cell. The comparing operation compares the data having the first state with the cell data read from the unit cell to verify whether or not the data is having the first state is the same as the cell data. The changing operation changes a write condition when the data having a first state is different from that of the cell data.09-16-2010
20100232216Phase-Change Memory Device - A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of cell matrixes and includes word line decoding units that are each shared by a plurality of cell matrixes arranged in a row direction and are configured to activate one of global row signals according to a first row address, local row switch units that are provided to the respective cell matrixes and are configured to connect local current lines to corresponding word lines in response to the activated global row signal, bus connecting units that are provided to the respective cell matrixes and are configured to connect the local current lines to global current lines, and enabling units configured to activate one of the global current lines according to a second row address.09-16-2010
20120087183METHODS OF OPERATING PRAMS USING INITIAL PROGRAMMED RESISTANCES AND PRAMS USING THE SAME - A method of operating a PRAM device can be provided by reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.04-12-2012
20120087182PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE - A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance.04-12-2012
20120327708HIGH-ENDURANCE PHASE CHANGE MEMORY DEVICES AND METHODS FOR OPERATING THE SAME - Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.12-27-2012
20120327709PROGRAMMING OF PHASE-CHANGE MEMORY CELLS - A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V12-27-2012
20120287707OPTOELECTRONIC MEMORY DEVICES - A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.11-15-2012
20120287706ISOLATION DEVICE FREE MEMORY - An integrated circuit memory is based on isolation device free memory cells. The memory cells are passively coupled to bit lines and word lines. The memory cells include an anti-fuse element and an element of phase change material in series. A rupture filament through the anti-fuse layer acts as an electrode for the phase change element. Control circuitry is configured to apply bias arrangements for operation of the memory cells, including a first write bias arrangement to induce a volume of the higher resistivity phase in the phase change material establishing a first threshold for the selected memory cell below a read threshold, a second write bias arrangement to induce a larger volume of the higher resistivity phase in phase change material establishing a second threshold for the selected memory cell above the read threshold, and a read bias arrangement to apply the read threshold to the selected memory cell.11-15-2012
20100214828SEMICONDUCTOR DEVICE - In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.08-26-2010
20100202195PHASE CHANGE MEMORY - The present disclosure includes devices and methods for operating resistance variable memory cells. One or more embodiments include applying a programming signal to a resistance variable material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.08-12-2010
20100202194DYNAMICALLY ALLOCABLE REGIONS IN NON-VOLATILE MEMORIES - An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the matrix into a plurality of subspaces; each subspace comprises at least one respective memory cell. The memory device further comprises selection means for selecting a subspace, operative means for performing an operation on all the memory cells of the selected subspace, and means for dynamically modifying the number of subspaces and/or the number of memory cells included in each subspace.08-12-2010
20100202193NON-VOLATILE MEMORY DEVICE - A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage application unit is arranged to write data by switching each cell between a first resistance state and a second, lower, resistance state. The voltage application unit is arranged to switch a cell to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by 0.5 volts or less. The voltage application unit is arranged to switch a cell to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by 0.5 volts or less. The current flow when switching between resistance states is less than 10 μA. The memory cells of the device can be toggled between the resistance states, and the resistance states are non-volatile.08-12-2010
20120140554COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT - A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.06-07-2012
20120140553REVERSIBLE LOW-ENERGY DATA STORAGE IN PHASE CHANGE MEMORY - A phase change memory (PCM) device utilizes low energy pulses to write data to PCM storage elements (cells). Methods, devices and systems are described that use low energy reset pulses to reset cells that have been previously set using a method that keeps a portion of the PCM cells in an amorphous phase. The reset is reversible by utilizing a low energy set pulse.06-07-2012
20130016557SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STRUCTURE - A three-dimensional memory device includes a stack of semiconductor layers. Phase change memory (PCM) cell arrays are formed on each layer. Each PCM cell includes a variable resistor as storage element, the resistance of which varies. On one layer, formed is peripheral circuitry which includes row and column decoders, sense amplifiers and global column selectors to control operation of the memory. Local bit lines and worldliness are connected to the memory cells. The global column selectors select global bitlines to be connected to local bit lines. The row decoder selects wordlines. Applied current flows through the memory cell connected to the selected local bitline and wordline. In write operation, set current or reset current is applied and the variable resistor of the selected PCM cell stores “data”. In read operation, read current is applied and voltage developed across the variable resistor is compared to a reference voltage to provide as read data.01-17-2013
20130016555SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAMEAANM KIM; Myoung SubAACI Ichon-siAACO KRAAGP KIM; Myoung Sub Ichon-si KRAANM Kim; Soo GilAACI Ichon-siAACO KRAAGP Kim; Soo Gil Ichon-si KRAANM Park; Nam KyunAACI Ichon-siAACO KRAAGP Park; Nam Kyun Ichon-si KRAANM Kim; Sung CheoulAACI Ichon-siAACO KRAAGP Kim; Sung Cheoul Ichon-si KRAANM Do; Gap SokAACI Ichon-siAACO KRAAGP Do; Gap Sok Ichon-si KRAANM Sim; Joon SeopAACI Ichon-siAACO KRAAGP Sim; Joon Seop Ichon-si KRAANM Lee; Hyun JeongAACI Ichon-siAACO KRAAGP Lee; Hyun Jeong Ichon-si KR - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.01-17-2013
20130016556PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS - A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region.01-17-2013
20100124102Phase-Change and Resistance-Change Random Access Memory Devices and Related Methods of Performing Burst Mode Operations in Such Memory Devices - Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.05-20-2010
20110157970Phase Change Memory That Switches Between Crystalline Phases - A phase change memory may transition between two crystalline states. In one embodiment, the phase change material is a chalcogenide which transitions between face centered cubic and hexagonal states. Because these states are more stable, they are less prone to drift than the amorphous state conventionally utilized in phase change memories.06-30-2011
20110157969SEMICONDUCTOR MEMORY APPARATUS, AND CIRCUIT AND METHOD FOR CONTROLLING FAULTY ADDRESS THEREIN - A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and an address storage and determination unit configured to receive the address signal, be driven by the driving signal to output the address signal or an inverted signal of the address signal.06-30-2011
20110157968SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device measures a leakage current generated when a unit cell is accessed during a test process. The semiconductor memory device includes a unit cell configured to include a memory element, a word line configured to be coupled to one end of the unit cell, and a bit line configured to be coupled to the other end of the unit cell. In a normal operation, a current signal flows from the bit line to the word line through the unit cell such that data stored in the memory element is read. In a test operation, the word line is deactivated and a read operation is carried out such that data stored in the memory element is read.06-30-2011
20130021845PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL - A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.01-24-2013
20120243307RESISTANCE CHANGE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a phase change memory includes a memory cell, a select transistor, and a memory cell array. The memory cell includes a chalcogenide wiring, resistance wirings and a cell transistor. The chalcogenide wiring becomes a heater. One end of a plurality of memory cells with sources and drains connected in series is connected to a source of the select transistor. The bit line is connected a drain of the select transistor. The memory cell array is obtained by forming a memory cell string.09-27-2012
20080291718VARIABLE RESISTANCE MEMORY DEVICE WITH AN INTERFACIAL ADHESION HEATING LAYER, SYSTEMS USING THE SAME AND METHODS OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material.11-27-2008
20080253177Write Operations for Phase-Change-Material Memory - Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.10-16-2008
20080239797INFORMATION RECORDING/REPRODUCING DEVICE - There is proposed a nonvolatile information recording/reproducing device with low power consumption and high thermal stability. The information recording/reproducing device according to an aspect of the present invention includes a recording layer, and mechanism for recording information by generating a phase change in the recording layer while applying a voltage to the recording layer. The recording layer is comprised one of a Wolframite structure and a Scheelite structure.10-02-2008
20080232160RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE - An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance in the ON state (because it is a metallic filament in the ON state). These attributes make it a near ideal diode. During the passage of current (during program/read/erase) of the memory element, the solid electrolyte material also programs into the low resistance state. The final state of the solid electrolyte material is reverted to a high resistance state while making sure that the final state of the memory material is the one desired.09-25-2008
20080232158OPTIMIZED PHASE CHANGE WRITE METHOD - A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.09-25-2008
20080225580Resistance variable memory with temperature tolerant materials - A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb09-18-2008
20080225579MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF - An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a bit line through respective first electrodes and access transistors controlled by respective word lines. The memory elements each have a respective second electrode coupled thereto which in cooperation with the bit line access transistors and first electrode, serves to apply read, write and erase signals to the memory element.09-18-2008
20080225578STRUCTURE FOR INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES - A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.09-18-2008
20110261616WRITE SCHEME IN PHASE CHANGE MEMORY - A method for writing a phase change memory includes receiving an input data corresponding to a plurality of memory cells, while reading a previous data from the plurality of memory cells and comparing the input data with the previous data. Upon determining that the input data is different from the previous data for one or more of the plurality of memory cells, and upon determining that a current value of a write counter is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the current value of the writer counter is incremented.10-27-2011
20110261615SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells.10-27-2011
20110261614Semiconductor device - A semiconductor device that needs a relatively long time to control a write operation and the like is reduced in size. The semiconductor device includes: first and second bit line control circuits which are arranged to correspond to first and second memory cell arrays, respectively; a control signal line that is connected to the first and second bit line control circuits in common and transmits a first control signal; and control signal lines that are connected to the first and second bit line control circuits, respectively, and transmit second and third control signals, respectively. The first bit line control circuit performs an operation control on the first memory cell array when the first and second control signals are activated. The second bit line control circuit performs an operation control on the second memory cell array when the first and third control signals are activated.10-27-2011
20110261611SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a period control signal generation unit configured to generate a period control signal which is activated after a first time, in response to a programming enable signal, a first write control code generation unit configured to generate first write control codes which are cyclically updated for a second time, in response to the programming enable signal, and update the first write control codes in response to the period control signal, a second write control code generation unit configured to generate a second write control code in response to the programming enable signal, and a data write unit configured to output a first programming current pulse which has a magnitude corresponding to a code combination of the updated first write control codes or a second programming current pulse which has a magnitude corresponding to the second write control code.10-27-2011
20130141968SEMICONDUCTOR STORAGE DEVICE - The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (06-06-2013
20080219047APPARATUS AND METHOD FOR WRITING DATA TO PHASE-CHANGE MEMORY BY USING POWER CALCULATION AND DATA INVERSION - Provided are an apparatus and method for writing data to a phase-change random access memory (PRAM) by using writing power calculation and data inversion functions, and more particularly, an apparatus and method for writing data which can minimize power consumption by calculating the power consumed while input original data or inverted data is written to a PRAM and storing the data consuming less power. A PRAM consumes a significant amount of power in order to store data in a memory cell since a large electric current is required to flow for a long period of time. According to the present invention, since the PRAM consumes different amounts of power when writing data with a value of 0 and data with a value of 1, the power consumed when input original data is stored and the power consumed when the input original data is inverted and stored are compared to each other, the data with a smaller power consumption is stored when the data is written to the PRAM as a word unit, and thus the power consumption of the PRAM can be reduced.09-11-2008
20080219046Writing method and system for a phase change memory - A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature.09-11-2008
20120250403Method for Programming A Resistive Memory Cell, A Method And A Memory Apparatus For Programming One Or More Resistive Memory Cells In A Memory Array - A method for programming a resistive memory cell is provided. The method may include providing a programming signal to the resistive memory cell. The programming signal may include an electrical pulse and a bias pulse coupled with the electrical pulse. The electrical pulse includes an electrical pulse portion, and the bias pulse includes at least two bias pulse portions, wherein the electrical pulse portion is positioned between the at least two bias pulse portions. The bias pulse includes a voltage below a threshold switching voltage of the resistive memory cell. The programming signal includes a peak voltage above the threshold switching voltage of the resistive memory cell.10-04-2012
20120250401PHASE CHANGE MEMORY (PCM) ARCHITECTURE AND A METHOD FOR WRITING INTO PCM ARCHITECTURE - A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described.10-04-2012
20130170291VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.07-04-2013
20130135925STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING - A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.05-30-2013
20130135923PHASE CHANGE MEMORY DEVICE AND DATA STORAGE DEVICE HAVING THE SAME - A phase change memory device includes a memory cell array including a plurality of memory cells each arranged at a region where a word line and a bit line cross each other, and a control logic including a reset program control logic configured to control a reset program operation for the plurality of memory cells and a set program control logic configured to control a set program operation for the plurality of memory cells.05-30-2013
20130094285PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.04-18-2013
20130141967VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an Sb06-06-2013
20110273927SEMICONDUCTOR DEVICE - A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).11-10-2011
20080316804Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices - In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship:12-25-2008
20110211391Programmable Resistance Memory - A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses.09-01-2011
20130148421METHODS OF PROGRAMMING TWO TERMINAL MEMORY CELLS - Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell.06-13-2013
20090027952PHASE CHANGE MEMORY DEVICE WITH REFERENCE CELL ARRAY - A phase change memory device includes a plurality of bit lines and a reference bit line intersecting a plurality of word lines. A cell array block has a phase change resistance cell arranged where a word line and a bit line intersect. A reference cell array block is configured to output a reference current and is formed where the word line and a reference bit line intersect. A column selecting unit is configured to select a corresponding bit line connected to the cell array block. A reference column selecting unit is connected to the reference cell array block and is configured to select the reference bit line. A sense amplifier is connected to the column selecting unit and the reference column selecting unit and is configured to receive the reference current and a cell data current of the bit line.01-29-2009
20100315868SEMICONDUCTOR DEVICE INCLUDING STORAGE DEVICE AND METHOD FOR DRIVING THE SAME - A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials.12-16-2010
20100315867SOLID-STATE MEMORY DEVICE, DATA PROCESSING SYSTEM, AND DATA PROCESSING DEVICE - A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.12-16-2010
20100315866PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.12-16-2010
20130155765PHASE CHANGE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME - A phase change memory device includes: a memory cell arranged at a region where a word line and a bit line cross each other; and a control logic including: a program control logic configured to control a program operation of the memory cell; a read control logic configured to control a read operation of the memory cell; and an operation complete signal transfer unit configured to adjust a transfer time point of an operation complete signal transferred between the program control logic and the read control logic.06-20-2013
20130155766PHASE CHANGE MEMORY DEVICES, METHOD FOR ENCODING, AND METHODS FOR STORING DATA - Phase change memory cells including a phase change media can be encoded using a source of energy that is not integral with the memory cell. External sources of energy include thermal heads, such as those used in direct thermal printing or thermal transfer printing and sources of electromagnetic radiation, such as lasers. Such types of phase change memory devices can be associated with substrates that include thermochromic materials or are suitable for thermal transfer printing so that the memory cells can be encoded and print media applied to the substrate using the same source of thermal energy.06-20-2013
20130155767APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE - A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.06-20-2013
20120281466PHASE CHANGE MEMORY ELEMENTS USING ENERGY CONVERSION LAYERS, MEMORY ARRAYS AND SYSTEMS INCLUDING SAME, AND METHODS OF MAKING AND USING SAME - A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.11-08-2012
20110310662STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING - A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.12-22-2011
20110310661MEMORY SENSING DEVICES, METHODS, AND SYSTEMS - The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents.12-22-2011
20110317481PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS - A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.12-29-2011
20120020150Integrated Circuits With Phase Change Devices - Embodiments include methods, apparatus, and systems with integrated circuits having phase change devices. One embodiment includes an integrated circuit die and a phase change die having a phase change material that changes phases when a temperature at the integrated circuit die exceeds a threshold for a predetermined amount of time.01-26-2012
20120020149Semiconductor device - A memory cell changes a potential of a bit line to a discharge potential from a precharge potential in correspondence with held data. A sense amplifier precharges a bit line by a precharge circuit, compares potential at a decision point linked with the potential of the bit line with a decision threshold and outputs a comparison result by an output circuit, and sets the potential at the decision point at a time of precharging in correspondence with the decision threshold. A capacitor element connects between the bit line and an input end of the output circuit. A potential setting circuit enables setting of an input end of the output circuit forming a decision point, to a prescribed potential between a precharge voltage of the bit line and the decision threshold at a time of precharging the bit line. Operating range of memory function is enlarged.01-26-2012
20120087181Cross-Point Self-Aligned Reduced Cell Size Phase Change Memory - A programmable memory array is disclosed in which the phase change memory cells are self-aligned at the access devices and at the cross-points of the bit lines and the word lines. A method for making the array employs one line mask to define the bit lines and another line mask to define the word lines. The front end of line (FEOL) memory cell elements are in the same layer as the polysilicon gates. The bit lines and the word lines intersect over the devices, and the memory cell elements are formed at the intersections of the bit lines and the word line.04-12-2012
20120092923READ DISTRIBUTION MANAGEMENT FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.04-19-2012
20130208537MEMORY DEVICE USING FLAG CELLS AND SYSTEM USING THE MEMORY DEVICE - A memory device may include a normal cell which is configured to be programmed to a first resistance and stabilized as a resistance of the normal cell drifts from the first resistance to a second resistance; a flag cell which is configured to be programmed to a third resistance smaller than the first resistance and stabilized as a resistance of the flag cell drifts from the third resistance to a fourth resistance smaller than the second resistance; and a decision circuit which is configured to decide whether the flag cell has been stabilized in order to determine whether the normal cell has been stabilized.08-15-2013

Patent applications in class Amorphous (electrical)