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Flip-flop (electrical)

Subclass of:

365 - Static information storage and retrieval

365129000 - SYSTEMS USING PARTICULAR ELEMENT

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Class / Patent application numberDescriptionNumber of patent applications / Date published
365156000 Complementary 134
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DocumentTitleDate
20130044536ARRAY-BASED INTEGRATED CIRCUIT WITH REDUCED PROXIMITY EFFECTS - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.02-21-2013
20110205787DUAL-RAIL SRAM WITH INDEPENDENT READ AND WRITE PORTS - A Static Random Access Memory comprising a matrix arrangement of cells, each cell comprising:—a bistable loop of a first inverter and a second inverter, in which an input of the first inverter is coupled to an output of the second inverter at a first bistable node and an input of the second inverter is coupled to an output of the first inverter at a second bistable node;—a first access transistor connected between the first bistable node and a write bitline, the first access transistor having a control terminal connected to a write wordline, and—a second access transistor connected between the second bistable node and a line being the complement of the write bitline, the second access transistor having a control terminal connected to the write wordline wherein—a first separate read port is connected between a read bitline and a source potential, which first read port has at least two control terminals, one control terminal being connected to the second bistable node and one to a read wordline, and—a second separate read port is connected between a line being the complement of the read bitline and a source potential, which second read port has at least two control terminals, one control terminal being connected to the first bistable node and one to the read wordline. At least one of the read ports can comprise two series-connected transistors, which may have mutually different threshold voltages.08-25-2011
20110205786MEMORY DESIGN - An improved memory design is described which removes the need to read firmware from ROM into RAM on start-up. A SRAM memory element comprises an influencing element which sets the state of the memory cells within the memory element on start-up to defined values. These defined values are set at the design stage such that on start-up the volatile memory contains firmware or other data. Dependent upon the implementation of the influencing element, the values of stored in the memory cells may be fixed or may subsequently be overwritten during operation of the device. In an example, the memory cell comprises two cross-coupled inverters and the influencing element comprises at least one transistor arranged to connect the input to one of the inverters to ground or a power supply rail when voltage is applied to a controlling node of the transistor.08-25-2011
20100073996SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage.03-25-2010
20130077387SEMICONDUCTOR DEVICE - There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.03-28-2013
20130039120STATIC RAM - A static RAM includes: a plurality of word lines; a plurality of pairs of local bit lines; a plurality of memory cells arranged in correspondence with intersections of the plurality of pairs of local bit lines and the plurality of word lines; a capacitance shared circuit arranged for each of the plurality of pairs of local bit lines; a common connection line connecting the plurality of capacitance shared circuits; and a pair of global bit lines connected to the plurality of pairs of local bit lines, wherein the capacitance shared circuit includes two N-channel transistors connected between the pair of local bit lines and the common connection line corresponding to each other.02-14-2013
20100046277Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability - A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.02-25-2010
20100046278Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage - A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.02-25-2010
20100046279SEMICONDUCTOR MEMORY DEVICE AND TRIMMING METHOD THEREOF - The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors.02-25-2010
20090185409ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACCESS TRANSISTORS AND DESIGN STRUCTURE FOR SAME - A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 07-23-2009
20090161412SEMICONDUCTOR MEMORY - In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.06-25-2009
20100046276Systems and Methods for Handling Negative Bias Temperature Instability Stress in Memory Bitcells - A system and method reduce stress caused by NBTI effects by determining if a trigger event has occurred and if so inverting all input data values to the memory and all output data values from the memory during a period of time defined by the determined trigger event. In one embodiment, the trigger event is an alternate memory power-up.02-25-2010
20130083591Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets - An integrated circuit memory is disclosed in which an array of 8 T SRAM cells is arranged in rows and columns using a plurality of write wordlines for each row of 8 T SRAM cells to control write access to cells in the row associated with a first parity/ECC word and a second write wordline operable to control write access to cells in the row associated with a second parity/ECC word.04-04-2013
20130028007SENSE AMPLIFIER - Embodiments of the invention provide a sense amplifier, a SRAM chip comprising the sense amplifier and a method for conducting read operation on a SRAM cell. The sense amplifier according to an embodiment of the invention comprises a cross coupling circuit, a tail current transistor and an output stage, wherein source of the tail current transistor is connected to a negative level. With the scheme according to embodiments of the invention, speed of the sense amplifier can be enhanced, thereby increasing read speed of the SRAM chip.01-31-2013
20130028006STATIC RANDOM ACCESS MEMORY STRUCTURE AND CONTROL METHOD THEREOF - A static random access memory (SRAM) is provided. The SRAM structure includes an SRAM array, a word line decoder, and a reference bit line device. The SRAM array comprises at least one SRAM bit cell made up of six transistors. The word line decoder is used for decoding a word line of the SRAM bit cell array such that the word line is activated at a starting time and is deactivated at a ending time. The reference bit line device is connected between the SRAM array and the word line decoder and is used for pre-deactivating the word line at a predetermined time before the ending time such that a voltage difference between a bit line and a bit line bar of the SRAM bit cell is equal to a predetermined voltage.01-31-2013
20130028008INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - A memory array including at least one cross-latched pair of transistors for storing data. The memory array further includes a first power line for supplying a first reference voltage and a second power line for supplying a second reference voltage. The memory array further includes a first switch having a first output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the first power line. The memory array further includes a second switch having a second output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the second power line. The first output is coupled to the second output.01-31-2013
20120182792BIASING CIRCUIT AND TECHNIQUE FOR SRAM DATA RETENTION - A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.07-19-2012
20130051130WEAK BIT COMPENSATION FOR STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) is provided. The SRAM includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, wherein the current path block is connected to the data line and the data line bar during an entire duration of operation of the SRAM.02-28-2013
20130051129MEMORY DEVICE AND SYSTEMS INCLUDING THE SAME - The memory device includes a memory cell array, an access control circuit configured to access the memory cell array, a control signal generation circuit configured to generate a control signal for controlling an operation of the access control circuit, and a variable delay circuit configured to generate a delay signal by variably delaying a clock signal according to an external signal. The control signal generation circuit adjusts an activation timing of the control signal in response to the delay signal.02-28-2013
20090303778Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices - Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.12-10-2009
20090303777SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second writing bit lines intersect with each other. In the semiconductor memory device, the memory cell includes a flip-flop circuit that includes first and second nodes of a complementary pair; a first transfer transistor that is connected between the first writing bit line and the first node, a gate of the first transfer transistor being connected to the writing word line; and a second transfer transistor that is connected between the second writing bit line and the second node, a gate of the second transfer transistor being connected to the writing word line. The first and second writing bit lines are in a floating state whenever data is not written in the memory cell.12-10-2009
20090303776STATIC RANDOM ACCESS MEMORY CELL - A six transistor (“6T) static random access memory (“SRAM”) cell and method for using the same are disclosed herein. The 6T SRAM cell includes a single read pass gate transistor and a single write pass gate transistor. The single read pass gate transistor is connected to a read bit line and a read word line. The single write pass gate transistor connected to a write bit line and a write word line.12-10-2009
20090091970SEMICONDUCTOR MEMORY DEVICE - Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.04-09-2009
20130058155SRAM DIMENSIONED TO PROVIDE BETA RATIO SUPPORTING READ STABILITY AND REDUCED WRITE TIME - A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the access transistor gate width multiplied by a ratio of the access transistor gate length to the pulldown transistor gate length is smaller than one. Furthermore, the pullup transistor gate width is greater than or equal to the pulldown transistor gate width.03-07-2013
20130064005TUNNEL TRANSISTOR, LOGICAL GATE COMPRISING THE TRANSISTOR, STATIC RANDOM-ACCESS MEMORY USING THE LOGICAL GATE AND METHOD FOR MAKING SUCH A TUNNEL TRANSISTOR - A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.03-14-2013
20130064006Apparatus for Selective Word-Line Boost on a Memory Cell - Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers.03-14-2013
20130064004SRAM CELL WRITABILITY - Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated. This bias voltage value is applied to word lines of SRAM cells in a model SRAM array. A first delay for a trigger signal rippled through the model SRAM array is detected and compared to a reference delay. A write assist indication is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell.03-14-2013
20130064003DUAL PORT STATIC RANDOM ACCESS MEMORY CELL - An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.03-14-2013
20130188416MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASED CONTROL - A memory circuit including at least one memory array and at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage. The memory circuit further includes at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line and a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.07-25-2013
20090231908SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF - A semiconductor storage device includes: a bit line; a first word line; a second word line; a first inverter in which one terminal of a first load transistor is connected to a first driver transistor and their junction point forms a first node; a second inverter in which one terminal of a second load transistor is connected to a second driver transistor and their junction point forms a second node; a first write transistor one terminal of which is connected to the first load transistor and the other terminal of which is connected to a power supply voltage; a second write transistor one terminal of which is connected to the first driver transistor and the other terminal is connected to a reference potential; and an access transistor one terminal of which is connected to the first node and the other terminal of which is connected to the bit line.09-17-2009
20090010043Configurable SRAM System and Method - A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.01-08-2009
20100085802Multi-State Latches From n-State Reversible Inverters - N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.04-08-2010
20130163311SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a memory cell array having memory cells each configured to hold data, a plurality of N ports, a port selection circuit that selects M (M06-27-2013
20080298116DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE - A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.12-04-2008
20100188886Implementing Enhanced SRAM Stability and Enhanced Chip Yield With Configurable Wordline Voltage Levels - An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.07-29-2010
20090027945Method and Apparatus for Implementing Enhanced SRAM Read Performance Sort Ring Oscillator (PSRO) - A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.01-29-2009
20100246242Soft Error Robust Storage SRAM Cells and Flip-Flops - A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the lower storage nodes act to limit feedback between the upper storage nodes with the same effect. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.09-30-2010
20130021839SEMICONDUCTOR MEMORY - A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.01-24-2013
20120106238STATIC RANDOM-ACCESS CELL, ACTIVE MATRIX DEVICE AND ARRAY ELEMENT CIRCUIT - A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected to a data input of the SRAM cell via the sampling switch, and to a data output of the SRAM cell independent of the feedback switch, an output of the second inverter is connected to the input of the first inverter via the feedback switch, and first and second clock inputs of the SRAM cell are configured to control the sampling switch and the feedback switch, respectively.05-03-2012
20090109732ASYMMETRICAL SRAM CELL WITH SEPARATE WORD LINES - An integrated circuit includes a memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. The plurality of memory cells include a plurality of asymmetric cells, each of the asymmetric cells configured with a strong side including a first inverter having a strong side latch node, and a strong side pass transistor coupled to the strong side latch node, and a weak side including a second inverter cross-coupled with the first inverter having a weak side latch node and a weak side pass transistor coupled to the weak side latch node. Separate ones of the plurality of word lines are coupled to a gate of the strong side pass transistor and a gate of the weak side pass transistor.04-30-2009
20110026308CELL STRUCTURE FOR DUAL PORT SRAM - A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor, wherein the pull down transistors of the first inverter are formed in a first active region, the pull down transistors of the second inverter are formed in a second active region, the pass gate transistors coupled to the data storage node are formed in a third active region and the pass gate transistors coupled to the data bar storage node are formed in a fourth active region.02-03-2011
20090161410SEVEN TRANSISTOR SRAM CELL - The present disclosure provides a seven transistor static random access memory (7T SRAM) cell. In one embodiment, the 7T SRAM cell includes a pair of cross-coupled inverters configured to provide a memory element having first and second storage nodes. The 7T SRAM cell also includes a Read isolation transistor having a control element connected to one of the storage nodes of the cross-coupled transistor inverters and configured to provide a buffered Read output. The 7T SRAM cell further includes a Read pass gate transistor controlled by a Read word line and connected between the Read isolation transistor and a read bit line. Additionally, the 7T SRAM cell still further includes a Write pass gate transistor controlled by a Write word line and connected between one of the storage nodes of the cross-coupled inverters and a Write bit line to write either state of the memory element.06-25-2009
20090080237SRAM MEMORY WITH REFERENCE BIAS CELL - A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells.03-26-2009
20080316800Semiconductor memory device - When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.12-25-2008
20080239793Generalized Interlocked Register Cell (GICE) - A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.10-02-2008
20100124098SRAM AND FORMING METHOD AND CONTROLLING METHOD THEREOF - An SRAM and a forming method and a controlling method thereof are provided. The above-mentioned SRAM includes a tracking column, a normal column, a cell voltage control circuit and a cell voltage pull-down circuit. Each of the tracking column and the normal column includes a plurality of memory cells. The cell voltage control circuit is coupled to the tracking column and the normal column for connecting an operation voltage to the two columns before a write operation of the SRAM starts and for disconnecting the operation voltage from the two columns after the write operation starts. The cell voltage pull-down circuit is coupled to the two columns for pulling down the cell voltages of the two columns after the write operation starts and for ceasing pulling down the cell voltage of the normal column when the cell voltage of the tracking column drops down to a predetermined voltage.05-20-2010
20100118599PROCESS FOR FORMING BOTH SPLIT GATE AND COMMON GATE FINFET TRANSISTORS AND INTEGRATED CIRCUITS THEREFROM - A method to fabricate an integrated circuit (IC) that includes a plurality of MOSFETs including at least one common gate FinFET device and at least one split gate FinFET device. A substrate having a semiconductor surface is provided. A plurality of fins are formed from the semiconductor surface including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height. Gate slacks are formed on the taller and shorter fins such that a gate electrode for the taller fin is a split gate electrode and a gate electrode for the shorter fin is a common gate electrode. Fabrication of the IC is completed, wherein the split gate FinFET includes the split gate electrode and the common gate FinFET device includes the common gate electrode. An IC includes a substrate having a semiconductor surface, a plurality of semiconductor fins including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height, and at least one common gate FinFET device formed from the shorter fin and at least one split gate FinFET device providing a parallel gate transistor pair comprising a first and a second transistor formed from the taller fin.05-13-2010
20120307549Nonvolatile Latch Circuit - A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal. The nonvolatile memory element is electrically coupled to the output terminal at a first end and to a intermediate voltage source at a second end. A logic state of the latch circuit responds to an input signal during an active period of a clock signal. A logic state of the nonvolatile memory element is controlled by a bidirectional current running between the first and second ends. An electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source.12-06-2012
20120106237BOOST CIRCUIT FOR GENERATING AN ADJUSTABLE BOOST VOLTAGE - A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.05-03-2012
20120106236TFET BASED 6T SRAM CELL - Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.05-03-2012
20090279346FAULT TOLERANT ASYNCHRONOUS CIRCUITS - New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.11-12-2009
20090279347SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in case where the cell power supply voltage in supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.11-12-2009
20090285010Write Assist Circuit for Improving Write Margins of SRAM Cells - A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.11-19-2009
20100103719Two-Stage 8T SRAM Cell Design - An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node.04-29-2010
20100061143Assembling and Applying Nano-Electro-Mechanical Systems - A method of constructing devices using semiconductor manufacturing processes includes fabricating a device having a movable portion and a fixed portion. The movable portion is connected to the fixed portion only through at least one sacrificial layer. The sacrificial layer is removed in the presence of a force of sufficient strength so as to controllably reposition the movable portion during the release process. The force can be externally applied, generated locally as a result of, for example, the relative positions of the fixed and movable portions, or some combination of the two. Several devices constructed according to such a method are also disclosed.03-11-2010
20090168498Spacer patterned augmentation of tri-gate transistor gate length - In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.07-02-2009
20090168496Memory Cell Having Improved Write Stability - A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through the write access circuit, changing a write word line that controls the write access circuit from a deactivated low voltage state to an activated high voltage state, and changing a read word line that controls the read access circuit from an activated low voltage state to a deactivated high voltage state, wherein the change in voltage on the read word line provides a voltage boost to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line to provide write assist to the memory cell during a write operation.07-02-2009
20090168497Memory Leakage Control Circuit and Method - In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and comprises a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage.07-02-2009
20080273373APPARATUS FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY - A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.11-06-2008
20080273374METHODS OF OPERATING AND DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY - A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.11-06-2008
20110007557SEMICONDUCTOR MEMORY DEVICE - An SRAM cell includes one pair of drive transistors, one pair of load transistors, one pair of write access transistors, one pair of read drive transistors, and one pair of access transistors. A voltage source potential is supplied to drains of the read drive transistors.01-13-2011
20080266936Memory device using SRAM circuit - A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which is connected to said first flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a first write signal to said first flip-flop circuit; and a second write control circuit which is connected to said second flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a second write signal to said second flip-flop circuit.10-30-2008
20080253172SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to respective rows of the plurality of memory cells, a plurality of word line drivers for driving the plurality of word lines, respectively, and a plurality of pull-down circuits connected to the plurality of word lines, respectively, for causing voltages of the respective connected word lines to be lower than or equal to a power supply voltage when the respective word lines are in an active state. The word line drivers each have a transistor for causing the corresponding word line to go into the active state. The pull-down circuits each have a pull-down transistor for pulling down the corresponding word line, the pull-down transistor being a transistor having the same conductivity type as that of the transistor included the word line driver for driving the corresponding word line.10-16-2008
20090190389MULTI-PORT SRAM WITH SIX-TRANSISTOR MEMORY CELLS - In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the 07-30-2009
20090303775Static random access memory cell and devices using same - A bit-cell may include a pair of cross-coupled inverters, a left bit-line, a right bit-line, a word-line and a write-line. The left bit-line may be coupled to a left inverter of the cross-coupled inverters via a left word-line transistor and a left write-line transistor. The right bit-line may be coupled to a right inverter of the cross-coupled inverters via a right word-line transistor and a right write-line transistor. The word-line may be coupled to the gates of the left and right word-line transistors and the write-line may be coupled to the gates of the left and right write-line transistors. A memory device may include a controller, an array of such bit-cells and a differential sensing buffers. Further, a computing device may include a processor and a memory device having the above bit-cells.12-10-2009
20100142258TEN-TRANSISTOR STATIC RANDOM ACCESS MEMORY ARCHITECTURE - The present invention discloses a 10T SRAM architecture, wherein two symmetric data access paths are added to a 6T SRAM architecture. Each data access path has two transistors, whereby the read signals are no more driven by the memory unit, wherefore the dimensions of the transistors inside the 10T SRAM cell are no more limited by the required driving capability. Thus, the 10T SRAM architecture can use the minimum-size transistors to achieve a higher operation speed and meet the requirement of the high-speed digital circuit. Further, the 10T SRAM cell of the present invention can achieve an SNM-free feature.06-10-2010
20090161411SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit line; and a sense circuit connected to sense node coupled to the bit line. The sense circuit includes a first transistor of the first conduction type having a gate connected to the sense node, a second transistor of the second conduction type having a source connected to a first power supply, a drain connected to the sense node, and a gate connected to the drain of the first transistor, a third transistor having a source connected to the first power supply, a drain connected to the drain of the first transistor, and a gate connected to a control signal line, and a fourth transistor having a source connected to a second power supply, a drain connected to the source of the first transistor, and a gate connected to the control signal line. The sense circuit is activated with a control signal given to the control signal line.06-25-2009
20090141537APPARATUS AND METHOD FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATIONAL CAPABILITY - A computational memory device includes an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.06-04-2009
20120069636STATIC RANDOM ACCESS MEMORY (SRAM) HAVING BIT CELLS ACCESSIBLE BY SEPARATE READ AND WRITE PATHS - A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition. One of a group consisting of a high impedance from the first bit cell to indicate that the logic state is a logic low and a signal voltage greater than the intermediate voltage to indicate that the logic state is a logic high is output from the first bit cell to the true read bit line.03-22-2012
20090141538Voltage Controlled Static Random Access Memory - A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL06-04-2009
20090141536Structure for a Configurable SRAM System and Method - A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.06-04-2009
20090052229MIS-TRANSISTOR-BASED NONVOLATILE MEMORY DEVICE WITH VERIFY FUNCTION - A nonvolatile semiconductor memory device includes a first latch to store data, a nonvolatile memory cell including two MIS transistors to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors selected in response to the data stored in the first latch, a second latch to store data obtained by sensing a difference in the transistor characteristics between the two MIS transistors, a logic circuit to produce a signal indicative of comparison between the data of the first latch and the data of the second latch, and a control circuit configured to repeat a store operation storing data in the nonvolatile memory cell, a recall operation storing data in the second latch, and a verify operation producing the signal indicative of comparison until the signal indicates that the data of the first latch and the data of the second latch are the same.02-26-2009
20090080236SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part.03-26-2009
20090219752Apparatus and Method for Improving Storage Latch Susceptibility to Single Event Upsets - An apparatus for improving storage latch susceptibility to single event upsets includes a dual interconnected storage cell (DICE) configured within a storage latch circuit; a pair of separate three-state circuits configured to write the DICE latch, with each three-state circuit coupled to separate data nodes within the DICE latch; and a pair of local clock circuits configured within the storage latch circuit, the pair of local clock circuits configured to generate a duplicate pair of control signals that separately control a corresponding one of the separate three-state circuits. In the event of a charge accumulation event on only one of the pair of local clock circuits so as to change the logical state of the corresponding control signal, the presence of the other of the pair of local clock circuits that remains unaffected by the charge accumulation event prevents an error in the logical state of the DICE latch.09-03-2009
20090244955SEMICONDUCTOR STORAGE DEVICE - This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels at a pair of storage nodes, and a pair of write transistors provided between the pair of storage nodes and a prescribed power supply voltage. Further, the gate potentials of the pair of write transistors are respectively controlled according to a row address, a column address, and write data.10-01-2009
20120195110SEMICONDUCTOR MEMORY DEVICE - When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.08-02-2012
20100265758Method for implementing an SRAM memory information storage device - A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.10-21-2010
20120195107Method for Selectable Guaranteed Write-Through With Early Read Suppression - A static random access memory with write-through capability includes a memory cell configured to store a bit of data. A write enable signal is configured to enable writing a write value from a write line input into the static random access memory cell and to enable reading a read value from the memory cell onto a DOT line. A local evaluation circuit is configured to place the write value from the write line onto the DOT line during a single clock cycle in which the value is being written into the memory cell. An early read suppression circuit is configured to electrically isolate the DOT line from a data out line thereby preventing a leakage current loss from the local evaluation circuit and is also configured to make the value placed on the DOT line to be read from the data out line during the single clock cycle.08-02-2012
20120195105SRAM BIT CELL - A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.08-02-2012
20100002495Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist - A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor.01-07-2010
20090116279Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.05-07-2009
20100259971Two-Port 8T SRAM Design - An integrated circuit includes a two-port static random access memory (SRAM) cell, which includes a first half write-port, a second half write-port, and a read-port. The first half write-port includes a first pull-up transistor, a first pull-down transistor, and a first pass-gate transistor interconnected to each other. The second half write-port includes a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor interconnected to each other and to the first half write-port. Channel lengths of the first pass-gate transistor and the second pass-gate transistor are less than channel lengths of the first pull-down transistor and the second pull-down transistor. The read-port includes a read-port pull-down transistor connected to the first half write-port, and a read-port pass-gate transistor connected to the read-port pull-down transistor.10-14-2010
20100188887Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.07-29-2010
20130215670MEMORY CIRCUIT AND FIELD PROGRAMMABLE GATE ARRAY - A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state.08-22-2013
20120195109SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a sense amplifier detects data stored in a memory cell based on potentials of bit lines of a bit line pair where bit line pairs are provided to correspond to columns of a memory cell array, respectively. Dummy cells are provided to correspond to rows of the memory cell array, respectively to simulate a read operation of the memory cells. A dummy bit line pair is driven in a complementary manner based on data read from the dummy cell. A read control unit controls the read operation of the memory cells based on the potential difference between dummy bit lines of the dummy bit line pair.08-02-2012
20100254180SYSTEM FOR BITCELL AND COLUMN TESTING IN SRAM - A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.10-07-2010
20090116278Semiconductor Device - A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode of the invention is a semiconductor device including a memory cell of a valid bit, where two inverters are connected in series to form a loop, a drain of an N-channel transistor is connected to an output signal line of one of the inverters, a gate thereof is connected to a reset signal line of a CPU, and a source thereof is connected to a ground line. The initial value of the memory cell is determined by inputting a reset signal of the CPU to the gate.05-07-2009
20120195108SRAM CELL HAVING A P-WELL BIAS - A process of performing an SRAM single sided write operation including applying a positive bias increment to an isolated p-well containing a passgate in an addressed SRAM cell. A process of performing an SRAM single sided read operation including applying a negative bias increment to an isolated p-well containing a driver in an addressed SRAM cell. A process of performing an SRAM double sided write operation including applying a positive bias increment to an isolated p-well containing a passgate connected to a low data line in an addressed SRAM cell. A process of performing an SRAM double sided read operation including applying a negative bias increment to an isolated p-well containing a bit driver and applying a negative bias increment to an isolated p-well containing a bit-bar driver in an addressed SRAM cell.08-02-2012
20120195106SRAM Timing Cell Apparatus and Methods - Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.08-02-2012
20090073746STATIC RANDOM ACCESS MEMORY CELL - A static random access memory means is provided. The SRAM memory means comprises a first pass-gate FET (T03-19-2009
20110032750SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS - A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.02-10-2011
20130128656SRAM MEMORY DEVICE AND TESTING METHOD THEREOF - A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.05-23-2013
20090109733Design structure for sram active write assist for improved operational margins - A design structure embodied in a machine-readable medium used in a design process is provided. The design structure comprises a static random access memory (“SRAM”), including a plurality of cells arranged in an SRAM having a plurality of columns; and a voltage control circuit operable to temporarily raise a voltage level of a low voltage reference to cells belonging to a column selected for writing from the plurality of columns, wherein the voltage control circuit includes a first n-type field effect transistor (“NFET”) and a second NFET, the first NFET having a conduction path connected between ground and the low voltage reference, the second NFET having a conduction path connected between a power supply and the low voltage reference.04-30-2009
20100220515SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR - Provided is a semiconductor memory device including: first and second SRAM cells; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line pair; and a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive, in a case of testing the first SRAM cell.09-02-2010
20080278992INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.11-13-2008
20120230086STATIC RANDOM ACCESS MEMORY CELL AND METHOD OF OPERATING THE SAME - A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.09-13-2012
20100302837MEMORY WITH READ CYCLE WRITE BACK - A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.12-02-2010
20130141962Methods and Apparatus for finFET SRAM Arrays in Integrated Circuits - Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y06-06-2013
20110007556SRAM Architecture - A SRAM architecture comprises a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( 01-13-2011
20110026312Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor - A semiconductor device includes a memory cell which includes a first inverter and a second inverter, the first inverter includes a first drive transistor and a first load transistor, the second inverter includes a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter, a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair, a second transmission transistor provided between the output terminal of the second inverter and another line of the first bit line pair, a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair, a fourth transmission transistor provided between the output terminal of the second inverter and another line of the second bit line pair, and a first isolation transistor which isolates the second drive transistor and the first transmission transistor. A first active region in which the first transmission transistor, the second transmission transistor, the second drive transistor, and the first isolation transistor are formed, is formed in a continuous region. The first isolation transistor is provided between the second drive transistor and the first transmission transistor.02-03-2011
20100165705SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 07-01-2010
20090067219Semiconductor memory device including SRAM cell having well power potential supply region provided therein - A semiconductor memory device includes a first well region of a first conductivity type, first and second SRAM cells adjacently arranged to each other, the first and second SRAM cells each including at least a first transfer transistor and a drive transistor formed on the first well, the first transfer transistor and the drive transistor being coupled in series between a bit line and a power source line, and a first diffusion region of the first conductivity type arranged between the drive transistor of the first SRAM cell and the drive transistor of the second SRAM cell, to apply a first well potential to the first well.03-12-2009
20090067220Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor - A semiconductor device has a first inverter including a drive transistor and a load transistor; a second inverter including a drive transistor and a load transistor, a transmission transistor provided between the output terminal of the first inverter and one line of a bit line pair, a transmission transistor provided between the output terminal of the second inverter and the other line of the bit line pair; and an isolation transistor for isolating the drive transistor and the transmission transistor. The transmission transistor, the transmission transistor, the drive transistor, and the isolation transistor are formed in a continuous active region and the isolation transistor is provided between the drive transistor and the transmission transistor.03-12-2009
20110026310POWER-SAVING SEMICONDUCTOR MEMORY - A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.02-03-2011
20110026311Memory device using SRAM circuit - A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which is connected to said first flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a first write signal to said first flip-flop circuit; and a second write control circuit which is connected to said second flip-flop circuit, is conducted by a write control signal supplied to said write word line, and supplies a second write signal to said second flip-flop circuit.02-03-2011
20110019463Static Random Access Memories and Access Methods Thereof - A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other.01-27-2011
20110026309SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL - A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.02-03-2011
20110044095Semiconductor memory device - The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.02-24-2011
2011004409410T SRAM Cell with Near Dual Port Functionality - An integrated circuit including a ram array with SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.02-24-2011
20090073745SEMICONDUCTOR INTEGRATED CIRCUIT - During a write cycle, a selected write-word-line driver drives the corresponding write word line such that the potential of the corresponding write word line is lower in a first period as a predetermined period after an initiation of the write cycle than in a second period as a predetermined period after the first period, and sense amplifiers amplify the potentials of the corresponding write bit lines in the first period.03-19-2009
20110242880MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity.10-06-2011
20110211384STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES - Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors.09-01-2011
20110242881SRAM DEVICE - An object of the present invention is to provide an SRAM device which can set a threshold voltage of a selection transistor appropriate for all the cells on an SRAM array. The SRAM device uses a field effect transistor as the selection transistor, the field effect transistor comprising a gate to drive the transistor and a terminal to control a threshold voltage, which are electrically separated from each other, wherein the SRAM device comprises a circuit which gradually increases, on a reading operation, a voltage supplied to the terminal to control the threshold of the selection transistor from a voltage at the start of the reading.10-06-2011
20110242882Semiconductor memory device including SRAM cell - A semiconductor memory device includes: a first word line and a second word line; a plurality of first SRAM cells; a plurality of second SRAM cells; and a mediating cell. Each first SRAM cell includes the first word line and the second word line and is connected to the first word line. Each second SRAM cell includes the first word line and the second word line and is connected to the second word line. The mediating cell is arranged between and adjacent to one first SRAM cell and one second SRAM cell and is connected to the first word line and the second word line. In the mediating cell and the plurality of first SRAM cells, cells adjacent to each other share a contact for the first word line. In the mediating cell and the plurality of second SRAM cells, cells adjacent to each other share a contact for the second word line.10-06-2011
20110242879TWO WORD LINE SRAM CELL WITH STRONG-SIDE WORD LINE BOOST FOR WRITE PROVIDED BY WEAK-SIDE WORD LINE - An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a read/write word line connected to provide row access to the array of SRAM cells. The SRAM also includes a coupling capacitance connected between the write word line and a detachable allocation of the read/write word line as well as an overdrive module connected to charge the coupling capacitance and provide an overdrive voltage on the detachable allocation of the read/write word line during activation of the write word line. A method of operating an integrated circuit having an SRAM includes providing an overdrive voltage on the detachable allocation of the read/write word line corresponding to a charge redistribution across the coupling capacitance during part of a write cycle.10-06-2011
20100259972SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory has a short transistor coupling complementary storage nodes of a latch circuit of a memory cell. A transfer transistor and the short transistor have a diffusion layer in common coupled to one of the storage nodes. The short transistor and a driver transistor have a diffusion layer in common coupled to the other storage node. The transfer transistor, the short transistor, and the driver transistor are continuously disposed via the diffusion layers in common, and thereby, variation of characteristics of the transfer transistor can be prevented. Accordingly, it may be possible to prevent that current supplying ability of the transfer transistor changes depending on a layout in the memory cell, and that an operation margin of the memory cell deteriorates.10-14-2010
20090323400SEMICONDUCTOR DEVICE - There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.12-31-2009
20100054025SEMICONDUCTOR INTEGRATED MEMORY CIRCUIT AND TRIMMING METHOD THEREOF - A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.03-04-2010
201001240998T LOW LEAKAGE SRAM CELL - This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.05-20-2010
20110075470EMBEDDED SRAM STRUCTURE AND CHIP - An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is defined by a first X-pitch and a first Y-pitch, the X-pitch being longer than the Y-pitch. A plurality of logic transistors are formed outside of the first SRAM array, the plurality of logic transistors including at least first and second logic transistor having first and second gate pitches defined between their source and drain contacts. The second gate pitch is the minimum logic gate pitch for the plurality of logic transistors. The first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one.03-31-2011
20120201072SRAM CELL HAVING AN N-WELL BIAS - An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell.08-09-2012
200802472218T SRAM CELL WITH HIGHER VOLTAGE ON THE READ WL - The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.10-09-2008
20080247220SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS OPERATED BY BOOSTED VOLTAGE - A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.10-09-2008
20110211385SEMICONDUCTOR DEVICE - There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.09-01-2011
20080253170SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage.10-16-2008
20110080772Body Controlled Double Channel Transistor and Circuits Comprising the Same - By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the device to an oxidizing ambient at elevated temperatures, thereby incorporating silicon dioxide into the non-oxidizable material. Hence, an increased compressive stress may be generated within the non-oxidizable layer.04-07-2011
20100110773SRAM CELL WITHOUT DEDICATED ACCESS TRANSISTORS - A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.05-06-2010
20100110774SRAM DEVICE - An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided.05-06-2010
20100165706STATIC MEMORY CELL HAVING INDEPENDENT DATA HOLDING VOLTAGE - A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.07-01-2010
20100195373Method of Operating a Memory Circuit using Memory Cells with Independent-Gate Controlled Access Devices - A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the first and second access devices are configured to operate in a single-gate mode with the READ word line “ON” and the WRITE word line “OFF” while the double-gate pull-down devices are configured to operate in a double gate mode. During a WRITE operation, the first and second access devices are configured to operate in a double-gate mode with the READ word line “ON” and the WRITE word line also “ON.”08-05-2010
20110188296Semiconductor Memory Device and Semiconductor Device - The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor.08-04-2011
20110134684INTEGRATED CIRCUITS WITH SPLIT GATE AND COMMON GATE FinFET TRANSISTORS - An integrated circuit includes common gate FinFET and split gate FinFET devices formed from different height fins at a semiconductor surface of a substrate. A patterned layer of gate electrode material formed over sides and unconnected over the tops of the taller fins defines respective gate electrodes for first and second paired transistors. The patterned layer of gate electrode material formed over the sides and connected over tops of the shorter fins defines common gate electrodes for transistors. In one embodiment, the common gate devices are used for cross-coupled inverters of a memory cell core storage element and the split gate devices are used for pass gates, with the gate electrodes coupled to wordlines and common source/drains coupled to bitline/complementary bitline and core element storage/complementary storage nodes.06-09-2011
20090175069STORAGE CELL HAVING BUFFER CIRCUIT FOR DRIVING THE BITLINE - An integrated circuit includes a memory array including a plurality of memory cells, the memory cells include a core storage element having at least a first storage node (S) and a complementary second storage node (S-bar), and a first pass gate ) coupled to the first storage node (S). A single bitline (BL) is coupled to a node in a source drain path of the first pass gate. The BL is for Reading data from and Writing data to the first storage node (S). A buffer circuit includes a second pass gate and a driver transistor, wherein the second pass gate is coupled between the driver transistor and the source drain path of the first pass gate. A gate of the driver transistor is coupled to the second storage node (S-bar). At least one wordline (WL) is coupled to the first pass gate and the second pass gate.07-09-2009
20090175067SRAM EMPLOYING A READ-ENABLING CAPACITANCE - Embodiments of the present disclosure provide a memory element, a method of constructing a memory element, a method of operating a memory cell, an SRAM cell and an integrated circuit. In one embodiment, the memory element includes a pair of cross-connected CMOS inverters having first and second storage nodes. Additionally, the memory element also includes a capacitive component connected between the first and second storage nodes and configured to provide a supplemental capacitance to extend a read signal for sensing a memory state of the inverters.07-09-2009
20090175070DUAL NODE ACCESS STORAGE CELL HAVING BUFFER CIRCUITS - An integrated circuit includes an array of memory cells, each including a core storage element with first and second complementary storage nodes and first and second cell pass transistors coupled to the first and second storage nodes, respectively. In the cell, a first bitline (BL) is coupled to a first BL node in a source drain path of the first cell pass transistor, and a second BL is coupled to a second BL node in a source drain path of the second cell pass transistor. Each of the memory cells also includes a first buffer circuit comprising a first buffer pass transistor and a first driver transistor coupled to the source drain path of the first cell pass transistor, where the first buffer pass transistor is between the first BL node and the first driver transistor. The memory cells also include a second buffer circuit comprising a second buffer pass transistor and a second driver transistor coupled to a source drain path of the second cell pass transistor, where the second buffer pass transistor is between the second BL node and the second driver transistor. The gates of the first and second driver transistors are coupled to the second and first storage nodes, respectively. The cells include at least a first wordline coupled to the first and second cell pass transistors and the first and second buffer pass transistors.07-09-2009
20090175068SRAM DEVICE, AND SRAM DEVICE DESIGN STRUCTURE, WITH ADAPTABLE ACCESS TRANSISTORS - An SRAM device comprising a pair of MCSFETs connected as access transistors (pass gates). An SRAM device design structure embodied or stored in a machine readable medium includes two MCSFETs connected as access transistors.07-09-2009
20110216579SEMICONDUCTOR DEVICE - A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.09-08-2011
20110216578System for Retaining State Data - According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.09-08-2011
20110051501MEMORY CONTROL WITH SELECTIVE RETENTION - The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (03-03-2011
20120307548DUAL-PORT SUBTHRESHOLD SRAM CELL - An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.12-06-2012
20110305072SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided in which erroneous writing to a dual port memory cell can be prevented without short-circuiting bit lines coupled to two ports. The first write driver applies voltage corresponding to the first write data to the first bit line, when activated. The first write assist driver applies voltage corresponding to the first write data to the second bit line, when activated. A row of the memory cell array for the first access through the first port is specified by the first row address, and a row of the memory cell array for the second access through the second port is specified by the second row address. The first write assist driver is activated at least on condition that the first write driver is activated and that the first row address and the second row address coincide.12-15-2011
201002599738T SRAM CELL WITH HIGHER VOLTAGE ON THE READ WL - The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.10-14-2010
20110063894SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line03-17-2011
20110063893SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING - A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.03-17-2011
20090147560NOVEL SRAM CELL DESIGN TO IMPROVE STABILITY - A design structure embodied in a machine readable medium for use in a design process, the design structure representing a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, the SRAM cell is an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, the SRAM cell is a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions.06-11-2009
201200024595T SRAM MEMORY FOR LOW VOLTAGE APPLICATIONS - An embodiment of a memory device of SRAM type integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of field effect main storage transistors coupled to the main terminal for maintaining the main terminal at the reference voltage corresponding to the stored logic value or to a complement thereof, a set of field effect complementary storage transistors coupled to the complementary terminal for maintaining the complementary terminal at the reference voltage corresponding to the complement of the logic value associated with the main terminal—and a field effect access transistor for accessing the main terminal. The chip includes an isolated well, the access transistor and at least one of the complementary storage transistors being formed in the isolated well.01-05-2012
20120155151Memory Device Having Memory Cells with Enhanced Low Voltage Write Capability - A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.06-21-2012
20120008376MEMORY WITH REGULATED GROUND NODES - Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.01-12-2012
20120008379GLOBAL BIT LINE RESTORE BY MOST SIGNIFICANT BIT OF AN ADDRESS LINE - An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines.01-12-2012
20120008378MEMORY DEVICES AND METHODS HAVING MULTIPLE ADDRESS ACCESSES IN SAME CYCLE - A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.01-12-2012
20120008377STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY - A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.01-12-2012
20120063210Semiconductor Device - Provided is a semiconductor device including an SRAM memory cell that includes: a first inverter and a second inverter that are connected to a single power-supply node and are cross-coupled to each other; a first transfer transistor; and a second transfer transistor. A predetermined voltage is applied from a voltage generation unit to a source terminal of an NMOS transistor included in the first inverter. An inversion detection unit is connected to the SRAM memory cell via the first and second transfer transistors. When a word-line selection potential is applied to a word line with the SRAM memory cell having data written therein, the inversion detection unit detects whether or not the data written in the SRAM memory cell is inverted. In accordance with the detection result of the inversion detection unit, a word-line selection-potential determination unit controls the word-line selection potential to be applied to the word line.03-15-2012
20120014171SCHMITT TRIGGER-BASED FINFET SRAM CELL - The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.01-19-2012
20120014172Static Random Access Memory Devices Having Read And Write Assist Circuits Therein That Improve Read And Write Reliability - Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The. write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. The memory device further includes at least one bit line electrically coupled to the memory cell and a read assist circuit. The read assist circuit may be configured to improve read reliability by partially discharging the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell.01-19-2012
20120057398SRAM DEVICE - An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided.03-08-2012
20100202191nvSRAM HAVING VARIABLE MAGNETIC RESISTORS - Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.08-12-2010
20120113708Stable SRAM Bitcell Design Utilizing Independent Gate Finfet - Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.05-10-2012
20120300538SRAM STRAP ROW DOUBLE WELL CONTACT - An integrated circuit containing an SRAM array having a strap row. The strap row has a well tap active area that partially overlaps adjacent first polarity wells and a second polarity well that is located between the adjacent first polarity wells. A well contact plug is disposed on a top surface of a tap layer located within the well tap active area.11-29-2012
20120300537SRAM STRAP ROW SUBSTRATE CONTACT - An integrated circuit containing an SRAM array having a strap row. The strap row has a substrate contact structure that includes a substrate contact plug and a tap layer.11-29-2012
20120300536SRAM STRAP ROW WELL CONTACT - An integrated circuit containing an SRAM array having a strap row and an SRAM cell row. The strap row includes a tap connecting region that connects two columnar regions of a first polarity well. The strap row also includes a well tap active area in a tap connecting well region. The well tap active area includes a tap layer and a well contact plug that is disposed on the top surface of the tap layer.11-29-2012
20080316799Read-Preferred SRAM Cell Design - A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM cell; and applying a static power to perform a read operation on the SRAM cell.12-25-2008
20120120716SECURE NON-VOLATILE MEMORY - A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.05-17-2012
20120127782STATIC RAM - A static RAM includes a plurality of word lines, a plurality of global bit line pairs, a plurality of static-type memory cells, a plurality of sense amplifiers, a plurality of local bit line pairs provided in correspondence with each global bit line pair, and a plurality of global switches, wherein the plurality of static-type memory cells is connected to the corresponding local bit line pair in response to a row selection signal, and at the time of read, the row selection signal is applied to the word line and after the corresponding local bit line pair is brought into a state corresponding to contents stored in the memory cell, application of the row selection signal is stopped and then the corresponding global switch is brought into a connection state and after changing the state of the global bit line pair, the corresponding sense amplifier is operated.05-24-2012
20120127783SRAM Cell for Single Sided Write - A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage.05-24-2012
20120163067VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.06-28-2012
20100020591Adaptive Voltage Control for SRAM - The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage.01-28-2010
20120134198MEMORY SYSTEM - A memory system includes a memory cell array including a plurality of memory cells electrically connected to pairs of bit lines once a word line is activated; latch portions connected to respective pairs of bit lines; a sense amplifier connected to the latch portions; and a control circuit configured to control the latch portions for a reading operation in order that data in all memory cells connected to the word line, once selected, come to be held in the corresponding latch portions as a group.05-31-2012
20120212997TEST STRUCTURE FOR CHARACTERIZING MULTI-PORT STATIC RANDOM ACCESS MEMORY AND REGISTER FILE ARRAYS - A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.08-23-2012
20120212996MEMORY DEVICE HAVING MEMORY CELLS WITH WRITE ASSIST FUNCTIONALITY - A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device.08-23-2012
20090059655Memory cell and semiconductor memory device having thereof memory cell - Conventional semiconductor memory devices have a problem of a data read failure caused by a leak current. To address this problem, a semiconductor memory device of the present invention including memory cells each formed of a transfer transistor, a load transistor and a drive transistor. Each of the memory cells includes: a first transfer transistor connected to a connection point of the drive transistor and the load transistor; a second transfer transistor connected between the first transfer transistor and a bit line DB; and a compensation transistor connected between a constant voltage node and a connection point of the first transfer transistor and the second transfer transistor. The compensation transistor is switched to a conductive state exclusively from at least one of the first transfer transistor and the second transfer transistor.03-05-2009
20100020590SRAM WITH IMPROVED READ/WRITE STABILITY - A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.01-28-2010
20120075920MEMORY BASE CELL AND MEMORY BANK - A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” Model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.03-29-2012
20120075919Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability - Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.03-29-2012
20120075918SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell Stability and Design Structure for Same - An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.03-29-2012
20120218812SEMICONDUCTOR DEVICE - A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.08-30-2012
20100002496SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and a back gate connected to a first node to which an output terminal of the first inverter and an input terminal of the second inverter are connected; a second transfer transistor including a front gate and a back gate connected to a second node to which an output terminal of the second inverter and an input terminal of the first inverter are connected; a driver transistor whose gate is connected to the second node; and a read transistor including a front gate, a back gate connected to the second node, and a current path whose one end is connected to one end of a current path of the driver transistor.01-07-2010
201002963338T SRAM Cell With One Word Line - An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments. The read buffer in addressed SRAM cells may be biased during read operations. The read buffer in half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. The read buffer in addressed and half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line.11-25-2010
20100296332SRAM Cell for Single Sided Write - A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage.11-25-2010
20110110146SEMICONDUCTOR MEMORY WHICH ENABLES RELIABLE DATA WRITING WITH LOW SUPPLY VOLTAGE BY IMPROVING THE CONDUCTANCE VIA ACCESS TRANSISTORS DURING WRITE OPERATION - A semiconductor memory maintains securely the stored contents in the memory cells, and it is written with data reliably even in a case where a relatively low supply voltage is applied. A memory cell M05-12-2011
20120262983SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - The circuit includes a first wiring for supplying a power supply potential to a signal processing circuit, a transistor for controlling electrical connection between the first wiring and a second wiring for supplying the a power supply potential, and a transistor for determining whether or not the first wiring is grounded. At least one of the two transistors is a transistor whose channel is formed in the oxide semiconductor layer. This makes it possible to reduce power consumption due to cutoff current of at least one of the two transistors.10-18-2012
20120257441MEMORY BIT REDUNDANT VIAS - An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.10-11-2012
201202300888T SRAM Cell With One Word Line - An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments. The read buffer in addressed SRAM cells may be biased during read operations. The read buffer in half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. The read buffer in addressed and half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line.09-13-2012
20120230087SRAM CIRCUITS FOR CIRCUIT IDENTIFICATION USING A DIGITAL FINGERPRINT - Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile.09-13-2012
20110122681SEMICONDUCTOR MEMORY DEVICE - An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.05-26-2011
20120320664SEMICONDUCTOR DEVICE - There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.12-20-2012
20100232214STATIC MEMORY MEMORY POINT AND APPLICATION TO AN IMAGE SENSOR - The invention relates to a memory point of SRAM (static memory) type memory. The memory point conventionally comprises two inverters mounted head-to-tail between two nodes, and at least one access transistor able to be made conductive during a writing phase and linked between a first node and a line of data to be written, characterized in that it comprises an isolating transistor inserted in series between the output of a first inverter and the first node, the isolating transistor being controlled by an insulation signal at the start of a writing phase. The current consumption is reduced when the state of the memory point has to be inverted.09-16-2010
20120281457Data Dependent SRAM Write Assist - A semiconductor chip has an SRAM (static random access memory). The SRAM includes a data dependent write assist circuit which, on writes, reduces a supply voltage on one of a cross coupled inverter pair in an SRAM cell, thereby making it easier to overcome the one of the cross coupled inverters.11-08-2012
20120327703Random Access Memory Controller Having Common Column Multiplexer and Sense Amplifier Hardware - Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.12-27-2012
20100202192STATIC MEMORY DEVICES - A semiconductor memory device includes n-wells (08-12-2010
20120140551STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL - A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages.06-07-2012
20120243302SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.09-27-2012
20120243301MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE - A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports; and a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein.09-27-2012
20120243300COMBINED DATA LEVEL-SHIFTER AND DE-SKEWER - Various embodiments of this disclosure may describe a circuit for transmitting data from a transmitting region of an integrated circuit to a receiving region of the integrated circuit. The circuit may level-shift the data to the appropriate voltage level and may have good tolerance to clock skews. Other embodiments, including an integrated circuit having the circuit or a system with the integrated circuit, may also be disclosed or claimed.09-27-2012
20080253171SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.10-16-2008
20080239792METAL SILICIDE ALLOY LOCAL INTERCONNECT - A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.10-02-2008
20090213641MEMORY WITH ACTIVE MODE BACK-BIAS VOLTAGE CONTROL AND METHOD OF OPERATING SAME - Data storage cells of a static random access memory array are selectively provided with back-bias voltages to reduce current leakage during an active mode of operation. Circuitry electrically connected with the array receives control signals and provides the back-bias voltages to certain idle data storage cells of the array based on the control signals.08-27-2009
20080225573STATIC RANDOM ACCESS MEMORY CELL WITH IMPROVED STABILITY - A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.09-18-2008
20110261609Retain-Till-Accessed Power Saving Mode in High-Performance Static Memories - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells of the 8-T or 10-T type, with separate read and write data paths. Bias devices are included within each memory array block, for example associated with individual columns, and connected between a reference voltage node for cross-coupled inverters in each memory cell in the associated column or columns, and a ground node. In a normal operating mode, a switch transistor connected in parallel with the bias devices is turned on, so that the ground voltage biases the cross-coupled inverters in each cell. In the RTA mode, the switch transistors are turned off, allowing the bias devices to raise the reference bias to the cross-coupled inverters, reducing power consumed by the cells in that mode.10-27-2011
20130170287STABLE MEMORY SOURCE BIAS OVER TEMPERATURE AND METHOD - Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature and a bias circuit operatively coupled to at least one of the plurality of memory cells, the bias circuit being configured to generate a bias voltage for the at least one of the plurality of memory cells. The bias circuit has a second electrical characteristic being variable based, at least in part, on temperature. The first electrical characteristic is approximately proportional to the second electrical characteristic over a predetermined range of temperatures, the predetermined range of temperatures being greater than zero. The bias voltage on each of the plurality of memory cells is approximately proportional with variations in the first electrical characteristic over the predetermined range of temperatures.07-04-2013
201301767698-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.07-11-2013
201301767708-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.07-11-2013
201301767718-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES - An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.07-11-2013
20130176772Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit - A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.07-11-2013
20130114333SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS THEREOF - A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.05-09-2013
20130114332REDUCING READ DISTURBS AND WRITE FAILS IN A DATA STORAGE CELL - A data storage cell having a data line configured to transmit a data value to and from the storage cell, a feedback loop configured to store the data value, a first access device to provide access between the data line and a first point in the feedback loop, a second access device to provide access between the data line and a second point in the feedback loop, the first access point being a less stable point in the feedback loop than the second access point such that a variation in a voltage at the first access point is more likely to disturb said data value stored in the feedback loop than a variation in voltage at the second access point.05-09-2013
20130100731INDEPENDENTY-CONTROLLED-GATE SRAM - The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-V04-25-2013
20130100730METHOD AND APPARATUS FOR WORD LINE SUPPRESSION - A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.04-25-2013
20110273925NONVOLATILE SRAM/LATCH CIRCUIT USING CURRENT-INDUCED MAGNETIZATION REVERSAL MTJ - The present invention is a memory circuit that includes a bistable circuit that stores data, and a ferromagnetic tunnel junction device that nonvolatilely stores the data in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, the data nonvolatilely stored in the ferromagnetic tunnel junction device being able to be restored in the bistable circuit. According to the present invention, writing data to and reading data from the bistable circuit can be performed at high speed. In addition, even though a power source is shut down, it is possible to restore data nonvolatilely stored in the ferromagnetic tunnel junction devices to the bistable circuit.11-10-2011
20130128655METHOD AND APPARATUS FOR DUAL RAIL SRAM LEVEL SHIFTER WITH LATCHING - An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.05-23-2013
20130148414SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS - A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.06-13-2013
20130148415SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, INCLUDING HIERARCHICAL AND/OR OTHER FEATURES - A hierarchical sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line in hierarchy, and associated systems and methods are described. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line, and wherein the sectioned bit lines are arranged in hierarchical arrays. In other implementations, a hierarchical SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.06-13-2013
20130148416SRAM CELL HAVING AN N-WELL BIAS - An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell.06-13-2013
20100315860INTEGRATED CIRCUIT WITH A MEMORY MATRIX WITH A DELAY MONITORING COLUMN - An integrated circuit has a matrix of rows and columns of cells (12-16-2010
20100315859Eight-Transistor SRAM Memory with Shared Bit-Lines - An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged along a row direction. A first word-line is coupled to the first SRAM cell. A second word-line is coupled to the second SRAM cell. A read bit-line is coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction. A write bit-line is coupled to the first SRAM cell and the second SRAM cell.12-16-2010
20130155758CIRCUIT AND METHOD FOR GENERATING A SENSE AMPLIFIER ENABLE SIGNAL BASED ON A VOLTAGE LEVEL OF A TRACKING BITLINE - A circuit is usable to generate a sense amplifier enable (SAE) signal for a static random access memory (SRAM) circuit. The circuit includes a first tracking bit line, a second tracking bit line, a tracking cell, and a control logic circuit. The second tracking bit line is electrically connected to the first tracking bit line. The tracking cell has a driving terminal and a non-driving terminal, where the non-driving terminal is connected to the second tracking bit line, and the driving terminal is connected to the first tracking bit line and configured to selectively charge or discharge a voltage on the first tracking bit line in response to a control signal. The control logic circuit is coupled to the first tracking bit line and configured to generate the SAE signal in response to the voltage level on the first tracking bit line.06-20-2013
20130182490Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction - Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.07-18-2013
20130182491SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER - Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel.07-18-2013
2013018249210T SRAM CELL WITH NEAR DUAL PORT FUNCTIONALITY - An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.07-18-2013
20130182493Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.07-18-2013
20130121065DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM - A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit includes a first input for activating the wordline assist circuit during a read or write cycle and includes a second input for deactivating the wordline assist circuit during the read or write cycle after a delay.05-16-2013
20130188417MEMORY CIRCUIT AND METHOD FOR ROUTING THE MEMORY CIRCUIT - A memory circuit includes a first row of memory cells, a first word line and a second word line over and electrically coupled to the first row of memory cells, a second row of memory cells aligned with the first row of memory cells along a predetermined direction, and a third word line and a fourth word line over and electrically coupled to the second row of memory cells. The first word line is aligned with the third word line, and the second word line is aligned with the fourth word line. One of the first word line or the second word line is electrically coupled with one of the third word line or the fourth word line. The other one of the first word line or the second word line is electrically decoupled from the other one of the third word line or fourth word line.07-25-2013
20120020146Static Random Access Memory Device Including Negative Voltage Level Shifter - Integrated circuit memory devices include an array of static random access memory (SRAM) cells arranged as a plurality of columns of SRAM cells electrically coupled to corresponding plurality of pairs of bit lines and a plurality of rows of SRAM cells electrically coupled to a corresponding plurality of word lines. A word line driver and a column decoder are provided. The word line driver, which is electrically coupled to the plurality of word lines, is configured to drive a selected word line with a positive voltage and a plurality of unselected word lines with a negative voltage during an operation to write data into a selected one of the SRAM cells. The column decoder includes a plurality of pairs of selection switches therein, which are electrically coupled to corresponding ones of the plurality of pairs of bit lines. The column decoder is configured to drive control terminals of a first of the plurality of pairs of selection switches coupled to the selected one of the SRAM cells with positive voltages concurrently with driving control terminals of a second of the plurality of pairs of selection switches coupled to an unselected one of the SRAM cells with negative voltages during the operation to write data.01-26-2012
20120020145Identification Circuit and Method for Generating an Identification Bit - A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.01-26-2012
20130194860Tracking for Write Operations of Memory Devices - Some aspects of the present disclosure relate to write tracking techniques for memory devices. In some embodiments, a memory device includes an array of SRAM cells, wherein each SRAM cell includes a pair of cross-coupled inverters having complimentary storage nodes, and a pair of access transistors that allow selective access to the complimentary storage nodes, respectively. To help ensure that wordline and bitline pulses are of sufficient length and intensity, one or more write tracking cells track a wordline tracking signal, which is representative of a wordline pulse applied to a wordline. In response to the wordline tracking signal, the write tracking cell internally generates a signal that models bitline loading, and provides an output tracking signal based on the wordline tracking and bitline loading signals. Bitline and/or wordline pulses can then be set based on the output tracking signal.08-01-2013
20130194861SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION - A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.08-01-2013
20130194859METHOD AND APPARATUS FOR SWITCHING POWER IN A DUAL RAIL MEMORY - A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column.08-01-2013
20130201753IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM - A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided. The circuit includes a write disable function to prevent discharge of a global bit line during a write operation. The write disable function disables a NAND gate driving a global pull down device during the write operation preventing the global pull down device from discharging the global bit line.08-08-2013
20120063211METHOD FOR IMPROVING WRITABILITY OF SRAM MEMORY - A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.03-15-2012
20120092922SEMICONDUCTOR INTEGRATED CIRCUIT - Flip-flop memory cells are connected to a pair of bit lines and respectively to word lines. A word line driver outputs a word line selection pulse to one of the word lines in a word line selection period. A write circuit gives a potential difference corresponding to input data to the pair of bit lines after a start of the word line selection period. In a first operation mode, the potential difference of the pair of bit lines is reset in the word line selection period, and in the second mode, the potential difference of the pair of bit lines is reset after the word line selection period.04-19-2012
20130208533MEMORY HAVING READ ASSIST DEVICE AND METHOD OF OPERATING THE SAME - A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.08-15-2013
20130208534SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.08-15-2013

Patent applications in class Flip-flop (electrical)

Patent applications in all subclasses Flip-flop (electrical)