Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


Capacitors

Subclass of:

365 - Static information storage and retrieval

365129000 - SYSTEMS USING PARTICULAR ELEMENT

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
365150000 Inherent 1
20090122595SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.05-14-2009
Entries
DocumentTitleDate
20110176354SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other.07-21-2011
20110199814Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems - Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.08-18-2011
20110310659VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT - A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.12-22-2011
20100085800Semiconductor devices including buried gate electrodes and methods of forming semiconductor devices including buried gate electrodes - A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.04-08-2010
20110194332SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device capable of accurate data retention even with a memory element including a depletion mode transistor. A gate terminal of a transistor for controlling input of a signal to a signal holding portion is negatively charged in advance. The connection to a power supply is physically broken, whereby negative charge is held at the gate terminal. Further, a capacitor having terminals one of which is electrically connected to the gate terminal of the transistor is provided, and thus switching operation of the transistor is controlled with the capacitor.08-11-2011
20110194331SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source and drain electrodes of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a signal line connected to a capacitor as a reading signal line or a signal line connected to one of a source and drain electrodes of the reading transistor as a reading signal line so that a reading potential is supplied to the reading signal line, and then detecting a potential of the bit line.08-11-2011
20090122594SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power supply voltage according to an operation mode in response to the detection signal, and an enable control unit configured to control the driving unit in response to a control signal corresponding to the operation mode.05-14-2009
20100118596Embedded DRAM with bias-independent capacitance - An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed.05-13-2010
20100073994LEAKAGE COMPENSATION CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS - A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time.03-25-2010
20130077385SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.03-28-2013
20130077386Semiconductor Device And Driving Method Of The Same - An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.03-28-2013
20130033924CODE COVERAGE CIRCUITRY - A circuit includes a memory (02-07-2013
20130033926SEMICONDUCTOR MEMORY DEVICE HAVING BALANCING CAPACITORS - A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.02-07-2013
20130033925Semiconductor Device - An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.02-07-2013
20130083590SENSE AMPLIFIER USING REFERENCE SIGNAL THROUGH STANDARD MOS AND DRAM CAPACITOR - A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.04-04-2013
20130083589NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.04-04-2013
20130083587SEMICONDUCTOR DEVICE AND STRUCTURE - An Integrated device comprising a first monocrystalline layer comprising logic circuit regions and a second monocrystalline layer comprising memory regions constructed above first monocrystalline layer, wherein the memory regions comprise second transistors, wherein said second transistors comprise drain and source that are horizontally oriented with respect to the second monocrystalline layer, and a multiplicity of vias through the second monocrystalline layer providing connections between the memory regions and the logic circuit regions, wherein at least one of the multiplicity of vias have a radius of less than 100 nm.04-04-2013
20130083588MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT - In a memory element including a pair of inverters, a capacitor which holds data, and a switching element which controls accumulating and releasing of electric charge of the capacitor are provided. For example, one electrode of the capacitor is connected to a first node, which is an input or output terminal of one of the pair of inverters, and the other electrode of the capacitor is connected to one electrode the switching element. The other electrode of the switching element is connected to a second node, which is the output or input terminal of the one of the pair of inverters. With such a connection structure, the absolute value of the potential difference between the first node and the second node at the time of data restoring can be large enough, whereby errors at the time of data restoring can be reduced.04-04-2013
20120182791SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A memory circuit is included. The memory circuit includes n field-effect transistors (n is a natural number of 2 or more) and n capacitors each including a pair of electrodes. A digital data signal is input to one of a source and a drain of the first field-effect transistor. One of a source and a drain of the k-th field-effect transistor (k is a natural number of greater than or equal to 2 and less than or equal to n) is electrically connected to the other of a source and a drain of the (k−1)-th field-effect transistor. One of the pair of electrodes of the m-th capacitor (m is a natural number of n or less) is electrically connected to the other of a source and a drain of the m-th field-effect transistor of the n field-effect transistors. At least two of the n capacitors have different capacitance values.07-19-2012
20120182790SEMICONDUCTOR MEMORY DEVICE - The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.07-19-2012
20120182789MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND DETECTING METHOD - To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor.07-19-2012
20120182788STORAGE ELEMENT, STORAGE DEVICE, SIGNAL PROCESSING CIRCUIT, AND METHOD FOR DRIVING STORAGE ELEMENT - A storage element capable of retaining data even after supply of power supply voltage is stopped is provided. In the storage element retaining data in synchronization with a clock signal, with the use of a capacitor and a transistor having a channel in an oxide semiconductor layer, the data can be retained even after supply of power supply voltage is stopped. Here, when the transistor is turned off while the level of the clock signal is kept constant before the supply of power supply voltage is stopped, the data can be retained accurately in the capacitor. By applying such a storage element to each of a CPU, a memory, and a peripheral control device, supply of power supply voltage can be stopped in the entire system, so that the power consumption of the entire system can be reduced.07-19-2012
20130051126CAPACITORS, APPARATUS INCLUDING A CAPACITOR AND METHODS FOR FORMING A CAPACITOR - Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor; and the second conductor does not cover the portion of the first conductor not covered by the dielectric.02-28-2013
20090059653MULTI-PORT DYNAMIC MEMORY METHODS - A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line, and a write-read bypass device operatively coupled to the at least one write bit line and the at least one read bit line and configured to selectively pass a write signal from a write bit line signal point along the at least one write bit line to a read bit line signal point along the at least one read bit line for output to a data output. the output signal is selectively passed to the at least one write bit line. The write signal is selectively passed from the write bit line signal point along the at least one write bit line to the read bit line signal point along the at least one read bit line for output to the data output.03-05-2009
20100002493SEMICONDUCTOR STORAGE DEVICE - A precharge circuit precharges a bit line paired with the bit line to which the selected one of the memory cells is connected, by applying to the former bit line an external reference voltage for comparison with a voltage in the bit line caused by selection of the memory cell. A precharge assist circuit, which is connected to the former bit line in parallel with the precharge circuit, charges the bit line to a predetermined potential by using a power supply voltage. A sense amplifier, which is connected to the pair of bit lines, senses and amplifies a potential of a bit line that is connected to a memory cell selected by word lines.01-07-2010
20130088912SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first bit line to which a first memory cell is connected, and a second bit line to which a second memory cell is connected, the second bit line being complementary to the first bit line, a sense amplifier that includes a first transistor and a second transistor connected in series between the first bit line and the second bit line, the sense amplifier including a first node between the first transistor and the second transistor, a gate of the first transistor being connected to the second bit line, and a gate of the second transistor being connected to the first bit line, and a voltage providing unit that provides a first voltage to the first node during presensing, and provides a second voltage, different from the first voltage, to the first node during main sensing.04-11-2013
20100271864SEMICONDUCTOR DEVICE - A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.10-28-2010
20090268510DYNAMIC RANDOM ACCESS MEMORY CIRCUIT, DESIGN STRUCTURE AND METHOD - Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.10-29-2009
20090237981DYNAMIC MEMORY WORD LINE DRIVER SCHEME - A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels V09-24-2009
20090237980ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME - A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.09-24-2009
20090010042Semiconductor integrated circuit device - In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.01-08-2009
20090010041Hybrid DRAM - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors.01-08-2009
20120236629MULTI-LEVEL DRAM CELL USING CHC TECHNOLOGY - A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.09-20-2012
20120236630BYPASS CAPACITOR CIRCUIT AND METHOD OF PROVIDING A BYPASS CAPACITANCE FOR AN INTEGRATED CIRCUIT DIE - A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.09-20-2012
20090323399SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.12-31-2009
20110280061SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.11-17-2011
20100008129SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes first and second bit lines complementary to each other, sense amplifiers, memory cells, first and second switches, an equalizer circuit, and a potential generation unit. The potential generation unit supplies a first potential to at least a selected one of the plurality of first and second bit lines through the plurality of first and second switches. The equalizer circuit sets the first and second bit lines at the second potential. When an access to the memory cell connected to the first and second bit lines, the potential generation unit gives the first potential to the second bit line.01-14-2010
20110128777SEMICONDUCTOR DEVICE - The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.06-02-2011
20090207649VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY - A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.08-20-2009
20110286262Semiconductor memory device - A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines and the bit lines, a word line driver which drives the word lines, and a plurality of word line potential stabilization transistors connected to the respective word lines and disposed on an opposite side of the word line driver with the memory cell array sandwiched between the word line potential stabilization transistors and the word line driver, each word line potential stabilization transistor turning on when the word line adjacent to a relevant one of the word lines is selected, thereby connecting the relevant word line to a non-selected potential, and turning off when the relevant word line is selected.11-24-2011
20120099368METHOD FOR DRIVING SEMICONDUCTOR DEVICE - It is an object to obtain a memory element (DRAM) storing multilevel data easily. The amount of charge accumulated in a capacitor of a memory element (DRAM) is controlled by changing the potential of a wiring (a bit line), which is used for writing data to the memory element (DRAM), in a period in which a transistor included in the memory element (DRAM) is on. Thus, multilevel data stored in the memory element (DRAM) can be obtained without a complex configuration of a semiconductor device including the memory element (DRAM).04-26-2012
200902572732T SRAM CELL STRUCTURE - A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.10-15-2009
20110134683SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.06-09-2011
20110199816SEMICONDUCTOR DEVICE AND DRIVING METHOD OF THE SAME - An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.08-18-2011
20100142257SEMICONDUCTOR STORAGE DEVICE06-10-2010
20110205785SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor and the semiconductor device includes a potential conversion circuit which functions to output a potential lower than a reference potential for reading data from the memory cell. With the use of a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and capable of holding data for a long time can be provided.08-25-2011
20090067217Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same - In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.03-12-2009
20090147559MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.06-11-2009
20080266935DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE - In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors.10-30-2008
20100128514Semiconductor memory devices having bit lines - A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.05-27-2010
20120188814MEMORY DEVICE AND SEMICONDUCTOR DEVICE - To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the driver circuit. Each of memory cells included in the cell array includes a switching element, and a capacitor in which supply, holding, and discharge of electric charge are controlled by the switching element. Further, a channel formation region of the transistor used as the switching element includes a semiconductor whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon.07-26-2012
20100080043APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS - Embodiments of the invention generally related to arrangements of decoupling capacitor arrays in an integrated circuit. A decoupling capacitor array may include a plurality of bit lines that are electrically coupled to each other, a plurality of word lines that are electrically coupled to each other, and a plurality of decoupling capacitors, each decoupling capacitor coupled to a respective bit line and word line. The decoupling capacitor array may further include an access circuit electrically coupled to the plurality of word lines and a power grid, the access circuit being configured to either connect or disconnect the decoupling capacitor array to the power grid based on a control signal.04-01-2010
20120033487SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.02-09-2012
20120033484SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - The semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, the timing of potential change in a signal line is delayed relative to the timing of potential change in a write word line. This makes it possible to prevent a data writing error.02-09-2012
20120033483SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE - A memory cell includes a capacitor, a first transistor, and a second transistor whose off-state current is smaller than that of the first transistor. The first transistor has higher switching speed than the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected in series. Accumulation of charge in the capacitor and release of charge from the capacitor are performed through the first transistor and the second transistor. In this manner, the power consumption of the semiconductor device can be reduced and data can be written and read at higher speed.02-09-2012
20090207648MULTI-LEVEL DYNAMIC MEMORY DEVICE - A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.08-20-2009
20110176356SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.07-21-2011
20100080044SEMICONDUCTOR MEMORY DEVICE HAVING BALANCING CAPACITORS - According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.04-01-2010
20120294066SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor.11-22-2012
20120106235IMPLEMENTING PHYSICALLY UNCLONABLE FUNCTION (PUF) UTILIZING EDRAM MEMORY CELL CAPACITANCE VARIATION - A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.05-03-2012
20110170336DRAM Device and Manufacturing Method Thereof - The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.07-14-2011
20090201718DRAM including a tunable gain amp as a local sense amp - DRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a capacitor, and gain of the tunable gain amp is adjusted by setting a local amp voltage for reading the memory cell more effectively with optimized gain. And a global sense amp is connected to the local sense amp for receiving a read output. When reading data, a voltage difference in the local bit line is converted to a time difference by the sense amps for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as a reference signal. In addition, alternative circuits are described.08-13-2009
20090296453Semiconductor Memory Apparatus - A semiconductor memory apparatus includes a unit cell with a transistor having a floated body and a capacitor for storing charges; a word line for activating the unit cell; and a bit line for transmitting data to the unit cell.12-03-2009
20090103352DRAM including a reduced storage capacitor - A reduced storage capacitor is used for shrinking a memory cell in DRAM, and local bit line is divided into short line for reducing parasitic capacitance. For reading, a first reduced swing amplifier as a local sense amp reads the memory cell through the local bit line, and a second reduced swing amplifier as a global sense amp reads the local sense amp through a global bit line. With the multi-stage sense amps, time domain sensing scheme is realized such that a voltage difference in the local bit line is converted to a time difference, for differentiating high data and low data, and also fast read operation is realized. And write operation is executed by a reduced swing write driver. With reduced voltage swing, pseudo negative word line scheme is realized for retaining data, and power consumption is reduced. In addition, various alternative circuits and memory cell structures are implemented.04-23-2009
20090103351Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module - According to one embodiment of the present invention, an integrated circuit includes at least one memory device including: a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer being disposed between the reactive electrode layer and the inert electrode layer; at least one interface layer being disposed between the solid electrolyte layer and the reactive electrode layer and/or between the solid electrolyte layer and the inert electrode layer. The material parameters of the at least one interface layer are chosen such that a crystallization of the solid electrolyte layer is at least partially suppressed.04-23-2009
20120294068MEMORY DEVICE AND SIGNAL PROCESSING CIRCUIT - A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a second node, a third node, and a fourth node; a first control circuit connected to the first node, the second node, and the third node; a second control circuit connected to the first node, the second node, and the fourth node; a first memory circuit connected to the first node, the first control circuit, and the second control circuit; and a second memory circuit connected to the second node, the first control circuit, and the second control circuit.11-22-2012
20120294069SIGNAL PROCESSING CIRCUIT - A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit including data latch terminals, a first non-volatile memory circuit electrically connected to one of the data latch terminals, a second non-volatile memory circuit electrically connected to the other of the data latch terminals, and a precharge circuit having a function of supplying a potential that is a half of a high power supply potential to the one and the other of the data latch terminals. Each of the first non-volatile memory circuit and the second non-volatile memory circuit includes a transistor having a channel formation region including an oxide semiconductor and a capacitor connected to a node that is brought into a floating state by turning off the transistor.11-22-2012
20120294067SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - In a semiconductor device performing pipeline processing with the use of a reading portion reading an instruction and an arithmetic portion performing an operation in accordance with the instruction, the instruction held in the reading portion is transmitted from the flip-flop to the memory when branch prediction turns out to be wrong. Note that the arithmetic portion controls transmission and reception of the instruction between the flip-flop and the memory which are included in the reading portion. This enables elimination of redundant operations in the reading portion in the case where an instruction read by the reading portion after the branch prediction turns out to be wrong is a subroutine, or the like. That is, the instruction held in the memory is transmitted back to the flip-flop without rereading of the same instruction by the reading portion, whereby the instruction can be output to the arithmetic portion.11-22-2012
20100128515SEMICONDUCTOR MEMORY - A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin.05-27-2010
20080278991SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line.11-13-2008
20080291717SEMICONDUCTOR STORAGE DEVICE INCORPORATED INTO A SYSTEM LSI WITH FINER DESIGN RULES - In the present invention, a row decoder circuit is made up of a transistor having a first gate oxide film thickness, a transistor having a second gate oxide film thickness, and a transistor having a third gate oxide film thickness. Thus even a control circuit at a lower voltage can drive word lines at high speeds while achieving reliability.11-27-2008
20080239789SEMICONDUCTOR MEMORY DEVICE - The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.10-02-2008
20120287701SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A memory device with low power consumption and a signal processing circuit including the memory device are provided. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a capacitor which holds data, and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For example, one of electrodes of the capacitor is connected to an input terminal or an output terminal of the phase-inversion element, and the other electrode is connected to a switching element. The above memory element is used for a memory device such as a register or a cache memory in a signal processing circuit.11-15-2012
20080212360PERSISTENT VOLATILE MEMORY CELL - A persistent volatile memory cell memorizes a binary datum during a retention time independent from a supply voltage of the memory cell. The memory cell comprises a capacitive memory point supplying a persistent voltage and having a determined discharge time, a switch for triggering the discharge of the memory point when an erase signal has an active value, a switch for triggering the charge of the memory point when a write signal has an active value, and a sense-amplifier circuit having an input receiving the persistent voltage, and an output supplying the binary datum. The memory cell can be applied to the management of an inventory flag in a contactless integrated circuit.09-04-2008
20080205120Multiple layer random accessing memory - The present invention provides a new semiconductor Random Access Memory, RAM which stores multiple bits per cell. When writing data, at least three levels of voltage sources are generated to charge the bit line and the RAM capacitive device through the selective devices. During reading data, at least three referencing voltage sources are input to at least three sense amplifiers to differentiate at least four levels of bit line voltages and convert the differential levels to at least two logic bits.08-28-2008
20090003038Capacitor supported precharching of memory digit lines - Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit.01-01-2009
20090161409CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic.06-25-2009
20090080235COMPACT AND HIGHLY EFFICIENT DRAM CELL - A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.03-26-2009
20120069635CAPACITY AND DENSITY ENHANCEMENT CIRCUIT FOR SUB-THRESHOLD MEMORY UNIT ARRAY - A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.03-22-2012
20120069634SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INSPECTING THE SAME - When the threshold voltage V03-22-2012
20090097301SEMICONDUCTOR STORAGE APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT INCORPORATING THE SAME - An object is to provide a semiconductor memory device which can dynamically change the number of memory cells used as by-pass capacitors. In each memory block, one selector signal line is provided in parallel to one word line. In a pair of the word line and the selector signal line adjacent to each other, states are maintained opposite to each other. Further, in a memory block, one branch of a supply line is provided in parallel to one bit line. In each of the memory cells, a first transistor connects a capacitor to the bit line in accordance with the state of the word line. Furthermore, a second transistor connects the same capacitor to the branch of the supply line in accordance with the state of the selector signal line. In the memory cells aligned in a row direction, gates of the first transistors are connected to the same word line, and gates of the second transistors are connected to the same selector signal line.04-16-2009
20090080234SEMICONDUCTOR DEVICE AND DRAM CONTROLLER - According to a semiconductor device of the present invention, a differential potential between a sense amplification level and a precharge level of a sense amplifier is set to a power supply potential (VCC-GND) so as to improve resistance against degradation of hold characteristics. Further, low power consumption can be realized along with the improvement. Additionally, the precharge level is set to a power supply of GND or VCC so as to realize a stable supply of the precharge level. Further, a chip size can be reduced since a power supply circuit for precharge is not needed.03-26-2009
20110141795MULTI-PORT MEMORY BASED ON DRAM CORE - A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.06-16-2011
20090103353SEMICONDUCTOR MEMORY DEVICE - Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.04-23-2009
20090244954STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS - A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).10-01-2009
20090251947Semiconductor device having single-ended sensing amplifier - A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.10-08-2009
20090251946DATA CELLS WITH DRIVERS AND METHODS OF MAKING AND OPERATING THE SAME - Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.10-08-2009
20090251948SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.10-08-2009
20100149854SEMICONDUCTOR DEVICE STORAGE CELL STRUCTURE, METHOD OF OPERATION, AND METHOD OF MANUFACTURE - A method of fabricating an integrated circuit device storage cell may include forming a channel region comprising a semiconductor material doped to a first conductivity type; forming a store gate structure comprising a semiconductor material doped to a second conductivity type in contact with the channel region; and forming a control gate terminal from at least a portion of a semiconductor layer deposited on a substrate surface in contact with the channel region, the portion of the semiconductor layer being doped to the second conductivity type.06-17-2010
20100149855INTEGRATED CIRCUITRY FOR SEMICONDUCTOR MEMORY - Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.06-17-2010
20100157660MULTIPLE-VALUED DRAM - Provided herein is an MV DRAM device capable of storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, wherein the gate of the transistor is connected to the ground voltage. According to the MV DRAM device of the present invention, since two or more multiple value data are stored in a cell, it is possible to increase the storage density of the device. In addition, since the MV DRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application.06-24-2010
20100182822DEVICE AND METHOD FOR USING DYNAMIC CELL PLATE SENSING IN A DRAM MEMORY CELL - A memory cell, device, system and method for operating a memory cell utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pass transistor and second capacitor are each configured in series for individual respective coupling between a first digit line and a second digit line. The first and second pass transistors are further configured for respective control by first and second wordlines. The memory cell further includes an interconnection formed on a cell plate conductor between a terminal end of the first capacitor and a terminal end of the second capacitor. Furthermore, the interconnection is electrically isolated from other portions of the cell plate conductor.07-22-2010
20120140550INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE - An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.06-07-2012
20100002494Memory Device with Memory Cell Including MuGFET and FIN Capacitor - One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.01-07-2010
20120195102NANO-ELECTRO-MECHANICAL DRAM CELL - A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.08-02-2012
20100149853THIN FILM CAPACITOR, AND DISPLAY DEVICE AND MEMORY CELL EMPLOYING THE SAME, AND MANUFACTURING METHODS OF THEM - A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (06-17-2010
20100214823SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CAPACITOR - A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.08-26-2010
20120195104SEMICONDUCTOR MEMORY DEVICE - The capacitance of a capacitor that is required in a DRAM is reduced, whereby a highly integrated DRAM is provided. In a divided bit line type DRAM, a sub bit line is formed below a word line and a bit line is formed above the word line. The parasitic capacitance of the sub bit line is reduced by employing the divided bit line method, and further, the off resistance of a cell transistor is set high according to need; thus, the capacitance can be one tenth or less of that of a conventional DRAM. Accordingly, even when a stacked capacitor is employed, the height of the capacitor can be one tenth or less of that of a conventional one, so that a bit line can be easily provided thereover. Further, by devising a structure of the cell transistor, the area per memory cell can be reduced to 4 F08-02-2012
20120195103SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY BIT LINE PAIR - Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.08-02-2012
20100254179DRAM including pseudo negative word line - For increasing retention time in DRAM, pseudo negative word line scheme is realized such that voltage of a local bit line pair is always higher than that of an unselected word line for applying negative gate voltage, but selected word line is asserted to a pre-determined voltage. For implementing the scheme, swing voltage of the local bit line pair is limited by a write path connecting to a global bit line pair when writing, and the local bit line pair is also limited when reading, because selected local bit line is slightly changed with charge re-distribution and unselected local bit line is at floating state. For minimizing sensing current, a locking signal is generated to cut off a current path from the global bit line pair to a local sense amp. And various alternative circuits are described for implementing the pseudo negative word line scheme.10-07-2010
20110058407SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array that includes a plurality of memory cells having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that switches the number of memory cells, for use in storage of data of 1 bit in a normal operation state, to m (m is a natural number) and switches the number of memory cells, for use in storage of data of 1 bit in a standby state, to n (n is a natural number larger than m); and a substrate potential control circuit that controls the substrate potential in the normal operation state to a first substrate potential and controls the substrate potential in the standby state to a second substrate potential (the second substrate potential>the first substrate potential).03-10-2011
20100039852Dynamic Memory Cell Methods - A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.02-18-2010
20100118597Multiple valued dynamic random access memory cell and thereof array using single electron transistor - Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET.05-13-2010
20090073743Method of Manufacturing a Memory Cell, Memory Cell, Integrated Circuit, and Memory Module - A method of fabricating a memory cell including a solid electrolyte layer doped with metallic material and an electrode layer arranged above the solid electrolyte layer. The method includes doping a solid electrolyte layer with metallic material and forming an electrode layer above the solid electrolyte layer, wherein doping the solid electrolyte layer is carried out before forming the electrode layer.03-19-2009
20090073744Semiconductor storage device - A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the second voltage being a non-selected voltage, a voltage difference between the first voltage and the second voltage is larger than a voltage difference between a power supply voltage and a ground voltage, and one of the ground voltage and the power supply voltage which is closer to the non-selected voltage is applied to a back gate of the transistor irrespective of selection or non-selection.03-19-2009
20100315858MEMORY ARCHITECTURE WITH A CURRENT CONTROLLER AND REDUCED POWER REQUIREMENTS - Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled current source in each memory bit cell is electrically connected to the read bit line through the read switch. The current from the current controller that controls and changes the read bit line voltage flows through the controlled current source in the memory bit cell. The value of this current is determined by a function of a difference between the voltage on the storage mechanism in the memory bit cell and a reference voltage from a reference voltage input to the current controller. In some versions an indicator is provided for indicating when to stop the current in the controlled current source that controls a voltage change on one of the read bit lines. The indicator has an on and an off condition and a switch is provided for stopping the current in the controlled current source when the indicator is activated in the on condition. The current in the controlled current source is stopped when the voltage change on the read bit line is greater than a predetermined threshold.12-16-2010
20100321983SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS - A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.12-23-2010
20100321984CONFIGURATION RANDOM ACCESS MEMORY - Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.12-23-2010
20110110145SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.05-12-2011
20100165704Circuit and Method for a High Speed Memory Cell - A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.07-01-2010
20110002159Semiconductor integrated circuit device - Provided are a memory array excellent in noise characteristics and small in size and a semiconductor integrated circuit device having such a memory array.01-06-2011
20120243299POWER EFFICIENT DYNAMIC RANDOM ACCESS MEMORY DEVICES - The present invention provides methods and structures for improving refresh power efficiency of dynamic random access memory devices. By measuring charge retention properties of reference cells that have substantially the same structures as normal DRAM memory cells, the refresh rate of DRAM devices can be adjusted with better reliability. The reliability is further improved by using ECC circuits and/or field programmable redundancy circuits.09-27-2012
20100220514STORAGE DEVICES WITH SOFT PROCESSING - A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.09-02-2010
20090040810SWITCHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS - A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.02-12-2009
20100054022Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material - In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.03-04-2010
20100054024CIRCUIT FOR READING A CHARGE RETENTION ELEMENT FOR A TIME MEASUREMENT - A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and a transistor with insulated control terminal for reading the residual charges, the reading circuit including; two parallel branches between two supply terminals, each branch including at least one transistor of a first type and one transistor of a second type, the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal, the respective drains of the transistors of the first type being connected to the respective inputs of a comparator whose output provides an indication of the residual voltage in the charge retention element.03-04-2010
20100054021Memory Device with Multiple Capacitor Types - An integrated circuit includes a memory array portion and a support circuitry portion arranged on a semiconductor substrate. An insulative layer is formed on the semiconductor substrate. Data storage capacitors are located in the memory array portion and extending through the insulative layer. Non-data storage capacitors are located in the support circuitry portion and terminating above the insulative layer.03-04-2010
20110176357SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING THE SAME - It is an object to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed and a signal processing circuit including the memory device. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a capacitor which holds data and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. The memory element is applied to a memory device such as a register or a cache memory included in a signal processing circuit.07-21-2011
20100135065POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.06-03-2010
20100135064SWITCH AND METHOD OF FORMING THE SAME - A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.06-03-2010
20110249488Data Cells with Drivers and Methods of Making and Operating the Same - Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.10-13-2011
20110249487SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device or a semiconductor device which has high reading accuracy is provided. A bit line, a word line, a memory cell placed in an intersection portion of the bit line and the word line, and a reading circuit electrically connected to the bit line are provided. The memory cell includes a first transistor and an antifuse. The reading circuit includes a pre-charge circuit, a clocked inverter, and a switch. The pre-charge circuit includes a second transistor and a NAND circuit. The semiconductor memory device includes transistor in each of which an oxide semiconductor is used in a channel formation region, as the first transistor and the second transistor.10-13-2011
20090109731DIELECTRIC LAYERS AND MEMORY CELLS INCLUDING METAL-DOPED ALUMINA - A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.04-30-2009
20120201071SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.08-09-2012
20120033486SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed.02-09-2012
20120033485SEMICONDUCTOR DEVICE - In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.02-09-2012
20120170356Semiconductor Memory Device with Hierarchical Bitlines - A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines. As a result, the local bitlines with higher per-length capacitance can be made shorter, since the global bitline with lower per-length capacitance is used to route the signal from the cell capacitances of the memory cells to the remote sense amplifiers.07-05-2012
20120170355STORAGE ELEMENT, STORAGE DEVICE, AND SIGNAL PROCESSING CIRCUIT - A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.07-05-2012
20120170354Apparatus and a method - An apparatus including a first electrode; a second electrode including graphene; and a dielectric between the first electrode and the second electrode; input circuitry configured to change a charge state of the dielectric by causing electric charges to be trapped in the dielectric; and output circuitry configured to detect a value dependent upon a quantum capacitance of the graphene of the second electrode, wherein the quantum capacitance of the graphene is dependent upon the charge state of the dielectric.07-05-2012
20110255332SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to the first bit line; a second memory cell connected to the second bit line; a first reference cell acting as the reference cell; a second reference cell acting as another reference cell; a potential line that supplies the reference potential to the first and second reference cells; and a dummy cell comprising a coupling capacitor that stabilizes potential of the potential line.10-20-2011
20120147661DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines.06-14-2012
20100110772Semiconductor memory device having bit line disturbance preventing unit - A read data path circuit for use in the semiconductor memory device includes a bit line sense amplifier, a local input/output line sense amplifier, a column selection unit operationally coupling a bit line pair with the local input/output line pair in response to a column selection signal, where the bit line pair is coupled to the bit line sense amplifier and the local input/output line pair is coupled to the local input/output line sense amplifier, and a bit line disturbance preventing unit configured to equalize signal levels of the local input/output line pair before the column selection signal is activated, and configured to sense and amplify signal levels of bit line data transferred to the local input/output line pair after the column selection signal is activated.05-06-2010
20100067284Semiconductor Memory Device - A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.03-18-2010
20110188295High Performance eDRAM Sense Amplifier - Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell.08-04-2011
20110176355SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.07-21-2011
20090175066High-speed DRAM including hierarchical read circuits - DRAM includes hierarchical read circuits with multi-divided bit lines, wherein a local read circuit receives an output from a memory cell through a bit line, a segment read circuit receives an output from one of multiple local read circuits through a segment read line, and a block read circuit receives an output from one of multiple segment read circuits through a block read line. Thus a voltage difference is converted to a time difference by the read circuits. In this manner, a time-domain sensing scheme is realized to differentiate high data and low data. For instance, high data is quickly transferred to a latch circuit through the read circuits with high gain, but low data is rejected by a locking signal based on high data as a reference signal. Additionally, various alternatives are described. And structures for the memory cell and layouts for the read circuits are illustrated.07-09-2009
20100232212SPLIT-GATE DRAM WITH LATERAL CONTROL-GATE MUGFET - A semiconductor structure of an array of dynamic random access memory cells. The structure includes: a first fin of a first split-gate fin-type field effect transistor (FinFET) device on a substrate; a second fin of a second split-gate fin-type field effect transistor (FinFET) device on the substrate; and a back-gate associated with the first fin and the second fin. The back-gate influences a threshold voltage of the first fin and a threshold voltage of the second fin.09-16-2010
20100226166MOS capacitor and charge pump with MOS capacitor - A MOS capacitor in a charge pump includes a MOS device with at least one body bias region and a device body of a same conductivity type for providing maximum capacitance over a wide voltage range. The MOS capacitor also includes a gate forming a first terminal of the MOS capacitor, and the at least one body bias region forms a second terminal of the MOS capacitor. The MOS capacitor further includes a multiple-well structure formed with the device body and a deep well in a substrate for enhanced noise immunity.09-09-2010
20120039114Memcapacitor - A memcapacitor device (02-16-2012
20110063892SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.03-17-2011
20110063891SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR SYSTEM - A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.03-17-2011
20110317474SEMICONDUCTOR DEVICE - A semiconductor device includes a source line, a bit line, and first to m-th (m is a natural number) memory cells connected in series between the source line and the bit line. Each of the first to m-th memory cells includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal, a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, and a capacitor. The node of the k-th memory cell is supplied with a potential higher than that of the second gate terminal of the k-th memory cell in a data holding period in which the second gate terminal is supplied with a potential at which the second transistor is turned off.12-29-2011
20110317475ELECTRONIC DEVICE - To suppress a timing window from being narrowed undesirably by the harmonic component of a signal output from a semiconductor component without imposing a burden on the semiconductor component that controls access.12-29-2011
20120044752HIGH DENSITY INTEGRATED CIRCUITRY FOR SEMICONDUCTOR MEMORY - Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells.02-23-2012
20120057395SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a cell block including a plurality of cell mats having a plurality of word lines and a plurality of bit lines perpendicular to the plurality of word lines, a cell plate electrode formed over a whole area of the cell block, and a plate power mesh line including a first plate power mesh line electrically connected to the cell plate electrode while extending in a direction parallel to the word lines, and a second plate power mesh line extending in a direction parallel to the bit lines. The first plate power mesh line includes at least one cutting part.03-08-2012
20120008375CMOS IMAGE SENSOR WITH NOISE CANCELLATION - A memory comprises a two dimensional array of memory cells. Each memory cell comprises a first transistor, a second transistor and a capacitor. A multi-bit datum is stored as one of a plurality of voltage signal levels driven over a vertical input signal line and further across a source and a drain of the first transistor to be stored onto a gate of the second transistor. The first transistor is selected by a horizontal WR control line. The gate of the second transistor is connected to a first terminal of the capacitor. A second terminal of the capacitor is connected to a horizontal RD control line. The RD control line is driven to couple the second transistor to drive a signal onto a vertical output signal line during a read of the stored signal on the gate.01-12-2012
20110080771DRAM POSITIVE WORDLINE VOLTAGE COMPENSATION DEVICE FOR ARRAY DEVICE THRESHOLD VOLTAGE AND VOLTAGE COMPENSATING METHOD THEREOF - The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage feedback signal, a second input terminal receiving a compensating reference of array device threshold voltage and an output terminal generating a first enable signal, an oscillator receiving the first enable signal and generating an oscillating signal when the first enable signal is active and a charge pump having a first input terminal receiving a second enable signal, a second input terminal receiving the oscillating signal and an output terminal generating a positive wordline voltage being a sum of a bitline high voltage, an array device threshold voltage and a voltage margin.04-07-2011
20120155150SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.06-21-2012
20120057397METHOD FOR DRIVING SEMICONDUCTOR DEVICE - In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. The potential of a bit line is detected while data writing is conducted, and thereby whether a potential corresponding to the written data is normally applied to the floating gate can be confirmed without a writing verify operation.03-08-2012
20120063207SEMICONDUCTOR DEVICE - An object of one embodiment of the present invention is to miniaturize a semiconductor device. Another object of one embodiment of the present invention is to reduce the area of a driver circuit of a semiconductor device including a memory element. A plurality of cells in which the positions of input terminals and output terminals are fixed is arranged in a first direction, wirings each of which is electrically connected to the input terminal or the output terminal of each cell are stacked over the plurality of cells, and the wirings extend in the same direction as the first direction in which the cells are arranged; thus, a semiconductor device in which a driver circuit is miniaturized is provided.03-15-2012
20120063205SEMICONDUCTOR DEVICE - A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.03-15-2012
20120063209MEMORY DEVICE AND SEMICONDUCTOR DEVICE - An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.03-15-2012
20120063208MEMORY DEVICE - In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.03-15-2012
20120014170Capacitive Crossbar Arrays - A capacitive crossbar array (01-19-2012
20120057396SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is provided with both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small) and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed). The peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion; thus, the area and size of the semiconductor device can be decreased.03-08-2012
20120113707SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.05-10-2012
20120063203DRIVING METHOD OF SEMICONDUCTOR DEVICE - A driving method of a semiconductor device is provided. In a semiconductor device including a bit line, a selection line, a selection transistor, m (m is a natural number greater than or equal to 2) writing word lines, m reading word lines, a source line, and first to m-th memory cells, each memory cell includes a first transistor and a second transistor that holds charge accumulated in a capacitor. The second transistor includes a channel formed in an oxide semiconductor layer. In a driving method of a semiconductor device having the above structure, when writing to a memory cell is performed, the first transistor is turned on so that a first source terminal or a first drain terminal is set to a fixed potential; thus, a potential is stably written to the capacitor.03-15-2012
20120063204SEMICONDUCTOR DEVICE - One object is to provide a novel semiconductor device which can hold stored data even when not powered and which has an unlimited number of writing operations. Another object is to reduce a circuit size and to improve reliability of writing and reading of data. When a memory cell using a transistor including an oxide semiconductor layer is subjected to the verification operation and reading of data, a dual-gate transistor showing different threshold voltages is used as a resistor; thus, stable verification operation and reading operation can be performed by only a reference potential circuit.03-15-2012
201200632023T DRAM CELL WITH ADDED CAPACITANCE ON STORAGE NODE - A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a second control element connected to a read word line. The 3T DRAM cell also includes a third transistor connected between the storage node and a write bit line having a third control element connected to a write word line. Additionally, the DRAM cell includes a supplemental capacitance connected to the storage node and configured to extend a refresh interval of the 3T DRAM cell. A method of operating an integrated circuit having a 3T DRAM cell includes providing a memory state on a storage node of the 3T DRAM cell and extending a refresh interval of the memory state with a supplemental capacitance added to the storage node.03-15-2012
20110103136SEMICONDUCTOR MEMORY DEVICE - A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.05-05-2011
20100091554SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THEREOF - A semiconductor device includes: a memory cell; a precharge circuit; a negative potential applying circuit; and a sense amplifier. The memory cell is connected to a first bit line and store data. The precharge circuit is connected to the first and second bit lines and precharges the first and second bit lines to a ground potential. The negative potential applying circuit is connected to the first bit line and applies a negative potential to the first bit line. The sense amplifier is connected to the first and second bit lines and read data based on a difference between a first potential of the first bit line and a second potential of the second bit line. An absolute value of the negative potential is smaller than the difference between the first potential and the second potential.04-15-2010
20120250397SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output from the first memory circuit, and during a part of a period when source voltage is supplied, which is before the supply of the source voltage is stopped, a data signal is input to the second memory circuit. In the case of low-frequency driving, during a period when source voltage is applied, a data signal is input to the second memory circuit, the data signal input to the second memory circuit is input to the first memory circuit, and the data signal input to the first memory circuit is output.10-04-2012
20120120715SEMICONDUCTOR DEVICE - Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines.05-17-2012
20100290268MEMORY CELL, PAIR OF MEMORY CELLS, AND MEMORY ARRAY - A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.11-18-2010
20100290267SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the plate line to a first power supply line when an access to the memory cell array is caused.11-18-2010
20120314484Multilevel DRAM - A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.12-13-2012
20120127781SEMICONDUCTOR MEMORY DEVICE - To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.05-24-2012
20100214822VOLTAGE-STEPPED LOW-POWER MEMORY DEVICE - This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process.08-26-2010
20120218811Circuit - An object of the current invention is to provide DRAM that is not limited by capacitors.08-30-2012
20110182111ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME - A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.07-28-2011
20110182110SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.07-28-2011
20090257272REDUCED SIZE CHARGE PUMP FOR DRAM SYSTEM - A memory system includes: a memory array, comprising a plurality of memory banks, respectively enabled by a plurality of bank enable signals; a bank selector circuit, for generating the plurality of bank enable signals; a plurality of charge pump components, coupled between the plurality of memory banks and the bank selector circuit, and respectively enabled by the plurality of bank enable signals; and a charge pump circuit, coupled to the plurality of charge pump components, for regulating a supply voltage required by the memory system.10-15-2009
20120212995PROGRAMMABLE LSI - A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.08-23-2012
20110199815Memcapacitor Devices, Field Effect Transistor Devices, Non-Volatile Memory Arrays, And Methods Of Programming - A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes. The semiconductive material and the barrier dielectric material are of different composition relative one another which is at least characterized by at least one different atomic element. One of the semiconductive material and the barrier dielectric material is closer to one of the pair of electrodes than is the other of the semiconductive material and the barrier dielectric material. The other of the semiconductive material and the barrier dielectric material is closer to the other of the pair of electrodes than is the one of the semiconductive material and the barrier dielectric material. Other implementations are disclosed, including field effect transistors, memory arrays, and methods.08-18-2011
20120075917SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m03-29-2012
20120314483SEMICONDUCTOR DEVICE - A semiconductor device includes a bit line, a memory cell, and a control circuit. The memory cell includes a switch circuit coupled to the bit line and a memory element configured to store either one of first and second data. The control circuit controls a voltage of the bit line to turn on the switch element in a first time period and to turn off the switch element in a second time period following the first time period when the control circuit writes the first data to the memory element. The control circuit controls the voltage of the bit line to turn on the switch element in the first time period and to maintain an on-state of the switch circuit in the second time period when the control circuit writes the second data to the memory element.12-13-2012
20120314482SEMICONDUCTOR MEMORY DEVICE - An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained.12-13-2012
20120188815TEMPORARY STORAGE CIRCUIT, STORAGE DEVICE, AND SIGNAL PROCESSING CIRCUIT - A temporary storage circuit including a reduced number of transistors is provided. The temporary storage circuit includes storage elements, each of which includes a first transistor and a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A signal potential corresponding to data is input to a gate of the second transistor through the first transistor which is turned on by a control signal input to a gate of the first transistor. Then, the first transistor is turned off by a control signal input to the gate of the first transistor, so that the signal potential is held in the gate of the second transistor. When one of a source and a drain of the second transistor is set to a first potential, the state between the source and the drain of the second transistor is detected, whereby the data is read out.07-26-2012
20120262982MEMORY DEVICE AND DRIVING METHOD OF THE MEMORY DEVICE - A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching element is designed so that the off-state current is sufficiently low. Therefore, even when power supply of the inverter is stopped after charge corresponding to data is stored in the capacitor, data can be held for a long period of time. In order to return data, potentials of output and input terminals of the inverter are set to a precharge potential, then charge in the capacitor is released, and power is supplied to the inverter. A switching element for supplying the precharge potential may be provided.10-18-2012
20120257440MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT - An object is to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed, and a signal processing circuit including the memory device. In a memory element including a phase-inversion element such as an inverter or a clocked inverter, a capacitor which holds data and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For the above switching element, a transistor including amorphous silicon, polysilicon, microcrystalline silicon, or a compound semiconductor such as an oxide semiconductor in a channel formation region is used. The channel length of the transistor is ten times or more as large as the minimum feature size or greater than or equal to 1 μm. The above memory element is used for a memory device such as a register or a cache memory in the signal processing circuit.10-11-2012
20120257439MEMORY DEVICE AND SEMICONDUCTOR DEVICE USING THE SAME - A memory device whose speed at the time of operation such as writing or reading is high and whose number of semiconductor elements per memory cell is small is provided. The memory device includes a control unit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from a main memory device and/or the arithmetic unit, in accordance with an instruction from the control unit. The buffer memory device includes a plurality of memory cells. The memory cells each include a transistor including a channel formation region including an oxide semiconductor, and a memory element to which charge with an amount in accordance with a value of the data is supplied through the transistor. Further, a data retention time of the memory cell corresponding to a valid bit is shorter than a data retention time of the memory cell corresponding to a data field.10-11-2012
20120081948SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a conventional DRAM, errors in reading data are likely to occur when the capacitance of a capacitor is reduced. A plurality of cells is connected to one main bit line Each cell includes a sub bit line and 2 to 32 memory cells. Further, each cell includes a selection transistor and a reading transistor, and a sub bit line is connected to a gate of the reading transistor. Since the parasitic capacitance of the sub bit line is sufficiently small, data of electric charge of a capacitor of each memory cell can be amplified without an error in the reading transistor and output to the main bit line.04-05-2012
20120320663MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A memory device with low power consumption is provided. A memory device includes a first logic element generating an output potential by inverting a polarity of a potential of a signal including data in accordance with a first clock signal; second and third logic elements holding the output potential generated by the first logic element; a switching element including a transistor; and a capacitor storing the data by being supplied with the output potential of the first logic element which is held by the second and third logic elements via the switching element. The second logic element generates an output potential by inverting a polarity of an output potential of the third logic element in accordance with a second clock signal different from the first clock signal, and the third logic element generates an output potential by inverting a polarity of the output potential of the second logic element.12-20-2012
20120268982METHODS AND APPARATUS OF STACKING DRAMS - Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.10-25-2012
20100232213CONTROL SIGNAL TRANSMITTING SYSTEM OF A SEMICONDUCTOR DEVICE - Exemplary embodiments relate to a control signal driving device of a semiconductor device, including: a bus line; a converter receiving a first periodic control signal having the period (frequency) of a clock signal, converting the first periodic control signal into a converted control signal that has twice the period (half the frequency) of the clock signal, and outputting the converted control signal to the bus line; and a restoring unit connected to the opposite end of the bus line and receiving the converted control signal and restoring the converted control signal back into the first periodic control signal.09-16-2010
20120087178SEMICONDUCTOR MEMORY DEVICE - Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.04-12-2012
20120087177SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING - A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.04-12-2012
20120087176DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.04-12-2012
20120287699SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.11-15-2012
20120287700GAIN CELL SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten.11-15-2012
20120287703SEMICONDUCTOR DEVICE - When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.11-15-2012
20120287702MEMORY CIRCUIT AND ELECTRONIC DEVICE - To provide a nonvolatile memory circuit having a novel structure. A first memory circuit, a second memory circuit, a first switch, a second switch, and a phase inverter circuit are included. The first memory circuit includes a first transistor formed using an oxide semiconductor film, a second transistor, a third transistor, and a capacitor. The first transistor formed using an oxide semiconductor film and the capacitor are used to form the nonvolatile memory circuit. Reductions in number of power supply lines and signal lines which are connected to the memory circuit and transistors used in the memory circuit allow a reduction in circuit scale of the nonvolatile memory circuit.11-15-2012
20100202190COMPACT AND HIGHLY EFFICIENT DRAM CELL - A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node,08-12-2010
20100202189SEMICONDUCTOR MEMORY DEVICE HAVING A DISCHARGE PATH GENERATOR FOR GLOBAL I/O LINES - A data path circuit includes a bit line sense amplifier, a local input/output line precharger connected to a local input/output line pair, a global input/output line precharger connected to a global input/output line pair, a column selector connecting a bit line pair connected to the bit line sense amplifier and the local input/output line pair to each other in response to a column selection signal, and a local input/output line selector connecting the local input/output line pair and the global input/output line pair to each other in response to a multiplexing control signal. A discharge path generator decreases the potential on the global input/output line pair down to a predetermined level in response to a data masking control signal which is activated earlier than the column selection signal during a data masking operation mode.08-12-2010
20110157962BIAS SENSING IN DRAM SENSE AMPLIFIERS THROUGH VOLTAGE-COUPLING/DECOUPLING DEVICE - Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.06-30-2011
20110157961SEMICONDUCTOR DEVICE - The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.06-30-2011
20100054023CHARGE STORAGE CIRCUIT, VOLTAGE STABILIZER CIRCUIT, METHOD FOR STORING CHARGE USING THE SAME - A charge storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a corresponding word line among the word lines and connected to a corresponding bit line among the bit lines. Each of the memory cells includes a transistor turned on in response to a predetermined voltage of the corresponding word line and connected to the corresponding bit line, and a capacitor having one end connected to the transistor and the other end connected to the corresponding word line.03-04-2010
20090067218Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same - An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) and (ii) sense amplifier circuitry, coupled to the memory cell array, to sense a data state stored in one of the memory cells during a sense phase of operation. In one embodiment, the sense amplifier circuitry includes first and second capacitors, a first input electrically coupled to (i) the memory cell to receive a signal which is representative of the data state stored therein and (ii) a first terminal of the first capacitor, and a second input electrically coupled to (i) a first predetermined voltage and (ii) a first terminal of the second capacitor. The sense amplifier circuitry further includes a current source and a transistor wherein the gate of the transistor is electrically coupled to the second terminals of the first and second capacitors, and a first region of the transistor is electrically coupled to the current source.03-12-2009
20130170286DECOUPLING CAPACITANCE CALIBRATION DEVICES AND METHODS FOR DRAM - A decoupling capacitance (decap) calibration device includes a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power supply and logic circuitry. The plurality of capacitors exhibit a plurality of different capacitance values and are configured to independently turn on or off according to a plurality of inputs. Decap calibration circuitry is configured to update the plurality of inputs in response to a determination signal. A voltage detector is configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage. The decap calibration device is configured to generate the determination signal in response to the voltage comparison.07-04-2013
20130176768REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT - A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.07-11-2013
20130114331CONTROL SIGNAL GENERATION CIRCUIT AND SENSE AMPLIFIER CIRCUIT USING THE SAME - A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.05-09-2013
20130100728SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase in reliability and stability of the semiconductor device. A semiconductor device includes a line pattern formed over a semiconductor substrate, a device isolation film formed at a center part of the line pattern, a contact part formed at both sides of the line pattern, configured to include an oxide film formed over the line pattern, and a bit line formed at a bottom part between the line patterns, and connected to the contact part.04-25-2013
20130100729DYNAMIC MEMORY CELL PROVIDED WITH A FIELD-EFFECT TRANSISTOR HAVING ZERO SWING - A memory cell is provided with a transistor which includes source and drain electrodes formed in a semiconductor film by respectively N-doped and P-doped areas. The transistor includes first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are shifted laterally and are opposed to the passage of the charge carriers emitted by the nearest source/drain electrode. One of the devices for generating the potential barrier is electrically connected to the gate. The other of the devices for generating the potential barrier is electrically connected to the counter-electrode. The writing of a high state is carried out by imposing on the P-doped electrode a potential higher than that of the N-doped electrode and charging the capacitor formed between the gate and the semiconductor film. The resetting of the memory cell is obtained by discharging the capacitor.04-25-2013
20130114330SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a conventional DRAM, a decrease in the capacitance of a capacitor causes an error in reading data. A plurality of memory blocks MB is connected to one bit line BL_m. Each memory block MB includes a sub bit line SBL, a plurality of memory cells, and a precharge transistor. The drain of a transistor of the memory cell is connected one of the bit line BL_m and the sub bit line SBL, whereas a capacitor of the memory cell is connected to the other one of the bit line BL_m and the sub bit line SBL. The capacitance of the sub bit line SBL is sufficiently low; thus, a potential change due to electric charges of the capacitor of the memory cell can be amplified by an amplifier circuit AMP without an error and the amplified signal can be output to the bit line.05-09-2013
20130141961STORAGE DEVICE AND DRIVING METHOD THEREOF - An object is to provide a highly integrated storage device which can operate at high speed and a driving method thereof. The storage device includes two storage portions, two precharge switches, and one sense amplifier. In each of the storage portions, storage elements are arranged in a matrix. In each of the storage elements, a node electrically connected to a source or a drain of a transistor whose off-state current is small is a memory storing portion. A page buffer circuit is unnecessary; thus, high-speed operation is possible and high integration is achieved.06-06-2013
20110273921INTEGRATABLE PROGRAMMABLE CAPACITIVE DEVICE - A circuit with a capacitive device is disclosed. The circuit may comprise a capacitive device connected between a first conductor and a second conductor. The capacitive device may comprise a first electrode connected to the first conductor and a second electrode being connected to the second conductor. A chalcogenide layer may be connected to the first electrode and to a metal chalcogenide layer.11-10-2011
20110273924SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power supply voltage according to an operation mode in response to the detection signal, and an enable control unit configured to control the driving unit in response to a control signal corresponding to the operation mode.11-10-2011
20110273923PASS-GATED BUMP SENSE AMPLIFIER FOR EMBEDDED DRAMS - A sensing circuit for use in a semiconductor memory device includes first and second conducting lines for conducting a bit signal to and from a memory cell. The circuit further includes a sense amplifier coupled to the first and second conducting lines for sensing a bit signal, a charge storing element for generating a predefined potential, and first and second switching element respectively coupled to the first and second conducting lines. The first and second switching elements are selectively controllable to connect the first and second conducting line to the charge storing element so as to induce the generated predefined voltage on the first or second conducting lines.11-10-2011
20110273922SENSE AMPLIFIER USING REFERENCE SIGNAL THROUGH STANDARD MOS AND DRAM CAPACITOR - A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.11-10-2011
20130148412SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats.06-13-2013
20130148411MEMORY DEVICE - A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.06-13-2013
20120275217LOW NOISE MEMORY ARRAY - A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (11-01-2012
20120275216LOW NOISE MEMORY ARRAY - A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (11-01-2012
20120275215SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a word line, a bit line, a power supply node, a memory element, and a capacitor. The memory element includes at least first and second regions that form a PN junction between the bit line and the power supply node, and a third region that forms a PN junction with the second region. The capacitor includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.11-01-2012
20120275214SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.11-01-2012
20120275213SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - In a semiconductor memory device, one electrode of a capacitor is connected to a bit line, and the other electrode of the capacitor is connected to a drain of a cell transistor. A source of the cell transistor is connected to a source line. When a stack capacitor, for example, is used in this structure, one electrode of the capacitor is used as part of the bit line. An impurity region formed on the semiconductor substrate or a wiring parallel to a word line can be used as the source line; thus, the structure of a DRAM is simplified.11-01-2012
20130182489REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT - A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.07-18-2013
20120281456SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes: a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; a capacitor for storing electric charge for reading data retained in the memory circuit; a charge storage circuit for controlling storage of electric charge in the capacitor; a data detection circuit for controlling data reading; a timing control circuit for generating a first signal controlling storage of electric charge in the capacitor (storage is conducted with the charge storage circuit, and the first signal is generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a period immediately after the supply of the supply voltage); an inverter circuit for outputting a potential obtained by inverting a potential of one electrode of the capacitor.11-08-2012
20120281455SEMICONDUCTOR DEVICE - A semiconductor device that has a simple peripheral circuit configuration, is unlikely to deteriorate due to repetitive data writing operations, and is used as a nonvolatile switch. Even when supply of a power supply voltage is stopped, data on a conduction state is held in a data retention portion connected to a thin film transistor including an oxide semiconductor layer having a channel formation region. The data retention portion is connected to a gate of a field-effect transistor in a current amplifier circuit (in which the field-effect transistor and a bipolar transistor are connected as a Darlington pair), and thus the conduction state is controlled without leaking charge in the data retention portion.11-08-2012
20110292717Semiconductor device - A semiconductor device may include, but is not limited to: a first memory cell; a first line; a second line; and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines.12-01-2011
20130121064Memory Based Illumination Device - The invention contained herein provides electrical circuits and driving methods to operate a memory cell comprising a capacitance coupled to a breakover conduction switch such as a thyristor, DIAC or one or more complementary transistor pairs. The memory cell comprises a cell capacitance for storing a memory state and for capacitively coupling an applied voltage to the switch. During operation, pulses are applied to write, read or maintain the cell's memory state. An illumination cell comprises an LED, OLED or electroluminescent material in series with each memory cell. Breakover conduction charge passes through the switch and the emissive element to charge the cell capacitance. A memory array of breakover conduction memory cells may be organized into rows and columns for reading and writing an addressable array memory cells. An organic light emitting display memory array may be fabricated using organic light emitting devices and/or materials.05-16-2013
20120020144SEMICONDUCTOR DEVICE HAVING FLOATING BODY TYPE TRANSISTOR - A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between the source and drain which is brought into an electrically floating state. The gate is connected to the signal line, and at least one of the source and drain is connected to a control node that is supplied with a control signal. The control signal is configured to receive a control signal that changes from the first level to a second level during the period of time when the drive circuit is driving the signal node.01-26-2012
20130194857SEMICONDUCTOR DEVICE HAVING BIT LINES HIERARCHICALLY STRUCTURED - Disclosed herein is a device that includes: a sense amplifier circuit activated in response to a first control signal; a first global bit line coupled to the sense amplifier circuit; a first local bit line; a first transistor electrically coupled between the first global bit line and the first local bit line, the first transistor being rendered conductive in response to a second control signal; a first memory cell; a first cell transistor electrically coupled between the first local bit line and the first memory cell, the first cell transistor being rendered conductive in response to a third control signal; and a control circuit producing the first, second, and third control signals such that the second control signal is produced after producing the third control signal and the first control signal is produced after producing the second and third control signals.08-01-2013
20130194858SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.08-01-2013
20120033488SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a memory cell formed using a wide bandgap semiconductor, for example, an oxide semiconductor is provided. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. With the use of the wide bandgap semiconductor, an off-state current of a transistor included in the memory cell can be sufficiently reduced, and the semiconductor device which can hold data for a long period can be provided.02-09-2012
20120294070METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined potential is held in the node. Data is read out from the memory cell by supplying a precharge potential to a bit line, stopping the supply of the potential to the bit line, and determining whether the potential of the bit line is kept at the precharge potential or decreased.11-22-2012
20130201752SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device in which stored data can be retained even when power is not supplied, and there is no limitation on the number of write cycles. The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, a memory cell connected between the source line and the bit line, a first driver circuit electrically connected to the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line and the source line. The first transistor is formed using a semiconductor material other than an oxide semiconductor. The second transistor is formed using an oxide semiconductor material.08-08-2013
20130201751MULTI-PORT MEMORY BASED ON DRAM CORE - A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.08-08-2013
20120063206SEMICONDUCTOR MEMORY DEVICE - An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit line and pre-charges the bit line with a specific potential in data reading; a data holding circuit comprising a capacitor which temporarily holds data read out from the memory cell or data which is written to the memory cell; and an inverted data output circuit which outputs inverted data of data held in the data holding circuit to the bit line. The inverted data output circuit includes a means for controlling output of inverted data of data held in the data holding circuit.03-15-2012
20130208532Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems - Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.08-15-2013

Patent applications in class Capacitors

Patent applications in all subclasses Capacitors