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Ferroelectric

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365 - Static information storage and retrieval

365129000 - SYSTEMS USING PARTICULAR ELEMENT

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DocumentTitleDate
20110199810Data Holding Device - A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NAND08-18-2011
20090010038LOW RESISTANCE PLATE LINE BUS ARCHITECTURE - An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.01-08-2009
20100020588SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes cell blocks configured to have a plurality of memory cells connected in series, each memory cell comprising a ferroelectric capacitor and a cell transistor connected in parallel with each other; word lines connected to gates of a plurality of the cell transistors; block selectors connected to first ends of the cell blocks; bit lines connected to the first ends of the cell blocks via the block selectors; and plate lines connected to second ends of the cell blocks, wherein the first ends of first and second cell blocks of the cell blocks respectively sharing the word lines are connected to the same bit line via the block selectors different from each other, and the second ends of the first and the second cell blocks respectively are connected to the plate lines different from each other.01-28-2010
20100014341SEMICONDUCTOR MEMORY DEVICE - A memory includes word lines; plate lines; first to eighth bit lines; cell transistors; ferroelectric capacitor connected in parallel with cell transistors; sense amplifiers, wherein cell transistors and ferroelectric capacitors configure cells, the cells are connected in series to configure first to eighth cell blocks, the cell blocks are connected to the same word lines, first ends of the cell blocks are respectively connected to the bit lines, second ends of the cell blocks are respectively connected to the different plate lines, one of the first to the fourth bit lines and one of the fifth to the eighth bit lines are configured to be selectively connected to the sense amplifier during an operation, numbers of the cells connected in series between the bit lines and the plate lines are different in the first to the fourth cell blocks, and are different in the fifth to the eighth cell blocks.01-21-2010
20100008121METHOD FOR DRIVING FERROELECTRIC MEMORY DEVICE, FERROELECTRIC MEMORY DEVICE, AND ELECTRONIC EQUIPMENT - A method for driving a ferroelectric memory device having a plurality of memory cells that store data and a memory cell for flag is provided. The method includes, upon writing to the plurality of memory cells, the steps of: reading data from the plurality of memory cells and the memory cell for flag; judging as to whether the data readout from the memory cell for flag is specified data; overwriting write data to the plurality of memory cells, and writing reverse data of the specified data to the memory cell for flag, when the data readout from the memory cell for flag is the specified data; and rewriting the data readout from the plurality of memory cells to the plurality of memory cells, and writing the reverse data to the memory cell for flag, when the data readout from the memory cell for flag is the reverse data.01-14-2010
20100046271SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING DATA INTO SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device including a ferroelectric random access memory serving as a ROM, the method comprising: writing data into the ferroelectric random access memory, the data having a polarity opposite to that of ROM data; performing bake processing for a predetermined time period; and writing the ROM data into the ferroelectric random access memory.02-25-2010
20100073989NONVOLATILE FERROELECTRIC MEMORY DEVICE USING SILICON SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND REFRESH METHOD THEREOF - A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.03-25-2010
20100073988NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources.03-25-2010
20100073987SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A memory includes a memory cell array comprising memory cells; word lines connected to gates of the cell transistors; bit lines connected to one ends of the memory cells on the cell transistor side; plate lines connected to the other ends of the memory cells on the ferroelectric capacitor side; a sense amplifier detecting data stored in the ferroelectric capacitor; an error correcting circuit correcting error bits when such error bits exist in pieces of data; a redundancy cell array comprising redundancy cells; and a ferroelectric fuse corresponding to the redundancy cell and configured to indicate whether data is stored in the corresponding redundancy cell, wherein when error bits exist in the data read from the memory cell array, the data corrected by the error correcting circuit is written in the redundancy cell and a polarization state of the ferroelectric fuse corresponding to that redundancy cell is changed accordingly.03-25-2010
20100073986SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of cell blocks each of which is configured by serially connecting a plurality of memory cells each of which comprises a ferroelectric capacitor and a cell transistor connected in parallel; a plurality of word lines connected to gates of the cell transistors; a plurality of block selectors each of which comprises an enhancement transistor and a depletion transistor serially connected to each other; a plurality of bit lines connected via the block selectors to one ends of the cell blocks; and a plurality of plate lines connected to the other ends of the cell blocks, wherein a gate length of the enhancement transistor is longer than that of the depletion transistor.03-25-2010
20130077378SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are positioned between a first electrode and a second electrode.03-28-2013
20100110754NON-DESTRUCTIVE READ BACK FOR FERROELECTRIC DATA STORAGE DEVICE - A data storage device comprising a ferroelectric layer, a perovskite structure, and at least one sensor, where the perovskite structure has a polarity discontinuity configured to generate capacitance voltages in the perovskite structure based on polarization charges of the ferroelectric material, and where the at least one sensor is configured to read the capacitance voltages from the perovskite structure.05-06-2010
20130051114DATA READ CIRCUIT, A NON-VOLATILE MEMORY DEVICE HAVING THE SAME, AND A METHOD OF READING DATA FROM THE NON-VOLATILE MEMORY DEVICE - A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.02-28-2013
20100002488F-SRAM Margin Screen - A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.01-07-2010
20090303771RADIO FREQUENCY IDENTIFICATION DEVICE INITIALIZING A MEMORY USING AN OFFSET VOLTAGE - An RFID device sets initial data stored in a memory using an offset voltage and includes an analog block, a digital block, and a memory block. The memory blocks is configured to read/write data in a cell array unit. The memory block includes an offset controller that is configured to set an offset voltage value of a bit line connected to the cell array unit.12-10-2009
20090040808Nondestructive methods of reading information in ferroelectric memory elements - The method of nondestructive data reading from the ferroelectric memory cell supplied with the electrodes was developed. This method implies supply of reading electric voltage to the memory element electrodes with the view of generation of resilience in the ferroelectric memory cell and registration of the resilience by the field transistor with the floating gate and/or by the conductive channel made from the material with the piezoelectric properties, and according to the value of the current running through the transistor degree and character of ferroelectric cell polarization are identified.02-12-2009
20090040807SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit. The control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading.02-12-2009
20090091965NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip.04-09-2009
20090091967NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip.04-09-2009
20090091966NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip.04-09-2009
20130114324Integrated Circuit Comprising a FRAM Memory and Method for Granting Read-Access to a FRAM Memory - An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.05-09-2013
20080273367MULTI-STACK FERROELECTRIC POLYMER MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A memory device and method for manufacturing the memory device are provided. The memory device including a first electrode, a first ferroelectric polymer layer over the first electrode, a second electrode over the first ferroelectric polymer layer, a second ferroelectric polymer layer over the second electrode, a third electrode over the second ferroelectric polymer layer, and a protective layer between the first and second ferroelectric polymer layers. The first, second and third electrodes and the first and second ferroelectric polymer layers define first and second ferroelectric capacitor structures, the second electrode being common to the first and second ferroelectric capacitor structures.11-06-2008
20090268504FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD FOR THE SAME - A ferroelectric memory device includes: a plurality of memory banks configured to include a memory cell array composed of a ferroelectric memory; a cache bank configured to be bus-connected with the memory banks, and for copying data stored in the memory banks; and a memory bank/cache control sequencer for accessing and refreshing to the memory banks and the cache bank, wherein a random access control to the ferroelectric memory is possible during each memory cycle without delay of refresh operation.10-29-2009
20120195093MEMORY SUPPORT PROVIDED WITH MEMORY ELEMENTS OF FERROELECTRIC MATERIAL AND IMPROVED NON-DESTRUCTIVE READING METHOD THEREOF - A method is for non-destructive reading of an information datum stored in a memory that includes a first wordline, a first bitline and a second bitline, and a first ferroelectric transistor, which is connected between the bitlines and has a control terminal coupled to the first wordline. The method includes applying to the first wordline a first reading electrical quantity, generating a first difference of potential between the first and second bitlines, generating a first output electrical quantity, and applying to the first wordline a second reading electrical quantity. The method further includes generating a second difference of potential between the first and second bitlines, generating a second output electrical quantity, and comparing the first and second output electrical quantities with one another. On the basis of a result of said comparison, the method includes determining the logic value of the information data.08-02-2012
20090231904FERROELECTRIC MEMORY WITH SUB BIT-LINES CONNECTED TO EACH OTHER AND TO FIXED POTENTIALS - A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.09-17-2009
20090231902SEMICONDUCTOR MEMORY DEVICE - A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors are connected to the plate lines, the other electrode of the ferroelectric capacitor is connected to one of the sub-bit lines, a source and a drain of the block selection transistor are connected to one of the sub-bit lines and one of the bit lines, a source of the reset transistor is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and the memory cell blocks configure a memory cell array.09-17-2009
20110044087SEMICONDUCTOR MEMORY DEVICE - A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end signal indicating end of an executable period for reading or writing data between the sense amplifier and the outside, the plate control circuit validating or invalidating the plate driving signal based on the write signal and the operation end signal wherein the plate control circuit validates the plate driving signal in the executable period, and the plate control circuit invalidates the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and keeps the plate driving signal valid when the write signal is activated in the executable period.02-24-2011
20100014342SEMICONDUCTOR STORAGE DEVICE - A memory includes a cell block comprises memory cells connected in series; block select transistors connected to one ends of the cell blocks; bit lines; plate lines; a sense amplifier comprises an N-type sensor and a P-type sensor, the N-type sensor applying a low-level potential to the bit line, and the P-type sensor applying a high-level potential to the bit line; local data lines corresponding to the bit lines respectively and transmitting data; and a column select transistor between one of the bit lines and one of the local data lines; wherein either one of the P-type sensor and the N-type sensor is set in an inactive state with the other one of the P-type sensor and the N-type sensor being in an active state, when the column select transistor is turned on to transmit the data to be written from the local data line to the bit line.01-21-2010
20110128769DATA HOLDING DEVICE - A data holding device comprises a loop structure part (LOOP) that holds data by use of logic gates connected in a loop (e.g., inverters INV06-02-2011
20100265756Ferroelectric Memory Bake for Screening and Repairing Bits10-21-2010
20110299318SEMICONDUCTOR MEMORY CELL AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory cell includes: a memory element formed by a first field effect transistor having a gate insulating film made of a ferroelectric film; and a select switching element formed by a second field effect transistor having a gate insulating film made of a paraelectric film. The ferroelectric film and the paraelectric film are stacked together with a semiconductor film of a compound semiconductor interposed therebetween. A first gate electrode of the first field effect transistor is formed on a side of the ferroelectric film, and a second gate electrode of the second field effect transistor is formed on a side of the paraelectric film so as to face the first gate electrode. The semiconductor film forms a common channel layer of the first and second field effect transistors.12-08-2011
20100034008MAGNETIC FIELD ASSISTED STRAM CELLS - Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations.02-11-2010
20090154220PLATELINE DRIVER FOR A FERROELECTRIC MEMORY - One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.06-18-2009
20100124093FERROELECTRIC MEMORY - A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines and the n bitlines, each of the m×n memory cells including a ferroelectric capacitor and a zener diode connected in series between any one of the m platelines and any one of the n bitlines.05-20-2010
20100124092FERROELECTRIC MEMORY DEVICE - According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor.05-20-2010
20100128512SEMICONDUCTOR MEMORY DEVICE HAVING CROSS-POINT STRUCTURE - A semiconductor memory device having a cross-point structure comprising a plurality of first electrode wirings extending in the same direction, a plurality of second electrode wirings intersecting with the first electrode wirings, and memory materials for storing data at the intersection points of the first and second electrode wirings has a problem that an effective voltage applied to the memory material fluctuates in a memory cell array due to the voltage drop caused by the wiring resistance of each electrode wiring. The sum of the wiring resistance of the first electrode wiring to a certain intersection point and the wiring resistance of the second electrode wiring to the certain intersection point is substantially constant at any intersection point, and the load resistors for adjusting the fluctuation of the electrode wiring resistances in a memory cell array are connected at least either one of the first and second electrode wirings.05-27-2010
20090207645Method and apparatus for accessing a bidirectional memory - A bidirectional memory cell includes an ovonic threshold switch (OTS) and a bidirectional memory element. The OTS is configured to select the bidirectional memory element and to prevent inadvertent accesses to the memory element.08-20-2009
20100080036UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.04-01-2010
20120294062STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR CODE SPACE AND A PORTION OF THE STACK MEMORY SPACE - A stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space. By storing some of the associated stacks in complementary metal oxide semiconductor (CMOS) or other volatile memory, read/write operations to only F-RAM would be obviated. As compared to an all F-RAM stack implementation, a faster, less power consuming and faster program execution time is provided. Firmware code can also be provided that will tend to concentrate the more intensive calculations to that part of the stack that is in volatile memory and minimize POP/PUSH operations to the F-RAM portion of the stack. Moreover, since only the top of the stack is maintained in volatile memory, most of it remains in F-RAM which means the application can still benefit from the high F-RAM endurance and shorter power-down times.11-22-2012
20090273963SEMICONDUCTOR STORAGE DEVICE, SEMICONDUCTOR STORAGE DEVICE MANUFACTURING METHOD AND PACKAGE RESIN FORMING METHOD - A ferroelectric capacitor comprising a transistor layer superimposed on a semiconductor substrate, a ferroelectric capacitor layer provided superior to the transistor layer, a wiring layer provided superior to the ferroelectric capacitor layer, and a passivation film. Further, at least one layer of barrier film capable of inhibiting penetration of moisture and hydrogen into the underlayer is provided between the ferroelectric capacitor layer and the passivation film, and the passivation film is characterized by containing a novolac resin.11-05-2009
20110170330Graphene Memory Cell and Fabrication Methods Thereof - The disclosed memory cell (07-14-2011
20090161404Asymmetric dipolar ring - A device having a dipolar ring surrounding an interior region that is disposed asymmetrically on the ring. The dipolar ring generates a toroidal moment switchable between at least two stable states by a homogeneous field applied to the dipolar ring in the plane of the ring. The ring may be made of ferroelectric or magnetic material. In the former case, the homogeneous field is an electric field and in the latter case, the homogeneous field is a magnetic field.06-25-2009
20090279342Method to Improve Ferroelectric Memory Performance and Reliability - One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.11-12-2009
20110170329NONVOLATILE FERROELECTRIC MEMORY DEVICE USING SILICON SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND REFRESH METHOD THEREOF - A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.07-14-2011
20090290404SEMICONDUCTOR MEMORY DEVICE - A memory cell includes a memory element including a MFSFET having a gate insulating film made of a ferroelectric film, and a selection switching element including a MISFET having a gate insulating film made of a paraelectric film. A load element for a read operation is connected in series to the memory cell. The ferroelectric film and the paraelectric film are stacked with a semiconductor film being interposed therebetween. The semiconductor film forms a common channel shared by the MFSFET and the MISFET. The load element includes a MISFET having a channel made of the semiconductor film or a resistance element having a resistor made of the semiconductor film.11-26-2009
20090103349SEMICONDUCTOR MEMORY DEVICE - A first memory cell array includes a first bit line and a second bit line arranged to read data out of a memory cell containing a ferroelectric capacitor. A second memory cell array includes a third bit line and a fourth bit line arranged to read data out of a memory cell containing a ferroelectric capacitor. A sense amp circuit detects and amplifies a potential difference caused between any two of the first through fourth bit lines. A decoupling circuit selectively connects any two of the first through fourth bit lines to the sense amp circuit and decouples the remainder from the sense amp circuit. A bit-line potential control circuit is arranged between the decoupling circuit and the first and second memory cell arrays to fix the bit lines decoupled from the sense amp circuit by the decoupling circuit to a first potential.04-23-2009
200901033482T/2C FERROELECTIC RANDOM ACCESS MEMORY WITH COMPLEMENTARY BIT-LINE LOADS - The signal margin of a small array 2T/2C memory is increased by writing the ferroelectric load capacitors on the bit lines to complementary states. A ferroelectric memory array includes rows and columns of 2T/2C memory cells, wherein each column of the memory array includes a first memory subcell having a first node coupled to a word line, a second node coupled to a first bit line, and a third node coupled to a first plate line, the first memory cell being poled in a first direction; a second memory subcell having a first node coupled to the word line, a second node coupled to a second bit line, and a third node coupled to the first plate line, the second memory cell being poled in a second direction; a first load subcell having a first node coupled to the word line, a second node coupled to the first bit line, and a third node coupled to a second plate line, the first load cell being poled in the first direction; and a second load subcell having a first node coupled to the word line, a second node coupled to a second bit line, and a third node coupled to the second plate line, the second load cell being poled in the second direction.04-23-2009
20080212358METHOD FOR MANUFACTURING FERROELECTRIC MEMORY DEVICE AND FERROELECTRIC MEMORY DEVICE - A method for manufacturing a ferroelectric memory device includes: forming a conductive base layer above a substrate; and laminating above the base layer a first electrode, a ferroelectric layer and a second electrode, wherein, prior to the step of forming the base layer, the method includes forming an active element in the substrate, forming an interlayer dielectric film on the substrate, and forming a contact plug in the interlayer dielectric film, and wherein the step of forming the base layer includes: forming a first conductive layer composed of a conductive material having a self-orienting property on the interlayer dielectric film including the contact plug; planarizing the first conductive layer by a chemical mechanical polishing method thereby forming a planarized first conductive layer that covers the interlayer dielectric film including the contact plug; applying an ammonia plasma process to a surface of the planarized first conductive layer; forming a titanium layer on the planarized first conductive layer treated with the ammonia plasma process; and heat-treating the titanium layer in a nitrogen atmosphere thereby changing the titanium layer to a titanium nitride layer which forms a second conductive layer.09-04-2008
20100103715SEMICONDUCTOR STORAGE DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor storage device includes: a plurality of memory cell arrays, each having a memory cell arranged therein, the memory cell including a ferroelectric capacitor and a transistor; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cell; a sense amplifier circuit including an amplifier circuit to compare and amplify potentials between a pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays. The reference potential correction capacitor shifts the reference potential by changing the amount of accumulated electric charges according to the correction signal.04-29-2010
20100290265POLYMER-BASED FERROELECTRIC MEMORY - Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.11-18-2010
20120170350METHOD AND APPARATUS PERTAINING TO A FERRO-MAGNETIC RANDOM ACCESS MEMORY - An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.07-05-2012
20100128513SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes a memory cell comprising a ferroelectric capacitor and a transistor arranged therein. A plate line applies a drive voltage to one end of the ferroelectric capacitor. A bit line reads data stored in the memory cell from the other end of the ferroelectric capacitor. A sense amplifier circuit detects and amplifies a signal read to the bit line from the ferroelectric capacitor. A bit line voltage control circuit performs control of changing a voltage of the bit line to which the signal is read, thereby pulling up a potential difference between the plate line and the bit line, prior to operation of the sense amplifier circuit for data read. The bit line voltage control circuit varies a range of variation of the voltage of the bit line depending on ambient temperature.05-27-2010
20090168488Method to Improve Ferroelectronic Memory Performance and Reliability - One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.07-02-2009
20090168490FERROELECTRIC MEMORY CELL WITH ACCESS TRANSMISSION GATE - One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a plateline. The ferroelectric memory cell also includes a complementary transmission gate configured to selectively couple the storage node to a bitline as a function of a wordline voltage and a complementary wordline voltage. Bias limiting circuitry selectively alters voltage on the storage node as a function of the wordline voltage or the complementary wordline voltage. Other methods, devices, and systems are also disclosed.07-02-2009
20090168489FERROELECTRIC MEMORY DEVICES WITH PARTITIONED PLATELINES - One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.07-02-2009
20090168487CYCLING TO MITIGATE IMPRINT IN FERROELECTRIC MEMORIES - One embodiment of the present invention relates to a method for reducing the imprint of a ferroelectric memory cell. The method comprises storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising comprises either performing one or more data read/re-write events or performing one or more simulated data read and data write events of an alternating high data state and a low data state to the memory cell associated with the weak data bit. Both the lifetime retention testing and the memory data state exercising are performed in the background of normal memory operation. Other methods and circuits are also disclosed.07-02-2009
20080273368Method and apparatus for reading data from a ferromagnetic memory cell - A ferromagnetic memory cell is disclosed. The cell includes a bit (11-06-2008
20080304309SEMICONDUCTOR MEMORY DEVICE - The sense amp circuit includes a first node given a first, positive constant voltage larger than a fixed potential before reading, a second node given a second, negative constant voltage smaller than the fixed potential before reading, and a third node to be connected to the first and second nodes on reading. A first transistor is connected between the first node and the bit line and operative to turn on when the potential on the bit line becomes smaller than the fixed potential. A second transistor is connected between the second node and the bit line and operative to turn on when the potential on the bit line becomes larger than the fixed potential. A first capacitor is connected between the first node and the fixed potential. A second capacitor is connected between the second node and the fixed potential.12-11-2008
20090003030METHODS FOR FERROELECTRIC DOMAIN READING - Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material between 1 nanometer (nm) and 50 nm in thickness. The embodiments may also include applying another voltage through the tip, thereby generating a current responsive to an orientation of the polarized domain. The embodiments may also include measuring the current and determining the orientation of the polarized domain, based upon the measuring.01-01-2009
20090003031Computation Processing Circuit Using Ferroelectric Capacitor - A computation processing device executes logic computation based upon input data X(t) and data X(t−1) stored in memory. A ferroelectric capacitor includes a first terminal and a second terminal, and provides a function as memory. A bit line driver switches the voltage to be applied to the first terminal or the second terminal of the ferroelectric capacitor. A sense amplifier outputs a computation result according to the voltage that occurs at either of the first terminal and the second terminal of the ferroelectric capacitor. For example, the bit line driver switches the direction of the voltage to be applied to the ferroelectric capacitor according to the input data X(t).01-01-2009
20080205117SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors. Ferroelectric capacitors corresponding in number to the cell transistors, are provided above the local bit line, where each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of the corresponding one of the cell transistors. A plate line is provided above the upper electrodes and electrically connected to the upper electrodes. A reset transistor and a block selection transistor are provided on the surface of the semiconductor substrate.08-28-2008
20090161405DATA STORAGE MEDIUM AND ASSOCIATED METHOD - A data storage medium includes06-25-2009
20120069623FERROELECTRIC MEMORY - One embodiment provides a ferroelectric memory including: memory cells each including a ferroelectric memory; first and second bitlines configured to read out cell signals from the memory cells; a first circuit configured to fix, when the cell signal is read from the memory cell to the first bitline, a voltage of the second bitline to a first power-supply voltage, and then set the second bitline to a second power-supply voltage different from the first power-supply voltage; a second circuit configured to set, after the first circuit sets the second bitline to the second power-supply voltage, the second bitline to a reference voltage; and a third circuit configured to amplify a voltage difference between the first bitline to which the cell signal is read and the second bitline to which the reference voltage is set.03-22-2012
20120069622Sector Array Addressing for ECC Management - An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.03-22-2012
20090052224Ferroelectric random access memory apparatus and method of driving the same - In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.02-26-2009
20090097299SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND SEMICONDUCTOR SWITCHING DEVICE - A first electrode is formed on a stacked-layer film, which is formed of a ferroelectric layer and a semiconductor layer, at the ferroelectric layer and a plurality of second electrodes are formed on the stacked-layer film at the semiconductor layer side. Each of parts of the semiconductor layer located in regions in which the second electrodes are formed functions as a resistance modulation element (memory) using the polarization assist effect of the ferroelectric layer. Information (a low resistance state or a high resistance state) held in a memory is read by detecting a value of a current flowing in each part of the semiconductor layer. Information is written in a memory by inverting a polarization of the ferroelectric layer.04-16-2009
20130215664ACTIVATE SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - An activate signal generating circuit, to which a first and a second activate signals which are pulse signals are applied, and which generates an internal activate signal, has a first delay element. The internal activate signal is activated based on timings of front (active transient) edges of the first and second activate signals. When a timing of a rear (inactive transient) edge of the first activate signal is earlier than a timing of a rear edge of the second activate signal, the internal activate signal goes inactivate based on the timing of the rear edge of the first activate signal, and when the timing of the rear edge of the first activate signal is later than the timing of the rear edge of the second activate signal, the internal activate signal goes inactivate after a predetermined delay time based on a delay time of the first delay element.08-22-2013
20090244952ELECTRODE MASTER FOR FERROELECTRIC RECORDING AND METHOD FOR RECORDING ON FERROELECTRIC RECORDING MEDIUM - The present invention provides an electrode master for ferroelectric recording that records information on a ferroelectric recording medium in which the direction of polarization of a ferroelectric material has been unified in one direction by applying a voltage thereto, based on the direction of polarization of the ferroelectric material by applying voltage pulses to the ferroelectric recording medium, the electrode master including: an electroconductive base material; a plurality of electrode convexes provided on a surface of the electroconductive base material so as to correspond to information to be recorded on the ferroelectric recording medium; and an electrode terminal conducted to each of the electrode convexes and provided on the electroconductive base material.10-01-2009
20090231903FERROELECTRIC MEMORY AND METHOD FOR TESTING THE SAME - A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a first bit-line precharge potential to a floating state, and the plate-line voltage is raised from the second plate-line voltage to a plate-line voltage.09-17-2009
20090244951SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.10-01-2009
20120195096DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.08-02-2012
20120195094MEMORY SUPPORT PROVIDED WITH ELEMENTS OF FERROELECTRIC MATERIAL AND PROGRAMMING METHOD THEREOF - Logic data is written in a memory having a first word line and a first bit line, with the memory including a first memory cell having a first ferroelectric transistor. The first ferroelectric transistor includes a layer of ferroelectric material and has a first conduction terminal coupled to the first bit line, and a control terminal coupled to the first word line. The logic data is written based on biasing the control terminal of the first ferroelectric transistor at a first biasing value, biasing the first conduction terminal of the first ferroelectric transistor at a second biasing value different from the first biasing value, and generating a stable variation of the state of polarization of the layer of ferroelectric material of the first ferroelectric transistor to write the logic data in the first memory cell.08-02-2012
20120195098METHOD AND SYSTEM FOR UTILIZING PEROVSKITE MATERIAL FOR CHARGE STORAGE AND AS A DIELECTRIC - A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines.08-02-2012
20100157650FERROELECTRIC MEMORY - A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.06-24-2010
20120033478NON-VOLATILE MEMORY DEVICE AND SENSING METHOD FOR FORMING THE SAME - A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate. A read operation of data is performed by sensing a current value changing with a polarity state of the ferroelectric layer on the condition that the read voltage is input to the control gate and a sensing bias voltage is input to one of the drain region and the source region.02-09-2012
20100002489PASSIVE MATRIX-ADDRESSABLE MEMORY APPARATUS - Disclosed is a passive matrix-addressable memory apparatus. The passive matrix-addressable memory apparatus comprises: a plurality of first electrode lines horizontally arranged with respect to each other; a plurality of second electrode lines disposed orthogonal to the plurality of first electrode lines to be horizontally arranged with respect to each other; a memory unit formed between the plurality of first electrode lines and the plurality of second electrode lines, and containing an electrically polarizable material exhibiting hysteresis; and a switch unit. The switch unit comprises: first electrodes of a cantilever structure respectively formed between the memory unit and the plurality of first electrode lines to be electrically connected to the plurality of first electrode lines; and second electrodes electrically connected to the memory unit to be spaced apart from the first electrodes to face the first electrodes.01-07-2010
20090316469FERROELECTRIC MEMORY BRAKE FOR SCREENING AND REPAIRING BITS12-24-2009
20120195097METHOD AND SYSTEM FOR UTILIZING PEROVSKITE MATERIAL FOR CHARGE STORAGE AND AS A DIELECTRIC - A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines.08-02-2012
20130215665VARIABLE RESISTANCE MEMORY DEVICE HAVING EQUAL RESISTANCES BETWEEN SIGNAL PATHS REGARDLESS OF LOCATION OF MEMORY CELLS WITHIN THE MEMORY ARRAY - A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells.08-22-2013
20120195095MEMORY SUPPORT PROVIDED WITH MEMORY ELEMENTS OF FERROELECTRIC MATERIAL AND NON-DESTRUCTIVE READING METHOD THEREOF - A method for non-destructive reading of logic data stored in a memory includes applying to a first wordline a reading voltage so as not to cause a variation of the stable state of polarization of a layer of ferroelectric material, and generating a difference of potential between first and second bitlines. An output current is generated comparing the output current with a plurality of comparison values, and determining the logic value of the logic data to be read on the basis of the comparison.08-02-2012
20100238699SEMICONDUCTOR MEMORY AND TEST METHOD FOR THE SEMICONDUCOR MEMORY - Semiconductor memory contains memory cells having ferroelectric capacitors and cell transistors, bit lines connected to memory cells, word lines connected to gate electrodes of cell transistors, plate lines connected to one of two electrodes of ferroelectric capacitors, sense amplifiers connected between each pair of bit lines. Further, a test pad is provided in order to apply an external voltage to each of bit lines, test transistors are provided corresponding to bit lines respectively, each of test transistors is connected between the test pad and each of bit lines, a fatigue test bias circuit is connected to a first node located between the test pad and test transistors. Test transistors are shared in a first test to apply a first voltage to ferroelectric capacitors from an outside via the test pad and a second test to apply a second voltage to ferroelectric capacitors from the fatigue test bias circuit.09-23-2010
20110058403FERRO-ELECTRIC RANDOM ACCESS MEMORY APPARATUS - A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout.03-10-2011
20090310397FERROELECTRIC MEMORY DEVICE, METHOD FOR DRIVING FERROELECTRIC MEMORY DEVICE, AND ELECTRONIC EQUIPMENT - A ferroelectric memory device includes: a memory cell having a ferroelectric capacitor connected between a plate line and a bit line; a first node connected to the bit line through a charge transfer MISFET; a potential generation circuit that has a first capacitor having a first terminal connected to the first node and a first switching MISFET connected to a second terminal of the first capacitor, and is capable of setting the first node to a negative potential; and a sense amplifier connected to the second terminal of the first capacitor. When reading a charge stored in the ferroelectric capacitor, the potential generation circuit sets the first node at a negative potential and then sets the first switching MISFET to an off state, thereby setting the second terminal of the first capacitor to a floating state, and the sense amplifier amplifies a potential on the second terminal of the first capacitor in the floating state.12-17-2009
20090040806Reading circuit and method in a data-storage system - A reading circuit for reading a datum stored in a storage material. In the reading circuit, a generating stage generates a read electrical quantity to be applied to the storage material, and a sensing stage is configured to generate an output electrical quantity that is indicative of a charge variation associated to the datum stored, and that occurs in the storage material due to application of the read electrical quantity; in particular, the sensing stage uses a charge-sensing amplifier electrically connected to the storage material.02-12-2009
20100195368F-RAM Device with Current Mirror Sense Amp - A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.08-05-2010
20110032744RECORDING METHOD FOR MAGNETIC MEMORY DEVICE - [Object] To provide a recording method for a magnetic memory device including a recording layer that holds information as a magnetization direction of a magnetic body and a magnetization reference layer that is provided with respect to the recording layer with an insulation layer interposed therebetween, the magnetic memory device being recorded with information by a current flowing between the recording layer and the magnetization reference layer via the insulation layer, the recording method being capable of maintaining, even when a write pulse considerably higher than an inversion threshold value is applied, the same level of error rate as in a case where a write pulse a little higher than the inversion threshold value is applied.02-10-2011
20090010037SEMICONDUCTOR MEMORY DEVICE WITH FERROELECTRIC DEVICE - A semiconductor memory device comprises a one-transistor (1-T) field effect transistor (FET) type ferroelectric device connected between a pair of bit lines and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer; a plurality of access transistors connected between the ferroelectric device and the pair of bit lines; and a plurality of port word lines configured to select the plurality of access transistors.01-08-2009
20080266930Piezoelectrically actuated ultrananocrystalline diamond tip array integrated with ferroelectric or phase change media for high-density memory - A compact large density memory piezoactuated storage device and process for its fabrication provides an integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure that features an integrated large density array of nanotips made of wear-resistant conductive ultrananocrystalline diamond (UNCD) in which the tips are actuated via a piezoelectric thin film integrated with the UNCD tips. The tips of the special piezoactuated storage device effectively contact an underlying metal layer (top electrode) deposited on a polarizable ferroelectric layer that is grown on top of another metal layer (bottom electrode) to form a ferroelectric capacitor. Information is imprinted in the ferroelectric layer by the polarization induced by the application of a voltage pulse between the top and bottom electrodes through the conductive UNCD tips. This integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure can be efficiently used to imprint data in the ferroelectric layer for memory storage with high density in the gigabit (Gb) to terabit (Tb) range. An alternative memory media to the ferroelectric layer can be a phase change material that exhibits two orders of magnitude difference in electrical resistance between amorphous and crystalline phases.10-30-2008
20100309711F-RAM Device with Current Mirror Sense Amp - A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.12-09-2010
20120134197MEMORY CELL AND MEMORY DEVICE USING THE SAME - Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.05-31-2012
20110019461F-SRAM Power-Off Operation - A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.01-27-2011
20090219748FERROELECTRIC MEMORY DEVICE - A ferroelectric memory includes ferroelectric capacitors including ferroelectric films between first electrodes and second electrodes; cell transistors; and a bit line contact connecting the cell transistors to a bit line, wherein the first electrode is connected to one of source and drain of the cell transistor at a first node, so that the ferroelectric capacitor and the cell transistor form a unit cell, the other of source and drain of the cell transistor for the unit cell is connected to the first node of other unit cell to serially connect the cell transistors for unit cells, so that the unit cells form a cell string, the word lines are connected to gates of the cell transistors or function as gates, the plate lines are connected to the second electrodes of the ferroelectric capacitors, and the bit line is connected to a cell transistor at an end of the cell string.09-03-2009
20100226162Memory Array Power Domain Partitioning - An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.09-09-2010
20110085369METHOD TO IMPROVE FERROELECTRIC MEMORY PERFORMANCE AND RELIABILITY - One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.04-14-2011
20100188882NONVOLATILE FERROELECTRIC MEMORY AND CONTROL DEVICE USING THE SAME - A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged in more significant bit region, the cell operation is not performed in the access of the page address buffer, thereby improving reliability of the cell and reducing power consumption.07-29-2010
20090316470SEMICONDUCTOR STORAGE DEVICE - According to the present invention, a semiconductor storage device includes: a first memory cell array including: a first bit line; a first plate line; a first memory cell; a first sense amplifier; a first reference power line configured to supply first reference voltage; a first switching module configured to control a connection between the first reference power line and the first bit line; a second memory cell array including: a second bit line; a second plate line; a second memory cell; a second sense amplifier; a second reference power line configured to supply second reference voltage; a second switching module configured to control a connection between the second reference power line and the second bit line; a control module configured to generate the control signal so as to control a time difference between the first memory cell array and the second memory cell array in precharge operation.12-24-2009
20090323390SEMICONDUCTOR MEMORY DEVICE - A memory includes a cell block including ferroelectric capacitors and cell transistors, the cell block being configured by unit cells formed by the ferroelectric capacitor and the cell transistor; a dummy block configured by having one end of dummy strings connected in common, the dummy string being formed by connecting in series dummy transistors; dummy word lines connected to gates of the dummy transistors; a dummy block selection transistor connected between the dummy block and a bit line; wherein in a data read operation, a dummy-word-line driver sets the dummy transistors to a conductive state, the number of the dummy transistors in the conductive state depends on the number of the cell transistors present between the unit cell to be read and the bit line, and the dummy transistors in a conductive state are conductive to the bit line.12-31-2009
20100039850SEMICONDUCTOR MEMORY DEVICE WITH FERROELECTRIC MEMORY - A semiconductor memory device includes plural word lines, plural first bit lines, plural plate lines formed corresponding to the word lines, plural second bit lines formed corresponding to the first bit lines, plural first ferroelectric capacitors each including a ferroelectric film between two electrodes, plural cell transistor formed corresponding to the first ferroelectric capacitors, and including a gate coupled to the word lines, plural second ferroelectric capacitors each including a ferroelectric film between two electrodes, and a sense amplifier configured to detect data stored in the first ferroelectric capacitors through the first bit lines or data stored in the second ferroelectric capacitors through the second bit line, or to write data in the first ferroelectric capacitors or the second ferroelectric capacitors. The first ferroelectric capacitors and the cell transistors connect between the first bit lines and the plate lines in series, and the second ferroelectric capacitors connect between the second bit lines and the word lines.02-18-2010
20100135061Non-Volatile Memory Cell with Ferroelectric Layer Configurations - In some embodiments of the invention a non-volatile memory cell is provided with a first electrode, a second electrode, and one or more side layers of a ferroelectric metal oxide and a ferroelectric material layer between the first and second electrodes. The ferroelectric material layer may be provided between, e.g., adjacent, two side layers of a ferroelectric metal oxide or between a single layer of a ferroelectric metal oxide and an electrode. The ferroelectric metal oxide may in some cases include a uniform layered structure such as a bismuth layer-structured ferroelectric material like Bi06-03-2010
20100135062Very high speed FRAM for replacing SRAM - For replacing SRAM with very high speed FRAM, new memory architecture is realized such that plurality of FRAM cells is connected to a local bit line pair, a local sense amp is connected to the local bit line pair, a global sense amp is connected to the local sense amp through a global bit line pair, and a locking signal generator is connected to the global sense amp for generating a locking signal which disables the local sense amp after reading for quick write-back operation. With short bit line architecture, bit lines are multi-divided for reducing parasitic capacitance of the local bit line, which realizes to reduce the ferroelectric capacitor proportionally. The FRAM cell includes an access transistor pair, a ferroelectric capacitor pair for storing positive data and negative data, and a reset transistor pair for resetting storage nodes. And various circuits for implementing the memory are described.06-03-2010
20090213638Magnectic memory element and magnetic memory apparatus - A magnetic memory element is provided with first and second ferromagnetic fixed layers, a ferromagnetic memory layer, nonmagnetic first and second intermediate layers. The memory layer is disposed between the first and second fixed layers, and has a variable magnetization direction. In order to cancel asymmetry of a write-in current of the element, the element is provided so that the memory layer receives a larger perpendicular stray field from the first fixed layer than from the second fixed layer, and then a magnetization direction of a portion of the memory layer being nearest to the first intermediate layer and the magnetization direction of the first fixed layer are antiparallel to each other whenever a magnetization direction of a portion of the memory layer being nearest to the second intermediate layer and the magnetization direction of the second fixed layer are parallel to each other, and vice versa.08-27-2009
20090213637Ferroelectric random access memory device - An FRAM device can includes first ferroelectric capacitors, second ferroelectric capacitors, first plate lines and second plate lines. The first ferroelectric capacitors can be connected between word lines and bit lines. The second ferroelectric capacitors can be connected between the word lines and bit line bars. The first plate lines can be connected to upper electrodes of the first ferroelectric capacitors. The second plate lines can be connected to upper electrodes of the second ferroelectric capacitors. Thus, the first ferroelectric capacitors connected to the bit lines and the second ferroelectric capacitors connected to the bit line bars can be connected to the different plate lines, so that data can be output from any one of the bit line and the bit line bar. As a result, a layout of a core region can be simplified.08-27-2009
20090213636Layered bi compound nanoplate array of such nanoplates, their making methods and devices using them08-27-2009
20120120708METHOD OF SWITCHING OUT-OF-PLANE MAGNETIC TUNNEL JUNCTION CELLS - A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.05-17-2012
20120134196ANALOG MEMORIES UTILIZING FERROELECTRIC CAPACITORS - A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.05-31-2012
20110063886SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information.03-17-2011
20100246238METHOD FOR MITIGATING IMPRINT IN A FERROELECTRIC MEMORY - An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access, or can be performed whenever convenient with a counter and a rejuvenate command.09-30-2010
20090016093MEMORY SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time. When power is turned on, the set data that are stored in the ferroelectric memory are stored and retained in a latch circuit by a control circuit. Based on the set data retained in the latch circuit, data writing is performed in the ferroelectric memory respectively in the power-on state and in the power-off instruction time. Thus, operations of the ferroelectric memory can be controlled with desired operation timings according to operating conditions for each memory system. Excessive stress application to the ferroelectric memory during the power-on state is prevented and endurance deterioration is suppressed, while data retention characteristics after power-off are improved.01-15-2009
20100118586FERROELECTRIC MEMORY - A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel. The memory includes first and second memory cell arrays, first and second bit lines arranged in the first and second memory cell arrays, respectively, first and second blocks connected to the first bit line, and including N05-13-2010
20100097839High speed ferroelectric random access memory - For realizing high speed ferroelectric random access memory, bit line is multi-divided for reducing parasitic capacitance, so that the bit line is quickly charged or discharged by a memory cell including a ferroelectric capacitor when reading. Particularly, a non-inverting local sense amp is devised for reducing area, such that the memory cell is read by the local sense amp through a lightly loaded local bit line, and the local sense amp is read by a global sense amp through a global bit line. By the sense amps, a voltage difference in the local bit line is converted to a time difference for differentiating data “1” and data “0”, and buffered data path is used for achieving fast data transfer. Additionally, various alternative circuits and memory cell structures for implanting the memory are described.04-22-2010
20090021975METHOD AND MEDIA FOR IMPROVING FERROELECTRIC DOMAIN STABILITY IN AN INFORMATION STORAGE DEVICE - A media for an information storage device comprises a substrate of single-crystal silicon, a buffer layer of an epitaxial single crystal insulator formed over the substrate, a bottom electrode layer of an epitaxial single crystal conductor formed over the buffer layer, a ferroelectric layer of an epitaxial single crystal ferroelectric material formed over the bottom electrode layer, and an overlayer of an epitaxial single crystal material formed over the ferroelectric layer. Dipole charges generally having a first orientation exist at an interface between the bottom electrode layer and the ferroelectric layer includes, while dipole charges generally having a second orientation opposite the first orientation exist at an interface between the ferroelectric layer and the overlayer includes.01-22-2009
20080285327Ferroelectric Memory and Semiconductor Memory - A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.11-20-2008
20120170351METHOD AND APPARATUS PERTAINING TO A FERRO-MAGNETIC RANDOM ACCESS MEMORY - An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).07-05-2012
20100309710Variable Impedance Circuit Controlled by a Ferroelectric Capacitor - A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.12-09-2010
20080253163FERROELECTRIC RANDOM ACCESS MEMORY CIRCUITS FOR GUARDING AGAINST OPERATION WITH OUT-OF-RANGE VOLTAGES AND METHODS OF OPERATING SAME - A semiconductor device can include a first ferroelectric random access memory to which a first voltage is applied and a second ferroelectric random access memory to which a second voltage is applied, where the second voltage is lower than the first voltage. A data protection circuit can determine whether test data is normally read from the second ferroelectric random access memory or whether a write-back operation is normally performed on the second ferroelectric random access memory on the basis of the second voltage. The data protection circuit can also generate a read prevention control signal to control whether a read operation is to be performed on the first ferroelectric random access memory based on the determined result.10-16-2008
20100321975FERROELECTRIC MEMORY DEVICE - By separately setting a capacitor on BL depending on whether the mode is a DRAM mode or an FRAM mode, it is compatible with improvement in a speed by BL capacitor reduction in the DRAM mode and a sufficient BL capacitance in the FRAM mode.12-23-2010
20110075467Ferroelectric memory devices and operating methods thereof - A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.03-31-2011
20100110755FERROELECTRIC RANDOM ACCESS MEMORY DEVICE - A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on.05-06-2010
20100110753Ferroelectric Memory Cell Arrays and Method of Operating the Same - An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices.05-06-2010
20110188288SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREFOR - A memory includes a first conductive-type first diffusion layer on the semiconductor substrate; second conductive-type bodies on the first diffusion layer(s); first conductive-type second diffusion layers on the bodies; first gate dielectric films comprising ferroelectric films and provided on first side surfaces of the bodies; second gate dielectric films comprising ferroelectric films and provided on second side surfaces of the bodies; first gate electrodes on the first gate dielectric film; and second gate electrodes on the second gate dielectric film, wherein the first and the second diffusion layers, the body, the first and the second gate dielectric films, and the first and the second gate electrodes constitute memory cells, and each of the memory cells stores a plural pieces of logical data depending on a polarization state of the first gate dielectric film and on a polarization state of the second gate dielectric film.08-04-2011
20110188287High speed FRAM including a deselect circuit - High speed FRAM including a deselect circuit is realized for replacing SRAM, wherein the deselect circuit is connected to a local bit line pair for forcing a middle voltage to storage nodes of ferroelectric capacitors of unselected memory cell while a plate line of the ferroelectric capacitors is forced to the middle voltage, so that the unselected memory cell is not polarized while selected memory cell is polarized by changing the local bit line pair when writing. With the deselect circuit, half of the memory cells are not accessed, which reduces number of sense amps. Furthermore, half of metal routing lines on the memory cells can be used for selecting columns and connecting global power as the convention SRAM configuration, while other half of metal routing lines are used for global bit lines. And various circuits for implementing the memory with the deselect circuit are described.08-04-2011
20110149633Memory devices and methods of operating the same - Memory devices and methods of operating the same. A memory cell of a memory device may include a ferroelectric layer and a semiconductor layer bonded to each other. The ferroelectric layer may be of a p-type and the semiconductor layer may be of an n-type. The memory cell may have a switching characteristic due to a depletion region that exists in a junction between the ferroelectric layer and the semiconductor layer. The memory device may be a device writing data using a polarization change of the ferroelectric layer.06-23-2011
20090175065SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device including a ferroelectric memory includes: a nonvolatile memory having higher data retention capability under high temperature than the ferroelectric memory; and a connection circuit for switching between connection and disconnection of the ferroelectric memory and the nonvolatile memory. The ferroelectric memory receives, through the connection circuit, at least part of data which is unique to the device and which has been written into the nonvolatile memory, and retains the received data.07-09-2009
20100039851SEMICONDUCTOR MEMORY - A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.02-18-2010
20100027313F-SRAM Before Package Solid Data Write - A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and then removing power from the integrated circuit. A process polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation, then removing power from the integrated circuit. A process of polarizing a programmable data storage component of an integrated circuit by polarizing corresponding ferroelectric capacitors in same orientations, then removing power from the integrated circuit. An integrated circuit containing a programmable data storage component and a ferroelectric capacitor polarization circuit that is configured to polarize a first data ferroelectric capacitor and a second data ferroelectric capacitor in desired polarization configurations by applying biases to a first state node, a second state node, a first plate node, and a second plate node.02-04-2010
20100020589SEMICONDUCTOR MEMORY DEVICE - The sense amplifier detects and amplifies a signal read via bit lines from the ferroelectric capacitor of the memory cell. The dummy capacitor provides a reference voltage to bit lines. The dummy capacitor includes a first dummy capacitor and a second dummy capacitor. The first dummy capacitor is provided with a first dummy plate potential at one end to set the reference voltage to a certain potential. The other end is connected to the bit line. The second dummy capacitor is provided with a second dummy plate potential at one end to fine-tune the reference voltage from the certain potential. The other end thereof is connected to the bit line.01-28-2010
20120147654Ferroelectric Random Access Memory with Single Plate Line Pulse During Read - A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In one embodiment of the invention, the fully polarized data states is present in those cells that previously stored that data state; for those cells storing the opposite state, a write-back pulse is executed. In another embodiment of the invention, the fully polarized data state results for each of the selected memory cells, by applying a plate line boost voltage of a higher magnitude. Those cells that are to store the opposite data state, as may be determined following error correction, are written back with that data state.06-14-2012
20110051491FERROELECTRIC RANDOM ACCESS MEMORY AND MEMORY SYSTEM - Certain embodiments provide a ferroelectric random access memory comprising a first buffer, a second buffer, a third buffer, a first controlling unit, a second controlling unit, a memory cell array, a sense amplifier circuit, and a third controlling unit. The first buffer outputs a first signal changed from a first value to a second value based on notification of power-down. The second buffer stops supply of inner clock signal with the change of the first signal from the first value to the second value. The third buffer receives an address signal corresponding to data to be read or written. The first controlling unit receives a command signal. The second controlling unit generates a basic signal that has a third value when the command signal indicates a bank active command and has a fourth value when the command signal indicates a precharge command and the first signal has the second value. The sense amplifier circuit reads data via a pair of bit lines from the memory cell corresponding to the address signal. The third controlling unit controls write back to the memory cell from which the data are read so as to be performed after an elapse of a predetermined time from the time the basic signal has the third value and when the basic signal has the fourth value.03-03-2011
20100302834F-RAM device with current mirror sense amp - A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.12-02-2010
20120307545Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories - A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (12-06-2012
20110305062MEMORY CELL AND MEMORY DEVICE USING THE SAME - Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference voltage is applied, a first switch configured to allow a source of the ferroelectric transistor to be connected to a first line in response to a scan signal, and a second switch configured to allow a gate of the ferroelectric transistor to be connected to a second line in response to the scan signal. The memory device enables random access and performs non-destructive read-out (NDRO) operations.12-15-2011
20110305061Ferroelectric Memories based on Arrays of Autonomous Memory Bits - A memory having a plurality of ferroelectric memory cells connected between first and second bit lines is disclosed. A read circuit is also connected between the first and second bit lines. A word select circuit selects one of the ferroelectric memory cells and generates a potential on the first hit line indicative of a value stored in the selected one of the plurality of ferroelectric memory cells. Each ferroelectric memory cell includes a ferroelectric capacitor and a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal. The ferroelectric capacitor is connected between the control terminal and the first switch terminal. First and second gates connect the ferroelectric memory cell to the bit lines in response to the word select circuit selecting that ferroelectric memory cell.12-15-2011
20100124094DATA HOLDING DEVICE - A data holding device includes a loop structure portion for holding data by using a plurality of logic gates connected like a loop, and a nonvolatile storage portion for storing data held in the loop structure portion, in a nonvolatile manner by using a hysteresis characteristic of a ferroelectric element. The loop structure portion and the nonvolatile storage portion are driven by being respectively supplied with power supply voltages that are different from each other.05-20-2010
20100097840FRAM including a tunable gain amp as a local sense amp - FRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a ferroelectric capacitor, and gain is adjusted by setting a local amp voltage for reading the memory cell more effectively with optimized gain. And a global sense amp is connected to the local sense amp for receiving a read output. When reading data, a voltage difference in the local bit line is converted to a time difference by the sense amps for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as a reference signal. Additionally, alternative circuits and memory cell structures for implementing the memory are described.04-22-2010
20120155145High speed FRAM - A memory cell includes four transistors and two ferroelectric capacitors, wherein one of the two ferroelectric capacitors is positively polarized and another one of the two ferroelectric capacitors is negatively polarized for storing a non-inverting data and an inverting data, and a pair of access transistors is connected to the two ferroelectric capacitors, a pair of reset transistors is connected to the two ferroelectric capacitors, where a local bit line pair is connected to the pair of access transistors and a local sense amp is connected to the local bit line pair. By storing the non-inverting data and inverting data in the memory cell, there is no need to generate reference voltage when reading, which simplifies array configuration and enhances performance for reading and writing.06-21-2012
20120155144FAST RESPONSE CIRCUITS AND METHODS FOR FRAM POWER LOSS PROTECTION - A circuit to protect data on an FRAM during a read operation includes an FRAM voltage regulator having an output to supply an FRAM operating voltage to the FRAM. A voltage monitor monitors a supply voltage for the FRAM to generate a voltage fault signal if the supply voltage falls below a predetermined value. And a circuit responsive to the voltage fault signal maintains the FRAM operating voltage above a voltage required to assure data integrity of the FRAM for a sufficient time required to perform an FRAM read operation.06-21-2012
20120008365METHOD FOR OPERATING A NONVOLATILE SWITCHING DEVICE - A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a current flows selectively between the first electrode and the second electrode, and a third state in which a current flows selectively between the first electrode and the third electrode. When any one of the first state, the second state and the third state is configured, voltages V01-12-2012
20120014159MEMORY DEVICE - A memory device includes a memory unit including a plurality of first conductive lines and a plurality of second conductive lines that cross the first conductive lines, and a driving unit module coupled with the plurality of the first conductive lines through respective ones of a plurality of contacts and coupled with and the plurality of the second conductive lines through respective ones of the plurality of contacts, wherein as the first conductive lines become farther from the driving unit module along a direction that the second conductive lines extend, the respective contacts of the first conductive lines have lower resistance values.01-19-2012
20120206957Identifying and Correcting a Bit Error in a FRAM Storage Unit of a Semiconductor Device - An embodiment of semiconductor device including a control unit and an FRAM storage unit is disclosed. The FRAM storage unit contains FRAM cells. The control unit includes a predetermined test data pattern. The control unit is configured to read the FRAM cells that contain a test data pattern in a margin-mode, compare the read out bit information with the test data pattern to determine whether a bit error is present in the dedicated FRAM cells. When a bit error is present, the control unit is configured to read-out the complete FRAM storage unit in a recovery-mode and refresh all FRAM cells of the FRAM storage unit by writing back the read out bit information to the respective FRAM cells. In the margin-mode, the read operation is performed using a lower read-sensitivity compared to the read operation reading out the complete FRAM storage unit that is performed in the recovery-mode.08-16-2012
20120106233REDUCED SWITCHING-ENERGY MAGNETIC ELEMENTS - A system includes a continuous thin-film ferromagnetic layer, N magnetic tunnel junction (MTJ) devices, and N write structures. The continuous thin-film ferromagnetic layer includes N modified regions. Each of the N modified regions is configured to stabilize a magnetic domain wall located in the continuous thin-film ferromagnetic layer. Each of the N MTJ devices includes one of N portions of the continuous thin-film ferromagnetic layer. Adjacent MTJ devices of the N MTJ devices are separated by one of the N modified regions. Each of the N write structures is configured to receive current and generate a magnetic field that magnetizes a different one of the N portions of the continuous thin-film ferromagnetic layer. N is an integer greater than 2.05-03-2012
20110090731GREEN TRANSISTOR FOR NANO-SI FERRO-ELECTRIC RAM AND METHOD OF OPERATING THE SAME - The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO04-21-2011
20120314476ORGANIC FERROELECTRIC MATERIAL BASED RANDOM ACCESS MEMORY - Illustrative embodiments provide a FETRAM that is significantly improved over the operation of conventional FeRAM technology. In accordance with at least one disclosed embodiment, a CMOS-processing compatible memory cell (see definition above) provides an architecture enabling a non-destructive read out operation using organic ferroelectric PVDF-TrFE as the memory storage unit and silicon nanowire as the memory read out unit.12-13-2012
20100091547SEMICONDUCTOR MEMORY DEVICE - A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed.04-15-2010
20120250392DATA HOLDING DEVICE AND LOGIC OPERATION CIRCUIT USING THE SAME - A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in a nonvolatile manner using hysteresis characteristics of the ferroelectric elements, and a circuit separation unit configured to electrically separate the loop structure unit and the nonvolatile storage unit. The ferroelectric elements of the nonvolatile storage unit are surrounded by a dummy element smaller in width than the ferroelectric elements.10-04-2012
20120127777METHOD TO IMPROVE FERROELECTRIC MEMORY PERFORMANCE AND RELIABILITY - One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.05-24-2012
20120127776FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device has word, bit, plate lines; memory cells having access gate and ferroelectric capacitor; latch amplifier for latching stored data; and write amplifier for driving bit lines according to write data. The bit lines are precharged to a reference potential before an active period. In active period, at a first time, selected word line and plate line are driven to a high-level potential so that ferroelectric capacitor output electric charge to selected bit line, and at a second time, selected bit line is brought to reference potential regardless of write data so that first data is written to selected memory cell, and at a third time, plate line is driven to reference potential and is maintained; and in a precharge period, the write amplifier drives selected bit line to high-level potential according to write data so that second data is written to selected memory cell.05-24-2012
20110182102SEMICONDUCTOR MEMORY DEVICE - A memory includes memory cells on a semiconductor layer, in which each of the memory cells includes a source layer and a drain layer in the semiconductor layer; an electrically floating body region provided in the semiconductor layer between the source layer and the drain layer and configured to accumulate or discharge electric charges in order to store logical data; a gate dielectric film provided on the body region and comprising a ferroelectric film with polarization characteristics; and a gate electrode provided on the gate dielectric film above the body region, wherein each memory cell stores a plurality of logical data depending on an amount of electric charges accumulated in the body region and on a polarization state of the ferroelectric film.07-28-2011
20090059647SEMICONDUCTOR STORAGE DEVICE - A memory cell array has memory cells, each of which has a ferroelectric capacitor and a selection transistor. A plate line is connected to one end of the ferroelectric capacitor and applied a certain plate line voltage. A sense amplifier circuit senses and amplifies voltage of the bit line. An error correction circuit corrects any error in retained data in the memory cells sensed by the sense amplifier. A plate line control circuit controls the timing for switching a potential of the plate line to a ground potential, based on absence or presence of error correction by the error correction circuit.03-05-2009
20090059649SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC APPARATUS - A semiconductor memory device includes: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; and two or more third wirings connecting the third terminals of the m memory cells, the third wirings including, from among unit blocks resulting from dividing the memory cell array into q sections in the first direction and r sections in the second direction, each unit block having s memory cells arranged in the first direction and t memory cells arranged in the second direction in a grid, first to t-th wiring parts connecting the s memory cells arranged in the first direction in a first unit block, first to t-th wiring parts connecting the s memory cells arranged in the first direction in a second unit block located next to the first unit block in the first direction, and connection wiring parts connecting the first to t-th wiring parts in the first unit block and the first to t-th wiring parts in the second unit block so that the wiring parts with the same level are not connected, and also connecting ends on the second unit block side of the wiring parts in the first unit block and ends on the first unit block side of the wiring parts in the second unit block, wherein the connection wiring parts are crossed between the first unit block and the second unit block.03-05-2009
20090059648FERROELECTRIC SEMICONDUCTOR STORAGE DEVICE - This ferroelectric semiconductor storage device includes: a ferroelectric capacitor; and a transistor having one end of its current path connected to one electrode of the ferroelectric capacitor. A plate line is connected to the other electrode of the ferroelectric capacitor. A word line is connected to the gate of the transistor. A bit line is connected to the other electrode of a capacitor and the other end of the transistor, the capacitor having its one electrode connected to the ground. A bit line potential detection circuit detects a potential of the bit line. A connection circuit provides the same potential between a potential of the plate line and a potential of the bit line based on an output from the bit line potential detection circuit.03-05-2009
20090059646SEMICONDUCTOR INTEGRATED CIRCUIT - A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.03-05-2009
20120170349Ferroelectric Memory with Shunt Device - A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.07-05-2012
20120170348Ferroelectric Memory Write-Back - A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.07-05-2012
20120075905SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor memory device includes a plurality of memory cells connected to a common bit line, a plurality of select lines each configured to select at least one of the memory cells, a plurality of drive circuits each configured to drive at least one of the select lines, a sense amplifier configured to amplify a voltage occurring at the bit line depending on data stored in the selected memory cell. A memory region where the memory cells are provided has a first region and a second region. When the first region is read, a larger number of the select lines are simultaneously driven by the corresponding common drive circuit than those in the second region, and a larger number of the memory cells are simultaneously selected than those in the second region.03-29-2012
20120176829SEMICONDUCTOR MEMORY DEVICE WITH FERROELECTRIC DEVICE AND REFRESH METHOD THEREOF - A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a read voltage is applied to the word line and a sensing bias voltage is applied to one of the drain region and the source region, and a data write operation is performed by a polarity of the ferroelectric layer changed depending on a voltage applied to the word line, the drain region and the source region.07-12-2012
20100020587SEMICONDUCTOR MEMORY DEVICE - A ferroelectric memory is provided with a voltage generating circuit configured to generate prescribed driving potential, a driving interconnection to which the driving potential is applied, a plurality of memory cells connected to the driving interconnections and an internal voltage comparison circuit configured to compare inputted potential and to output results thereof. A plurality of voltage monitoring interconnections are provided to connect between a portion of the driving interconnection disposed at a position distant from the voltage generating circuit on the substrate and the internal voltage comparison circuit. The internal voltage comparison circuit compares potential inputted through the voltage monitoring interconnection with the driving potential.01-28-2010
20100296329Differential Plate Line Screen Test for Ferroelectric Latch Circuits - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.11-25-2010
20100195369MULTILAYER FERROELECTRIC DATA STORAGE SYSTEM WITH REGENERATIVE READ - A data storage system comprises first and second storage layers, a reader and a writer. The first storage layer has a first coercive potential and a first polarization. The second storage layer has a second coercive potential that is less than the first coercive potential, and a second polarization that is coupled to the first polarization. The writer performs a write operation in which a write potential is imposed across the first and second storage layers, such that the first coercive potential is exceeded across the first storage layer and the second coercive potential is exceeded across the second storage layer. The reader performs a read operation in which a read potential is imposed across the first and second storage layers, such that the second coercive potential is exceeded across the second storage layer and the first coercive potential is not exceeded across the first storage layer.08-05-2010
20120230079ACTUATOR AND STORAGE DEVICE - In one embodiment, an actuator has a movable member, a frame, and first and second electrodes. Each of the first electrodes has a pair of first and second planes perpendicular to a third direction which is orthogonal to the first and the second directions approximately. The second electrodes are provided alternately with the first electrode respectively and with a distance from the first electrode. Each of the second electrodes has a pair of third and fourth planes perpendicular to the third direction. The first and the second planes have a deviation in the third direction with respect to the third and the fourth planes, respectively. The amount of the deviation is larger than a maximum value of the amount of displacement of the movable member in the third direction. The amount of displacement is produced by gravity when a component of the gravity in the third direction is maximum.09-13-2012
20110122674REVERSE CONNECTION MTJ CELL FOR STT MRAM - Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower I05-26-2011
20130016551MAGNETIC RANDOM ACCESS MEMORY CELL WITH IMPROVED DISPERSION OF THE SWITCHING FIELDAANM Lombard; LucienAACI GrenobleAACO FRAAGP Lombard; Lucien Grenoble FRAANM Prejbeanu; Ioan LucianAACI Seyssinet ParisetAACO FRAAGP Prejbeanu; Ioan Lucian Seyssinet Pariset FR - The present disclosure concerns a magnetic random access memory MRAM cell comprising a tunnel magnetic junction formed from a first ferromagnetic layer, a second ferromagnetic layer having a second magnetization that can be oriented relative to an anisotropy axis of the second ferromagnetic layer at a predetermined high temperature threshold, and a tunnel barrier; a first current line extending along a first direction and in communication with the magnetic tunnel junction; the first current line being configured to provide an magnetic field for orienting the second magnetization when carrying a field current; wherein the MRAM cell is configured with respect to the first current line such that when providing the magnetic field, at least a component of the magnetic field is substantially perpendicular to said anisotropy axis. The MRAM cell has an improved switching efficiency, lower power consumption and improved dispersion of the switching field compared to conventional MRAM cells.01-17-2013
20130021833DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.01-24-2013
20120243291Crosspoint Array and Method of Use with a Crosspoint Array Having Crossbar Elements Having a Solid Electrolyte Material Used as a Rectifier with a Symmetric or Substantially Symmetric Resistive Memory - A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state.09-27-2012
20080225570OVER-DRIVEN ACCESS METHOD AND DEVICE FOR FERROELECTRIC MEMORY - An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line /bit-line voltage using the plate-line /bit-line driven method.09-18-2008
20080225569FERROELECTRIC CAPACITOR AND ITS MANUFACTURING METHOD - A ferroelectric capacitor includes: a ferroelectric film, and a lower electrode and an upper electrode interposing the ferroelectric film, wherein the ferroelectric film includes a first ferroelectric layer of ferroelectric material having a perovskite type crystal structure expressed by a general formula ABO09-18-2008
20080219038FERROELECTRIC MEMORY DEVICE - Disclosed is a ferroelectric memory device. Multiple memory cells are connected between bit lines and a plate line, and constitute a memory cell array. Each of the memory cells is composed of a first ferroelectric capacitor and a memory cell transistor. The gates of the memory cell transistors are connected to multiple word lines, respectively. The bit lines are connected to multiple sense amplifiers for amplifying information. One end of the second ferroelectric capacitor is electrically connected to a corresponding one of the bit lines, and the other end of the second ferroelectric capacitor is electrically connected to a power supply.09-11-2008
20120250391MAGNETIC RANDOM ACCESS MEMORY CELL WITH A DUAL JUNCTION FOR TERNARY CONTENT ADDRESSABLE MEMORY APPLICATIONS - The present disclosure concerns a MRAM cell comprising a first tunnel barrier layer comprised between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer comprised between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.10-04-2012
20130094274METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - An object of the present invention is to provide a novel method for driving a semiconductor memory device.04-18-2013
20130100724HIGH DENSITY MOLECULAR MEMORY STORAGE WITH READ AND WRITE CAPABILITIES - A memory element is provided that includes a ferromagnetic (FM) layer having one or more ferromagnetic materials. One or more first molecule layers are positioned on the FM layer where charge transfer and interface chemistry between the one or more first molecule layers and FM layer induces a magnetic moment in the one or more first molecule layers. The magnetic moment is stored in the one or more first molecule layers acting as bit information that is retained or written into the one or more first molecule layers. One or more spin-filter layers are positioned on the one or more first molecule layers. The one or more spin-filter layers are positioned on the one or more spin-filter layers to form a physical or a chemical π-dimer layer structure.04-25-2013
20080198644Data Storage Device - In a non-volatile electric memory system a memory unit (08-21-2008
20130135918SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.05-30-2013
20110255328SEMICONDUCTOR MEMORY DEVICE - The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.10-20-2011
20120275209Embedded Non-Volatile Memory Circuit for Implementing Logic Functions Across Periods of Power Disruption - A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.11-01-2012
20120281451Ferro-Resistive Random Access Memory (FERRO-RRAM), Operation Method and Manufacturing Method Thereof - The invention provides a Ferro-RRAM, a method of operating the Ferro-RRAM, and a method of fabricating the Ferro-RRAM, and pertains to the technical field of memory. The Ferro-RRAM comprises an upper electrode, a lower electrode, and a ferroelectric semiconducting thin-film layer provided between the upper electrode and the lower electrode and serving as a storage function layer; wherein the ferroelectric semiconducting thin-film layer is operable to generate a diode conduction characteristic by ferroelectric domain reorientation, and is operable to modulate the diode conduction characteristic by variation of the ferroelectric domain orientation; the Ferro-RRAM stores information according to variation of modulation of the diode conduction characteristic. The Ferro-RRAM has such characteristics of being simple in structure and fabrication, non-destructive readout and nonvolatile storage.11-08-2012
20110310651Variable Impedance Circuit Controlled by a Ferroelectric Capacitor - A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.12-22-2011
20110310650 SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING THEREOF - In the operating method of the semiconductor memory device, (1) voltages V12-22-2011
20130188411Analog Memories Utilizing Ferroelectric Capacitors - A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes having a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.07-25-2013
20130188412FERROELECTRIC RANDOM ACCESS MEMORY AND MEMORY SYSTEM - In one embodiment, a non-volatile memory includes a first buffer that receives notification of power-down and outputs a first signal changed from a first value to a second value based on the notification, a first controlling unit that receives and outputs a command signal, a second controlling unit that generates and outputs a basic signal that has a third value when the command signal output from the first controlling unit indicates an active command and has a fourth value when the command signal indicates a command corresponding to a write back instruction or the first signal has the second value, a memory cell array in which memory cells are arrayed, and a sense amplifier circuit that reads data from the memory cell.07-25-2013
20120081943Polarization-Coupled Ferroelectric Unipolar Junction Memory And Energy Storage Device - A memory device is provided. The memory device includes a plurality of memory cells and a controller to write data to and read data from the memory cells. Each memory cell includes a first semiconductor material having a spontaneous polarization, a resistive ferroelectric material having a switchable spontaneous polarization, and a second semiconductor material having a spontaneous polarization, the resistive ferroelectric material being positioned between and in contact with the first and second semiconductor materials. The memory device can be configured to store energy that can be released by applying a voltage pulse to the memory device.04-05-2012
20120092918VERIFICATION SYSTEM - A verification system of the present invention is provided to perform unidirectional or bidirectional verification between a master apparatus and a slave apparatus comprising the master apparatus having a master memory capable of storing verification key code in a non-volatile manner and the slave apparatus having a slave memory capable of storing verification key code in the non-volatile manner, wherein at least the slave memory is one of the group consisting of non-volatile logic circuit and ferroelectric an memory, both of which use hysteresis characteristics of ferroelectric components.04-19-2012

Patent applications in class Ferroelectric