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READ ONLY SYSTEMS (I.E.. SEMIPERMANENT)

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365 - Static information storage and retrieval

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
365096000 Fusible 103
365103000 Semiconductive 70
365100000 Resistive 16
365102000 Capacitative 4
20130083586INTEGRATED CIRCUIT WITH A SELF-PROGRAMMED IDENTIFICATION KEY - A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.04-04-2013
20100061137One-time programmable read only memory - For realizing high speed one time programmable memory, bit line is multi-divided for reducing capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for connecting divided bit line, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp for reading the memory cell, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a voltage difference in the bit line is converted to a time difference for differentiating high data (programmed) and low data (unprogrammed) by the multi-stage sense amps. And buffered data path is connected to the global sense amp for realizing fast data transfer. Additionally, alternative circuits and memory cell structures are described.03-11-2010
20120099361SEMICONDUCTOR CAPACITOR, ONE TIME PROGRAMMABLE MEMORY CELL AND FABRICATING METHOD AND OPERATING METHOD THEREOF - A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.04-26-2012
20120087170Single Polysilicon Non-Volatile Memory - A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.04-12-2012
365097000 Magnetic 1
20100091546HIGH DENSITY RECONFIGURABLE SPIN TORQUE NON-VOLATILE MEMORY - One time programmable memory units include a magnetic tunnel junction cell electrically coupled to a bit line and a word line. The magnetic tunnel junction cell is pre-programmed to a first resistance state, and is configured to switch only from the first resistance state to a second resistance state by passing a voltage across the magnetic tunnel junction cell. In some embodiments, a transistor is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. In other embodiments, a device having a rectifying switching characteristic, such as a diode or other non-ohmic device, is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. Methods of pre-programming the one time programmable memory units and reading and writing to the units are also disclosed.04-15-2010
Entries
DocumentTitleDate
20090207644MEMORY CELL ARCHITECTURE - Embodiments of the present invention disclose a memory architecture for optimizing memory performance and size. Memory optimization is realized by configuring the memory to a particular logic state; that is, restricting memory data storage to either logic “0” or “1.” The opposite logic state, “1” or “0,” can be available through initialization and, therefore, may be presumed. Accordingly, the presumed, initialized logic state is available unless the configured logic state in memory changes the initialized data during memory access. Memory size reduction is realized by restricting physical memory to contain only cells that store data. Memory size can be further reduced by eliminating redundant data rows and columns. By reducing memory size, processing speed can be enhanced and power consumption reduced relative to conventional memory structures.08-20-2009
20130039114WRITING CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND WRITING METHOD - A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.02-14-2013
20130039116PROGRAMMABLE READ-ONLY MEMORY DEVICE AND METHOD OF WRITING THE SAME - A bit cell of the PROM-device comprises a carbon nanotube having a tilted portion comprising a free end and a fixed portion which is to the reference node. The carbon nanotube comprises a structural defect between the fixed and the tilted portion which causes the carbon nanotube to tilt such that the free end is electrically connected to either the storage electrode or an opposite release electrode.02-14-2013
20130039115FIELD PROGRAMMABLE READ-ONLY MEMORY DEVICE - The field programmable read-only memory device comprises a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between word line and a bit line and comprises a static body and a moveable connecting element. The switchable electrical connection is non-volatile.02-14-2013
20120182782METHODS FOR TESTING UNPROGRAMMED OTP MEMORY - Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test cells having an access transistor identically configured to the access transistor of a normal memory cell, but omitting the anti-fuse device found in the normal memory cell, for testing the presence of a connection of the normal memory cell to the bitline. Such a test cell can be used in a further test for determining the level of capacitive coupling of the wordline voltage to the bitlines relative to that of a normal memory cell under test.07-19-2012
20090237973Design method for read-only memory devices - A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.09-24-2009
20090046494Semiconductor memory device - Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory device includes a plurality of memory banks, a plurality of second bit lines, a plurality of selector circuits, a voltage supply circuit. Each of the memory banks includes a plurality of first bit lines, a plurality of word lines, and a plurality of memory banks which are installed between the first bit lines and the word lines. The voltage supply circuit holds non-select bit lines of the first bit lines at the GND level at all times.02-19-2009
20130188410METHOD AND APPARATUS FOR TESTING ONE TIME PROGRAMMABLE (OTP) ARRAYS - An array of one time programmable (OTP) devices includes a first set of pre-configurable memory devices appended to one or more columns of me array and a second set of pre-configurable memory devices appended to one or more rows of the array. The pre-configurable memory devices may be additional OTP devices or read only memory (ROM) devices that can be configured to store a predetermined test pattern for the array. Rows, columns and functionalities of the array can be tested based on the stored test pattern. OTP devices in the array may then be programmed after successful testing based on the test pattern stored.07-25-2013
20110292710SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR - A semiconductor device includes a first and a second ROMs; and a first control circuit having an input node and sets a first and a second addresses that are different each other to be respectively recorded in the first and second ROMs from a plurality of input addresses supplied sequentially into the input node, on the basis of a setting signal, the plurality of input addresses including the first and second addresses, wherein the first control circuit being configured to set an input address as the first address based on the setting signal, and the first control circuit further being configured to set an input address as the second address on the basis of the setting signal when the first and second addresses are different each other in a predetermined portion of bits after the first address is set to the first ROM.12-01-2011
20120106231LOW-PIN-COUNT NON-VOLATILE MEMORY INTERFACE - A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. In one embodiment, the low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface.05-03-2012
20090262565METHOD FOR PROGRAMMING NONVOLATILE MEMORY DEVICE - Disclosed is a method for programming a nonvolatile memory device including one time programmable unit cells. The method for programming a nonvolatile memory device including one time programmable (OTP) unit cells, the method comprising applying a pulse type program voltage having a plurality of cycles. The present invention relates to a method for programming a nonvolatile memory device, which can prevent malfunctions by enhancing a data sensing margin in a read operation through the normal dielectric breakdown of an antifuse during a program operation, and thus improve the reliability in the read operation of an OTP unit cell.10-22-2009
20080212354BIASED SENSING MODULE - A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.09-04-2008
20110007542TESTING ONE TIME PROGRAMMING DEVICES - A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.01-13-2011
20110141791SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY - A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins.06-16-2011
20090086524PROGRAMMABLE ROM USING TWO BONDED STRATA AND METHOD OF OPERATION - A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.04-02-2009
20090086525Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array.04-02-2009
20100259965HIGH SPEED OTP SENSING SCHEME - A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.10-14-2010
20100188880POWER SWITCHING FOR PORTABLE APPLICATIONS - A voltage generation and power switching apparatus, method and system is described. The apparatus includes a digital media processing chip. The digital media processing chip includes a control unit, a one-time programmable memory, a charge pump and a switching network. The control unit is to receive an operating state. The charge pump is connected to a first voltage and configured to generate a second voltage using the first voltage. The control unit activates the charge pump based upon the received operating state. The one-time programmable memory is connected to the charge pump via a switching network. The switching network is configured by the control unit to provide a voltage required by the received operating state to the one-time programmable memory.07-29-2010
20090316464LOW POWER READ SCHEME FOR READ ONLY MEMORY (ROM) - A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.12-24-2009
20090316463Semiconductor Device and Method for Making Same - Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.12-24-2009
20130215662ANTI-FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.08-22-2013
20090251942METHOD OF PROGRAMMING A MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE AND INTEGRATED CIRCUIT INCORPORATING SUCH A MEMORY - A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.10-08-2009
20110235387SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.09-29-2011
20090316465EFFICIENT WORD LINES, BIT LINE AND PRECHARGE TRACKING IN SELF-TIMED MEMORY DEVICE - A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.12-24-2009
20110019459Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space - The present invention discloses a three-dimensional mask-programmable read-only memory with reserved space (3D-MPROM01-27-2011
20100177547MEMORY DEVICE AND MEMORY ACCESS METHOD - Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.07-15-2010
20110122671Systems and methods for controlling integrated circuit operation with below ground pin voltage - Systems and methods for controlling operation of an integrated circuit by applying below ground voltage to one or more pins of the integrated circuit, and in which the application of a below ground pin voltage may be employed as an initiator of (or condition for) a given mode of circuit operation in a manner that prevents the inadvertent initiation of the given mode of operation that may otherwise occur due to accidental application of an above ground voltage to one or more pins of the integrated circuit.05-26-2011
20090323387One-Time Programmable Memory and Operating Method Thereof - A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on one of the source/drain regions; a capacitive dielectric layer disposed on the gate electrode and the other of the source/drain regions; a first conductive plug disposed on the first salicide layer; and a second conductive plug disposed on the capacitive dielectric layer. The size of the first conductive plug is different form the size of the second conductive plug.12-31-2009
20130163306One-Time Programmable Memory Cell, Memory and Manufacturing Method Thereof - The present invention pertains to the technical field of one-time programmable memory (OTP), and in particular to a one-time programmable memory unit, OTP, and method of fabricating the same. The OTP unit comprises a lower electrode, an upper electrode and a storage medium layer placed between the upper electrode and the lower electrode, the storage medium layer comprises a first metal oxide layer and a second metal oxide layer, wherein an adjoining area for programming is formed between the first metal oxide layer and the second metal oxide layer. The OTP comprises a plurality of the above-described one-time programmable memory units arranged in rows and columns. The OTP unit and the OTP have such characteristics as low programming voltage, small unit area, being able to integrate into a back-end structure of integrated circuit, great process flexibility, and the method of fabricating the OTP unit and the OTP is relatively simple and low in cost.06-27-2013
20100195366Reducing Leakage Current in a Memory Device - Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.08-05-2010
20100195365ROM array - A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design.08-05-2010
20100027312Compact Virtual Ground Diffusion Programmable ROM Array Architecture, System and Method - A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.02-04-2010
20100165698NON-VOLATILE ONE-TIME - PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY CONFIGURATION CIRCUIT - A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.07-01-2010
20110317467SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element.12-29-2011
20120026775METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.02-02-2012
20130010519SYSTEM AND METHOD FOR UPDATING READ-ONLY MEMORY IN SMART CARD MEMORY MODULES - A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may be accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from “read-only” to “read/write” to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only.01-10-2013
20130010518ANTI-FUSE MEMORY ULTILIZING A COUPLING CHANNEL AND OPERATING METHOD THEREOF - An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.01-10-2013
20110128768MEMORY INTERFACE CIRCUIT - According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit controls, taking into account a state of a past input signal output from the differential circuit, the potential of the present differential signal output from the differential circuit. A sense amplifier detects a state of the differential signal output from the equalizing circuit. A state holding circuit holds a past state of the differential signal detected by the sense amplifier and supplies the state to the equalizing circuit.06-02-2011
20120163062MEMORY DEVICE AND MEMORY ACCESS METHOD - Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data, the memory device being built from an OTP memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the memory sets operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.06-28-2012
20100208505ANTI-CROSS-TALK CIRCUITRY FOR ROM ARRAYS - A circuit and method precharge a selected bit-line in a read only memory (ROM) array during a precharge period of a read cycle. At least one bit-line adjacent to the selected bit-line is discharged during the precharge period. After the precharge period, the selected bit-line is read such that parasitic capacitance effects on the selected bit-line are reduced.08-19-2010
20110182101SEMICONDUCTOR MEMORY DEVICE WITH SECURITY FUNCTION AND CONTROL METHOD THEREOF - A semiconductor memory device includes a security controller. When a one time programmable (OTP) device is programmed, the semiconductor memory device prohibits lock-status information pre-stored in an OTP lock register from being changed to an unlock status, such that it increases the stability of data stored in an OTP area. The semiconductor memory device includes an OTP device configured to determine whether or not data is changed according to a lock/unlock status when a program command is received, and an OTP controller configured to prohibit the lock status from being changed to the unlock status.07-28-2011
20120081942TEST CELLS FOR AN UNPROGRAMMED OTP MEMORY ARRAY - Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order to detect mask misalignment along that dimension. Any fabricated test cell which cannot be programmed indicates a level of fabrication mask misalignment has occurred and the OTP memory array should not be used.04-05-2012
20120327699WORD LINE FAULT DETECTION - In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word line driver, a selected word line, and, for each bit position, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line. In response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously.12-27-2012
20100202183HIGH RELIABILITY OTP MEMORY - A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in a multi-cell per bit mode. By storing one bit of data in at least two OTP memory cells, defective cells or weakly programmable cells are compensated for since the additional cell or cells provide inherent redundancy. Program reliability is ensured by programming the data one bit at a time, and verifying all programmed bits in a single-ended read mode, prior to normal operation where the data is read out in the multi-cell per bit mode. Programming and verification is achieved at high speed and with minimal power consumption using a novel program/verify algorithm for anti-fuse memory. In addition to improved reliability, read margin and read speed are improved over single cell per bit memories.08-12-2010
20110157956METHOD AND APPARATUS FOR INCREASING YIELD - Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.06-30-2011
20080212355Compact Virtual Ground Diffusion Programmable ROM Array Architecture, System and Method - A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.09-04-2008
20080205115APPARATUS AND METHOD FOR TRIMMING INTEGRATED CIRCUIT - A trimming apparatus including a switch transistor and a one-time programming (OTP) memory component is provided. The switch transistor has a first source/drain terminal connected to a first bias voltage, a gate terminal used for receiving a switch signal, and a second source/drain terminal connected to a first source/drain terminal of the OTP memory component. When the trimming apparatus provided by the present invention intends to perform trimming for an integrated circuit, the switch transistor is conducted to program the OTP memory component.08-28-2008
20100315855ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.12-16-2010
20090207644MEMORY CELL ARCHITECTURE - Embodiments of the present invention disclose a memory architecture for optimizing memory performance and size. Memory optimization is realized by configuring the memory to a particular logic state; that is, restricting memory data storage to either logic “0” or “1.” The opposite logic state, “1” or “0,” can be available through initialization and, therefore, may be presumed. Accordingly, the presumed, initialized logic state is available unless the configured logic state in memory changes the initialized data during memory access. Memory size reduction is realized by restricting physical memory to contain only cells that store data. Memory size can be further reduced by eliminating redundant data rows and columns. By reducing memory size, processing speed can be enhanced and power consumption reduced relative to conventional memory structures.08-20-2009
20130039114WRITING CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND WRITING METHOD - A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.02-14-2013
20130039116PROGRAMMABLE READ-ONLY MEMORY DEVICE AND METHOD OF WRITING THE SAME - A bit cell of the PROM-device comprises a carbon nanotube having a tilted portion comprising a free end and a fixed portion which is to the reference node. The carbon nanotube comprises a structural defect between the fixed and the tilted portion which causes the carbon nanotube to tilt such that the free end is electrically connected to either the storage electrode or an opposite release electrode.02-14-2013
20130039115FIELD PROGRAMMABLE READ-ONLY MEMORY DEVICE - The field programmable read-only memory device comprises a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between word line and a bit line and comprises a static body and a moveable connecting element. The switchable electrical connection is non-volatile.02-14-2013
20120182782METHODS FOR TESTING UNPROGRAMMED OTP MEMORY - Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test cells having an access transistor identically configured to the access transistor of a normal memory cell, but omitting the anti-fuse device found in the normal memory cell, for testing the presence of a connection of the normal memory cell to the bitline. Such a test cell can be used in a further test for determining the level of capacitive coupling of the wordline voltage to the bitlines relative to that of a normal memory cell under test.07-19-2012
20090237973Design method for read-only memory devices - A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.09-24-2009
20090046494Semiconductor memory device - Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory device includes a plurality of memory banks, a plurality of second bit lines, a plurality of selector circuits, a voltage supply circuit. Each of the memory banks includes a plurality of first bit lines, a plurality of word lines, and a plurality of memory banks which are installed between the first bit lines and the word lines. The voltage supply circuit holds non-select bit lines of the first bit lines at the GND level at all times.02-19-2009
20130188410METHOD AND APPARATUS FOR TESTING ONE TIME PROGRAMMABLE (OTP) ARRAYS - An array of one time programmable (OTP) devices includes a first set of pre-configurable memory devices appended to one or more columns of me array and a second set of pre-configurable memory devices appended to one or more rows of the array. The pre-configurable memory devices may be additional OTP devices or read only memory (ROM) devices that can be configured to store a predetermined test pattern for the array. Rows, columns and functionalities of the array can be tested based on the stored test pattern. OTP devices in the array may then be programmed after successful testing based on the test pattern stored.07-25-2013
20110292710SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR - A semiconductor device includes a first and a second ROMs; and a first control circuit having an input node and sets a first and a second addresses that are different each other to be respectively recorded in the first and second ROMs from a plurality of input addresses supplied sequentially into the input node, on the basis of a setting signal, the plurality of input addresses including the first and second addresses, wherein the first control circuit being configured to set an input address as the first address based on the setting signal, and the first control circuit further being configured to set an input address as the second address on the basis of the setting signal when the first and second addresses are different each other in a predetermined portion of bits after the first address is set to the first ROM.12-01-2011
20120106231LOW-PIN-COUNT NON-VOLATILE MEMORY INTERFACE - A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. In one embodiment, the low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface.05-03-2012
20090262565METHOD FOR PROGRAMMING NONVOLATILE MEMORY DEVICE - Disclosed is a method for programming a nonvolatile memory device including one time programmable unit cells. The method for programming a nonvolatile memory device including one time programmable (OTP) unit cells, the method comprising applying a pulse type program voltage having a plurality of cycles. The present invention relates to a method for programming a nonvolatile memory device, which can prevent malfunctions by enhancing a data sensing margin in a read operation through the normal dielectric breakdown of an antifuse during a program operation, and thus improve the reliability in the read operation of an OTP unit cell.10-22-2009
20080212354BIASED SENSING MODULE - A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.09-04-2008
20110007542TESTING ONE TIME PROGRAMMING DEVICES - A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.01-13-2011
20110141791SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY - A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins.06-16-2011
20090086524PROGRAMMABLE ROM USING TWO BONDED STRATA AND METHOD OF OPERATION - A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.04-02-2009
20090086525Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array.04-02-2009
20100259965HIGH SPEED OTP SENSING SCHEME - A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.10-14-2010
20100188880POWER SWITCHING FOR PORTABLE APPLICATIONS - A voltage generation and power switching apparatus, method and system is described. The apparatus includes a digital media processing chip. The digital media processing chip includes a control unit, a one-time programmable memory, a charge pump and a switching network. The control unit is to receive an operating state. The charge pump is connected to a first voltage and configured to generate a second voltage using the first voltage. The control unit activates the charge pump based upon the received operating state. The one-time programmable memory is connected to the charge pump via a switching network. The switching network is configured by the control unit to provide a voltage required by the received operating state to the one-time programmable memory.07-29-2010
20090316464LOW POWER READ SCHEME FOR READ ONLY MEMORY (ROM) - A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.12-24-2009
20090316463Semiconductor Device and Method for Making Same - Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.12-24-2009
20130215662ANTI-FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.08-22-2013
20090251942METHOD OF PROGRAMMING A MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE AND INTEGRATED CIRCUIT INCORPORATING SUCH A MEMORY - A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.10-08-2009
20110235387SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.09-29-2011
20090316465EFFICIENT WORD LINES, BIT LINE AND PRECHARGE TRACKING IN SELF-TIMED MEMORY DEVICE - A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.12-24-2009
20110019459Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space - The present invention discloses a three-dimensional mask-programmable read-only memory with reserved space (3D-MPROM01-27-2011
20100177547MEMORY DEVICE AND MEMORY ACCESS METHOD - Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.07-15-2010
20110122671Systems and methods for controlling integrated circuit operation with below ground pin voltage - Systems and methods for controlling operation of an integrated circuit by applying below ground voltage to one or more pins of the integrated circuit, and in which the application of a below ground pin voltage may be employed as an initiator of (or condition for) a given mode of circuit operation in a manner that prevents the inadvertent initiation of the given mode of operation that may otherwise occur due to accidental application of an above ground voltage to one or more pins of the integrated circuit.05-26-2011
20090323387One-Time Programmable Memory and Operating Method Thereof - A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on one of the source/drain regions; a capacitive dielectric layer disposed on the gate electrode and the other of the source/drain regions; a first conductive plug disposed on the first salicide layer; and a second conductive plug disposed on the capacitive dielectric layer. The size of the first conductive plug is different form the size of the second conductive plug.12-31-2009
20130163306One-Time Programmable Memory Cell, Memory and Manufacturing Method Thereof - The present invention pertains to the technical field of one-time programmable memory (OTP), and in particular to a one-time programmable memory unit, OTP, and method of fabricating the same. The OTP unit comprises a lower electrode, an upper electrode and a storage medium layer placed between the upper electrode and the lower electrode, the storage medium layer comprises a first metal oxide layer and a second metal oxide layer, wherein an adjoining area for programming is formed between the first metal oxide layer and the second metal oxide layer. The OTP comprises a plurality of the above-described one-time programmable memory units arranged in rows and columns. The OTP unit and the OTP have such characteristics as low programming voltage, small unit area, being able to integrate into a back-end structure of integrated circuit, great process flexibility, and the method of fabricating the OTP unit and the OTP is relatively simple and low in cost.06-27-2013
20100195366Reducing Leakage Current in a Memory Device - Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.08-05-2010
20100195365ROM array - A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design.08-05-2010
20100027312Compact Virtual Ground Diffusion Programmable ROM Array Architecture, System and Method - A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.02-04-2010
20100165698NON-VOLATILE ONE-TIME - PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY CONFIGURATION CIRCUIT - A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.07-01-2010
20110317467SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element.12-29-2011
20120026775METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.02-02-2012
20130010519SYSTEM AND METHOD FOR UPDATING READ-ONLY MEMORY IN SMART CARD MEMORY MODULES - A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may be accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from “read-only” to “read/write” to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only.01-10-2013
20130010518ANTI-FUSE MEMORY ULTILIZING A COUPLING CHANNEL AND OPERATING METHOD THEREOF - An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.01-10-2013
20110128768MEMORY INTERFACE CIRCUIT - According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit controls, taking into account a state of a past input signal output from the differential circuit, the potential of the present differential signal output from the differential circuit. A sense amplifier detects a state of the differential signal output from the equalizing circuit. A state holding circuit holds a past state of the differential signal detected by the sense amplifier and supplies the state to the equalizing circuit.06-02-2011
20120163062MEMORY DEVICE AND MEMORY ACCESS METHOD - Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data, the memory device being built from an OTP memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the memory sets operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.06-28-2012
20100208505ANTI-CROSS-TALK CIRCUITRY FOR ROM ARRAYS - A circuit and method precharge a selected bit-line in a read only memory (ROM) array during a precharge period of a read cycle. At least one bit-line adjacent to the selected bit-line is discharged during the precharge period. After the precharge period, the selected bit-line is read such that parasitic capacitance effects on the selected bit-line are reduced.08-19-2010
20110182101SEMICONDUCTOR MEMORY DEVICE WITH SECURITY FUNCTION AND CONTROL METHOD THEREOF - A semiconductor memory device includes a security controller. When a one time programmable (OTP) device is programmed, the semiconductor memory device prohibits lock-status information pre-stored in an OTP lock register from being changed to an unlock status, such that it increases the stability of data stored in an OTP area. The semiconductor memory device includes an OTP device configured to determine whether or not data is changed according to a lock/unlock status when a program command is received, and an OTP controller configured to prohibit the lock status from being changed to the unlock status.07-28-2011
20120081942TEST CELLS FOR AN UNPROGRAMMED OTP MEMORY ARRAY - Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order to detect mask misalignment along that dimension. Any fabricated test cell which cannot be programmed indicates a level of fabrication mask misalignment has occurred and the OTP memory array should not be used.04-05-2012
20120327699WORD LINE FAULT DETECTION - In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word line driver, a selected word line, and, for each bit position, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line. In response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously.12-27-2012
20100202183HIGH RELIABILITY OTP MEMORY - A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in a multi-cell per bit mode. By storing one bit of data in at least two OTP memory cells, defective cells or weakly programmable cells are compensated for since the additional cell or cells provide inherent redundancy. Program reliability is ensured by programming the data one bit at a time, and verifying all programmed bits in a single-ended read mode, prior to normal operation where the data is read out in the multi-cell per bit mode. Programming and verification is achieved at high speed and with minimal power consumption using a novel program/verify algorithm for anti-fuse memory. In addition to improved reliability, read margin and read speed are improved over single cell per bit memories.08-12-2010
20110157956METHOD AND APPARATUS FOR INCREASING YIELD - Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.06-30-2011
20080212355Compact Virtual Ground Diffusion Programmable ROM Array Architecture, System and Method - A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.09-04-2008
20080205115APPARATUS AND METHOD FOR TRIMMING INTEGRATED CIRCUIT - A trimming apparatus including a switch transistor and a one-time programming (OTP) memory component is provided. The switch transistor has a first source/drain terminal connected to a first bias voltage, a gate terminal used for receiving a switch signal, and a second source/drain terminal connected to a first source/drain terminal of the OTP memory component. When the trimming apparatus provided by the present invention intends to perform trimming for an integrated circuit, the switch transistor is conducted to program the OTP memory component.08-28-2008
20100315855ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.12-16-2010

Patent applications in class READ ONLY SYSTEMS (I.E.. SEMIPERMANENT)

Patent applications in all subclasses READ ONLY SYSTEMS (I.E.. SEMIPERMANENT)