Class / Patent application number | Description | Number of patent applications / Date published |
365052000 | HARDWARE FOR STORAGE ELEMENTS | 20 |
20080291713 | MODULAR FLASH MEMORY CARD EXPANSION SYSTEM - A memory card system is disclosed. The memory card system comprises at least one flash memory card and a module for holding the at least one memory card. The module comprises a plurality of supports. The supports include rails to guide the at least one memory card in place and a latch system for securing the at least one memory card to the module. The present invention provides a modular flash memory card expansion system using any standard Secure Digital card; the flash memory card can be any flash-based memory card, such as SD, Compact Flash (CF), MMC, Memory Stick or others. | 11-27-2008 |
20090021972 | MEMORY ARRAY USING MECHANICAL SWITCH AND METHOD FOR OPERATING THEREOF - A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V | 01-22-2009 |
20090122588 | PHASE CHANGE MEMORY CELL INCLUDING A THERMAL PROTECT BOTTOM ELECTRODE AND MANUFACTURING METHODS - Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a bottom electrode, a thermal protect structure on the bottom electrode, and a multi-layer stack on the thermal protect structure. The thermal protect structure comprises a layer of thermal protect material, the thermal protect material having a thermal conductivity less than that of the bottom electrode material. | 05-14-2009 |
20100085791 | DRIVER UNIT - A driving apparatus ( | 04-08-2010 |
20110128765 | IDENTIFYING AND ACCESSING INDIVIDUAL MEMORY DEVICES IN A MEMORY CHANNEL - In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register. | 06-02-2011 |
20110216570 | RANK SELECT USING A GLOBAL SELECT PIN - Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks. | 09-08-2011 |
20120075902 | IDENTIFYING AND ACCESSING INDIVIDUAL MEMORY DEVICES IN A MEMORY CHANNEL - In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register. | 03-29-2012 |
20150294712 | PRINTED CIRCUIT BOARD AND PRINTED WIRING BOARD - A first reception circuit and a second reception circuit are mounted on a printed circuit board, and receive signals via wiring thereof from a transmission circuit. The printed wiring board includes a trunk wiring, a first branched line branching from a first branch connection point, and a second branched line branching from a second branch connection point in order. A wiring area between the start end and the first branch connection point is divided into a first wiring portion and a second wiring portion, in order from the start end, and a wiring area between the first branch connection point and the second branch connection point is a third wiring portion. The characteristic impedance of the first wiring portion is set to equal or lower than the characteristic impedance of the third wiring portion, and the characteristic impedance of the second wiring portion is set higher than the characteristic impedance of the first wiring portion. | 10-15-2015 |
20150340074 | MEMORY MODULE HAVING ADDRESS MIRRORING FUNCTION - A memory module having an address minoring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored. | 11-26-2015 |
20150371684 | ULTRA HIGH CAPACITY SSD - The solution described here is a modular, very high capacity SSD realization. The SSD design and modular memory elements renders the SSD both factory and field serviceable as well as facilitating just-in-time manufacturing processes. In the case of improving the factory reparability of the drive, the modular memory elements can be tested (and repaired) independent of the main SSD. This reduces costs and risks in the manufacturing and repair process. The manufacturing process is improved by allowing for the staging of elements, such as variable sized memory cards, to facilitate last minute assembly and test of the product. By separating the assembly and test of the expensive and complex main board, with its FPGA control, power and memory elements (DRAM), from the simpler memory card, the timing to delivery is improved, the risk is reduced, and inventory costs are minimized. From a field-repairable perspective, the solution is conceived such that a failing storage element can be replaced in the field and the lost memory image automatically rebuilt on the next power up using the integrated redundancy (RAID) capability while continuing to run host initiated commands, albeit at a reduced performance level. | 12-24-2015 |
365053000 | Shields | 9 |
20090073737 | Integrated Circuits; Methods for Manufacturing an Integrating Circuit; Memory Modules - Embodiments of the invention relate generally to integrated circuits, to methods for manufacturing an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit is provided having a memory cell. The memory cell may include a first magnetic layer structure, a tunnel barrier layer structure disposed above the first magnetic layer structure, a second magnetic layer structure disposed above the tunnel barrier layer structure, and at least one sacrificial material layer to suppress electrochemical corrosion of the first magnetic layer structure or the second magnetic layer structure. | 03-19-2009 |
20090073738 | Active Shielding for a Circuit Comprising Magnetically Sensitive Materials - The present invention provides a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials, comprising actively shielding the circuit from a disturbing magnetic field. A corresponding semiconductor device is also provided. The method and device allows shielding for strong disturbing magnetic fields. | 03-19-2009 |
20110007540 | MAGNETIC SHIELDING FOR INTEGRATED CIRCUIT - A shielded integrated circuit structure including an integrated circuit having a plurality of functional elements thereon, and a tiled array comprising a plurality of shielding elements, each functional element having one of the plurality of shielding elements proximate thereto. The shielding elements comprise a magnetic material having a saturation less than or equal to 20,000 gauss. | 01-13-2011 |
20110019456 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes a second sense voltage on the sense node in response to the first sense voltage. The reference input stage circuit comprises an output node and a second input node, which is for maintaining a first reference voltage established by the reference current and establishes a second reference voltage on the reference node in response to the first reference voltage. The output stage circuit obtains a sense result in response to the second reference voltage and the second sense voltage. The first shielding circuit shields the output node from being interfered with the second reference voltage on the reference node. | 01-27-2011 |
20110317464 | PORTABLE INFORMATION APPARATUS - The present disclosure provides a portable information apparatus, including, an apparatus main body, an incidental article mounted on the apparatus main body when the portable information apparatus is used, a solid-state magnetic memory provided at a portion of the apparatus main body at which the incidental article is mounted and adapted to retain information in accordance with a magnetization state of a magnetic material, and a magnetic shield provided on the incidental article including a portion opposed to the solid-state magnetic memory when the incidental article is mounted on the apparatus main body. | 12-29-2011 |
20120127773 | SEMICONDUCTOR DEVICE HAVING DATA BUS - A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers. | 05-24-2012 |
20130051109 | Method of reading a ferroelectric memory cell - A method of reading a memory cell is disclosed. The method includes the step of connecting ( | 02-28-2013 |
20140112047 | SEMICONDUCTOR DEVICE HAVING DATA BUS - A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers. | 04-24-2014 |
20150070958 | LINE LAYOUT FOR SEMICONDUCTOR MEMORY APPARATUS - Provided is a line layout for a semiconductor memory apparatus, which is a line layout of a line layer formed over a memory region so as to cross the memory region. The line layout includes as unit lines: a data line disposed between a pair of shielding lines; a pair of address line groups disposed at one side of the shielding lines; and a power supply line disposed between the pair of address line groups. | 03-12-2015 |
365055000 | Magnetic | 1 |
20110286255 | Magnetic Logic Circuits Formed with Tapered Magnetic Wires - A magnetic circuit in one aspect comprises a plurality of tapered magnetic wires each having a relatively wide input end and a relatively narrow output end, with the output end of a first one of the tapered magnetic wires being coupled to the input end of a second one of the tapered magnetic wires. Each of the tapered magnetic wires is configured to propagate a magnetic domain wall along a length of the wire in a direction of decreasing width from its input end to its output end. In an illustrative embodiment, the magnetic circuit comprises a logic buffer that includes at least one heating element. The heating element may be controlled to facilitate transfer of a magnetic moment from the output end of the first tapered magnetic wire to the input end of the second tapered magnetic wire. | 11-24-2011 |