Entries |
Document | Title | Date |
20080212350 | CAM Asynchronous Search-Line Switching - This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements | 09-04-2008 |
20080239778 | HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIES AND OTHER DATA STRUCTURES - A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line. | 10-02-2008 |
20080273362 | LOW POWER CONTENT ADDRESSABLE MEMORY - A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines. | 11-06-2008 |
20080278986 | High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array - A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements. | 11-13-2008 |
20080298110 | Content addressable memory - Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes defining the CAM into an array of data words having M rows and N columns, with each of N and M being greater than one. The data words of the CAM are arranged according to a 2-dimensional priority scheme. Data words outside a selected 1×M column are masked to be ignored in determining a match, and the CAM is searched. Each search includes N compare cycles and each compare cycle having a different 1×M column selected. A highest priority match per compare cycle is pipelined from a priority encoder with the pipelined matches arranged to communicate a priority order in a first dimension of the 2-dimensional priority scheme. | 12-04-2008 |
20090034311 | LOW POWER TERNARY CONTENT-ADDRESSABLE MEMORY (TCAM) - An integrated circuit ( | 02-05-2009 |
20090040801 | Content Addressable Memory - A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance. | 02-12-2009 |
20090059639 | Tree-style and-type match circuit device applied to content addressable memory - A tree-style AND-type match circuit device applied to the content addressable memory (CAM) is provided. In this tree-style AND-type match circuit device, a plurality of AND-type match circuit groups branchingly connect with each other by a first AND logic gate. The tree-style AND-type match circuit increases the parallelism of the evaluation of the entire match circuit so that it can efficiently reduce the searching period and the switching activity. Thus, the switching caused by the transformation activity is also shortened. As a result, the match circuit device will not increase the loading of the clock signal so the power consumption is reduced significantly. | 03-05-2009 |
20090097294 | Dual-ported and-type match-line circuit for content-addressable memories - A dual-ported AND-type match-line circuit includes at least one dual-ported dynamic AND gate. The dual-ported dynamic AND gate includes a group of CAM cells and a dual-ported dynamic circuit. A group of CAM cells connected to a dual-ported dynamic circuit and to the GND. The dual-ported dynamic circuit is connected to a group of CAM cells. The dual-ported dynamic circuit includes a setting circuit, a first directing circuit, a second directing circuit, a first AND dynamic output circuit and a second AND dynamic output circuit. | 04-16-2009 |
20090141527 | APPARATUS AND METHOD FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES - A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation. | 06-04-2009 |
20090141528 | APPARATUS AND METHOD FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY - A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array. | 06-04-2009 |
20090141529 | DESIGN STRUCTURE FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES - A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation. | 06-04-2009 |
20090141530 | STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY - A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array. | 06-04-2009 |
20090141531 | ASSOCIATIVE MEMORY AND SEARCHING SYSTEM USING THE SAME - Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times. | 06-04-2009 |
20090147556 | LOW POWER MATCH-LINE SENSING CIRCUIT - A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In other words, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current. | 06-11-2009 |
20090168479 | THREE PORT CONTENT ADDRESSABLE MEMORY - A novel schematic for executing search, write and valid bit clear operations in one cycle in a CAM system that includes a plurality of CAM blocks is disclosed. In one embodiment, the plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. The write operation depends on the output of the search operation, wherein the same data is written in to the CAM when the search operation results in a miss in a given cycle. Further, during the same cycle a valid bit clear operation is also performed. The resulting CAM cell provides a high speed three port operation. | 07-02-2009 |
20090190385 | SRAM including reduced swing amplifiers - SRAM includes reduced swing amplifiers, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing amplifier serves as a segment sense amp for reading the local sense amp, and a third reduced swing amplifier serves as a global sense amp for reading the segment sense amp through a global bit line. When reading data, a voltage difference in the local bit line is converted to a time difference by the sense amps for differentiating low data and high data, which realizes low power consumption with the reduced swing amplifiers. And, lightly local bit line is quickly discharged when reading, which realizes fast operation. Furthermore, the local bit line is discharged by the reduced memory cell, which reduces area. Additionally, alternative circuits and memory cell structures for implementing the SRAM are described. | 07-30-2009 |
20090190386 | HYBRID CONTENT ADDRESSABLE MEMORY - A CAM device memory array having different types of memory cells is disclosed. A CAM device memory array is subdivided into at least two different portions, where each portion uses only one particular type of CAM cell, and each portion is dedicated to storing a particular type of data. In particular, at least one portion consists of binary CAM cells and the other portion consists of ternary CAM cells. The portions can be partitioned along the row, or matchline, direction or along the bitline direction. Since particular data formats only require predefined bit positions of a word of data to be ternary in value, the remaining binary bit positions can be stored in binary CAM cells. Therefore, the CAM device memory array will occupy an overall area that is less than memory arrays of the same density consisting exclusively of ternary CAM cells. | 07-30-2009 |
20090201709 | CONTENT ADDRESSABLE MEMORY - The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry. | 08-13-2009 |
20090219739 | Range-Matching Cell and Content Addressable Memories Using the Same - A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell ( | 09-03-2009 |
20090290399 | CONTENT ADDRESSABLE MEMORY BASED ON A RIPPLE SEARCH SCHEME - A scheme for ultra-low power content addressable memory based on a ripple search is disclosed. In one embodiment, a system for content addressable memory (CAM), includes a storage unit for storing a portion of content data, and a match module for comparing the portion of the content data with a respective portion of search data received by the match module. The match module includes a first static logic gate associated with a first half of the storage unit storing a sub-portion of the portion of the content data, and a second static logic gate associated with a second half of the storage unit. The first static logic gate forwards a signal for disabling the second static logic gate if the sub-portion of the portion of the content data does not match with a respective sub-portion of the portion of the search data. | 11-26-2009 |
20090290400 | BIT CELL DESIGNS FOR TERNARY CONTENT ADDRESSABLE MEMORY - A scheme for bit cell designs for ternary content addressable memory for comparing search data with content data is disclosed. In one embodiment, a system for comparing search data with content data stored in a ternary content addressable memory (TCAM) unit, includes a first static logic gate for comparing a first content data with a first search data, and a second static logic gate coupled to the first static logic gate for comparing a second content data with a second search data. The content data comprises the first content data and the second content data and the search data comprises the first search data and the second search data. The first static logic gate forwards a signal for disabling the second static logic gate if the first content data does not match with the first search data. | 11-26-2009 |
20090303767 | SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS - An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data. | 12-10-2009 |
20090310395 | Content-Addressable Memory - A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, and compares the second data bit with a second search bit to determine if they are matched. The first CAM cell comprises a first logic circuit, the second CAM cell comprises a second logic circuit, and the first logic circuit and the second logic circuit form a static CMOS logic circuit. | 12-17-2009 |
20090323383 | COMPARING DATA REPRESENTATIONS TO STORED PATTERNS - A search engine includes a storage module to store a plurality of data patterns, a plurality of busses to receive a plurality of representations of a search word, a selector corresponding to at least one of the plurality of data patterns to select one of the plurality of representations of the search word for comparing to the at least one of the plurality of data patterns, and a logic circuit operatively coupled to the storage module, to the plurality of busses, and to the selector to compare the selected one of the plurality of representations of the search word to the at least one of the plurality of data patterns. | 12-31-2009 |
20090323384 | HIGH DENSITY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - A content addressable memory array storing stored words in memory elements. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is the use of a biasing circuit to bias the access devices during a search operation. During the search operation, a search word containing a bit string is received. Each access device is biased to a complementary resistance value of a corresponding search bit in the search word. A match between the search word and stored word is indicated if the bits stored in the memory elements are complementary to the bits represented by the resistances in the access devices. | 12-31-2009 |
20100002481 | CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device. | 01-07-2010 |
20100002482 | MEMORY DEVICE AND METHOD - A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor. | 01-07-2010 |
20100002483 | Range checking content addressable memory array - A disclosed embodiment is a range checking CAM array comprising a plurality of words, where each of the plurality of words comprises a plurality of bound check cells. Each of the plurality of bound check cells outputs a corresponding plurality of match signals and a corresponding plurality of bound check signals. The corresponding plurality of match signals and corresponding plurality of bound check signals are combined to produce a range check output indicating whether data on a data input bus is within a target range. The plurality of bound check cells may be coupled to form at least one cascade of bound check cells, where each cascade of bound check cells may be terminated at a ripple logic. The CAM array produces a final range check output based on the corresponding plurality of match signals and the corresponding plurality of bound check signals. | 01-07-2010 |
20100002484 | Content addressable memory array with an invalidate feature - A disclosed embodiment is a CAM (content addressable memory) array with an invalidate feature, the CAM array includes a plurality of words, where each of the plurality of words includes a respective invalidate circuit. Each respective invalidate circuit is configured to invalidate stored data in each corresponding plurality of words if compare data on a data input bus uniquely identifies, i.e. matches, the stored data. Each of the plurality of words is coupled to the data input bus. In one embodiment, each invalidate circuit includes a memory cell which stores a valid bit to configure the invalidate circuit to invalidate the stored data in a respective word. Each of the plurality of words further includes a respective plurality of CAM cells, which store the stored data. Each CAM cell outputs a match signal that is coupled to a latch. The match signals are also coupled to corresponding invalidate circuits. | 01-07-2010 |
20100046265 | Separate CAM Core Power Supply For Power Saving - A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic & control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage. | 02-25-2010 |
20100054011 | High speed SRAM - High speed SRAM is realized such that a first dynamic circuit serves as a local sense amp for reading a memory cell through a lightly loaded local bit line, a second dynamic circuit serves as a segment sense amp for reading the local sense amp, and a tri-state inverter serves as an inverting amplifier of a global sense amp for reading the segment sense amp. When reading, a voltage difference in the local bit line is converted to a time difference for differentiating low data and high data by the sense amps for realizing fast access with dynamic operation. Furthermore, a buffered data path is used for achieving fast access and amplify transistor of the sense amps is composed of relatively long channel transistor for reducing turn-off current. Additionally, alternative circuits and memory cell structures for implementing the SRAM are described. | 03-04-2010 |
20100054012 | CONTENT ADDRESABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE - A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous. | 03-04-2010 |
20100054013 | CONTENT ADDRESABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTER CIRCUITS - A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row. | 03-04-2010 |
20100067277 | Content-Addressable Memory - A CAM includes first and second memory units. The first memory unit includes: a first data memory cell for storing a first data bit; a first comparison circuit for comparing a first search bit with the first data bit to determine if there is a match, and outputting a first comparison result; and a first CMOS logic circuit for performing a logic operation on the first comparison result and outputting a first matching result. The second memory unit includes: a second data memory cell for storing a second data bit; a second comparison circuit for comparing a second search bit with the second data bit to determine if there is a match, and outputting a second comparison result; and a second static CMOS logic circuit for performing a logic operation on the first matching result and the second comparison result, and outputting an output matching result. | 03-18-2010 |
20100103712 | MEMORY TEST DEVICE AND METHODS THEREOF - In accordance with a specific embodiment of the present disclosure, a content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches one of a plurality of values stored at memory locations of the CAM. In a test mode of operation, a plurality of test signals are applied to the CAM, and the CAM provides a match value in response to assertion of one of the test signals. The match value is applied to a functional module associated with the CAM to determine a test result. Accordingly, the test signals applied to the CAM provide a flexible way to generate match values and apply those values to the functional module during testing of the data processing device. | 04-29-2010 |
20100142242 | READ AND MATCH CIRCUIT FOR LOW-VOLTAGE CONTENT ADDRESSABLE MEMORY - The present invention discloses a read and match circuit for a low-voltage content addressable memory, wherein the write circuit inputs the signals needing storing into the memory cells, and the read circuit retrieves the stored signals from the memory cells, and the match circuit compares the data stored in the memory cell with the data searched by the match circuit. As the circuits for writing, reading and matching are separated from each other and exempt from mutual interference, the present invention can achieve high reliability and low power consumption under a low-voltage operation environment without using a special fabrication process. In the present invention, the circuit is optimized to meet different requirements. The present invention enables the user to determine whether to have high speed or to have low power consumption. Further, the present invention can overcome the problems of current leakage and noise allowance in a low-voltage environment. | 06-10-2010 |
20100165691 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. | 07-01-2010 |
20100182816 | Power Saving Static-Based Comparator Circuits and Methods and Content-Addressable Memory (CAM) Circuits Employing Same - Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data. | 07-22-2010 |
20100202178 | OFFSET REMOVAL CIRCUIT, ASSOCIATIVE MEMORY INCLUDING THE SAME, AND OFFSET VOLTAGE REMOVAL METHOD - An offset removal circuit ( | 08-12-2010 |
20100214811 | CODING TECHNIQUES FOR IMPROVING THE SENSE MARGIN IN CONTENT ADDRESSABLE MEMORIES - A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word. | 08-26-2010 |
20100226161 | TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care. | 09-09-2010 |
20100232194 | Content Addressable Memory Having Bidirectional Lines That Support Passing Read/Write Data And Search Data - A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair. | 09-16-2010 |
20100232195 | Content Addressable Memory (CAM) Array Capable Of Implementing Read Or Write Operations During Search Operations - A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result. | 09-16-2010 |
20100265748 | HIGH DENSITY TERNARY CONTENT ADDRESSABLE MEMORY - A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device is the use of a single memory element and an access device in the memory cells. The memory cells are arranged such that each memory cell is electrically coupled to a single bit line, a single match line, and a single word line. The memory elements in the memory cells store low resistance states if the data bit value is the first binary value, high resistance states if the data bit value is the second binary value, and very high resistance states if the data bit value is the don't care value. | 10-21-2010 |
20100271854 | Ternary Content Addressable Memory Having Reduced Leakage Effects - A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced. | 10-28-2010 |
20100321970 | CONTENT ADDRESSABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE - A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous. | 12-23-2010 |
20100321971 | CONTENT ADDRESSABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTER CIRCUITS - A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row. | 12-23-2010 |
20100328981 | CONTENT ADDRESSABLE MEMORY DEVICE FOR SIMULTANEOUSLY SEARCHING MULTIPLE FLOWS - A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of a selected flow over the match results of the other flows in response to a flow select signal, which can be toggled to alternately select the match results of various flows. In this manner, the match results of the selected flow are generated and output even if the HPM index of the selected flow is of a lower priority than those of the non-selected flows, thereby ensuring an even distribution of match results reporting between different flows. | 12-30-2010 |
20100328982 | CONTENT ADDRESSABLE MEMORY DESIGN - A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries. | 12-30-2010 |
20110026288 | CONTENT ADDRESSABLE MEMORY - The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers. | 02-03-2011 |
20110051485 | CONTENT ADDRESSABLE MEMORY ARRAY WRITING - A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array. | 03-03-2011 |
20110051486 | CONTENT ADDRESSABLE MEMORY REFERENCE CLOCK - A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic. | 03-03-2011 |
20110085364 | SEMICONDUCTOR SIGNAL PROCESSING APPARATUS - A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths. | 04-14-2011 |
20110103120 | BINRAY CONTENT ADDRESSABLE MEMORY - The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration and improving power consumption. According to the present invention, since the binary content addressable memory according to the present invention has a smaller number of transistors than those of the conventional binary content addressable memory, a memory can be fabricated in a smaller size, thereby improving the degree of integration as one of most important factors in the memory design. In addition, improvement of the degree of integration contributes to miniaturization and lightweightness of the product in its design. Further, the inventive binary content addressable memory performs its own function using a smaller number of transistors, thereby reducing power consumption. | 05-05-2011 |
20110134677 | CONTENT ADDRESSABLE MEMORY - The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry. | 06-09-2011 |
20110170327 | DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY - The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention. | 07-14-2011 |
20110194325 | ERROR DETECTION IN A CONTENT ADDRESSABLE MEMORY (CAM) - A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit. | 08-11-2011 |
20110216569 | CONTENT ADDRESSABLE MEMORY DEVICE - A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A. | 09-08-2011 |
20110228580 | Methods and Apparatus for Sum of Address Compare Write Recode and Compare Reduction - Techniques are described for sum address compare (A+B=K) operation for use in translation lookaside buffers and content addressable memory devices, for example. Address input signals A and B are supplied as input to the A+B=K operation and K is a previous value stored in a plurality of memory cells. In each memory cell, a single logic gate circuit output and its inversion are generated in response to updating the memory cells, wherein each single logic gate circuit has as input an associated memory cell output and a next lowest significant bit adjacent memory cell output. In each of the memory cells, a portion of the A+B=K operation associated with each memory cell is generated in a partial lookup compare circuit wherein the corresponding address input signals A and B are combined with the associated memory cell output and the generated single logic gate circuit output and its inversion during a read lookup compare operation. | 09-22-2011 |
20110255322 | Encoding Data for Storage in a Content Addressable Memory - An encoding scheme is disclosed that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in each CAM cell, data may be stored more efficiently and CAM systems may consume less power. The encoded data words can be balanced data words that have equal number of logic high and logic low values. | 10-20-2011 |
20110310648 | SEMICONDUCTOR STORAGE DEVICE - To provide a semiconductor storage device capable of performing a search of the next data while performing a search of certain data. | 12-22-2011 |
20110317462 | System for Dynamically Managing Power Consumption in a Search Engine - The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool. | 12-29-2011 |
20120063189 | LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES AND RELATED METHODS - Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein. | 03-15-2012 |
20120113703 | SYSTEM FOR DYNAMICALLY MANAGING POWER CONSUMPTION IN A SEARCH ENGINE - The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool. | 05-10-2012 |
20120120702 | POWER SAVING TECHNIQUE IN A CONTENT ADDRESSABLE MEMORY DURING COMPARE OPERATIONS - An apparatus comprising a first circuit, a driver circuit and a memory circuit. The first circuit may be configured to generate a supply voltage that changes between (i) a first voltage when an input signal is in a first state and (ii) a second voltage when the input signal is in a second state. The driver circuit may be configured to generate a wordline signal in response to (i) the supply voltage, (ii) a clock signal and (iii) a select signal. The memory circuit may be configured to perform a read/write operation in a response to the wordline signal. | 05-17-2012 |
20120127772 | LOW POWER SRAM BASED CONTENT ADDRESSABLE MEMORY - An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality of the columns. The plurality of processing circuits may each be configured to compare (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of the plurality of columns to determine a match. The compare may occur on a first clock cycle of an input clock signal. Each of the plurality of processing circuits may be configured to power down a respective column of the memory array if the test bit of the input data word does not match the test bit of said column. | 05-24-2012 |
20120140541 | MEMORY BUILT-IN SELF TEST SCHEME FOR CONTENT ADDRESSABLE MEMORY ARRAY - A method and apparatus for testing a content addressable memory (CAM) array includes writing known data to the CAM array and providing comparison data to the CAM array. A determination is made whether the CAM array is operating correctly responsive to a comparison of the known data and the comparison data. | 06-07-2012 |
20120147643 | System for reducing power consumption and increasing speed of content-addressable memory - According to one disclosed embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements. | 06-14-2012 |
20120170344 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 07-05-2012 |
20120188811 | ASSOCIATIVE MEMORY - An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data. | 07-26-2012 |
20120206951 | HIGH DENSITY CAM ARRAY ARCHITECTURES WITH ADAPTIVE CURRENT CONTROLLED MATCH-LINE DISCHARGE - An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line. | 08-16-2012 |
20120236618 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value. | 09-20-2012 |
20120243284 | USING STORAGE CELLS TO PERFORM COMPUTATION - A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern. | 09-27-2012 |
20120262972 | CONTENT ADDRESSABLE MEMORY - The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers. | 10-18-2012 |
20120287693 | SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SEMICONDUCTOR DEVICE - To provide a semiconductor device whose power can be turned off without the need for a peripheral circuit for data to escape temporarily and in which stored data is not lost even in an off state of the power of the device, and a memory device including the semiconductor device. In a holding circuit of the semiconductor device, a transistor that includes a semiconductor layer (at least a channel formation region) including an oxide semiconductor material with which small off-state current can be achieved is used. Further, the semiconductor device includes a switching element which enables a comparison circuit in which comparison between data stored in the holding circuit and reference data input from the outside does not need to be performed to become forcibly inactive. | 11-15-2012 |
20120327696 | CONTENT ADDRESSABLE MEMORY ARRAY HAVING VIRTUAL GROUND NODES - Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced. | 12-27-2012 |
20130010513 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 01-10-2013 |
20130039109 | SELECTABLE MULTI-WAY COMPARATOR - A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value. | 02-14-2013 |
20130058145 | MEMORY SYSTEM - A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells. | 03-07-2013 |
20130083581 | NEAREST NEIGHBOR SERIAL CONTENT ADDRESSABLE MEMORY - A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs. | 04-04-2013 |
20130114322 | ASSOCIATIVE MEMORY - An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT | 05-09-2013 |
20130121053 | METHODS AND CIRCUITS FOR LIMITING BIT LINE LEAKAGE CURRENT IN A CONTENT ADDRESSABLE MEMORY (CAM) DEVICE - A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit car have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state prior to, and for a duration of at least of a portion of an access operation. | 05-16-2013 |
20130170273 | Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers - A CAM circuit includes a plurality of core memory cells, each cell including comparison logic for generating a local match signal based on a comparison between stored data in the cell and a compare value. The CAM circuit includes a plurality of local match lines, each local match line coupled with a corresponding cell and adapted to convey the local match signal generated by the cell. The CAM circuit includes combination logic for receiving respective local match signals generated by a subset of the cells and for generating an output word match signal having a value indicative of the local match signals. The subset of cells is arranged with at least one block having a word size that is limited based on available space for routing tracks used to convey the local match signals and at least one word match signal in a base metal layer across the cells. | 07-04-2013 |
20130182482 | CONTENT ADDRESSABLE MEMORY DEVICE - A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance. | 07-18-2013 |
20130242632 | CONTENT ADDRESSABLE MEMORY SYSTEM - There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. | 09-19-2013 |
20130250642 | Low Power Content-Addressable Memory - According to one disclosed embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements. | 09-26-2013 |
20130258739 | CONTENT ADDRESSABLE MEMORY CHIP - A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a CAM cell array, according to the voltage of a match line. The match amplifier zone comprises one or more NMOS transistors and one or more PMOS transistors. The match amplifier zone has a dead zone to an input of a voltage of the match line, and has a property that no flow-through current is present in the match amplifier zone. | 10-03-2013 |
20130279231 | Power Limiting in a Content Search System - A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic. | 10-24-2013 |
20130286705 | LOW POWER CONTENT ADDRESSABLE MEMORY HITLINE PRECHARGE AND SENSING CIRCUIT - An apparatus and a method of operating the apparatus. The apparatus includes a driver circuit and a memory circuit. The driver circuit may be configured to precharge a hitline in response to a predetermined voltage level and a control signal and sense a result of a compare operation based upon a hitline signal on the hitline. The driver circuit generally precharges the hitline to a voltage level lower than the predetermined voltage level and senses the result of the compare operation using the full predetermined voltage level. The memory circuit may be configured to perform the compare operation using the hitline. | 10-31-2013 |
20130322146 | NONVOLATILE MEMORY APPARATUS - A nonvolatile memory apparatus includes a memory cell area including memory cells for storing data input from an external apparatus, a redundancy cell area including memory cells configured to substitute failed memory cells, and a flag cell area including memory cells for storing whether most significant bits of the memory cells have been programmed. The flag cell area is configured in a part of the redundancy cell area. | 12-05-2013 |
20140003112 | System and Method for Storing Integer Ranges in a Memory | 01-02-2014 |
20140063886 | TECHNIQUES FOR SUPPRESSING MATCH INDICATIONS AT A CONTENT ADDRESSABLE MEMORY - A content addressable memory (CAM) suppresses an indication of a match in response to determining that the entry that stores data matching received compare data is the subject of a write operation. To suppress the indication, an address decoder decodes a write address associated with the write operation to determine the entry of the CAM that is the subject of the write operation, and provides control signaling indicative of the determined entry. The CAM uses the control signaling to suppress any match indications for the entry being written, thereby preventing erroneous match indications. | 03-06-2014 |
20140071726 | OTP Memories Functioning as an MTP Memory - Techniques, systems and circuitry for using One-Time Programmable (OTP) memories to function as a Multiple-Time Programmable (MTP) memory. The OTP-for-MTP memory can include at least one OTP data memory to store data, and at least one OTP CAM to store addresses and to search input address through valid entries of the OTP CAM to find a latest entry of the matched valid addresses. The OTP-for-MTP memory can also include a valid-bit memory to find a next available entry of the OTP data memory and OTP CAM. When programming the OTP-for-MTP memory, address and data can be both programmed into the next available entry of the OTP CAM and the OTP data memory, respectively. When reading the OTP-for-MTP memory, the input address can be used to compare with valid entries of the addresses stored in the OTP CAM so that the latest entry of the matched valid addresses can be output. | 03-13-2014 |
20140071727 | Reduced Power Consumption Content-Addressable Memory - According to one disclosed embodiment, a content-addressable memory (CAM) system configured for reduced power consumption includes a sensing circuit utilized to apply a sense voltage to a matchline of the CAM system, a valid bit cell coupled to the matchline, and a power cut-off circuit configured to isolate the sense voltage from the matchline when an invalid validity state is stored in the valid bit cell, thereby reducing power consumption by the CAM system. In one embodiment, the power cut-off circuit isolates the sense voltage from the matchline by decoupling the sensing circuit from a control signal when an invalid validity state is stored in the valid bit cell. | 03-13-2014 |
20140085957 | Shared Stack dual Phase Content Addressable Memory (CAM) Cell - A shared stack dual-phase CAM cell is provided. The CAM cell includes at least first and second stacks that share a single pair of pull-down transistors. At least one pair of pull-down transistors can thus be eliminated, reducing the area and power consumption of the CAM cell. Sharing of the single pair of pull-down transistors is enabled by time-staggered pre-charge and compare operations such that the pre-charge interval of the first stack corresponds to the compare interval of the second stack, and vice versa. | 03-27-2014 |
20140085958 | Pre-Computation Based Ternary Content Addressable Memory - A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to not match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM. | 03-27-2014 |
20140104914 | CONTENT ADDRESSABLE MEMORY AND RELATED COLUMN REPAIR METHOD - A content addressable memory (CAM) has a CAM array, a path selection circuit and a control circuit. The CAM array has a plurality of main columns of CAM cells and at least one redundant column of CAM cells. The path selection circuit receives an input search data, and outputs a plurality of bits of the input search data to a plurality of selected columns in the CAM array, respectively. The control circuit controls the path selection circuit to couple to the selected columns, and sets each CAM cell of at least one faulty column found in the main columns at a match state. The at least one faulty column is not included in the selected columns, and the at least one redundant column is included in the selected columns. | 04-17-2014 |
20140112045 | MEMORY SYSTEM INCORPORATING A CIRCUIT TO GENERATE A DELAY SIGNAL AND AN ASSOCIATED METHOD OF OPERATING A MEMORY SYSTEM - Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells. | 04-24-2014 |
20140126264 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 05-08-2014 |
20140160825 | SEARCH SYSTEM SEARCHING FOR DATA WORD MATCHING SEARCH KEY - A search system is obtained by combining a TCAM and a search engine not using the TCAM. The search engine not using the TCAM is constructed using a general-purpose memory cell structure, and includes a different-sized memory spaces each corresponding to an effective bit length of search target data. | 06-12-2014 |
20140177310 | PSEUDO-NOR CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY - A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match. | 06-26-2014 |
20140185348 | HYBRID TERNARY CONTENT ADDRESSABLE MEMORY - A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage. | 07-03-2014 |
20140185349 | STATIC NAND CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) - A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor. | 07-03-2014 |
20140192580 | LOW POWER CONTENT ADDRESSABLE MEMORY SYSTEM - A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare circuit to compare a reference input to the stored bit and to the stored complementary bit. The compare circuit may be implemented to compare a single-ended reference input to each of the stored bit and the complementary bit. The compare circuit may include a pass circuit to selectively provide the reference input to an output under control of the stored bit and the stored complementary bit, a pull-up circuit to selectively pull-up the output under control of the reference input and the stored complementary bit, and a pull-down circuit to selectively pull-down the output under control of the reference input and the stored bit. The reference input may be provided to multiple CAM cells, which may share compare circuitry. | 07-10-2014 |
20140204644 | LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES AND RELATED METHODS - Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein. | 07-24-2014 |
20140218994 | Power Savings in a Content Addressable Memory Device Using Masked Pre-Compare Operations - A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array. | 08-07-2014 |
20140268971 | TCAM WITH EFFICIENT RANGE SEARCH CAPABILITY - An embodiment of the invention includes a ternary content addressable memory (TCAM) that has input search data bits, TCAM words and range search input data bits. Each TCAM word is operable to store a match pattern and provide a match output. The match output indicates a match when the match pattern of the TCAM word matches the TCAM input search data bits. The range search input data bits are separated into groups. Each group has a bit width N where N is the number of range search input data bits. For the match pattern in each group, there is a Boolean function that uses the N range of search input data bits. (2 | 09-18-2014 |
20140268972 | TCAM WITH EFFICIENT MULTIPLE DIMENSION RANGE SEARCH CAPABILITY - An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the TCAMs includes a plurality of words, stores TCAM match entries and outputs a TCAM match signal for each word in the plurality of words. The first vector includes first TCAM group enable register bits. An enabling value on the first TCAM register bit indicates that the first TCAM match signal and the neighboring first TCAM match are in the same TCAM group. The TCAM match-merge unit receives the first TCAM match signal from each of the words and the first vector and outputs a first TCAM group match signal for each of the words. The TCAM match-merge unit outputs a match indication when any of the TCAM match signals indicate a match and outputs a mismatch when none of the TCAM match signals match. | 09-18-2014 |
20140286072 | IDENTIFYING A RESULT USING MULTIPLE CONTENT-ADDRESSABLE MEMORY LOOKUP OPERATIONS - In one embodiment, a first search operation is performed based on a base lookup word on a first plurality of content-addressable memory entries of an overall plurality of priority-ordered content-addressable memory entries to identify a first matching entry and a corresponding first overall search position of the first matching entry within the overall plurality of priority-ordered content-addressable memory entries. A second search operation is performed based on the base lookup word on a second plurality of content-addressable memory entries of the overall plurality of priority-ordered content-addressable memory entries to identify a second matching entry and a corresponding second overall search position of the second matching entry within the overall plurality of priority-ordered content-addressable memory entries. The corresponding first overall search position is compared to the corresponding second overall search position to determine the overall search result. | 09-25-2014 |
20140313808 | CONTENT ADDRESSABLE MEMORY CHIP - A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a CAM cell array, according to the voltage of a match line. The match amplifier zone comprises one or more NMOS transistors and one or more PMOS transistors. The match amplifier zone has a dead zone to an input of a voltage of the match line, and has a property that no flow-through current is present in the match amplifier zone. | 10-23-2014 |
20140347906 | TCAM MEMORY CELL AND COMPONENT INCORPORATING A MATRIX OF SUCH CELLS - A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data item) and a second storage cell (storing a potential representing the second reference binary data item). A comparison circuit is connected to the first and second storage circuits and to the input terminal SL. A comparison node presents a potential representing the comparison of the input binary data item with the first and second reference data items. The comparison node is connected to an output stage, and the output stage is connected to the match line. The signal on the match line is based on the potential of the comparison node. | 11-27-2014 |
20140347907 | ELECTRONIC COMPONENT INCLUDING A MATRIX OF TCAM CELLS - Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied. | 11-27-2014 |
20140369103 | CONTENT ADDRESSABLE MEMORY CELLS AND TERNARY CONTENT ADDRESSABLE MEMORY CELLS - An embodiment of the invention provides a binary CAM cell. The binary CAM cell includes a storage circuit, a first discharging circuit, and a second discharging circuit. The storage circuit is configured to provide a first stored bit and a second stored bit, which are complimentary bits of each other. The first discharging circuit is configured to either discharge or not discharge a match line according to the first stored bit provided by the storage circuit and a first searched bit provided by a first search line. The first discharging circuit includes a first PMOS transistor. The second discharging circuit is configured to either discharge or not discharge the match line according to the second stored bit provided by the storage circuit and a second searched bit provided by a second search line. The second discharging circuit includes a second PMOS transistor. | 12-18-2014 |
20150055389 | SELF-TIMED, SINGLE-ENDED SENSE AMPLIFIER - An integrated circuit including a sense amplifier connected to a sense line is provided. The sense amplifier is configured to end a precharge phase of the sense line based on a state of the sense amplifier. | 02-26-2015 |
20150055390 | CONTENT ADDRESSABLE MEMORY - The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers. | 02-26-2015 |
20150070957 | SEMICONDUCTOR DEVICE AND METHOD OF WRITING/READING ENTRY ADDRESS INTO/FROM SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address. | 03-12-2015 |
20150109842 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device | 04-23-2015 |
20150131355 | ASSOCIATIVE MEMORY CIRCUIT - An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage. | 05-14-2015 |
20150138861 | CONTENT ADDRESSABLE MEMORY - This disclosure provides a content addressable memory which includes: a data memory cell for storing a data bit; a mask memory cell for storing a mask bit; and a comparing and readout unit connected to at least one read word line for receiving at least one read word signal, connected to at least one function bit line for receiving a search bit signal, and connected to the data memory cell and the mask memory cell for receiving the data bit and the mask bit; wherein the data memory cell is connected to a data-use write word line for receiving a data-use write word signal, the mask memory cell is connected to a mask-use write word line for receiving a mask-use write word signal, so as to decide whether a write bit signal can be written into the data bit and the mask bit through a pair of write bit lines. | 05-21-2015 |
20150332767 | HIGH DENSITY SEARCH ENGINE - A content addressable memory (CAM) search engine is disclosed. The CAM search engine includes a data compare plane having a content addressable memory die including an array of comparison cells. The CAM search engine further includes a memory stack on the data compare plane. The memory stack has stacked memory dies including memory banks. The array of comparison cells includes parallel interconnects. The parallel interconnects electrically connect to outputs of the memory banks. The comparison cells are time-shared among the one or more memory banks | 11-19-2015 |
20150348628 | SEMICONDUCTOR INTEGRATED CIRCUIT - A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor. | 12-03-2015 |
20150348629 | Non-Volatile Ternary Content-Addressable Memory with Resistive Memory Device - A scheme for non-volatile ternary content-addressable memory with resistive memory device is proposed. The non-volatile ternary content-addressable memory comprises five transistors including a pair of search transistors with a first search transistor and a second search transistor, a read transistor, a write transistor and a match line transistor, wherein a match line is coupled to the match line transistor; and a pair of variable resistances have a first variable resistance and a second variable resistance. The pair of search transistors is coupled to the pair of variable resistances. | 12-03-2015 |
20160049198 | CONTENT ADDRESSABLE MEMORY CELL AND ARRAY - A content addressable memory (CAM) cell system is provided. The CAM cell system includes a first memory cell, a first logic circuitry and a first compare circuitry. The first logic circuit includes a first n-FET, a first p-FET, and a first input terminal. A gate of the first n-FET and a gate of the first p-FET are galvanically coupled to the first input terminal. The first compare circuitry is communicatively coupled to the first memory cell via a first coupling, and to the first input terminal via a second coupling. The first compare circuitry is configured to receive first data stored in the first memory cell via the first coupling, receive first match data, transmit a first binary logical value to the first input terminal via the second coupling in response to the first data not matching the first match data, and transmit a second binary logical value to the first input terminal via the second coupling in response to the first data matching the first match data. | 02-18-2016 |
20160099029 | TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES - A memory device with word-line voltage boosting includes a set of first switches that are operable to couple a word-line of the memory device to a supply voltage to pull the word-line up to a rail voltage. A dummy line including a conductive route can be disposed in a vicinity of the word-line to form a parasitic coupling capacitance with the word-line. A second switch is operable to couple the dummy line to the supply voltage to pull the dummy line to the rail voltage. Pulling up the dummy line boosts the word-line voltage above the rail voltage by a boost voltage. | 04-07-2016 |
20160099053 | CONTENT ADDRESSABLE MEMORY ARRAY - A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells. | 04-07-2016 |
20160099054 | ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIONS WITH CONTENT ADDRESSABLE MEMORY (CAM) CIRCUITS - An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines. | 04-07-2016 |
20160104532 | CONTENT ADDRESSABLE MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME - A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F | 04-14-2016 |
20160148688 | Sense Amplifier having a Timing Circuit for a Presearch and a Main Search - A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing the presearch line. The main search block is coupled to a main line for sensing the main line. The timing circuit operates the presearch block and the main search block for charging and sensing of the presearch line and the main line. The timing circuit initiates the main search block to determine a match condition for the main line based on whether a match condition is determined for the presearch line. | 05-26-2016 |
20160148689 | Sense Amplifier for Single-ended Sensing - A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks coupled between the near end of the single ended line and the far end of the single ended line, a single ended line comparator coupled to the near end of the single ended line configured to compare a voltage at the near end of the single ended line to provide a logic state output, and a charge transistor coupled to the single ended line at a point that is between the near end of the single ended line and the far end of the single ended line to shift occurrence of snap back from strong charging of the single ended line. | 05-26-2016 |
20160163385 | DUO CONTENT ADDRESSABLE MEMORY (CAM) USING A SINGLE CAM - Disclosed is a content addressable memory (CAM). The content addressable memory array includes a memory array and a data match module. The memory array includes multiple memory rows. Each memory row is configured to store a first data word and a second data word. The data match module includes a first match circuitry configured to compare a first match word to the first data word of a memory row, and to generate a first match output based on the comparison between the first match word and the first data word of the memory row. The data match module further includes a second match circuitry configured to compare a second match word to the second data word of the memory row, and to generate a second match output based on the comparison between the second match word and the second data word of the memory row. | 06-09-2016 |
20160203868 | CONFIGURABLE NON-VOLATILE CONTENT ADDRESSABLE MEMORY | 07-14-2016 |
20170236585 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED POWER CONSUMPTION | 08-17-2017 |
20190147952 | TERNARY CONTENT ADDRESSABLE MEMORY | 05-16-2019 |