Entries |
Document | Title | Date |
20080205164 | Decoding control with address transition detection in page erase function - Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks. | 08-28-2008 |
20080205165 | Semiconductor Memory Device - Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in. | 08-28-2008 |
20080205166 | TRAPPING STORAGE FLASH MEMORY CELL STRUCTURE WITH INVERSION SOURCE AND DRAIN REGIONS - Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers. | 08-28-2008 |
20080212376 | METHODS OF OPERATING AND MANUFACTURING LOGIC DEVICE AND SEMICONDUCTOR DEVICE INCLUDING COMPLEMENTARY NONVOLATILE MEMORY DEVICE, AND READING CIRCUIT FOR THE SAME - Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous. | 09-04-2008 |
20080219059 | Method for Cache Page Copy in a Non-Volatile Memory - A non-volatile memory and methods include cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out of the memory group-by-group according to a predetermined order for data-processing. Modified data are returned for updating the respective data group. The predetermined order is such that as more of the data groups are processed and available for programming, more of the higher programmed states are decodable. An adaptive full-sequence programming is performed concurrently with the processing. The programming copies the read data to another group of memory cells associated with a second word line, typically in a different erase block and preferably compensated for perturbative effects due to a word line adjacent the first word line. | 09-11-2008 |
20080225601 | EEPROM MEMORY DEVICE WITH CELL HAVING NMOS IN A P POCKET AS A CONTROL GATE, PMOS PROGRAM/ERASE TRANSISTOR, AND PMOS ACCESS TRANSISTOR IN A COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 09-18-2008 |
20080225602 | DATA PROCESSING SYSTEM AND NONVOLATILE MEMORY - Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough. | 09-18-2008 |
20080239828 | FLASH MEMORY DEVICE AND ERASE METHOD THEREOF - An erase operating time can be shortened and an erase operating characteristic can be improved in a flash memory device. The flash memory device includes a plurality of memory cell blocks, an operating voltage generator and a controller. Each of the plurality of memory cell blocks includes memory cells connected to a plurality of word lines. A voltage generator is configured to apply an erase voltage to a memory cell block selected for an erase operation, and change a level of the erase voltage if an attempt of the erase operation is not successful. A controller is configured to control the voltage generator to apply a first erase voltage to a memory cell block selected for an erase operation. The first erase voltage corresponds to a previous erase voltage that was used successfully in completing a previous erase operation. The first erase voltage is an erase voltage that is used in a first erase attempt for the erase operation. | 10-02-2008 |
20080239829 | MEMORY APPARATUS INCLUDING PROGRAMMABLE NON-VOLATILE MULTI-BIT MEMORY CELL, AND APPARATUS AND METHOD FOR DEMARCATING MEMORY STATES OF THE CELL - Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout. | 10-02-2008 |
20080239830 | Methods of Operating Memory Devices Including Discharge of Source/Drain Regions and Related Electronic Devices - A memory device may include a memory cell array having a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. The string selection transistor may be coupled between the string and a bit line, and the ground selection transistor may be coupled between the string and a common source line. In addition, each memory cell transistor may includes a floating gate between a control gate electrode and a semiconductor substrate, and source/drain regions of the semiconductor substrate may be included on opposite sides of the control gate electrode. Responsive to an erase command, the memory cell transistors of the string may be erased. Further responsive to the erase command and after erasing the memory cell transistors of the string, electrical charge from the source/drain regions of the memory cell transistors may be discharged through the ground selection transistor to the common source line and/or through the string selection transistor to the bit line. Related devices are also discussed. | 10-02-2008 |
20080266982 | CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES - A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise. | 10-30-2008 |
20080273400 | FAST ERASABLE NON-VOLATILE MEMORY - A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories. | 11-06-2008 |
20080279014 | MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY - Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines. | 11-13-2008 |
20080298136 | ENHANCED ERASING OPERATION FOR NON-VOLATILE MEMORY - Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage. | 12-04-2008 |
20080304328 | Nonvolatile memory devices and methods of operating the same - Example embodiments include nonvolatile memory devices that have good operation performance and may be made in a highly integrated structure, and methods of operating the same. Example embodiments of the nonvolatile memory devices include a substrate electrode, and a semiconductor channel layer on the substrate electrode, a floating gate electrode on the substrate electrode, wherein a portion of the floating gate electrode faces the semiconductor channel layer, a control gate electrode on the floating gate electrode, and wherein a distance between a portion of the floating gate electrode and the substrate electrode is smaller than a distance between the semiconductor channel layer and the substrate electrode wherein charge tunneling occurs. | 12-11-2008 |
20080310237 | CMOS Compatible Single-Poly Non-Volatile Memory - The present invention teaches a single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. The single-poly non-volatile memory cell in accordance with the present invention comprises a program transistor with a program terminal; a sensing transistor with a sensing terminal; and an erase transistor with an erase terminal, wherein the sensing transistor shares a floating gate with the program transistor and the erase transistor. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided. | 12-18-2008 |
20080310238 | Methods of Programming Data in a Non-Volatile Memory Device and Methods of Operating a Nand Flash Memory Device Using the Same - Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate. | 12-18-2008 |
20090003084 | Driving Method of Flash Memory Device - In a driving method of a flash memory device including a selected first bit line and an unselected second bit line, a program voltage of a pulse is applied to word lines of all memory cells in a block passing an erase verify operation. After the first and second bit lines are precharged to a predetermined level, a ground voltage is applied to the word lines of all the memory cells in the block. The memory cells are evaluated for a predetermined time shorter than an evaluation time of a read operation. Whether or not a memory cell passing a verify operation exists among the memory cells is sensed. Resultantly, when the memory cell passing the verify operation exists, the memory cells in the block are programmed to a desired level using a predetermined program voltage and a step voltage. | 01-01-2009 |
20090003085 | NONVOLATILE MEMORY SYSTEM, SEMICONDUCTOR MEMORY, AND WRITING METHOD - A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation. | 01-01-2009 |
20090021988 | Nonvolatile memory device and method of operating fabricating the same - Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line. | 01-22-2009 |
20090052259 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device is provided. A gate electrode configuring a memory cell is turned into floating state and a potential of a gate electrode adjacent thereto is changed, and reduce the potential of the gate electrode by this change of potential and the capacitive coupling. Furthermore, charge sharing is carried out by connecting two gate electrodes, and the voltage of the gate electrode is reduced by capacitive coupling with another gate electrode adjacent thereto, to largely reduce the potential of the gate electrode. Thereby, the voltage level generated by the charge pump circuit can be reduced. As a result, the size of the charge pump circuit can be reduced, or the circuit itself can be eliminated, resulting in reduction of the chip area. | 02-26-2009 |
20090059678 | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device - In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well. | 03-05-2009 |
20090059679 | ERASING METHOD OF NON-VOLATILE MEMORY - An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a first dielectric layer disposed on the floating gate, a second dielectric layer disposed on sidewalls of the floating gate, and an erase gate. The erasing method includes applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased. | 03-05-2009 |
20090073776 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device is provided in which stable transistor characteristics with little variation can be obtained, and sufficient threshold voltage and ON current fluctuations can be obtained. A source | 03-19-2009 |
20090103371 | MEMORY CELL OPERATION - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses. | 04-23-2009 |
20090116296 | FLASH MEMORY DEVICE APPLYING ERASE VOLTAGE - A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation. | 05-07-2009 |
20090122618 | Method for Programming and Erasing an Array of NMOS EEPROM Cells that Minimizes Bit Disturbances and Voltage Withstand Requirements for the Memory Array and Supporting Circuits - A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation. | 05-14-2009 |
20090129171 | Nonvolatile semiconductor memory and method of driving the same - It is an object of the present invention to provide a nonvolatile semiconductor memory including memory cells using side walls of island semiconductor layers which avoid lowing of the writing speed and the reading speed. In the nonvolatile semiconductor memory having the nonvolatile semiconductor memory cells each having an island semiconductor layer formed on a semiconductor substrate, the island semiconductor layer having a drain diffusing layer formed on top thereof, a source diffusion layer formed on the lower side thereof, a charge-storage layer formed on a channel area on the side wall interposed between the drain diffusion layer and the source diffusion layer via a gate insulation film, and a control gate formed on the charge-storage layer arranged in matrix, bit lines connected to the drain diffusion layers are arranged in the column direction, control gate lines are arranged in the row direction, and source lines connected to the source diffusion layers are arranged in the column direction, the above-described object is achieved by the nonvolatile semiconductor memory characterized in that common source lines connected to the source lines are formed at every predetermined number of control gate lines, the common source lines are formed of metal, and the common source lines are arranged in the row direction. | 05-21-2009 |
20090135659 | ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE - Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift | 05-28-2009 |
20090147588 | MEMORY DEVICES HAVING REDUCED WORD LINE CURRENT AND METHOD OF OPERATING AND MANUFACTURING THE SAME - There is provided a memory array and methods for manufacturing the same. In one embodiment, there is provided a string comprising a plurality of transistors. Each of the plurality of transistors includes: a charge storage node, a control gate, and at least one resistive element coupled to the string. The control gate of at least one of the plurality of transistors can be selectively coupled to a reference potential via a corresponding one of the at least one resistive element. | 06-11-2009 |
20090154254 | CLUSTER BASED NON-VOLATILE MEMORY TRANSLATION LAYER - An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to the physical blocks/sectors is necessary for a non-volatile memory to appear as a freely rewriteable device to a system or processor. Embodiments of the present invention utilize cluster based address translation to translate logical block addresses to physical block addresses, wherein each cluster contains a plurality of sequentially addressed logical blocks. This allows the use of a smaller RAM table for the address translation lookup and/or faster scanning of the memory device or memory subsystem for the matching cluster address. In one embodiment, a specially formatted cluster is utilized for frequently updated sectors/logical blocks, where the cluster stores a single logical block and a new sequential physical block of the cluster is written in turn with each update. | 06-18-2009 |
20090161441 | Nonvolatile semiconductor memory and method for driving the same - To provide a NOR-type nonvolatile semiconductor memory that can inject electric charge into a charge accumulation layer through the use of an FN tunnel current without compromising an increase in the packing density of memory cells. The above problem is solved by a nonvolatile semiconductor memory in which nonvolatile semiconductor memory cells are arranged in a matrix, each nonvolatile semiconductor memory cell having an island semiconductor layer in which a drain diffusion layer formed in the upper part of the island semiconductor layer, a source diffusion layer formed in the lower part of the island semiconductor layer, a charge accumulation layer formed on a channel region of the side wall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulation film, and a control gate formed on the charge accumulation layer are formed. Further, bit lines connected to the drain diffusion layer are laid out in a column direction, control gate lines are laid out in a row direction, and source lines connected to the source diffusion layer are laid out in the column direction. | 06-25-2009 |
20090168543 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - A method of operating a non-volatile memory device changes a read voltage by determining a degree that threshold voltages of memory cells are changed and overlap each other. The method of operating the non-volatile memory device includes performing a least significant bit (LSB) program of memory cells and determining a first error rate, performing a most significant bit (MSB) program of the memory cells and determining a second error rate, and setting a read voltage corresponding to a value at which the first and second error rates are minimum values. | 07-02-2009 |
20090168544 | ERASE METHOD AND SOFT PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - An erase method and a soft programming method of a non-volatile memory device includes performing an erase operation on a memory cell block; applying a pass voltage to a memory cell adjacent to a select transistor of the memory cell block; applying a soft program voltage to the remaining memory cells of the memory cell block; and performing a soft program operation. | 07-02-2009 |
20090196105 | Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V | 08-06-2009 |
20090196106 | MEM SUSPENDED GATE NON-VOLATILE MEMORY - A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention. | 08-06-2009 |
20090213662 | MEMORY DEVICE AND APPLICATIONS THEREOF - A system that incorporates teachings of the present disclosure may include, for example, a memory device having a memory cell to selectively store holes by photon and bias voltage induction as a representation of binary values. Additional embodiments are disclosed. | 08-27-2009 |
20090244985 | METHOD FOR ERASING A P-CHANNEL NON-VOLATILE MEMORY - A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge storage structure by substrate hole injection effect. Hence, the applied operational voltage is low, so the power consumption is lowered, and the efficiency of erasing is enhanced. As a result, an operational speed of the memory is accelerated, and the reliability of the memory is improved. | 10-01-2009 |
20090251973 | Trench monos memory cell and array - The MONOS vertical memory cell of the present invention allow miniaturization of the memory cell area. The two embodiments of split gate and single gate provide for efficient program and erase modes as well as preventing read disturb in the read mode. | 10-08-2009 |
20090257283 | METHOD FOR DELETING DATA FROM NAND TYPE NONVOLATILE MEMORY - To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element. | 10-15-2009 |
20090262584 | Nonvolatile Memory Cell and Data Latch Incorporating Nonvolatile Memory Cell - A nonvolatile memory cell, comprising: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor. | 10-22-2009 |
20090268527 | SONOS MEMORY DEVICE AND METHOD OF OPERATING A SONOS MEMORY DEVICE - The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-V | 10-29-2009 |
20090290433 | METHOD OF INPUTTING ADDRESS IN NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE - A method of inputting address in a nonvolatile memory device includes inputting a row address including an information for selecting a memory block and an information for selecting a page, and inputting a column including an information for selecting a column and an information for selecting a plane. | 11-26-2009 |
20090296491 | MEMORY HAVING P-TYPE SPLIT GATE MEMORY CELLS AND METHOD OF OPERATION - A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region. | 12-03-2009 |
20090296492 | METHOD FOR ERASING FLASH MEMORY - A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially. | 12-03-2009 |
20090296493 | MID-SIZE NVM CELL AND ARRAY UTILIZING GATED DIODE FOR LOW CURRENT PROGRAMMING - A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided. | 12-03-2009 |
20090310424 | METHOD OF ERASING A FLASH EEPROM MEMORY - The invention is a new method for erasing a flash EEPROM memory device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the first semiconductor region, a well terminal inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer, and a control terminal electrically isolated from the charge storing layer by a inter layer dielectric. The method comprises the steps of: applying a first voltage bias of first polarity to the well terminal; allowing a first time period to elapse; applying a second voltage bias of second polarity opposite to the first polarity to the control terminal; resetting the first voltage bias to zero; allowing a second time period to elapse; and resetting the second voltage bias to zero. | 12-17-2009 |
20090310425 | MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME - In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region. | 12-17-2009 |
20090310426 | SEMICONDUCTOR MEMORY DEVICE - There is offered a semiconductor memory device that has reduced number of high withstand voltage transistors so as to suppress an increase in a die size. A second transistor of N channel type is connected between a word line and a decoder circuit. A control signal from a control circuit is applied to a gate of the second transistor. When an output of the decoder circuit is at a low level, the word line is in a non-selected state, and a high voltage from a switching circuit is not outputted to the word line. Instead, the word line is provided with the ground voltage (=non-erasing voltage) from the decoder circuit through the second transistor. | 12-17-2009 |
20090310427 | EEPROM DEVICES AND METHODS OF OPERATING AND FABRICATING THE SAME - In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions. | 12-17-2009 |
20090316491 | NON-VOLATILE MEMORY DEVICES AND METHODS OF ERASING NON-VOLATILE MEMORY DEVICES - In one embodiment, an erase method for a memory including a memory array having at least first and second programmable transistors connected in series, includes restricting flow of electrons from the first programmable transistor into the second programmable transistor during an erase operation. | 12-24-2009 |
20100027352 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor. | 02-04-2010 |
20100039869 | MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING - A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area. | 02-18-2010 |
20100054043 | Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing - An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency. | 03-04-2010 |
20100061155 | MEMORY ARRAY SEGMENTATION AND METHODS - An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions; and applying a third voltage to those first well regions that do not include the at least one target memory cell. | 03-11-2010 |
20100074027 | HIGH SECOND BIT OPERATION WINDOW METHOD FOR VIRTUAL GROUND ARRAY WITH TWO-BIT MEMORY CELLS - A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array. | 03-25-2010 |
20100074028 | Memory Architecture Having Two Independently Controlled Voltage Pumps - In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell. | 03-25-2010 |
20100074029 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A p-type well region is formed at a main surface of a semiconductor substrate. An n-type impurity region is located under the p-type well region. A first insulating layer ( | 03-25-2010 |
20100103745 | Nand Flash Memory With a Programming Voltage Held Dynamically in a Nand Chain Channel Region - Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access lines are disconnected. In a memory have an array of NAND chains, the capacitance of the channel of each NAND chain can latch a voltage to either enable or inhibit programming. The bit lines can then be disconnected during programming of the group and be used for another memory operation. In one embodiment, the bit lines are precharged for the next verifying step of the same group. In another embodiment, two groups of memory cells are being programmed contemporarily, so that while one group is being programmed, the other group can be verified with the use of the bit lines. | 04-29-2010 |
20100128537 | METHOD OF PROGRAMMING A NON-VOLATILE MEMORY - A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times. | 05-27-2010 |
20100149880 | WINDOW ENLARGEMENT BY SELECTIVE ERASE OF NON-VOLATILE MEMORY CELLS - A method is described for enlarging a programming window of charge trapping memory cells in a virtual ground charge trapping memory EEPROM array. The method substantially eliminates second bit effects and program disturbances to nearby charge trapping memory cells. | 06-17-2010 |
20100157690 | Semiconductor Memory Device of Single Gate Structure - A single gate semiconductor memory device includes a high-potential well on an upper portion of a semiconductor substrate; a first well on an upper portion of the high potential second conductive type well; a second well spaced apart from the first well on the upper portion of the high potential well and across the high-potential well; a floating gate on the first well and the second well; a first ion implantation region in the first well on one side of the floating gate; a second ion implantation region in the first well on an opposite side of the floating gate; a first complementary ion implantation region in the first well next to the second ion implantation region; a third ion implantation region in the second well on one side of the floating gate; and a second complementary ion implantation region in the second well on the opposite side of the floating gate. | 06-24-2010 |
20100165746 | SEMICONDUCTOR MEMORY CELL, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR OPERATING THE SAME - A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a common source and/or an N-well region, grounding and/or floating a control gate, and/or grounding a word line and/or a bit line. A method of operating may include erasing a semiconductor memory cell by floating and/or grounding a word line, applying a preset erase voltage to a control gate, and/or grounding an N-well, a bit line and/or a common source. A method of operating may include reading a semiconductor memory cell by grounding and/or floating a control gate, applying a preset read voltage to an N-well and/or a common source, grounding a word line, and/or applying a preset drain voltage to a bit line. | 07-01-2010 |
20100165747 | NON-VOLATILE MEMORY CELL HEALING - Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string. | 07-01-2010 |
20100172189 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current. | 07-08-2010 |
20100177570 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF COMPENSATING VARIATION WITH TIME OF PROGRAM VOLTAGE - A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase. | 07-15-2010 |
20100182847 | NONVOLATILE MEMORY SYSTEM, SEMICONDUCTOR MEMORY AND WRITING METHOD - A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation. | 07-22-2010 |
20100208526 | Non-volatile memory device and method of operation therefor - In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well. | 08-19-2010 |
20100208527 | SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY - A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase. | 08-19-2010 |
20100238738 | EEPROM Having Single Gate Structure and Method of Operating the Same - An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap. | 09-23-2010 |
20100259996 | System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory - A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells. | 10-14-2010 |
20100296347 | Method of erasing device including complementary nonvolatile memory devices - Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous. | 11-25-2010 |
20100302870 | Nonvolatile memory device and method of operating and fabricating the same - Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line. | 12-02-2010 |
20100315884 | Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof - A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices. | 12-16-2010 |
20100322013 | Nonvolatile Semiconductor Memory Device - In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device. | 12-23-2010 |
20100329037 | CIRCUIT FOR SUPPLYING WELL VOLTAGES IN NONVOLATILE MEMORY DEVICE - A circuit for supplying well voltages in a nonvolatile memory device includes an erase voltage supply unit for supplying an erase voltage to a well in response to an erase enable signal, a discharge unit for discharging the erase voltage, supplied to the well, in response to a discharge control signal, and a negative voltage supply unit for supplying a negative voltage to the well in response to a negative voltage output enable signal. | 12-30-2010 |
20100329038 | METHODS OF OPERATING MEMORY DEVICES INCLUDING DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size. | 12-30-2010 |
20110007574 | METHOD OF ERASING AN NVM CELL THAT UTILIZES A GATED DIODE - A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time. | 01-13-2011 |
20110032772 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel includes the channel configured to be protruded from a substrate, a tunnel insulation layer configured to surround the channel, a plurality of floating gate electrodes and a plurality of control gate electrodes configured to be alternately stacked along the channel, and a charge blocking layer interposed between the plurality of the floating gate electrodes and the plurality of the control gate electrodes alternately stacked. | 02-10-2011 |
20110044115 | Non-volatile memory using pyramidal nanocrystals as electron storage elements - A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices. | 02-24-2011 |
20110051527 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V | 03-03-2011 |
20110096610 | METHOD FOR ENABLING A SONOS TRANSISTOR TO BE USED AS BOTH A SWITCH AND A MEMORY - There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor. | 04-28-2011 |
20110116324 | MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells. | 05-19-2011 |
20110182124 | NON-VOLATILE MEMORY LOW VOLTAGE AND HIGH SPEED ERASURE METHOD - A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory. | 07-28-2011 |
20110188321 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film, a first insulating film provided adjacent to one surface of the charge storage film, a second insulating film provided adjacent to one other surface of the charge storage film, a semiconductor portion provided adjacent to the first insulating film and a plurality of electrode portions provided adjacent to the second insulating film. The control unit performs a control of applying a first voltage to electrode portions adjacent to each other in one direction at different timing respectively, in an erasing. The erasing is performed by at least one selected from injecting electron holes into the charge storage film and removing electrons from the charge storage film. The first voltage is applied from one of the electrode portions to the charge storage film to be erased. | 08-04-2011 |
20110194357 | NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings. | 08-11-2011 |
20110235437 | Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction - A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first pate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor. | 09-29-2011 |
20110255350 | METHOD OF OPERATING MEMORY CELL - A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively. | 10-20-2011 |
20110267896 | Non-Volatile Semiconductor Memory with Page Erase - In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages. | 11-03-2011 |
20110286284 | MULTI-TRANSISTOR NON-VOLATILE MEMORY ELEMENT - The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates. | 11-24-2011 |
20110317493 | Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit - Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. | 12-29-2011 |
20120002485 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory circuit, a write voltage generation circuit receives an output voltage of a voltage boosting circuit to generate a write voltage to a memory cell. When the write voltage is low, a number-of-bits adjustment circuit increases the number of write bits of memory cells before write operation is performed. On the other hand, when the write voltage to a memory cell is high, the number-of-bits adjustment circuit decreases the number of write bits of memory cells before write operation is performed. The area and write time of the voltage boosting circuit can be reduced while the current supply capability of the voltage boosting circuit is efficiently used. | 01-05-2012 |
20120057410 | Method and Apparatus for the Erase Suspend Operation - Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector. | 03-08-2012 |
20120099381 | EMBEDDED NON-VOLATILE MEMORY CELL, OPERATION METHOD AND MEMORY ARRAY THEREOF - The present invention discloses an embedded non-volatile memory cell, an operation method and a memory array thereof. The method includes using a gate of a selection transistor as a floating gate of a memory, and using a source electrode and a drain electrode of the selection transistor as a source electrode and a drain electrode of the memory; and then changing a threshold of the device by varying the electrode voltages, thereby realizing a storage and change of information. The invention has advantages of a small area, a low operating voltage, high operating speed and high reliability. | 04-26-2012 |
20120113727 | CONFIGURATION FINALIZATION ON FIRST VALID NAND COMMAND - A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the memory device. Upon receipt of a valid command, startup functions are ceased at the high current consumption, and normal operation begins without the need for using an unreliable low voltage power on reset circuit. | 05-10-2012 |
20120182811 | METHOD OF ERASING A FLASH EEPROM MEMORY - A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics. The method comprises the steps of: applying a first voltage bias to both the well electrode and the second semiconductor region and a second bias to the control gate electrode for a duration of F/N tunneling; applying a third voltage bias to the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation; and, after the duration of traps depopulation, applying a fourth voltage bias to the control gate electrode and a second zero voltage bias to the well electrode and the second semiconductor region for a duration of traps assisted tunneling. | 07-19-2012 |
20120188825 | MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS - Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing. | 07-26-2012 |
20120188826 | MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS - In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell. | 07-26-2012 |
20120195129 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit controls various kinds of operations on the memory cell array. The control circuit executes a pre-erase stress application operation in which, when an erase operation on one of the memory cells is executed, prior to the erase operation, a first voltage belonging in a certain voltage range is applied to the control gate while a second voltage having a value smaller than a value of the first voltage is applied to the channel region, whereby a stress is applied to the memory cell due to a potential difference between the first voltage and the second voltage. | 08-02-2012 |
20120195130 | SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF - A semiconductor memory device includes: a plurality of memory cells coupled in series between a bit line and a source line; and a bit line control voltage supply unit configured to provide a control voltage to the bit line according to an operation mode, wherein the bit line control voltage supply unit provides a control voltage having a ground voltage level to the bit line during a soft programming operation. | 08-02-2012 |
20120213009 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities. | 08-23-2012 |
20120218829 | NAND FLASH ARCHITECTURE WITH MULTI-LEVEL ROW DECODING - A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector. | 08-30-2012 |
20120230117 | NONVOLATILE SEMICONDCUTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes semiconductor regions provided on a substrate and electrically separated from each other, a memory cell block provided in each of the semiconductor regions and includes nonvolatile memory cells, word lines connected to control gates of memory transistors so as to commonly connect memory transistors in a same row, select gate lines connected to gates of select transistors so as to commonly connect select transistors in a same row, and a row decoder configured to apply a first negative voltage to a selected word line from which data is erased, and to apply a second positive voltage to a non-selected word lines from which data is not erased while an erasing voltage is applied to the semiconductor region upon erasing operation. | 09-13-2012 |
20120230118 | NON-VOLATILE MEMORY CELL HAVING A HEATING ELEMENT AND A SUBSTRATE-BASED CONTROL GATE - The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing. | 09-13-2012 |
20120230119 | WORD LINE DRIVER IN FLASH MEMORY - A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal. | 09-13-2012 |
20120230120 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device including a first bit line commonly coupling drain sides memory cells; a word line commonly coupling control gates of memory cell transistors; a column decoder coupled to a second bit line; a row decoder coupled to a word line; a first transistor having a source coupled to the first bit line and having a drain electrically coupled to the column decoder via the second bit line; and a first control unit for controlling potential of a gate of the first transistor, the memory cell transistor being formed over a first well, the first transistor being formed over a second well electrically isolated from the first well, a film thickness of a gate insulation film of the first transistor being smaller than that of a gate insulation film of a second transistor formed in the row decoder and coupled to the word line. | 09-13-2012 |
20120243337 | P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT - Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+. | 09-27-2012 |
20120243338 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device of an embodiment includes: a cell array including a plurality of memory cells formed on a well and configured by a charge accumulating layer and a control gate; a plurality of control gate lines that are paths for supplying a voltage necessary to access the memory cells to the control gates of the memory cells; and an erasing circuit that performs an erasing operation configured by an erasing period during which data of the memory cells are erased and a resetting period during which a post processing of the erasing period is performed, the erasing circuit applying an erasing voltage necessary to erase the data to the well of the memory cells during the erasing period, and discharging the erasing voltage applied to the well of the memory cells to a ground line via the control gate lines during the resetting period. | 09-27-2012 |
20120243339 | NONVOLATILE MEMORY DEVICES INCLUDING NOTCHED WORD LINES - Nonvolatile memory devices can include a floating gate on a substrate, with a first tunnel insulating film therebetween. A memory gate can be on the floating gate, with a blocking insulating film therebetween. A word line can be located at a first side of both the memory gate and the floating gate, with a second tunnel insulating film therebetween. The first side of the floating gate can protrude beyond the first side of the memory gate toward the word line. | 09-27-2012 |
20120257458 | NON-VOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SAME - A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a n-type floating gate, a coupling gate, a first n-type source/drain, a second n-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a p-type semiconductor substrate. The n-type floating gate is formed on the gate dielectric layer. The first n-type source/drain and the second n-type source/drain are formed in the p-type semiconductor substrate. The first and second contact plugs are formed on the first and second n-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the n-type floating gate, and the third contact plug is formed on the capacitor dielectric layer. | 10-11-2012 |
20120300553 | Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit - Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. | 11-29-2012 |
20120307569 | Printed Non-Volatile Memory - A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology. | 12-06-2012 |
20120314509 | NON-VOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SAME - A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer. | 12-13-2012 |
20120320685 | ERASE OPERATION CONTROL SEQUENCING APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage. | 12-20-2012 |
20120327720 | ADAPTIVE WRITE PROCEDURES FOR NON-VOLATILE MEMORY USING VERIFY READ - A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A determination is made if the voltage insufficient for performing the write operation on the memory cells of the memory array. If a level of the voltage is insufficient, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells. The reduced number of memory cells is a first subset of the memory cells. | 12-27-2012 |
20130003466 | APPLICATION CIRCUIT AND OPERATION METHOD OF SEMICONDUCTOR DEVICE - An application circuit and an operation method of a semiconductor device are provided. A leakage current among a control gate diffusion layer, a source diffusion layer and a drain is reduced by adjusting biases applied on a double well region, so as to reduce the product cost and improve the accuracy of a battery-less electronic timer that uses the semiconductor device. | 01-03-2013 |
20130016570 | N-Channel Erasable Programmable Non-Volatile Memory - In an embodiment of the invention, a method of fabricating a floating-gate NMOSFET (n-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves as the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation. | 01-17-2013 |
20130021850 | MEMORY ARRAY AND METHOD OF OPERATING THE SAME - A memory device comprises at least one memory array on a semiconductor substrate. Each said memory array comprises a page control line and a plurality of pages, each said page is arranged in a row comprising a plurality of bytes which couple to a page control transistor with its drain terminal connected to the page control line. Each said byte includes at least one memory cell. Said memory array further comprises a plurality of source control devices which are configured to provide either predetermined biases or floating potentials to source lines, each said source line couples to all the bytes on the same byte segment of the memory array. Read, erase, and program methods are provided to operate said memory devices in byte addressable fashion. | 01-24-2013 |
20130033941 | Non-Volatile Semiconductor Memory Having Multiple External Power Supplies - A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory. | 02-07-2013 |
20130114346 | METHOD OF OPERATING A FLASH EEPROM MEMORY - The invention is a new method for operating a flash EEPROM memory device and in particular for programming and erasing the device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the first semiconductor region, a well terminal inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer, and a control terminal electrically isolated from the charge storing layer by a inter layer dielectric. The method comprises the steps of: applying a first voltage bias of first polarity to the well terminal; allowing a first time period to elapse; applying a second voltage bias of second polarity opposite to the first polarity to the control terminal; resetting the first voltage bias to zero; allowing a second time period to elapse; and resetting the second voltage bias to zero. | 05-09-2013 |
20130121085 | Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate - A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions. | 05-16-2013 |
20130148437 | THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT - In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range. | 06-13-2013 |
20130215682 | Method for Reading Data Stored in a Flash Memory According to a Threshold Voltage Distribution and Memory Controller and System Thereof - A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution. | 08-22-2013 |
20130215683 | Three-Dimensional Flash-Based Combo Memory and Logic Design - A three-dimensional NAND-based NOR nonvolatile memory cell has two three-dimensional SONOS-type charge-retaining transistors arranged in a series string such that one of the charge-retaining transistors functions as a select gate transistor to prevent leakage current through the charge-retaining transistors when the charge-retaining transistors is not selected for determining a data state of the three-dimensional NAND-based NOR nonvolatile memory cell. The first charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the second charge retaining transistor's source is connected to a source line and is parallel to the bit line. The three-dimensional NAND-based NOR nonvolatile memory cell may be reconfigured to function as a PLD cell, an FPGA switching cell, and an EEPROM cell | 08-22-2013 |
20130215684 | NONVOLATILE MEMORY DEVICE, METHOD FOR OPERATING THE SAME, AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string. | 08-22-2013 |
20130229876 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 09-05-2013 |
20130242672 | Non-volatile Memory Device And A Method Of Operating Same - An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells. | 09-19-2013 |
20130250700 | NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL - The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells. | 09-26-2013 |
20130258785 | APPARATUSES AND METHODS INCLUDING MEMORY WRITE, READ, AND ERASE OPERATIONS - Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The memory cell string can include a body associated with the memory cells. At least one of such embodiments can include a module configured to apply a negative voltage to at least a portion of the body of the memory cell string during an operation of the apparatus. The operation can include a read operation, a write operation, or an erase operation. Other embodiments are described. | 10-03-2013 |
20130265830 | MULTIPLE WRITE OPERATIONS WITHOUT INTERVENING ERASE - A method may be performed by a data storage device and includes writing first data to a group of storage elements. Each particular storage element of the group of storage elements is assigned to a particular state of a first set of states based on a first data value to be stored in the particular storage element. The method also includes overwriting the first data in the group of storage elements with second data. Each particular storage element of the group of storage elements is assigned to a particular state of a second set of states based on a second data value to be stored in the particular storage element. At least one state is included in the first set of states and is excluded from the second set of states. | 10-10-2013 |
20130279267 | METHODS AND SYSTEMS FOR ERASE BIASING OF SPLIT-GATE NON-VOLATILE MEMORY CELLS - Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down failures. The adjusted select-gate erase voltages provide bias voltages on the select-gates that are configured to have the same polarity as the control-gate erase voltages applied during erase operations and that are different from select-gate read voltages applied during read operations. Certain additional embodiments use discrete charge storage layers for the split-gate NVM cells and include split-gate NVM cells having gap dielectric layer thicknesses that are dependent upon control gate dielectric layer widths. | 10-24-2013 |
20130279268 | EEPROM CELL WITH STORAGE CAPACITOR - In an EEPROM cell, as a storage capacitor is added between a control plate and a tunneling plate, after the storage capacitor is charged for a time that is relatively smaller than a time necessary for writing or erasing data of the EEPROM cell, the EEPROM cell that can perform operation of writing or erasing data of the EEPROM cell using a charge voltage that is stored at the storage capacitor is provided. Therefore, operation of writing or erasing data of the EEPROM cell within a short time using the EEPROM cell can be performed, and thus entire productivity of the EEPROM can be improved. | 10-24-2013 |
20130301363 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - Upon programming a semiconductor memory device including a first and a second n-wells, a first and a second p-channel memory transistors respectively formed in the first and the second n-wells, and a bit line connected to a drain of the first p-channel transistor and a drain of the second p-channel memory transistor, a first voltage is applied to the first bit line, a second voltage is applied to the first n-well, and a third voltage lower than the second voltage is applied to the second n-well. | 11-14-2013 |
20140003159 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME | 01-02-2014 |
20140056079 | Method and System for Switchable Erase or Write Operations in Nonvolatile Memory - Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory. | 02-27-2014 |
20140056080 | NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME AND METHOD OF FABRICATING THE SAME - A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings. | 02-27-2014 |
20140078832 | NON-VOLATILE MEMORY HAVING DISCRETE ISOLATION STRUCTURE AND SONOS MEMORY CELL, METHOD OF OPERATING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory. | 03-20-2014 |
20140085990 | VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations. | 03-27-2014 |
20140085991 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 03-27-2014 |
20140140142 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF - A method for programming data is provided for a memory storage device having a rewritable non-volatile memory module and a buffer memory. The method includes receiving a plurality of data including a first-type data and at least one second-type data, and a size of the first-type data is smaller than a data size threshold. The method includes temporarily storing the plurality of data into the buffer memory, and programming the first-type data and at least one part of the at least one second-type data stored in the buffer memory into a physical program unit set if it is determined that the plurality of data are complied with a predetermined condition. The method includes obtaining writing statuses of the first-type data and the at least one part of the at least one second-type data at the same time. | 05-22-2014 |
20140169105 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device includes a semiconductor substrate including a plurality of active regions and a pair of first pillars protruding from each active region. A pair of drain selection lines surround each pillar of the pair of first pillars. A pair of second pillars, wherein each second pillar is disposed over a corresponding first pillar, of the pair of the first pillars, and is formed of a semiconductor material. A plurality of word lines and a source selection line form a stack that surrounds the pair of second pillars. A source line is formed over and connected with the pair of second pillars. Drain contacts are formed at both sides of each active region except between pairs of the drain selection lines. A bit line is formed over and connected with the drain contacts. | 06-19-2014 |
20140219035 | SEMICONDUCTOR MEMORY DEVICE - Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in. | 08-07-2014 |
20140233323 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage. The control circuit is configured to, during the erase operation, set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the second voltage differing from the first voltage. In addition, the control circuit is configured to, during the erase operation, apply in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of dummy memory transistors in a dummy memory string, and apply a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 08-21-2014 |
20140254285 | Temperature-Based Adaptive Erase or Program Parallelism - A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells. | 09-11-2014 |
20140254286 | THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT - In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range. | 09-11-2014 |
20140269102 | EEPROM MEMORY CELL WITH LOW VOLTAGE READ PATH AND HIGH VOLTAGE ERASE/WRITE PATH - An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches. | 09-18-2014 |
20140269103 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly, the reliability of the nonvolatile memory device is improved. | 09-18-2014 |
20140340967 | Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing - A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto. | 11-20-2014 |
20140369136 | SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES - Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device. | 12-18-2014 |
20150023111 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well. | 01-22-2015 |
20150036436 | METHOD AND APPARATUS FOR REDUCING ERASE TIME OF MEMORY BY USING PARTIAL PRE-PROGRAMMING - Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells. | 02-05-2015 |
20150049557 | NON-VOLATILE MEMORY DEVICE AND OPERATION AND FABRICATING METHODS THEREOF - Provided is a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are disposed on a substrate, arranged periodically and extended along a first direction. First inter-poly dielectric films are disposed on the substrate and respectively beneath the first word lines. Second inter-poly dielectric films are disposed on the substrate and respectively beneath the second word lines, wherein the first inter-poly dielectric films are thinner than the second inter-poly dielectric films. A floating gate is disposed between the substrate and each of the first and second inter-poly dielectric films. A tunnel oxide film is disposed between the substrate and each of the floating gates. Bit lines are disposed above the first and second word lines and extended along a second direction different from the first direction. | 02-19-2015 |
20150063038 | MEMORY CELL, MEMORY ARRAY AND OPERATION METHOD THEREOF - A memory cell, a memory array and an operation method are disclosed herein. The memory cell includes a substrate with a first conductivity type, a first doped region with a second conductivity type, a second doped region with the second conductivity type, a first floating gate, a second floating gate and a word gate. The first and the second doped region are disposed in the substrate. The first floating gate is disposed on the substrate and electrically coupled to the first doped region. The second floating gate is disposed on the substrate and electrically coupled to the second doped region. The word line gate is disposed on the substrate and between the first and second doped region, wherein the word gate includes a first part extending over the first floating gate and a second part extending over the second floating gate. | 03-05-2015 |
20150078100 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - A nonvolatile memory cell array is divided into first and second cell arrays, the page buffer circuit is arranged between the first and second cell arrays, a second latch circuit is arranged by the outside edge section of the first cell array, and the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array. The data writing to the first or second cell array is controlled by transmitting the writing data to the page buffer circuit via the global bit line from the second latch circuit, after the writing data is latched in the second latch circuit. The data reading of outputting the data read from the first or second cell array to the external circuit is controlled by transmitting data to the second latch circuit from the page buffer circuit via the global bit line. | 03-19-2015 |
20150103603 | METHODS FOR ERASING, READING AND PROGRAMMING FLASH MEMORIES - The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of −7V˜−10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC−6.5V˜VCC−4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V. In full consideration of factors including the chip manufacturing process, chip circuit design, chip quality and cost, optimal operating conditions fit for erasing, reading and programming, a NOR-type embedded 2T PMOS flash memory are determined. | 04-16-2015 |
20150117116 | Method for Writing into and Reading a Multi-Levels EEPROM and Corresponding Memory Device - During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped. | 04-30-2015 |
20150117117 | MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CONTROL GATES - The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection. | 04-30-2015 |
20150117118 | NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. | 04-30-2015 |
20150131386 | DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A data writing method, a memory storage device, and a memory controlling circuit unit are provided. The writing method includes: grouping logical erasing units into a first region and an second region; determining if a first logical erasing unit which a host system intends to write belongs to the first region or the second region; if the first logical erasing unit belongs to the first region, writing data to a spare physical programming unit, wherein the physical erasing unit to which the spare physical programming belongs further stores data belonging to another logical erasing unit; if the first logical erasing unit belongs to the second region, writing data to a physical erasing unit in which all the valid data belong to the first logical erasing unit. Accordingly, a speed of sequential writing is guaranteed to be greater than a target value. | 05-14-2015 |
20150131387 | LOGIC EMBEDDED NONVOLATILE MEMORY DEVICE - A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line supplied with an erase voltage; and an erase gate selection switch formed between the first memory cells and the second memory cells, wherein the erase gate selection switch connects the global erase gate line to the first erase gate line or the second erase gate line according to an erase control signal. | 05-14-2015 |
20150146490 | NON-VOLATILE MEMORY WITH REDUCED SUB-THRESHOLD LEAKAGE DURING PROGRAM AND ERASE OPERATIONS - A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. | 05-28-2015 |
20150310919 | MEMORY CELL - The invention relates, inter alia, to a memory cell ( | 10-29-2015 |
20150325300 | System And Method To Reducing Disturbances During Programming Of Flash Memory Cells - An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector. | 11-12-2015 |
20150332774 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE - According to one embodiment, a first well of the first conductivity type which is formed in a substrate, a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. | 11-19-2015 |
20150348635 | METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY CELL COMPRISING A SHARED SELECT TRANSISTOR GATE - The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state. | 12-03-2015 |
20150348640 | DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASE TRANSISTOR - The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer. | 12-03-2015 |
20150348981 | INDIVIDUALLY READ-ACCESSIBLE TWIN MEMORY CELLS - The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell. | 12-03-2015 |
20150349142 | SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE - A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer. | 12-03-2015 |
20160005477 | SELECTING MEMORY CELLS - A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals. | 01-07-2016 |
20160005487 | VOLTAGE SWITCH CIRCUIT - A voltage switch circuit includes plural transistors, a first control circuit and a second control circuit. The first transistor has a source terminal connected to a first voltage source and a gate terminal connected to a node b | 01-07-2016 |
20160013194 | NON-VOLATILE MEMORY WITH A SINGLE GATE-SOURCE COMMON TERMINAL AND OPERATION METHOD THEREOF | 01-14-2016 |
20160042790 | Flash Memory System With EEPROM Functionality - The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable. | 02-11-2016 |
20160042795 | NON-VOLATILE MEMORY APPARATUS AND ERASING METHOD THEREOF - The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different. | 02-11-2016 |
20160056301 | RECONFIGURABLE ELECTRONIC DEVICES AND OPERATION METHOD THEREOF - Provided is a reconfigurable electronic device which is implemented by forming independent upper gates and lower gates, wherein in comparison with an existing reconfigurable electronic device having the same function, a degree of integration is greatly increased, a non-volatile memory function is included in the device, and in operation of a reconfigurable circuit based on an independent lower electrode array, dynamic parasitic component is decreased and a complexity of wire lines can be reduced, so that power consumption can be reduced. In addition, in comparison with an existing reconfigurable electronic device, the device exhibits remarkably excellent performance in terms of various characteristics such as diversity of functions of a multi-functional device, alignment margin in process, performance of implementation of infinitesimal electrical doping in a channel, compatibility with bottom-up and top-down method in process, and compatibility with a 1D or 2D material. | 02-25-2016 |
20160064410 | U-SHAPED COMMON-BODY TYPE CELL STRING - A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source. | 03-03-2016 |
20160078951 | PROGRAMMING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A programming method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a first write command; and selecting a first physical erasing unit and sending a first skipping write command sequence according to the first write command. The first skipping write command sequence instructs to execute a first skipping programming process. The first skipping programming process includes: programming first data into a first word line of the first physical erasing unit; and after the first word line is programmed, skipping a second word line adjacent to the first word line, and programming the first data into a third word line not adjacent to the first word line. | 03-17-2016 |
20160078952 | OPERATING METHOD OF NAND FLASH MEMORY UNIT - A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased. | 03-17-2016 |
20160079258 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing. | 03-17-2016 |
20160086672 | ACCESS LINE MANAGEMENT IN A MEMORY DEVICE - Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device. | 03-24-2016 |
20160093395 | One Time Accessible (OTA) Non-Volatile Memory - A programmable non-volatile memory device effectuates two different functions (read, erase (re-program)) during a single instruction or command. During a first phase of the command a cell state is determined by a memory controller circuit, and in a second phase of the same command the cell state is re-written. This implementation is useful for applications where it is desirable to permit one time access only of particular data/content. | 03-31-2016 |
20160099062 | DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first logical unit and at least one second logical unit, and the data includes first data and second data; storing first data into at least one first physical erasing unit and filling the first physical erasing unit with the first data; storing second data into at least one second physical erasing unit; determining whether a remaining space of each second physical erasing unit is less than a threshold; if the remaining space of one of the at least one second physical erasing unit is less than the threshold, selecting at least one fourth physical erasing unit from a spare area and writing the second data into the at least one second physical erasing unit and the at least one fourth physical erasing unit. | 04-07-2016 |
20160099072 | NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES - A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory. | 04-07-2016 |
20160104535 | NONVOLATILE MEMORY HAVING MEMORY ARRAY WITH DIFFERENTIAL CELLS - A nonvolatile memory includes a memory array. The memory array is connected to m word lines and (2+n) bit line pairs. These bit line pairs include an erase bit line pair, a program bit line pair and n data bit line pairs. Each word line is connected with (2+n) differential cells of a corresponding row. The (2+n) differential cells include an erase flag differential cell, a program flag differential cell and n data differential cells. The erase flag differential cell is connected with the erase bit line pair. The program flag differential cell is connected with the program line pair. The n data differential cells are connected with the data line pairs. The n data differential cells are determined as erased cells or programmed cells according to setting conditions of the erase flag differential cell and the program flag differential cell. | 04-14-2016 |
20160104536 | EEPROM BACKUP METHOD AND DEVICE - An electrically erasable programmable read-only memory (EEPROM) device includes a plurality of data areas in the EEPROM associated with a corresponding plurality of memory addresses, respectively, a data status indicator associated with each of the plurality of data areas. The data status indicator is configured to indicate that a data area is in an erase state, an uncertain state, or a valid state. The EEPROM device also includes a controller. A first data area and a second data area are configured to be a backup storage area for each other. In an erase and program cycle, at least one of the first or second memory areas is in a valid state throughout the erase and program cycle. Further, in an erase and program cycle, an erase operation is performed in one of the first or second memory areas, and a program operation is performed in the other data areas. | 04-14-2016 |
20160104537 | MEMORY ARRAY WITH MEMORY CELLS ARRANGED IN PAGES - A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal. | 04-14-2016 |
20160104802 | NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT - According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film. | 04-14-2016 |
20160133330 | NONVOLATILE MEMORY DEVICE AND AN ERASING METHOD THEREOF - An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time. | 05-12-2016 |
20160133639 | Virtual Ground Non-volatile Memory Array - A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region. | 05-12-2016 |
20160141040 | METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE - A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal | 05-19-2016 |
20160148942 | FLASH MEMORY UNIT AND MEMORY ARRAY, AND PROGRAMMING, ERASING AND READING METHOD THEREOF - A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate. | 05-26-2016 |
20160155510 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME | 06-02-2016 |
20160180941 | SEMICONDUCTOR DEVICE | 06-23-2016 |
20160181265 | MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE | 06-23-2016 |
20160189780 | Memory, And Erasing Method, Programming Method And Reading Method Thereof - Memory, and erasing, programming and reading method thereof are provided. In the memory, a first isolation cell, a second isolation cell and a memory cell have same structure. A first doped region of the memory cell and a second doped region of the first isolation cell are connected with a first bit line, a second doped region of the memory cell and a first doped region of the second isolation cell are connected with a second bit line. A first doped region of the first isolation cell serves as a connection terminal thereof, first and second control gate structures of the first isolation cell are connected together to serve as a control terminal thereof, a second doped region of the second isolation cell serves as a connection terminal thereof, first and second control gate structures of the second isolation cell are connected together to serve as a control terminal thereof. | 06-30-2016 |
20160189781 | Circuit For Erasing Data - A circuit for erasing data includes: a high voltage generation unit, adapted for generating an erasing signal; a first control unit, adapted for modifying the erasing signal to a first conduction control signal with a decreased voltage ascending speed; a second control unit, adapted for sending a second conduction control signal based on the first conduction control signal; a lift unit, adapted for lifting an output voltage for erasing data based on the first conduction control signal; a switch unit, adapted for forming an electrical access between the high voltage generation unit and the output end of the circuit for erasing data; and a reference current generation unit, adapted for providing a bias current to the first control unit and the second control unit. Under a circumstance that erasing effect of storage units is improved, area of a chip is relatively reduced by using the circuit for erasing data. | 06-30-2016 |
20160189782 | PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY - A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number of program/erase cycles has been previously applied to one or more memory cells of an array of memory cells of the memory device, using the counter to increment the number of program/erase cycles each time an additional program/erase cycle is applied to the one or more memory cells, using compare logic of the control logic to compare the incremented number of program/erase cycles to a numerical value, and using starting-voltage level control logic of the control logic to adjust a program starting voltage level and/or an erase starting voltage level based on the comparison of the incremented number of program/erase cycles to the numerical value. | 06-30-2016 |
20160203869 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM | 07-14-2016 |
20160379712 | LOW VOLTAGE DIFFERENCE OPERATED EEPROM AND OPERATING METHOD THEREOF - The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure. | 12-29-2016 |
20160379713 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part. | 12-29-2016 |
20170236589 | MEMORY DEVICES WITH A CONNECTING REGION HAVING A BAND GAP LOWER THAN A BAND GAP OF A BODY REGION | 08-17-2017 |