Class / Patent application number | Description | Number of patent applications / Date published |
365185260 | Floating electrode (e.g., source, control gate, drain) | 25 |
20080198669 | METHOD OF OPERATING NON-VOLATILE MEMORY - A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers. | 08-21-2008 |
20080266978 | Arrangements for operating a memory circuit - In one embodiment a method for programming memory cells is disclosed. The method can include applying a programming voltage to a selected memory cell during a lower page programming procedure, the selected memory cell can be part of a string of memory cells containing unselected memory cells, where the string of cells have a source side between the selected memory cell and a source line and have a drain side between the selected memory cell and bit line. The method can also include applying pass voltages to the unselected memory cells during the lower page programming procedure and applying pass voltages to the unselected memory cells during the upper cell programming procedure. The pass voltages can be higher during the upper page programming than during the lower page programming procedure. | 10-30-2008 |
20080273398 | Semiconductor device storage cell structure, method of operation, and method of manufacture - The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least a first source/drain region and a second source/drain region separated from one another by the channel region. A control gate structure, comprising a semiconductor layer doped to the first conductivity type can be formed over a substrate surface. The control gate structure can be in contact with the channel region. Such a storage cell can be more compact and/or provide longer data retention times than conventional storage cells, such as many conventional dynamic random access memory (DRAM) type cells. | 11-06-2008 |
20090016118 | NON-VOLATILE DRAM WITH FLOATING GATE AND METHOD OF OPERATION - A non-volatile capacitor-less 1T DRAM has a semiconductor substrate of a first conducting type with a surface. A first region of a second conductivity type is in the substrate on the surface. A second region of the second conductivity type is in the substrate on the surface, spaced apart from the first region. A body region of the first conductivity type is in the substrate between the first region and the second region. The body region is bound by the surface, one or more insulating regions and the first and second regions. The DRAM further has a floating gate insulated from the surface and is positioned between the first region and the second region. A control gate is capacitively coupled to the floating gate. | 01-15-2009 |
20090244984 | METHOD FOR DRIVING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode. The method includes to achieve a state in which charges having a first polarity are injected into the floating electrode: providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film; subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode. | 10-01-2009 |
20090316490 | METHOD OF WRITING DATA INTO SEMICONDUCTOR MEMORY AND MEMORY CONTROLLER - A method of writing data into a semiconductor memory ( | 12-24-2009 |
20100034027 | Method for programming a nonvolatile memory - A method for programming a nonvolatile memory is provided. The method includes applying at least a voltage to a source or a drain, so as to inject carriers of the source or drain into a substrate; applying a third voltage to a gate or the substrate, so that the carriers which are in the substrate having enough energy can surmount an oxide layer to reach a charge storage device. | 02-11-2010 |
20100103744 | Non-volatile memory device and method of driving the same - A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors. | 04-29-2010 |
20100165745 | NON-VOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - A non-volatile memory device and a driving method thereof. The non-volatile memory device includes a floating gate formed on and/or over a first type well, and transistors formed on and/or over a second type well and connected in series to the floating gate. One of the transistors is a first transistor for program and erase operations, and the other one is a second transistor for a reading operation. | 07-01-2010 |
20100202217 | NAND FLASH MEMORY PROGRAMMING - A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described. | 08-12-2010 |
20100232234 | MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION - Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation. | 09-16-2010 |
20100232235 | Memory Device Having Buried Boosting Plate and Methods of Operating the Same - Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed. | 09-16-2010 |
20110063923 | TRENCH MEMORY STRUCTURE OPERATION - Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls. | 03-17-2011 |
20110216604 | METHOD FOR OPERATING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential. | 09-08-2011 |
20110235436 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes. | 09-29-2011 |
20110280085 | MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION - Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation. | 11-17-2011 |
20120201084 | OPERATING METHODS OF FLASH MEMORY AND DECODING CIRCUITS THEREOF - A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating. | 08-09-2012 |
20120206979 | 3-D STRUCTURED NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes channel structures that each extend in a first direction, wherein the channel structures each include channel layers and interlayer dielectric layers that are alternately stacked; source structure extending in a second direction crossing the first direction and connected to ends of the channel structures, wherein the source structure includes source lines and interlayer dielectric layers that are alternately stacked; and word lines extending in the second direction and formed to surround the channel structures. | 08-16-2012 |
20120287724 | METHOD OF PROGRAMMING MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD - A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection. | 11-15-2012 |
20130016567 | NON-VOLTOLE MEMORY CELL AND METHODS FOR PROGRAMMING, ERASING AND READING THEREOFAANM CHANG; Chia-ChuanAACI Miaoli CountyAACO TWAAGP CHANG; Chia-Chuan Miaoli County TWAANM Chen; Wei-SungAACI Hsinchu CountyAACO TWAAGP Chen; Wei-Sung Hsinchu County TWAANM Wu; Chung-HoAACI Hsinchu CityAACO TWAAGP Wu; Chung-Ho Hsinchu City TW - A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a substrate having a first conductive type. A first transistor, a second transistor and a select transistor having a second conductive type are disposed in the substrate, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. A source region of the first transistor is coupled to a bit line. A drain region of the second transistor and a gate of the select transistor are coupled to a select gate line. A drain region of the first transistor is coupled to a source region of the select transistor. A drain region of the select transistor is coupled to a select line. A bit is stored in the first and second gates by controlling the bit line and the select gate line. A bit stored in the first and second gates is erased by controlling the bit line and the select gate line. | 01-17-2013 |
20130016568 | NON-VOLTOLE MEMORY CELL AND METHODS FOR PROGRAMMING, ERASING AND READING THEREOFAANM CHANG; Chia-ChuanAACI Miaoli CountyAACO TWAAGP CHANG; Chia-Chuan Miaoli County TWAANM Chen; Wei-SungAACI Hsinchu CountyAACO TWAAGP Chen; Wei-Sung Hsinchu County TWAANM Wu; Chung-HoAACI Hsinchu CityAACO TWAAGP Wu; Chung-Ho Hsinchu City TW - A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line. | 01-17-2013 |
20130016569 | MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION - Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation. | 01-17-2013 |
20130044549 | APPARATUS AND METHODS INCLUDING SOURCE GATES - Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described. | 02-21-2013 |
20140050032 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes. | 02-20-2014 |
20140369135 | Ultra-Low Power Programming Method for N-Channel Semiconductor Non-Volatile Memory - An Ultra-low power programming method for N-channel semiconductor Non-Volatile Memory (NVM) is disclosed. In contrast to the grounded voltage at the source electrode of an N-channel semiconductor NVM for the conventional Channel Hot Electron Injection (CHEI) programming, the source electrode in the programming method of the invention is necessarily floating with no voltage bias to prevent applied electrical fields toward the source electrode. The drain electrode of the N-channel semiconductor NVM is reversely biased with a positive voltage V | 12-18-2014 |