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Line charging (e.g., precharge, discharge, refresh)

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365 - Static information storage and retrieval

365185010 - FLOATING GATE

365185180 - Particular biasing

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DocumentTitleDate
20100074026Flash memory device and systems and reading methods thereof - A read method of a flash memory device is provided which comprises reading a plurality of adjacent memory cells connected with a word line different from a plurality of selected memory cells; reading the plurality of selected memory cells one or more times using a plurality of coupling compensation parameters; and selectively latching the read result of the selected memory cells based on the read result of the adjacent memory cells.03-25-2010
20100039866SENSING OF MEMORY CELLS IN A SOLID STATE MEMORY DEVICE BY FIXED DISCHARGE OF A BIT LINE - In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit line is sensed by sense amplifiers to determine the read voltage (i.e., threshold voltage) applied to a word line coupled to the target cell in order to turn on the target cell. The threshold voltage is indicative of the analog voltage stored on the target memory cell.02-18-2010
20130033940APPARATUS AND METHODS OF BIT LINE SETUP - Methods and apparatus are disclosed, including an apparatus that has a memory cell array with a memory cell selectively coupled to a bit line. A control circuit is configured to provide a control signal. A voltage generator is configured to provide a sense signal and a precharge signal in response to the control signal. The apparatus further includes a page buffer configured to provide a bit line voltage to the bit line based on the sense signal and the precharge signal, to thereby control a programming of the memory cell.02-07-2013
20120206978Non-Volatile Memory and Method for Power-Saving Multi-Pass Sensing - A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduce the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.08-16-2012
20100103743Flash memory device and method of testing the flash memory device - A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.04-29-2010
20100135085MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.06-03-2010
20100085814SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device capable of shortening a chip reset period (time) is provided. The semiconductor integrated circuit device has a nonvolatile memory which performs a reading operation of trimming information after completion of precharge of a data line, and a power-on reset circuit (04-08-2010
20120236658SYSTEMS AND METHODS FOR REFRESHING NON-VOLATILE MEMORY - Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved portion. The reserved portion can then be monitored for storage deterioration over time. After determining that storage deterioration of the reserved portion has occurred, the NVM can be refreshed. In some embodiments, a controller can attempt to distinguish data errors due to leakage effects from data errors due to disturb issues.09-20-2012
20090273984BIASING SYSTEM AND METHOD - Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state.11-05-2009
20120287723METHOD AND CIRCUIT TO DISCHARGE BIT LINES AFTER AN ERASE PULSE - Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.11-15-2012
20090207666Methods of Restoring Data in Flash Memory Devices and Related Flash Memory Device Memory Systems - Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.08-20-2009
20110286282SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD - Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.11-24-2011
20110299343NON-VOLATILE MEMORY DEVICE, PRECHARGE VOLTAGE CONTROLLING METHOD THEREOF, AND SYSTEM INCLUDING THE SAME - A non-volatile memory device, precharge voltage control method thereof, and system including the same are provided. The non-volatile memory device includes a bit line connected with a non-volatile memory cell, a precharge voltage generation circuit configured to generate a precharge voltage during a precharge operation, and a control circuit configured to apply the precharge voltage of a second level to the bit line in response to a control signal at a first level during a precharge period in a normal read operation and to apply the precharge voltage of a fourth level to the bit line in response to the control signal at the third level during a precharge period in a verify read or erase operation.12-08-2011
20110299342Flash memory device and systems and reading methods thereof - A read method of a flash memory device is provided which comprises reading a plurality of adjacent memory cells connected with a word line different from a plurality of selected memory cells; reading the plurality of selected memory cells one or more times using a plurality of coupling compensation parameters; and selectively latching the read result of the selected memory cells based on the read result of the adjacent memory cells.12-08-2011
20120008418SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes even page buffers coupled to even memory cells through respective even bit lines, odd page buffers coupled to odd memory cells through respective odd bit lines, first BL selectors, each configured to couple each of the even bit lines to the respective even page buffers and to couple each of the even page buffers to respective odd bit lines so that the even and odd page buffers precharge the odd bit lines in a precharge operation for the odd bit lines, and second BL selectors, each configured to couple each of the odd bit lines to the respective odd page buffers and to couple each of the odd page buffers to respective even bit lines so that the even and odd page buffers precharge the even bit lines in a precharge operation for the even bit lines.01-12-2012
20120008416SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.01-12-2012
20090003080METHOD OF DEPRESSING READ DISTURBANCE IN FLASH MEMORY DEVICE - A method of reading a NAND flash memory device includes a cell string having a drain selection transistor, a plurality of memory cells and a source selection transistor which are in series connected to each other. The method comprises the steps of applying a first voltage to a gate of the drain selection transistor in order to turn on the drain selection transistor, applying a read voltage to a gate of a selected memory cell among the plurality of memory cells, and applying first and second pass voltages to gates of unselected memory cells of the plurality of memory cells, wherein the first pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are adjacent to the selected memory cell and wherein the second pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are not adjacent to the selected memory.01-01-2009
20090190409Integrated Circuit, Cell Arrangement, Method for Operating an Integrated Circuit and for Operating a Cell Arrangement, Memory Module - An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one monitoring memory cell and at least one memory cell, wherein the at least one monitoring memory cell has a shorter retention time than the at least one memory cell. The cell arrangement further includes a detector to detect the memory status of the at least one monitoring memory cell, a comparator to compare the detected memory status of the at least one monitoring memory cell with a predefined memory status for the at least one monitoring memory cell, and a controller to control a refresh operation of the at least one memory cell dependent from the comparing result.07-30-2009
20090316489DYNAMIC PASS VOLTAGE - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.12-24-2009
20100118612SEMICONDUCTOR MEMORY DEVICE AND READ ACCESS METHOD THEREOF - The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the precharging and transition to a read access. The first signal is wired through one or more delay circuits to arrive at each memory cell array with a time difference, and the second signal is wired not through the one or more delay circuits.05-13-2010
20100080067MEMORY AND READING METHOD THEREOF - A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period.04-01-2010
20120106262PROGRAMMING METHOD FOR NONVOLATILE MEMORY APPARATUS - Provided is a method for programming a nonvolatile memory apparatus which includes a bit line selector coupled to first and second bit lines and a page buffer including a main data transmission switch coupled to the bit line selector, a first latch coupled to the main data transmission switch, a temporary data transmission switch coupled to the bit line selector, and a second latch coupled between the temporary data transmission switch and the first latch. In the programming when the first bit line is precharged to a power supply voltage level, a main data transmission switch and a temporary data transmission switch are simultaneously turned on to set up a voltage of the second bit line depending on data levels stored in the first and second latches.05-03-2012
20110170361Electronic Device Comprising Non Volatile Memory Cells and Corresponding Programming Method - A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one program load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit-lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor.07-14-2011
20090290430Method And Apparatus For Reading And Programming A Non-Volatile Memory Cell In A Virtual Ground Array - A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line.11-26-2009
20090290429ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE - Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.11-26-2009
20090290431NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a page buffer circuit. The page buffer circuit includes a memory cell area, a first bit line select unit, and a second bit line select unit. A plurality of memory cells of the memory cell area is connected by bit lines and word lines. The first bit line select unit i s connected to one or more bit lines of the memory cell area and is configured to precharge or discharge a selected bit line in response to a control signal. The second bit line select unit is connected to the same bit line as the first bit line select unit and is configured to precharge or discharge the selected bit line simultaneously with the first bit line select unit.11-26-2009
20090290432METHOD OF READING DATA IN A NON-VOLATILE MEMORY DEVICE - A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature of memory cells, setting a first voltage and a second voltage of a bit line sensing signal in accordance with the sensed temperature, precharging a bit line in accordance with the set first voltage, evaluating a change of a voltage level of the bit line based on whether a memory cell for a read operation is programmed, and sensing data of the memory cell in accordance with the set second voltage. The method may read/verify data constantly even though a temperature is changed.11-26-2009
20090147587CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE - Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.06-11-2009
20100110799NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell.05-06-2010
20100061153Refresh Method for a Non-volatile Memory - A refresh method for a non-volatile memory for preventing disturb phenomenon includes dividing a plurality of sectors of a block of the non-volatile memory into a plurality of groups, determining a first group of the plurality of groups according to a first value when a first sector of the plurality of sectors is performed an erase operation, and reading and rewriting data of sectors of the first group.03-11-2010
20090168542NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell.07-02-2009
20080273397Switched bitline VTH sensing for non-volatile memories - A transistor provides a voltage source commonly switched by SE and SO switches to pre-charge both the even bitline and the odd bitline. The SE and SO switches are open during a sensing stage to determine whether the cell side or the reference side has a higher current and determine the charge stored by a memory cell transistor.11-06-2008
20080304327Methods and apparatuses for refreshing non-volatile memory - Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.12-11-2008
20080291742SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is disclosed, which includes a plurality of NAND cells each comprising a plurality of series-connected memory cell transistors, and a drain-side select transistor and a source-side select transistor connected to a drain-side end and a source-side end of the series-connected memory cell transistors, respectively, a source line commonly connected to the source-side select transistors in the plurality of NAND cells, a first discharge circuit which is connected between the source line and a reference potential and whose conduction/non-conduction is controlled by a first control signal, and a second discharge circuit which is connected between the source line and the reference potential and whose conduction/non-conduction is controlled by a second control signal different from the first control signal.11-27-2008
20090180331Semiconductor memory device having bit line pre-charge unit separated from data register - A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row decoder, and a column decoder. The memory cell array includes a pre-charge unit that is placed between a plurality of memory cell arrays. The pre-charge unit pre-charges a bit line in a read operation. A data register is separated from the pre-charge unit and is located away from the arrays. Write data are coupled from a data register to the arrays, and read data are coupled from the arrays to the data register.07-16-2009
20110205809Bit Line Decoder Architecture for NOR-Type Memory Array - An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines. During sensing of a state of a given memory cell, the bit line decoder (i) precharges a first bit line of the two corresponding bit lines to which the given memory cell is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and (ii) precharges a second bit line of the two corresponding bit lines to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential.08-25-2011
20120069683SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.03-22-2012
20120069682WORD LINE BOOSTER FOR FLASH MEMORY DEVICE - A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with the specific voltage as a drive voltage during an operation of the memory device, wherein the word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel each other adapted to generate a boosting voltage and a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor. the word line booster circuit further includes a third boosting capacitor operatively connected to the first boosting capacitor and the second boosting capacitor via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled. In addition, the word line booster circuit includes a high voltage detector to generate a detecting signal in response to a control signal from an address transition detector and the output signal generated by the third boosting capacitor and load resistor and a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first boosting capacitor and the second boosting capacitor upon receiving the control signal from the address transition detector and the detecting signal from the voltage detector. The word line booster circuit further includes a discharge circuit to discharge the boosting voltage at a node connected to the third boosting capacitor.03-22-2012
20090052258Systems, methods and devices for a memory having a buried select line - Embodiments are described for programming and erasing a memory cell by utilizing a buried select line. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.02-26-2009
20100014357FLASH-BASED FPGA WITH SECURE REPROGRAMMING - A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.01-21-2010
20100182846Flash memory with two-stage sensing scheme - For the flash memory, two-stage sensing scheme is realized such that a tiny local sense amp is devised in order to insert between memory cells, which minimizes area penalty, wherein the local sense amp is connected to a global sense amp through a global bit line for configuring two-stage sensing scheme. By inserting as many as local sense amps, long bit line is multi-divided into short bit lines. By the sensing scheme, cell current difference is converted to time difference when reading data. With the short bit line architecture, bit line capacitance is significantly reduced, so that low current memory cell can be used for storing data, and which cell may reduce programming time as well. Furthermore, the memory cell can be formed from thin-film transistor even though the thin-film transistor can flow lower current, which realizes multi-stacked memory cells. Additionally, alternative circuits and memory cell structures are described.07-22-2010
20110058427FLASH MEMORY DEVICE CONFIGURED TO REDUCE COMMON SOURCE LINE NOISE, METHODS OF OPERATING SAME, AND MEMORY SYSTEM INCORPORATING SAME - A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL.03-10-2011
20090010074SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.01-08-2009
20090073774Pre-charge sensing scheme for non-volatile memory (NVM) - The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.03-19-2009
20100220532Readout Circuit for Rewritable Memories and Readout Method for Same - In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.09-02-2010
20100302867CIRCUIT FOR PRECHARGING BIT LINE AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - A nonvolatile memory device includes a memory cell array configured to comprise a number of cell strings, a number of page buffers each coupled to the cell strings of the memory cell array through bit lines, and a bit line precharge circuit configured to precharge a selected bit line up to a voltage of a first level before one of the page buffers precharges the selected bit line.12-02-2010
20100302866METHOD OF TESTING FOR A LEAKAGE CURRENT BETWEEN BIT LINES OF NONVOLATILE MEMORY DEVICE - A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.12-02-2010
20100302868METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.12-02-2010
20110122708METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS - A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.05-26-2011
20110019486SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines.01-27-2011
20110116322CHARGE RECYCLING MEMORY SYSTEM AND A CHARGE RECYCLING METHOD THEREOF - A memory system, including a nonvolatile memory device, a charge recycler configured to discharge charges from the nonvolatile memory device and recycle the discharged charges, and a controller configured to control the nonvolatile memory device and the charge recycler, wherein the controller controls the charge recycler to recycle the discharged charges, wherein during the recycling the charge recycler charges the charges discharged from the nonvolatile memory device.05-19-2011
20100195407READ OPERATION METHOD OF MEMORY DEVICE - A read operation method of a memory device includes applying a first voltage to each of a first memory cell and a second memory cell during a first read operation, applying the first voltage to the first memory cell and a second voltage to the second memory cell during a second read operation, and applying the second voltage to the first memory cell and the first voltage to the second memory cell during a third read operation.08-05-2010
20110249509SEMICONDUCTOR MEMORY DEVICE CAPABLE OF EXECUTING HIGH-SPEED PAGE COPY - According to one embodiment, a semiconductor memory device includes a memory cell array, first and second data caches, and a control circuit. The control circuit is configured to control, with use of the first and second data caches, a read operation of reading data from the selected memory cell of the memory cell array, and a write operation of writing data in the selected memory cell of the memory cell array. The control circuit is configured to execute, at a time of the read operation, an arithmetic operation of the data held in the first data cache by using the first and second data caches, and to generate the data which is to be written in the selected memory cell.10-13-2011
20100246274SEMICONDUCTOR MEMORY DEVICE HAVING BIT LINE PRE-CHARGE UNIT SEPARATED FROM DATA REGISTER - A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row decoder, and a column decoder. The memory cell array includes a pre-charge unit that is placed between a plurality of memory cell arrays. The pre-charge unit pre-charges a bit line in a read operation. A data register is separated from the pre-charge unit and is located away from the arrays. Write data are coupled from a data register to the arrays, and read data are coupled from the arrays to the data register.09-30-2010
20100302869FLASH MEMORY DEVICE OPERATING AT MULTIPLE SPEEDS - A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.12-02-2010
20100296346NAND MEMORY DEVICE COLUMN CHARGING - Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.11-25-2010
20100259995METHOD OF PERFORMING READ OPERATION OF NONVOLATILE MEMORY DEVICE - In a method of performing a read operation of a nonvolatile memory device, a selected bit line is precharged. A pass voltage is sequentially applied to all word lines. The pass voltage applied to a word line, selected from among all the word lines, is changed for a read voltage. The read voltage is applied to the selected word line. Data of a memory cell coupled to the selected word line is read.10-14-2010
20090129170METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device includes, a bit line, to which a program-inhibited cell is connected, being precharged. After precharging the bit line, a program voltage is applied to a first word line selected for program. When a memory cell connected to a second word line, which is adjacent to the first word line in a direction of a drain select line, is a cell to be programmed, a first pass voltage is applied to the second word line and a second pass voltage is applied to the remaining word lines other than the first and second word lines.05-21-2009
20080291743SEMICONDUCTOR STORAGE DEVICE - This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node.11-27-2008
20120170379SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device according to an aspect of the present disclosure includes a first page buffer coupled to a first even bit line and a first odd bit line, a second page buffer coupled to a second even bit line and a second odd bit line, and a controller configured to control the first and the second page buffers so that the second page buffer sets the second even bit line in a floating state such that the voltage of the second even bit line is changed according to a shift in the voltage of the first odd bit line, when a read operation for memory cells coupled to the first odd bit line is performed, and the second page buffer stores data corresponding to the level of threshold voltages of the memory cells by detecting a shift in the voltage of the second even bit line.07-05-2012
20110255347SEMICONDUCTOR MEMORY - A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.10-20-2011
20100329036NONVOLATILE MEMORY DEVICE AND READING METHOD THEREOF - In a nonvolatile memory device and operating method thereof, data programmed into a second memory cell is sensed and a first memory cell adjacent the second memory cell is read in accordance with the data sensed from the second memory cell.12-30-2010
20100329034ESTIMATING VALUES RELATED TO DISCHARGE OF CHARGE-STORING MEMORY CELLS - One or more groups of charge-storing memory cells are selected from a plurality of regular charge-storing memory cells of a storage device. The selected memory cells are initialized with initial binary data, by charging them with corresponding amounts of electric charge, or the selected memory cells are simply used as is containing user data. Then, while the selected memory cells undergo a self discharge process, collective changes in the binary states of the selected memory cells are used to estimate discharge-determining conditions such as elapsed time, wear rate or wear level of the memory cells. The adverse effects of the erratic behavior of individual charge-storing memory cells on such estimations is mitigated by using a large group of charge-storing memory cells, and the effect of temperature on the aforesaid estimations is reduced by using two or more large groups of charge-storing memory cells.12-30-2010
20100329035NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DISCHARGE CIRCUIT THEREOF - A discharge circuit of a nonvolatile semiconductor memory device includes a memory array region including a plurality of floating gate type MOS memory cell transistors each including a source, a drain and a control gate which are formed in a P-well, where the P-well is formed in an N-well of a P-type semiconductor substrate. The discharge circuit further includes a plurality of terminals formed in the memory array region, and respectively connected to the control gate, the P-well and the N-well, a plurality of constant current transistors respectively connected to the plurality of terminals, and a plurality of switching transistors respectively connected to the plurality of constant current transistors. The respective constant current transistors and switching transistors are turned on at a same timing during a discharge operation.12-30-2010
20100195406METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor, including precharging a sense node to thereby precharge a bit line coupled to the cell string for a program or data read operation; and simultaneously resetting a cell channel in a state in which the drain select transistor is turned off, the source select transistor is turned on, and the memory cells are turned on by applying a first voltage to a number of word lines coupled to the memory cells during a first time period, wherein the first time period is less than a bit line precharge time period.08-05-2010
20120307566MEMORY CELL SENSING USING A BOOST VOLTAGE - The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.12-06-2012
20090003079METHOD AND CIRCUIT FOR PERFORMING READ OPERATION IN A NAND FLASH MEMORY - Disclosed is a method and semiconductor circuit for providing a read operation in a NAND flash memory. The NAND flash memory includes an array of bit lines. The method includes selecting a first set of bit lines of the array of bit lines for performing the read operation. The first set of bit lines are pre-charged to a pre-defined voltage level. At the same time, a second set of bit line are also charged to the pre-defined voltage. The second set of bit lines are in anti-phase to the first set of bit lines. Further, reading of the first set of bit-lines is performed. The second set of bit lines is maintained at the pre-defined voltage level during the reading of the first set of bit lines.01-01-2009
20120307567METHOD OF OPERATING NON-VOLATILE MEMORY DEVICE - A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word lines of the memory cell block.12-06-2012
20110063922NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Nonvolatile semiconductor memory device according to one embodiment includes: a plurality of planes; a memory cell array provided in the plurality of planes respectively; bit lines; and a control circuit. Each memory cell array is configured as an array of NAND cell units each including a memory string. The memory string includes a plurality of nonvolatile memory cells connected in series. The bit lines are connected to a first end of the NAND cell units, respectively. The control circuit controls a write operation of charging the bit lines up to a certain voltage value, and then setting data in the nonvolatile memory cells to a certain threshold voltage distribution state. The control circuit is configured to be capable of executing an operation of charging the bit lines in a write operation by varying timings of starting charging the bit lines among the plurality of planes.03-17-2011
20120008419SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes cells strings including memory cells and coupled between a common source line and bit lines, respectively, a peripheral circuit configured to store data in the memory cells or read data stored in the memory cells, a main voltage supply unit configured to generate operating voltages to be supplied to the peripheral circuit, a precharge voltage supply unit configured to generate a precharge voltage for precharging the bit lines, and a switching circuit configured to transfer the precharge voltage to the common source line and one of the bit lines when a bit line precharge operation is performed.01-12-2012
20120008415SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING THE SAME - A method of erasing a semiconductor memory device includes precharging a channel of a selected memory cell of a selected string including memory cells; boosting a channel of the selected string by supplying a positive voltage to word lines of the respective memory cells of the selected string; and erasing the selected memory cell by supplying an erase voltage lower than the positive voltage to a selected word line associated with the selected memory cell.01-12-2012
20120008417NONVOLATILE MEMORY AND OPERATION METHOD OF THE SAME - A nonvolatile memory includes a first bit line coupled to a first cell string, a second bit line coupled to a second cell string, and a bit line precharge unit configured to precharge the first bit line and the second bit line before a program operation. A bit line selected from among the first bit line and the second bit line is precharged to a lower voltage level than a target voltage level, and an unselected bit line is precharged to the target voltage level.01-12-2012
20120063238PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM) - The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.03-15-2012
20120014187Non-volatile memory device and method of operation therefor - In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.01-19-2012
20120014186Fast Random Access To Non-Volatile Storage - Techniques are disclosed herein for efficiently operating memory arrays of non-volatile storage devices. In one embodiment, when reading data from an MLC block, reading is sped up by not discharging bit lines between successive sensing operations. For example, all even bit lines are charged up and odd bit lines are grounded to set up sensing of memory cells that are associated with a first word line and the even bit lines. Then, memory cells associated with the first word line and the even bit lines are read by, for example, sensing the even bit lines. Then, while the even bit lines are still charged, memory cells associated with another word line and the even bit lines are read. Because the even bit lines remain charged between the two sensing operations, time is saved in not having to re-charge the bit lines to an appropriate level for sensing.01-19-2012
20120057409NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME - A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells, precharging bit lines coupled to undetermined memory cells whose data has not been determined by the first read operation, and performing a second read operation by supplying a second reference voltage to the memory cells in order to determine data stored in the undetermined memory cells.03-08-2012
20090161440INTEGRATED CIRCUITS AND DISCHARGE CIRCUITS - An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.06-25-2009
20120026801SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DISCHARGING WORDLINE THEREOF - Various embodiments of a semiconductor apparatus having a discharge technology are disclosed. In one exemplary embodiment, the semiconductor apparatus may include a plurality of lines in which a selected line is driven by a first control voltage and an unselected line is driven by a second control voltage with a level lower than the first control voltage. The apparatus may also include a discharge control unit configured to form a discharge current path between a discharge node of the selected line and a common discharge node of the unselected line and induce a predetermined voltage difference between the discharge node and the common discharge node; and a common discharge unit configured to discharge current flowing through the discharge current path.02-02-2012
20110090744CHANNEL PRECHARGE AND PROGRAM METHODS OF A NONVOLATILE MEMORY DEVICE - A channel pre-charge method of a nonvolatile memory device including a cell string includes pre-charging a channel of the cell string according to a first word line bias condition and pre-charging the channel of the cell string according to a second word line bias condition, different than the first word line bias condition.04-21-2011
20110032771Memory and Reading Method Thereof - A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period.02-10-2011
20100091576Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device - A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively, to charge the channels; and applying a word line voltage for a program after charging the channels. A channel voltage boosting of each of the channels is determined according to data loaded in adjacent page buffers.04-15-2010
20100091575PROGRAMMING METHOD AND INITIAL CHARGING METHOD OF NONVOLATILE MEMORY DEVICE - A programming method of a nonvolatile memory device includes precharging bit lines of the nonvolatile memory device based on loaded data, boosting channels corresponding to the respective precharged bit lines, after supplying word lines adjacent to a selected word line of the nonvolatile memory device with an initializing voltage, the selected word line is a word line selected for programming, and supplying a word line voltage for programming to the channels, after the channels are boosted.04-15-2010
20120314506SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes cell strings that each include a plurality of memory cells, a page buffer having latches coupled to bit lines and precharge the bit lines in response to page buffer control signals, a page buffer control circuit configured to generate the page buffer control signals using a high voltage source, and a controller configured to generate control signals for controlling the page buffer control circuit.12-13-2012
20120163097MEMORY DEVICE, MEMORY CONTROL METHOD, AND PROGRAM - A memory device includes: a non-volatile memory erasing data in a block unit and writing and reading data to and from a block; and a control unit controlling an access operation to the non-volatile memory, monitoring levels of a data change state of the non-volatile memory, and controlling a refresh operation of the non-volatile memory. The control unit executes the refresh operation in accordance with a comparison result between a plurality of set emergency levels of the refresh operation and the levels of the data change state.06-28-2012
20120170381NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.07-05-2012
20120170380SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a first detecting circuit, a second detecting circuit, a switching circuit and a recovery control circuit. The first detecting circuit outputs a first detection signal which shows whether an externally supplied external power supply is equal to or more than a first voltage. The second detecting circuit outputs, at a higher speed than the first detecting circuit, a second detection signal which shows whether the external power supply is equal to or more than the first voltage. In a write operation, the switching circuit outputs the second detection signal output from the second detecting circuit. In an operation other than the write operation, the switching circuit outputs the first detection signal output from the first detecting circuit. The recovery control circuit terminates the write operation according to the second detection signal output from the switching circuit.07-05-2012
20120075935VOLTAGE DISCHARGE CIRCUITS AND METHODS - Memory devices, memory systems, discharge circuits, and methods for discharging a capacitance are disclosed. In one such memory device, a discharge circuit is coupled to memory support circuitry. When a supply voltage decreases to be less than or equal to a trip voltage, the discharge circuit discharges a voltage from a capacitance of the memory support circuitry.03-29-2012
20120257457METHOD AND APPARATUS FOR PRE-CHARGING DATA LINES IN A MEMORY CELL ARRAY - Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference.10-11-2012
20120081972MEMORY ARRAYS AND METHODS OF OPERATING MEMORY - Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.04-05-2012
20120230116SENSE OPERATION IN A STACKED MEMORY ARRAY DEVICE - Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).09-13-2012
20080298134METHOD OF READING CONFIGURATION DATA IN FLASH MEMORY DEVICE - Provided is a method of reading configuration data in a flash memory device, including a memory cell array which stores configuration data about an operating environment of the flash memory device. The method includes setting a read time of the configuration data to differ from a read time of normal data, and reading the configuration data.12-04-2008
20120320684METHOD FOR DISCHARGING A VOLTAGE FROM A CAPACITANCE IN A MEMORY DEVICE - In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit.12-20-2012
20090073775Bit line setup and discharge circuit for programming non-volatile memory - A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages. A first stage pre-charges all bit lines via PMOS pull-up, and the second stage uses the latches to discharge or leave charged the selected bit lines depending on respective data bits being stored. The gate voltages of NMOS transistors in the programming circuitry can be controlled to reduce noise caused by discharging selected bit lines through the latches.03-19-2009
20090086547CIRCUIT FOR PERFORMING READ OPERATION IN NAND FLASH MEMORY AND METHOD THEREOF - A circuit for performing a read operation in a NAND flash memory is disclosed. The NAND flash memory includes an array of bit lines grouped into first group of bit lines and second group of bit lines. The circuit includes a plurality of pre-charging and reading circuitries connected at first end of the array of bit lines and a plurality of pre-charging circuitries connected at second end of the array of bit lines. The pre-charging and reading circuitries include a select circuit which selects one group from the first and the second group of bit lines; a first and a second circuit to pre-charge and read the selected group of bit lines from the first end. The plurality of pre-charging circuits include two select lines to select one group of bit lines, and a plurality of pre-charging transistors to pre-charge the selected group of bit lines from the second end.04-02-2009
20110235435Non-Volatile Memory and Method for Power-Saving Multi-Pass Sensing - A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.09-29-2011
20120092933MEMORY ERASE METHODS AND DEVICES - Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.04-19-2012
20100202216NON-VOLATILE MEMORY DEVICE AND SYSTEM HAVING REDUCED BIT LINE BIAS TIME - A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time.08-12-2010
20110158002SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory string coupled between a common source line and a bit line, a page buffer configured to supply a first precharge voltage to the bit line and to latch data corresponding to a threshold voltage level of a memory cell of the memory string, wherein the data is detected according to a shift in a voltage of the bit line, in a precharge operation, a precharge circuit configured to supply a second precharge voltage to the common source line in the precharge operation, and a voltage supply circuit configured to generate operating voltages for turning on the memory string in the precharge operation. While the first precharge voltage is supplied from the page buffer to the bit line, the second precharge voltage is supplied to the bit line through the memory string.06-30-2011
20120243335NON-VOLATILE SEMICONDUCTOR MEMORY WITH BIT LINE HIERARCHY - Local bit lines (LBL) are respectively provided for a plurality of sectors, corresponding to each of the global bit lines (GBL). Sector select transistors connect a LBL to a GBLector select lines control the on/off state of the sector select transistors for the corresponding sectors. A plurality of word lines (WL) intersect the local bit lines. Memory cells are located at the intersections between the LBL and the WL. Each memory cell connects a source line with the corresponding LBL and includes an n-channel transistor that is turned on/off by the corresponding WL. A precharge voltage is applied to a charging line. Charging transistors connect the LBL to the charging line. A charging gate line controls the on/off state of the charging transistors.09-27-2012
20090059675Radiation hardened multi-bit sonos non-volatile memory - In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+ implant or a blanket P+ implant is disposed in a substrate. A portion of the recessed P+ implant or a portion of the blanket P+ implant is disposed beneath outer edges of the poly-silicon gate, in a channel separating the buried source and the buried drain.03-05-2009
20080225600METHOD OF READING DATA IN A NON-VOLATILE MEMORY DEVICE - A method of reading data in a non-volatile memory device includes providing a plurality of blocks and a plurality of bit lines, each block having a plurality of memory cells, each block coupled to at least one bit line. Frst and second bit lines are discharged to be at a low level, the first bit line coupled to a first block, the second bit line coupled to a second block. A read voltage is applied to a first word line coupled to a memory cell to be read in the first block. A pass voltage is applied to a second word line coupled to a memory cell not to be read in the first block. The first bit line coupled to the memory cell to be read is precharged to a high level after applying the read voltage to the first word line and the pass voltage to the second word line. A voltage level of the first bit line is evaluated. Data stored in the memory cell to be read is sensed in accordance with the evaluated voltage level of the first bit line.09-18-2008
20130170303NONVOLATILE MEMORY DEVICE, METHOD FOR OPERATING THE SAME, AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.07-04-2013
20130176793FLASH MEMORY APPARATUS - A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.07-11-2013
20130176794METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage.07-11-2013
20110267895METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A method of operating a semiconductor memory device includes selecting one of a plurality of word lines, applying a program voltage, gradually dropping from a third level to a first level, to the selected word line, and discharging bit lines whenever a level of the program voltage is changed.11-03-2011
20110267894SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a voltage transfer unit configured to transfer a first word line control voltage among a plurality of word line control voltages to an assigned word line in a first operational period, and to transfer a second word line control voltage among the plurality of word line control voltages to the assigned word line in a second operational period; and a word line discharge unit configured to discharge the word line to a voltage level that is higher than a ground voltage and lower than the first and second word line control voltages in a discharge period between the first operational period and the second operational period.11-03-2011
20080198668NONVOLATILE SEMICONDUCTOR MEMORY AND DRIVING METHOD THEREOF - A nonvolatile semiconductor memory according to an aspect of the invention comprises a plurality of serially connected memory cells arranged on a P-well area within a semiconductor substrate, select gate transistors connected to one end and the other of the serially connected memory cells, a P-well control circuit which controls the P-well area, a plurality of word lines connected to the plurality of memory cells, a row control circuit which controls the plurality of word lines, and an operation control circuit which controls the P-well control circuit and the row control circuit, wherein, when writing to a selected one of the plurality of memory cells, the operation control circuit controls the P-well control circuit to apply a precharge potential to the P-well area and thus precharge channel areas of the plurality of memory cells.08-21-2008
20080198667NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.08-21-2008
20110235434SYSTEMS AND METHODS FOR REFRESHING NON-VOLATILE MEMORY - Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved portion. The reserved portion can then be monitored for storage deterioration over time. After determining that storage deterioration of the reserved portion has occurred, the NVM can be refreshed. In some embodiments, a controller can attempt to distinguish data errors due to leakage effects from data errors due to disturb issues.09-29-2011
20100315883NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device comprises a memory cell array including a number of bit lines commonly coupled to a source line and each coupled to a number of memory cells, a delay unit configured to delay a sense signal in response to a voltage level of the source line and to output a delayed sense signal, and a page buffer unit configured to sense voltage levels of the bit lines in response to the delayed sense signal.12-16-2010
20100315882NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a memory cell array including a number of memory cells coupled to a selected bit line, a bit line selection unit configured to select and precharge the selected bit line, and a potential control unit configured to control a voltage level of the precharged bit line in response to a voltage level corresponding to a value of program data.12-16-2010
20130155777CURRENT SENSING TYPE SENSE AMPLIFIER AND METHOD THEREOF - The configurations of sense amplifier and methods thereof are provided. The proposed sense amplifier includes a switch circuit having a main control switch, a sensing switch and a holding switch, wherein the three switches have a first bias, a second bias and a third bias respectively, and an auxiliary control switch electrically connected to the holding switch to control an operation of the holding switch.06-20-2013
20130155778NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, memory strings formed above the semiconductor substrate, and a control circuit configured to control voltages applied to the memory cells. In a read operation, when the control circuit precharges a first source line electrically connected to a selected memory string to a first voltage, the control circuit precharges a second source line electrically connected to an unselected memory string to a second voltage, the second voltage being higher than the first voltage, and after the second source line is precharged, the control circuit precharges a first bit line electrically connected to the selected memory string to the second voltage.06-20-2013
20110292737NONVOLATILE MEMORY APPARATUS - A nonvolatile memory apparatus includes: a plurality of drain selection switches coupled to a plurality of memory cell strings, respectively; and a drain selection switch controller configured to selectively drive a drain selection switch coupled to an even bit line or a drain selection switch coupled to an odd bit line, in response to a page address and a global drain selection signal.12-01-2011
20110310675LOCAL SENSING IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells.12-22-2011
20130188427COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.07-25-2013
20120020167FLASH MEMORY DEVICE AND A METHOD OF PROGRAMMING THE SAME - A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.01-26-2012

Patent applications in class Line charging (e.g., precharge, discharge, refresh)