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Drive circuitry (e.g., word line driver)

Subclass of:

365 - Static information storage and retrieval

365185010 - FLOATING GATE

365185180 - Particular biasing

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DocumentTitleDate
20110128792SEMICONDUCTOR STORAGE DEVICE AND BOOSTING CIRCUIT - A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor. The switch circuit conducts changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal.06-02-2011
20130077411Dynamic Switching Approach to Reduce Area and Power Consumption of High Voltage Charge Pumps - A charge pump system uses a dynamic switching approach, where the pump connections are independent of the load for each output. One large pump is designed to be shared between all of the outputs for use during the ramp up during recovery, with each output level also have one designated pump to maintain its level when under regulation. Each small pump is designed with capability that can maintain its output at its regulation level. Each of these pumps can be tailored to the corresponding output level, such as the number of stages being higher in the pump to supply the higher output level. The large pump unit is constructed to be ample to provide sufficient drive to be able to assist in the ramp up phase for all of the outputs and has as many switches needed to connect the pump with all the needed outputs.03-28-2013
20130077413SEMICONDUCTOR MEMORY DEVICE - A flash memory 03-28-2013
20130077412ROW DRIVER CIRCUIT FOR NAND MEMORIES INCLUDING A DECOUPLING INVERTER - Devices and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.03-28-2013
20090244982MEMORY BLOCK REALLOCATION IN A FLASH MEMORY DEVICE - A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.10-01-2009
20090175088METHOD AND ARCHITECTURE FOR FAST FLASH MEMORY PROGRAMMING - Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.07-09-2009
20120218828Methods for Programming Nonvolatile Memory Devices - Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.08-30-2012
20110058426NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.03-10-2011
20120195127NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory includes a plurality of memory cells and a driver for selectively driving the memory cells. The driver includes a first drive portion and a second drive portion. The first drive portion is provided for applying a source voltage higher than a power source voltage to a source region of the memory cell. The second drive portion is provided for applying a specific low voltage to a drain region of the memory cell for writing data having a first logic level, so that a writing current flows in the memory cell. Further, the second drive portion is provided for applying a specific high voltage higher than the power source voltage as a writing prohibition voltage to a drain region of the memory cell for writing data having a second logic level, so that the writing current is prevented from flowing in the memory cell.08-02-2012
20090010073Non-Volatile Memory System Including Spare Array and Method of Erasing a Block in the Same - Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller.01-08-2009
20090010072SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells (01-08-2009
20130163345SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell.06-27-2013
20110141820SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.06-16-2011
20100008152SEMICONDUCTOR DEVICE INCLUDING DRIVING TRANSISTORS - A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.01-14-2010
20090052257NONVOLATILE SEMICONDUCTOR MEMORIES FOR PREVENTING READ DISTURBANCE AND READING METHODS THEREOF - A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.02-26-2009
20080266976NAND MEMORY DEVICE AND PROGRAMMING METHODS - A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines.10-30-2008
20100118611DELAYED ACTIVATION OF SELECTED WORDLINES IN MEMORY - Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.05-13-2010
20100080066MEMORY, MEMORY OPERATING METHOD, AND MEMORY SYSTEM - A memory includes a plurality of memory cells each of which includes a memory transistor and a selection transistor; a control gate line; a selection gate line; a source line; a bit line; a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation; a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage; and a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed.04-01-2010
20090046516DATA WRITING METHOD FOR FLASH MEMORIES - A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave signal to the switching unit for the bit line of the flash memory to receive a fixed drain voltage.02-19-2009
20100128535SEMICONDUCTOR MEMORY AND METHOD AND SYSTEM FOR ACTUATING SEMICONDUCTOR MEMORY - A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line coupled to a gate electrode of the selection transistor, a selection gate driver configured to apply a voltage to the selection gate line, a switch circuit configured to couple the control gate line to the selection gate line, and a level converting unit coupled to the control gate line and a voltage line and configured to convert a voltage of the control gate line into a voltage of the voltage line.05-27-2010
20100220530CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY - An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.09-02-2010
20090296490NON-VOLATILE MEMORY DEVICE, COMPUTING SYSTEM AND WORDLINE DRIVING METHOD - A nonvolatile memory device including a memory cell; a word line coupled to the memory cell; a drive line; a switch coupled between the word line and the drive line, and configured to electrically connect the word line and the drive line; and a voltage generator coupled to the drive line and configured to charge the drive line to a precharge voltage. The precharge voltage is higher than a bias voltage applied to the word line during a corresponding operation on the memory cell.12-03-2009
20110199833NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.08-18-2011
20080291741BIT LINE DECODER ARCHITECTURE FOR NOR-TYPE MEMORY ARRAY - A bit line decoder for sensing states of memory cells of a memory array includes control devices and a control module. The control devices selectively communicate with bit lines. The control devices are arranged in a multi-level configuration having a plurality of levels, each level having a plurality of the control devices. The control module selects from the bit lines a first bit line and a second bit line associated with a memory cell located in the memory array when determining a state of the memory cell. The control module generates first control signals that deselect one or more of the control devices at each level. When one or more control devices at each level are deselected, a first group of the bit lines including the first bit line is charged to a first potential, and a second group of the bit lines including the second bit line is charged to a second potential.11-27-2008
20080273396Nonvolatile semiconductor memory device - A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.11-06-2008
20110205808SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened.08-25-2011
20090073773MEMORY CIRCUIT, DRIVE CIRCUIT FOR A MEMORY AND METHOD FOR WRITING WRITE DATA INTO A MEMORY - A first and second non-volatile memory transistor each have a floating gate electrode and a gate terminal. A first switch is connected between a first drain terminal and a bit line for reading out information, and a second switch is connected between a second drain terminal and the bit line. The first and second switch are designed to selectively couple the first or second drain terminal to the bit line during readout. A drive circuit is designed to write data into one of the transistors and to apply equal signals to the gate terminals of the first and second transistors based on the data, to apply a programming signal at a source terminal of the transistor to be written to and to drive a source terminal of a transistor not to be written to such that a state stored in the transistor not to be written to is not changed.03-19-2009
20090161439Nonvolatile Semiconductor Memory Device - According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.06-25-2009
20090135658Flash memory device and read method thereof - A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic.05-28-2009
20080316834BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE - A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.12-25-2008
20120069680NAND WITH BACK BIASED OPERATION - Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts03-22-2012
20120069679NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second signal is applied to a second cell. The driving unit applies a third signal to the gate electrodes of all the memory cells prior to the sequential reading. The third signal has a voltage smaller than the second signal and time duration equal to or more than that of a sum of time duration during which the first signal is applied to all the memory cells. In a period prior to the third signal application, the driving unit performs at least one of applying a fourth signal to the gate electrodes and matching a potential of the gate electrodes with that of the semiconductor layer.03-22-2012
20120069678NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR DRIVING THE SAME - A storage device according to one embodiment includes memory cells which are connected in series in a first direction and are arranged in a matrix by the arranged series connections, and word lines which connect control gates of the memory cells in a second direction perpendicular to the first direction, in which a first interval and a second interval wider than that are alternately repeated for intervals in the second direction between the memory cells. The storage device according to the embodiment comprises a drive unit for writing data in a first cell, then writing data in a second cell which is connected to the same word line as the first cell and is spaced at the first interval in the second direction, then reading the data in the second cell, and reading the data in the first cell with correction based on the read value of the second cell.03-22-2012
20110228611System and Method for Bit-Line Control - In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The bit-line driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor.09-22-2011
20110141821NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.06-16-2011
20090080265MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE - An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.03-26-2009
20090219762SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprise a second transistor including second gate insulation films and drive the control gate line and the source line with a boost voltage higher than the first driving voltage.09-03-2009
20090244983FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area is provided.10-01-2009
20090244981NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS WRITING METHOD - It is made possible to provide a non-volatile semiconductor memory device capable of improving the writing efficiency and its writing method. Predetermined voltages are respectively applied to a drain region and a control gate, and then the voltage applied to the control gate is opened.10-01-2009
20100157689SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells (06-24-2010
20090116292SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. The memory cell unit includes a plurality of memory cells connected in series. Each of the memory cells includes a charge accumulation layer and a control gate. The word lines are connected to the control gate. The driver circuit selects one of the word lines and applies voltages to a selected word line and unselected word lines. The voltage generator includes first and second charge pump circuits and outputs a voltage generated by the first and second charge pump circuits to the driver circuit. The first charge pump circuit is exclusively used to generate a voltage for a first word line. The first word line is one of the unselected word lines located adjacent to the selected word line.05-07-2009
20100157688PUSH-PULL MEMORY CELL CONFIGURED FOR SIMULTANEOUS PROGRAMMING OF N-CHANNEL AND P-CHANNEL NON-VOLATILE TRANSISTORS - A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0 v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive voltage wordlines any row in which programming of memory cells is to be performed; driving to a positive voltage the bitlines for any column in which programming of memory cells is to be inhibited; driving to a negative voltage the bitlines for any column in which programming of memory cells is to be performed; driving to one of 0 v and a negative voltage a center wordline for any row in which programming of memory cells is to be inhibited; and driving to one of 0 v and a positive voltage the center wordline for any row in which programming of memory cells is to be performed.06-24-2010
20110110163WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME - A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.05-12-2011
20090116293Memory and method for charging a word line thereof - A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.05-07-2009
20090273983NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - Disclosed is a programming method for a nonvolatile memory device. The method includes; charging word-line signal lines to a pass voltage during a pass voltage charge operation, simultaneously executing an initial precharge operation for strings including program-inhibited cells during the pass voltage charge operation, and applying the pass voltage to word lines from the word-line signal lines in response to a block-selection enabling signal11-05-2009
20080291740SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array, a row decoder which selects a word line, and applies a voltage to the selected word line, and a voltage generator which generates a boosted voltage, and outputs the boosted voltage as the voltage, the voltage generator includes a comparator which compares a first voltage with a second voltage, and outputs a comparison result signal, a constant current circuit which generates a first control signal in accordance with the comparison result signal, a first delay circuit which generates a second control signal by delaying the comparison result signal, and a charge pump circuit which generates the boosted voltage in response to the first and second control signals.11-27-2008
20100296345SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.11-25-2010
20100322011SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS HAVING CHARGE ACCUMULATION LAYER - According to one embodiment, a semiconductor memory device includes memory cells, a memory cell array, a word line, a bit line, a source line, a row decoder, a sense amplifier, and a first MOS transistor. The word line is connected to gates of the memory cells. The bit line is electrically connected to drains of the memory cells. The source line is electrically connected to sources of the memory cells. The row decoder selects the word line. The sense amplifier senses and amplifies data read onto the bit line in a read operation. The first MOS transistor is capable of connecting a well region where the memory cells are formed with the source line and is arranged between the row decoder or the sense amplifier and the memory cell array.12-23-2010
20110242904Read Only Memory and Operating Method Thereof - A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages.10-06-2011
20110116321SEMICONDUCTOR DEVICE FOR PREVENTING ERRONEOUS WRITE TO MEMORY CELL IN SWITCHING OPERATIONAL MODE BETWEEN NORMAL MODE AND STANDBY MODE - When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.05-19-2011
20100149877FLASH MEMORY DEVICE AND READ METHOD - A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address during a read operation, and a word line driver configured to receive data identifying the selected word line and the neighboring non-selected word line from the word line decoder, and applying a read voltage to the selected word line, a first voltage to non-selected word lines other than the neighboring non-selected word line, and a second voltage to the neighboring non-selected word line.06-17-2010
20110176370NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected to control gate electrodes of the plurality of memory cell transistors; and a word line driver which selects supplied voltages and supplies the selected voltages to second ends of the plurality of transfer MOS transistors. The nonvolatile semiconductor memory further comprises a voltage generation circuit which supplies voltages to the word line driver; and a control circuit which controls operation of the row decoder, the word line driver and the voltage generation circuit.07-21-2011
20100039865NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING THE SAME - A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.02-18-2010
20100135084WORDLINE VOLTAGE TRANSFER APPARATUS, SYSTEMS, AND METHODS - The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.06-03-2010
20110069558LOCAL WORD LINE DRIVER OF A MEMORY - A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor.03-24-2011
20110255346SUB VOLT FLASH MEMORY SYSTEM - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.10-20-2011
20120170377LOCAL WORD LINE DRIVER AND FLASH MEMORY ARRAY DEVICE THEREOF - In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.07-05-2012
20080266975NON-VOLATILE STORAGE WITH REDUCED POWER CONSUMPTION DURING READ OPERATIONS - A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.10-30-2008
20120243334FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the i09-27-2012
20080253196METHOD AND APPARATUS FOR CHARGING LARGE CAPACITANCES - A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a voltage representing the voltage on the capacitance and a multiplexer routes one of an external voltage or an operating voltage derived from said external voltage to charge the capacitance depending on the output of the comparator.10-16-2008
20080205161FLASH MEMORY DEVICE UTILIZING MULTI-PAGE PROGRAM METHOD - A flash memory device is configured to store multi-bit data on one cell utilizing fewer program operations. The flash memory device includes a memory cell, a sense amplifier and a write driver circuit. The sense amplifier is connected to a word line and a bit line. The sense amplifier and write driver circuit store data bits to be programmed on the memory cell. The sense amplifier and write driver circuit drives the bit line through a program voltage during a program execution period when at least one bit from among the data bits to be programmed is a program data bit, and performs a verify read operation when a program verify code representing a verify read period corresponds to a state of the data bits to be programmed.08-28-2008
20080205163NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.08-28-2008
20080205162Non-Volatile Memory Device and Driving Method Thereof - This patent relates to a non-volatile memory device and a driving method thereof The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate are electrically isolated from each other, and a plurality of word lines formed between the source select line and the drain select line.08-28-2008
20100214851System and Method for Bit-Line Control - In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor.08-26-2010
20100020618NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM - A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.01-28-2010
20100020617NONVOLATILE SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.01-28-2010
20110216603Non-Volatile Memory Device, Erasing Method Thereof, And Memory System Including The Same - Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.09-08-2011
20110063921Circuit Arrangement with a Column Latch and Method for Operating a Column Latch - In one embodiment, a circuit arrangement with a column latch has a first terminal (A03-17-2011
20120044772NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY - A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.02-23-2012
20120063235Memory Devices For Reducing Boosting Charge Leakage And Systems Including The Same - A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.03-15-2012
20120014185CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY - An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.01-19-2012
20100202215Methods for Programming Nonvolatile Memory Devices - Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.08-12-2010
20120026800SEMICONDUCTOR APPARATUS AND METHOD FOR TRANSFERRING CONTROL VOLTAGE - A semiconductor apparatus includes a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines, to second transmission lines in response to a select signal transmitted through a select signal transmission line; a select signal driving unit configured to drive the select signal to the select signal transmission line; and a voltage boosting control unit configured to float the select signal transmission line when a voltage level of the select signal transmission line increase to or above a target level.02-02-2012
20110090743Sub Volt Flash Memory System - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.04-21-2011
20110103154LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME - Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.05-05-2011
20110103153NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.05-05-2011
20120314505ROW DECODER AND NON-VOLATILE MEMORY DEVICE - A non-volatile memory device and a row decoder, the non-volatile memory device including: a memory cell array comprising a plurality of memory cells and each memory cell includes a first cell transistor and a second cell transistor; and a row decoder comprising a first driver and a second driver for generating first and second control signals. The first cell transistor is connected to the row decoder to receive the first control signal and the second cell transistor is connected to the row decoder to receive the second control signal. The first driver includes a first NMOS transistor and a first PMOS transistor formed adjacent to the first NMOS transistor. The second driver includes a second NMOS transistor and a second PMOS transistor formed adjacent to the second NMOS transistor. The first and second NMOS transistors are disposed between the first PMOS transistor and the second PMOS transistor.12-13-2012
20120075934ACCESS LINE MANAGEMENT IN A MEMORY DEVICE - Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.03-29-2012
20090027972WORDLINE DRIVER FOR A NON-VOLATILE MEMORY DEVICE, A NON-VOLATILE MEMORY DEVICE AND METHOD - A wordline driver, for a non-volatile memory device, comprises a wordline driver output, a first power source, adapted to provide an erase level voltage for erasing portions of the non-volatile memory device, a second power source, adapted to provide read and program level voltages for reading and programming portions of the non-volatile memory device and first switching means, including an isolation transistor, adapted to connect the wordline driver output to a one of the first and second power sources dependent upon an operating mode of the wordline driver. The wordline driver further comprises a programmable switch controller for providing a variable control signal to a control electrode of the isolation transistor. The programmable switch controller is arranged to set the variable control signal to a value dependent upon the operating parameters of the non-volatile memory device and such that the endurance of the isolation transistor is maximised.01-29-2009
20120327719THERMALLY ASSISTED FLASH MEMORY WITH SEGMENTED WORD LINES - A memory includes an array of memory cells including rows and columns including segmented word lines along the rows. The segments of the segmented word lines include local word lines. First and second switches are coupled to corresponding first and second ends of local word lines. The memory includes circuitry coupled to the first and second switches to connect bias voltages to the local word lines to induce current flow for thermal anneal. The circuitry includes pairs of global word lines along corresponding rows. The pairs of global word lines include first global word lines coupled to the first switches in the local word lines along the corresponding rows, and second global word lines coupled to the second switches in the local word lines along the corresponding rows. The memory includes bit lines along corresponding columns. Bit lines can comprise local bit lines coupled to global bit lines.12-27-2012
20100232232SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.09-16-2010
20100232233NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in which a negative-threshold cell read operation is performed by biasing a source line and well line to a positive voltage includes a first drive circuit that sets at least unselected word line in a floating state at a negative-threshold cell read time.09-16-2010
20080232173NON-VOLATILE MEMORY HAVING A ROW DRIVING CIRCUIT WITH SHARED LEVEL SHIFT CIRCUITS - Non-volatile memory includes a row driving circuit with shared level shift circuits, so as to minimize the chip area of the non-volatile memory. The row driving circuit includes a plurality of word line driving circuits, a plurality of level shift high circuits, and a plurality of level shift low circuits. The plurality of word line driving circuits share the plurality of level shift high circuits and the plurality of level shift low circuits. Each word line driving circuit includes a plurality of driving units, a level shift high circuit, and a level shift low circuit. The plurality of driving units share the level shift high circuit and the level shift low circuit of the word line driving circuit.09-25-2008
20130128673SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells storing data based on respective threshold voltages, having a positive threshold voltage in a data erased state, and includes respective control electrodes. Word lines are selectively electrically connected to the control electrodes of the memory cells, and charged to a potential before writing data to the memory cells. A voltage generator outputs a voltage at an output and includes a first path which discharges the output. A connection circuit is selectively electrically connected to the output of the voltage generator and a first word line, and selectively electrically connects the first word line to a first node which supplies a potential.05-23-2013
20080198663FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A flash memory device which comprises a memory cell array having memory cells arranged in rows and columns; a word line voltage generator circuit configured to generate a program voltage, a dielectric breakdown prevention voltage, and a pass voltage at a program operation; and a row selector circuit that receives the program voltage, the dielectric breakdown prevention voltage, and the pass voltage and selecting one of the rows in response to a row address. The dielectric breakdown prevention voltage is lower than the program voltage and higher than the pass voltage; and the row selector circuit drives the selected row with the program voltage, drives at least one row just adjacent to, or neighboring, the selected row with the dielectric breakdown prevention voltage and drives remaining rows with the pass voltage.08-21-2008
20130148435NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.06-13-2013
20120275234NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS AND COMPUTING SYSTEMS - A nonvolatile memory device configured to apply a wordline erase voltage to a plurality of wordlines connected to a plurality of memory cells, apply an erase voltage to a substrate where a memory cell string is formed while applying a specific voltage to at least one ground selection line connected to at least one ground selection transistor, and float the at least one ground selection line when a target voltage of the substrate reaches a target voltage.11-01-2012
20100315881NON-VOLATILE MEMORY DEVICE AND METHOD OF READING DATA IN A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a row decoder and a memory cell array. The row decoder generates a read voltage, and first, second and third drive voltages. The memory cell array includes a selected word line receiving the read voltage, a first neighboring word line of the selected word line receiving the second word line drive voltage, a second neighboring word line of the selected word line receiving the third word line drive voltage, and a non-neighboring word line of the selected word line receiving the first word line drive voltage.12-16-2010
20120281482WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME - A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.11-08-2012
20120281481THERMALLY ASSISTED DIELECTRIC CHARGE TRAPPING FLASH - A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function.11-08-2012
20110310674System and Method for Bit-Line Control - In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor.12-22-2011
20130208545SEMICONDUCTOR MEMORY APPARATUS, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME - A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cells each coupled between a word line and a bit line; and a controller configured to set a word line voltage and a bit line voltage at the same time, in response to a program command.08-15-2013

Patent applications in class Drive circuitry (e.g., word line driver)