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Sensing circuitry (e.g., current mirror)

Subclass of:

365 - Static information storage and retrieval

365185010 - FLOATING GATE

365185180 - Particular biasing

365185200 - Reference signal (e.g., dummy cell)

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DocumentTitleDate
20090196104MEMORY AND METHOD OPERATING THE MEMORY - A memory comprises a memory array, a sense unit, and a biasing and shielding circuit. The biasing and shielding circuit is coupled to the memory array and the sense unit, wherein the biasing and shielding circuit comprises a first transistor, a second transistor, and a capacitor. The first transistor has a gate coupled to a biasing voltage and a first terminal coupled to the sense unit. The second transistor has a gate coupled to the biasing voltage and a first terminal coupled to a first potential. The capacitor is coupled to the sense unit and the first transistor.08-06-2009
20130135939NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.05-30-2013
20100046302Complementary Reference method for high reliability trap-type non-volatile memory - Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.02-25-2010
20130083607METHOD OF READING MEMORY CELLS WITH DIFFERENT THRESHOLD VOLTAGES WITHOUT VARIATION OF WORD LINE VOLTAGE AND NONVOLATILE MEMORY DEVICE USING THE SAME - A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells.04-04-2013
20090154249SENSE AMPLIFIER FOR LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS - A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.06-18-2009
20100329025NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have the same characteristics; and a reference current source that generates, as a reference current for determining the logic level of the readout target memory cell, a current obtained by adding one constant current, out of a first constant current flowing through the first constant current source or a second constant current flowing through the second constant current source, with a reference memory cell current flowing in the reference memory cell, and by subtracting the other constant current, out of the first constant current or the second constant current, from the added current.12-30-2010
20120182810METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES - The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.07-19-2012
20130051154Method for and Flash Memory Device Having Improved Read Performance - A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.02-28-2013
20090303798MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.12-10-2009
20090040834SEMICONDUCTOR MEMORY DEVICE - A memory cell array forms a plurality of control areas in a direction orthogonal to the direction of extension of a bit line. A sense amplifier initially charges a bit line in each control area in the memory cell array with a charging voltage controlled by a respective individual bit-line control signal. Bit-line control signal generator circuits are provided plural in accordance with the control areas in the memory cell array. Each bit-line control signal generator circuit receives the potential on a cell source line in a corresponding control area, individually generates and provides the bit-line control signal in the each control area in accordance with the received voltage on the cell source line in each control area.02-12-2009
20100085813METHOD OF DRIVING A SEMICONDUCTOR MEMORY DEVICE AND A SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a driving method of a memory having cells of floating body type which comprises executing, during a write operation, a first cycle of applying a first potential to the bit lines corresponding to the first selected cells and of applying a second potential to the selected word line to write first data; executing, during the write operation, a second cycle of applying a third potential to the bit lines corresponding to a second selected cell among the first selected memory cells and of applying a fourth potential to the selected word line to write second data, wherein the second potential is a potential biased to a reversed side against the polarity of the carriers with reference to potentials of the source and the first potential, and the fourth potential is a biased to same polarity as the polarity of the carriers with reference to the potentials of the source and the third potential.04-08-2010
20130058169NON-VOLATILE MEMORY SYSTEMS - In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.03-07-2013
20090296489Non-Volatile Memory With Improved Sensing By Reducing Source Line Current - One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.12-03-2009
20090067253Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations - Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.03-12-2009
20130064016SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.03-14-2013
20090231926ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.09-17-2009
20090231925READ REFERENCE TECHNIQUE WITH CURRENT DEGRADATION PROTECTION - A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.09-17-2009
20090021987Analog sensing of memory cells in a solid state memory device - A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.01-22-2009
20090010069SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR DEVICE - The present invention is directed to a semiconductor device having a non-volatile memory cell 01-08-2009
20120236655Reference Voltage Optimization for Flash Memory - A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.09-20-2012
20130163342PROGRAM TEMPERATURE DEPENDENT READ - Methods and non-volatile storage systems are provided for using compensation that depends on the temperature at which the memory cells were programmed. Note that the read level compensation may have a component that is not dependent on the memory cells' Tco. That is, the component is not necessarily based on the temperature dependence of the Vth of the memory cells. The compensation may have a component that is dependent on the difference in width of individual Vth distributions of the different states across different temperatures of program verify. This compensation may be used for both verify and read, although a different amount of compensation may be used during read than during verify.06-27-2013
20130163343SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.06-27-2013
20100014356SENSE AMPLIFIER USED IN ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND THE IMPLEMENTING METHOD THEREOF - The present invention discloses a sense amplifier used in an Electrically Erasable Programmable Read-only Memory; the sense amplifier includes a reference current generation circuit, which is used for providing a reference current with a settable temperature coefficient for a main circuit of the sense amplifier; the sense amplifier further includes the main circuit, which is used for comparing the reference current with a storage cell current, and distinguishing between 0 Storage Cell and 1 Storage Cell. The present invention further discloses a method of implementing the sense amplifier that is as below: With an additional current reference circuit, generating the reference current with a positive/negative/zero temperature coefficient to be inputted into the main circuit, by mixing a proportional absolute temperature current and a constant current according to different ratios; and providing a storage cell selection tube in a mirror branch of a biased current of the main circuit, so as to constitute a source degeneration circuit, thus making the biased current change with the power supply voltage and the process as well as realizing a gain compensation function. The sense amplifier of the present invention can automatically compensate the process, the power supply voltage and temperature, and possesses the dynamic high speed property.01-21-2010
20110280084DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.11-17-2011
20090034338SYSTEM AND METHOD FOR READING MEMORY - One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.02-05-2009
20100182843CURRENT SENSING FOR FLASH - A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing process that places a current source to provide current to the bit line. The voltage level of the bit line is then set by the current provided by the current source and the current sunk from the bit line through the selected memory cell to the source line, which is dependent on the threshold voltage of its programmed or erased state. If the selected memory cell is erased, current flows through the memory cell to the source line and the bit line voltage falls. If the selected memory cell is programmed, little or no current flows through the cell, and the bit line voltage rises and is sensed by the sense amplifier.07-22-2010
20110286281REFERENCE CURRENT GENERATOR USED FOR PROGRAMMING AND ERASING OF NON-VOLATILE MEMORY - A reference current generator used for programming and erasing of the non-volatile memory. Wherein, a self-biasing reference generator is used to generate a first reference voltage of a negative temperature coefficient and a second reference voltage of a positive temperature coefficient. A voltage converter receives said first reference voltage and generate a third reference voltage having its temperature coefficient less than that of said first reference voltage, and said second reference voltage and said third reference voltage are input to a reference current source, such that said reference current source generates a reference current of low temperature sensitivity. Through said reference current source, said second reference voltage and said third reference voltage are used to compensate said negative temperature coefficient of a threshold voltage of a transistor, thus reducing difference of times required for programming and erasure under various operation temperatures.11-24-2011
20110299340Non-Volatile Memory Having 3d Array of Read/Write Elements and Read/Write Circuits and Method Thereof - A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.12-08-2011
20130215681CURRENT SENSING FOR FLASH - Sense amplifiers and memory devices include a current source coupled to a bit line connection, a sensing transistor having a control gate coupled to the bit line connection, and a data latch coupled to a source/drain region of the sensing transistor. The sensing transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier and/or the current source comprises a transistor having a channel length greater than one and a half times the channel length of a conventional transistor of the semiconductor manufacturing process utilized to form the sense amplifier08-22-2013
20110292735NONVOLATILE MEMORY DEVICE WITH REDUCED CURRENT CONSUMPTION - A nonvolatile memory device includes one or more reference cell transistors, one or more memory cell transistors, and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and another field effect transistor, currents flowing through the two or more field effect transistors being combined to flow through the one or more reference cell transistors, and another field effect transistor having a drain thereof connected to one of the one or more memory cell transistors.12-01-2011
20110292736SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor memory device includes a plurality of memory cells in which data can be rewritable, a plurality of bit lines connected to the plurality of memory cells, and a plurality of sense circuits that are connected to the plurality of bit lines, respectively, sense data written in the memory cells to perform a verify operation with the bit lines charged to first potentials, and charge a bit line, which is connected to a memory cell determined to be defective as a result of the verify operation, to the first potential in the verify operation.12-01-2011
20090168540Low Noise Sense Amplifier Array and Method for Nonvolatile Memory - In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.07-02-2009
20080273394SYMMETRIC DIFFERENTIAL CURRENT SENSE AMPLIFIER - A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.11-06-2008
20090190407SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device, which realizes characteristic evaluation even in a case where a threshold voltage is a negative potential by a test method which is similar to a case of a positive potential. The semiconductor memory device includes a plurality of memory cells for storing data. When a test signal is input, the semiconductor memory device changes from a normal mode to a test mode for evaluating characteristics of the plurality of memory cells. The semiconductor memory device also includes: a memory cell selecting portion for selecting a memory cell; a constant voltage portion for generating a reference voltage; a constant current portion for generating a reference current; an X switch voltage switching control circuit for supplying one of an X selection signal and a voltage signal input from an external terminal to a gate of the memory cell; a Y switch portion for supplying the reference current to a drain of the memory cell selected by a Y selection signal; a comparator for detecting whether or not a drain voltage that is a voltage of the drain has exceeded the reference voltage; and a decision level changing portion for adjusting a current value of the reference current and a voltage value of the reference voltage so as to change a decision level of the comparator based on a control signal in the test mode.07-30-2009
20090147586Non-Volatile Memory and Method With Improved Sensing Having Bit-Line Lockout Control - In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.06-11-2009
20080266974NON-VOLATILE MEMORY HAVING A STATIC VERIFY-READ OUTPUT DATA PATH - A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.10-30-2008
20100124125NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.05-20-2010
20110261625Low Noise Sense Amplifier Array and Method for Nonvolatile Memory - In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.10-27-2011
20110267892SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string.11-03-2011
20120106258READOUT CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - A readout circuit has a sense amplifier to compare a cell current which changes according to whether a memory cell is on or off with a reference current, to output a comparison signal of a first logic upon detecting that the cell current is smaller than the reference current, and to output a comparison signal of a second logic upon detecting that the cell current is greater than the reference current, the readout circuit outputting a data output signal depending upon an output of the sense amplifier. The reference current is set to be greater than a middle value between a first cell current which flows when the memory cell is in an off-state and a second cell current which flows when the memory cell is in an on-state and which is greater than the first cell current, and to be smaller than the second cell current. Unless the sense amplifier detects that the cell current is smaller than the reference current as a result of comparison made between the cell current and the reference current, the sense amplifier outputs the comparison signal of the second logic regardless of whether the sense amplifier detects that the cell current is greater than the reference current.05-03-2012
20090103369Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.04-23-2009
20090103368SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.04-23-2009
20090296488High Speed Sense Amplifier Array and Method for Nonvolatile Memory - Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.12-03-2009
20090296487INCREASING READ THROUGHPUT IN NON-VOLATILE MEMORY - Read throughput is increased in a non-volatile memory device by sensing storage elements which are of interest as soon as a word line voltage has propagated to them, but before the word line voltage has propagated to other storage elements which are not of interest. The delay which would be incurred by waiting for the voltage to propagate along the entire word line is avoided. The sensing can occur during programming, as a verify operation, or after programming, as where user data is read. Further, the storage elements may be sensed concurrently, e.g., via sense amplifiers. Data from the storage elements of interest is processed and data from the other storage elements is discarded. A time for sensing the storage elements of interest can be set by identifying which storage elements are being verified or include data which is requested by a read command.12-03-2009
20080239825FLOATING GATE MEMORY DEVICE WITH IMPROVED REFERENCE CURRENT GENERATION - A non-volatile semiconductor memory device is provided with: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of the first memory cell; a second bitline connected to a diffusion layer which is used as a drain of the first memory cell; a first reference cell including a floating gate transistor; a third bitline electrically isolated from the first bitline and connected to a diffusion layer which is used as a source of the first reference cell; a read circuit identifying data stored in the first memory cell in response to a memory cell signal received from the first memory cell through the second bitline and a reference signal received from the first reference cell through the fourth bitline; and a bitline level controller controlling a voltage level of the third bitline.10-02-2008
20090003076MEMORY DEVICE AND READING METHOD - A memory device according to an embodiment of the present invention, comprises a common source line current detection unit for detecting current in a common source line of a memory cell array and outputting a control signal; and a control unit for controlling an evaluation time for reading data of a page buffer coupled to the memory cell array according to the control signal output from the common source line current detection unit.01-01-2009
20110205804High Speed Sense Amplifier Array and Method for Non-Volatile Memory - Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.08-25-2011
20080304325NON-VOLATILE MEMORY WITH IMPROVED SENSING HAVING BIT-LINE LOCKOUT CONTROL - In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.12-11-2008
20080310235SENSING CIRCUIT FOR MEMORIES - A memory apparatus includes a plurality of memory units, a sensing circuit and a bias-generating circuit. The plurality of memory units respectively outputs a data current to the sensing circuit, while the sensing circuit further includes a plurality of first transistors, a plurality of second transistors and a plurality of sensing amplifiers. In order to speed up the access time of the memory units, the bias-generating circuit rapidly provides a bias signal to the sensing circuit to turn on the first transistors of the sensing circuit. In the present invention, the sensing circuit uses a common reference voltage to reduce the circuit utilization area of the memory apparatus.12-18-2008
20110188316SEMICONDUCTOR MEMORY DEVICE - This invention offers a semiconductor memory device, with which a resolution to read-out data is not reduced even at the time of verify and a stable read-out operation is possible even when a power supply voltage is reduced. A read-out circuit is provided with a current-voltage conversion circuit, that converts a cell current into a data voltage, and a sense amplifier that compares the data voltage with a reference voltage. The current-voltage conversion circuit is formed to include a variable load resistor that is connected to the memory cell through a bit line. The variable load resistor is formed to include P channel type MOS transistors that make load resistors and P channel type MOS transistors that constitute a switching circuit.08-04-2011
20090129169METHOD AND APPARATUS FOR READING DATA FROM FLASH MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).05-21-2009
20120069676SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.03-22-2012
20090097324NON-VOLATILE MEMORY DEVICE AND A PROGRAMMABLE VOLTAGE REFERENCE FOR A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a voltage reference generator comprising a programmable voltage reference for generating a voltage signal having a programmable voltage level. In an embodiment, the programmable voltage reference provides the voltage signals for a wordline driver and/or a bitline current generator of the non-volatile memory device. The programmable voltage reference may comprise a Digital-to-Analog converter coupled between first and second supply voltages. A programmable current reference is also disclosed.04-16-2009
20090097323BITLINE CURRENT GENERATOR FOR A NON-VOLATILE MEMORY ARRAY AND A NON-VOLATILE MEMORY ARRAY - A bitline current generator, for a non-volatile memory array which comprises a plurality of memory bitcells and bitlines, comprises a switching means for each bitline for coupling a bitline to a program voltage supply when the bitline is selected for programming and a variable current source for providing a programming current to said selected bitlines. The variable current source is adapted to select a level of said programming current such that the programming of the selected memory bitcells does not disturb the programmed state of the unselected memory bitcells on unselected bitlines.04-16-2009
20090244978SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.10-01-2009
20100054042SEMICONDUCTOR MEMORY DEVICE AND METHOD OF INSPECTING THE SAME - A semiconductor memory device comprises a sense amplifier circuit having a first and a second input terminal, the sense amplifier configured to compare current flowing in the first input terminal with current flowing in the second input terminal, and the sense amplifier configured to provide the result to external; a first gate circuit connected to the first input terminal, the first gate circuit configured to pass a cell current flowing in a memory cell to the first input terminal; a reference current source, the reference current source configured to feed a reference current to the second input terminal, the reference current serving as the reference for level sensing the cell current; a second gate circuit connected to the second input terminal, the second gate circuit including a replica circuit of the first gate circuit; a first current source configured to feed a first current to the first input terminal, the first current corresponding to the offset at the time of read from a first-state cell; and a second current source configured to feed a second current to the second input terminal, the second current corresponding to the offset at the time of read from a second-state cell.03-04-2010
20090290425SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefore, the semiconductor device including a first current-voltage conversion circuit (11-26-2009
20100188902Differential, level-shifted EEPROM structures - Memory embodiments are provided to operate in memory systems which are configured to have a system ground and a system substrate that are biased at different voltages. At least one of these embodiments includes a memory cell and write and read circuits in which the memory cell is coupled to the system substrate and the write and read circuits are coupled to the system ground. The memory cell preferably has a cross-coupled pair of transistors which can be set in first and second states. The write circuit is arranged and level shifted to drive the cross-coupled pair into either selected one of the states and the read circuit is arranged and level shifted to provide a data signal indicative of the selected state.07-29-2010
20100182841NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a data latch unit configured to store data to be programmed into a memory cell or store data read from a memory cell, and page buffers each comprising a sense node discharge unit configured to selectively ground a sense node depending on data stored in the data latch unit and in response to a sense node discharge signal.07-22-2010
20100182842Sense Amplifier and Data Sensing Method Thereof - A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage.07-22-2010
20100226181Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System - A non-volatile memory device comprises an array of non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection to a low voltage source. The array has a first side adjacent to a first column of memory cells, and a second side opposite the first side, a third side adjacent to a first row of memory cells, and a fourth side opposite the third side. The memory device further comprises a plurality of columns of reference memory cells embedded in the memory array, with a plurality of reference cells in each row of the array of non-volatile memory cells, substantially evenly spaced apart from one another. Each of the reference memory cells is substantially the same as the non-volatile memory cells, and has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source and a low voltage terminal for connection to a low voltage source. A high voltage decoder is positioned on the first side, and has a plurality of high voltage lines, with each high voltage line connected to the high voltage terminal of the memory cells and reference cells in the same row. A low voltage row decoder is positioned on the second side, and has a plurality of low voltage lines, with each low voltage line connected to the low voltage terminal of the memory cells and reference cells in the same row. A plurality of sense amplifiers are positioned on the third side, with each sense amplifier connected to the bit terminal of one column of non-volatile memory cells and to the bit terminal of a column of reference memory cells. This invention also includes N-of-M selective reference scheme, distributed source line pull down, source line resistance strap compensation, replica-data-pattern current consumption, data current compensation, and bit line voltage error compensation.09-09-2010
20110110162STRUCTURES AND METHODS FOR READING OUT NON-VOLATILE MEMORIES - Non-differential sense amplifier circuitry for reading out Non-Volatile Memories (NVMs) and its operating methods are disclosed. Such non-differential amplifier circuitry requires exceptionally low power and achieves moderate sensing speed, as compared to a conventional sensing scheme.05-12-2011
20100214848NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a first node, a current source configured to have a current value determined according to a voltage supplied to the first node, and a memory cell string coupled to the first node, the memory cell string including at least one memory cell. Whether a memory cell included in the memory cell string has been programmed is determined based on the voltage supplied to the first node.08-26-2010
20100238736Semiconductor storage device - 1. A semiconductor storage device has a first MOS transistor connected at a first end thereof to a power supply and diode-connected; a second MOS transistor connected in parallel with the first MOS transistor; a memory cell connected between the second end of the first MOS transistor and ground, the memory cell capable of adjusting a current flowing through the memory cell; a third MOS transistor connected at a first end thereof to the power supply, and diode-connected; a fourth MOS transistor connected in parallel with the third MOS transistor; a fifth MOS transistor connected between the second end of the fourth MOS transistor and the ground and supplied at a gate thereof with the first reference voltage; and an amplifier circuit which compares the sense voltage with the comparison voltage, and which outputs a comparison result signal depending upon a result of the comparison.09-23-2010
20110058425Integrated Flash Memory Systems And Methods For Load Compensation - Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.03-10-2011
20100254194MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - The invention provides a method for reading a first data storage of a memory cell. The method comprises sensing a first current of the memory cell by applying a first bit line voltage on the memory cell. When the first current is larger than a first reference current with respect to the first bit line voltage, the first data storage is determined to be at an un-programmed state. Otherwise, a second current of the memory cell is sensed by applying a second bit line voltage on the memory cell. When the difference between the first current and the second current is larger than the difference between the first reference current and the second reference current, the first data storage is determined to be at the un-programmed state. Otherwise, the first data storage is determined to be at a programmed state10-07-2010
20090040835SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line, and a sense amplifier of the current sense type. The sense amplifier includes an initial charging circuit capable of initially charging the bit line with a suppressed value of current only for a certain starting period during an initial charging period. The sense amplifier detects a value of current flowing in the bit line to decide data read out of each of the memory cells.02-12-2009
20100302863Reading Method for MLC Memory and Reading Circuit Using the Same - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.12-02-2010
20130141983SYSTEM AND METHOD TO ENABLE READING FROM NON-VOLATILE MEMORY DEVICES - A system and method to enable reading from non-volatile memory (NVM) devices is described. In one embodiment, the method includes setting a sensing parameter used to read data stored in a NVM device, reading from pluralities of locations of the NVM device with the sensing parameter set at the first value. The locations of the NVM device store an identical value. The method also includes verifying whether the identical value is read correctly from the locations of the NVM device. The method also includes setting the sensing parameter to a second value when the identical value is not read correctly with the sensing parameter set at the first value. The method further includes determining a third value for the sensing parameter from the identical value and setting the sensing parameter to the third value when the identical value is read correctly.06-06-2013
20110019485Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.01-27-2011
20110044114APPARATUS AND METHOD FOR BIT LINES DISCHARGING AND SENSING - Some embodiments include first bit lines coupled to a first junction bus and second bit lines coupled to a second junction bus. Such embodiments can also include a first network to discharge at least one of the first bit lines through the first junction bus and to discharge at least one of the second bit lines through the second junction bus. Such embodiments can further include a second network to couple a sense amplifier to at least one of the first junction bus and the second junction bus. Other embodiments are described.02-24-2011
20110116320VOLTAGE GENERATOR TO COMPENSATE SENSE AMPLIFIER TRIP POINT OVER TEMPERATURE IN NON-VOLATILE MEMORY - In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.05-19-2011
20100220529NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a sensing circuit that is configured to detect a charge of a common source line and a voltage controller that is configured to vary a level of a voltage being inputted to a word line in response to a result of the detection of the sensing circuit.09-02-2010
20110085383CURRENT SINK SYSTEM FOR SOURCE SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.04-14-2011
20110085384CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.04-14-2011
20100135083NONVOLATILE MEMORY DEVICE - A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed. The memory device comprising: a first current detecting circuit comprising a first transistor of a first conductive type coupled in a diode configuration, wherein current flows according to a reference cell through the first transistor; a second current detecting circuit comprising a second transistor of the first conductive type coupled in a diode configuration, wherein current flows according to a selected memory cell through the second transistor; a bias circuit comprising a third transistor of the first conductive type that is coupled to the first transistor by a current mirror configuration; and a differential amplifying circuit comprising a fourth transistor of the first conductive type which is coupled to the second transistor, wherein the differential amplifying circuit outputs a signal corresponding to a difference between current flowing through the third transistor and current flowing through the fourth transistor; and wherein the first transistor, the second transistor, the third transistor and the fourth transistor are comprised of one predetermined sized unit transistor element of the first conductive type, or are comprised of parallel couplings of predetermined sized unit transistor elements of the first conductive type06-03-2010
20110249508NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a memory string, a bit line, a sense simplifier, a first MOS, a first charging-circuit, a second-charging circuit, and a controller. The memory string includes memory cells. The bit line is connected to the memory cell. The sense amplifier applies a voltage to the bit line. The first MOS is electrically connected between the sense amplifier and bit line. The first charging circuit has a first current supply capacity and transfers a first current. The second charging-circuit has a second current supply capacity. The controller controls a first timing to switch from the first current to the second current.10-13-2011
20090027971Apparatuses, computer program products and methods for reading data from memory cells - In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the received voltage value. The at least one first voltage range includes a first upper limit voltage value and a first lower limit voltage value. A data value of the memory cell is set as a first data value when the received voltage value is within the specific voltage range.01-29-2009
20110069555NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.03-24-2011
20090003077NON-VOLATILE MEMORY DEVICE - A non-volatile memory device for adjusting level of a verifying voltage supplied to a word line in accordance with occurrence of a source line bouncing phenomenon is disclosed. The non-volatile memory device includes a bouncing sensing circuit configured to compare a source line current passing through a common source line with a reference current, and output a bouncing sensing signal in accordance with the comparing result, and a word line voltage controller configured to provide a verifying voltage increased by a certain level to a word line in accordance with level of the bouncing sensing signal.01-01-2009
20080247238METHOD FOR SENSING NEGATIVE THRESHOLD VOLTAGES IN NON-VOLATILE STORAGE USING CURRENT SENSING - Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.10-09-2008
20080285354Self reference sensing system and method - A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication.11-20-2008
20080273393Programmable Heavy-Ion Sensing Device for Accelerated Dram Soft Error Detection - Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.11-06-2008
20080266973REDUCING POWER CONSUMPTION DURING READ OPERATIONS IN NON-VOLATILE STORAGE - Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.10-30-2008
20120243327NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.09-27-2012
20120243325SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to one embodiment includes: a memory cell array including electrically-rewritable memory cells; bit lines each connected to one end of the memory cells and charged in response to a certain operation; and a voltage generating circuit configured to control a charging operation on the bit lines. The voltage generating circuit includes: a regulator configured to regulate voltages of a first node and a second node; and a clamp transistor connected at its one end to a bit line and connected at its gate to the first node. The regulator includes a first transistor diode-connected between the first node and the second node to form a current path therebetween and configured to let flow therethrough an output current variable according to an output signal of the regulator. The first transistor and the clamp transistor have approximately equal threshold voltages.09-27-2012
20080253195SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA READOUT METHOD THEREOF - A semiconductor memory device includes first and second memory cells and a sense amplifier. The first memory cell includes a MOS transistor and is capable of retaining n-bit (n is a natural number more than one) first data. The MOS transistor includes a charge accumulation layer and a control gate. The second memory cell retains second data. The second data is a criterion for the first data. The sense amplifier determines the first data read out from the first memory cell and amplifies the first data using a first reference level and a second reference level. The first reference level is obtained based on the second data read out from the second memory cell. The second reference level is generated inside based on the first reference level.10-16-2008
20100309726REFERENCE VOLTAGE OPTIMIZATION FOR FLASH MEMORY - A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.12-09-2010
20080205158READING METHOD AND CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE BASED ON THE ADAPTIVE GENERATION OF A REFERENCE ELECTRICAL QUANTITY - A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a determination stage, which compares an array electrical quantity, correlated to a current flowing in the array memory cell, with a reference electrical quantity, and supplies an output signal indicative of the datum, based on the comparison; and a generator circuit, provided with an input receiving a target electrical quantity correlated to a current flowing in use in the reference memory cell, and an output, which supplies the reference electrical quantity with a controlled value close or equal to that of the target electrical quantity. The generator circuit is provided with a variable generator, and a control unit connected to, and designed to control, the variable generator so that it will generate the controlled value of the reference electrical quantity.08-28-2008
20110069554SENSE-AMPLIFIER CIRCUIT FOR NON-VOLATILE MEMORIES THAT OPERATES AT LOW SUPPLY VOLTAGES - A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.03-24-2011
20100329026SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER - According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.12-30-2010
20100329024MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS - A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.12-30-2010
20110080790Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System - An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.04-07-2011
20100165744SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.07-01-2010
20100165743Non-Volatile Memory And Method With Continuous Scanning Time-Domain Sensing - A page of non-volatile multi-level memory cells on a word line is sensed in parallel by sense amps via bit lines. A predetermined input sensing voltage as an increasing function of time applied to the word line allows scanning of the entire range of thresholds of the memory cell in one sweep. Sensing of the thresholds of individual cells is then reduced to a time-domain sensing by noting the times the individual cells become conducting. Each conducting time, adjusted for delays in the word line and the bit line, can be used to derive the sensing voltage level that developed at the word line local to the cell when the cell became conducting. The locally developed sensing voltage level yields the threshold of the cell. This time-domain sensing is relative insensitive to the number of levels of a multi-level memory and therefore resolve many levels rapidly in one sweep.07-01-2010
20100067308Sub Volt Flash Memory System - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.03-18-2010
20100195402PAGE BUFFER CIRCUIT - A page buffer circuit comprises a first sensing unit configured to sense a voltage of a bit line and change a voltage of a first sense node, a data conversion unit configured to sense a voltage level of the first sense node and change a voltage level of a second sense node or to couple the second sense node and the first sense node, and first and second latch units coupled in common to the second sense node.08-05-2010
20090175086ENABLE SIGNAL GENERATOR METHOD AND APPARATUS - According to the embodiments described herein, an enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.07-09-2009
20100027349 CURRENT SENSING SCHEME FOR NON-VOLATILE MEMORY - A current sensing scheme for non-volatile memory is disclosed comprising an apparatus for determining one or more memory cell states in a non-volatile memory device. The apparatus having a first memory cell coupled to a first bitline and a first sensing element coupled to the first bitline, the first sensing element operable to sense a voltage corresponding to a state of the memory cell wherein the sensed voltage is independent of a bitline voltage discharge over time of the first memory cell.02-04-2010
20110216601CURRENT SINK SYSTEM BASED ON SAMPLE AND HOLD FOR SOURCE SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and the sink current during the second time interval.09-08-2011
20110051522METHOD OF PROGRAMMING FLASH MEMORY OF THE DIFFERENTIAL CELL STRUCTURES FOR BETTER ENDURANCE - A method of programming a differential flash memory cell having a first and a second memory cell is disclosed. The first memory cell includes a first transistor associated with a first threshold voltage and the second memory cell includes a second transistor associated with a second threshold voltage. The method includes reading the first and second memory cells to determine a current associated with the first and second threshold voltages. The first threshold voltage is equal to a first value and the second threshold voltage is equal to a second value. The method further includes determining if the first current corresponds to a predetermined logic state. If the current does not correspond to the predetermined logic state, the first and second memory cells are programmed. The programming includes changing the first threshold voltage from the first value to a third value and the second threshold voltage from the second value to a fourth value.03-03-2011
20090141558Sensing memory cells - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.06-04-2009
20120099379SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF OPERATING THE SAME - A semiconductor memory apparatus includes a memory block including memory strings having respective channel layers coupled between respective bit lines and a source line, an operation circuit group configured to supply hot holes to the channel layers and to perform an erase operation on memory cells of the memory strings, an erase operation determination circuit configured to generate a block erase enable signal when hot holes of at least a target number are supplied to a first channel layer of the channel layers, and a control circuit configured to perform the erase operation in response to the block erase enable signal.04-26-2012
20110063920SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.03-17-2011
20110157996NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.06-30-2011
20080310236Subtraction circuits and digital-to-analog converters for semiconductor devices - A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes an adder with first and second inputs and an output. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the adder, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the adder.12-18-2008
20120206974SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.08-16-2012
20120206973Digital Method to Obtain the I-V Curves of NVM Bitcells - A calibration table (08-16-2012
20120026799NON-VOLATILE MEMORY DEVICE HAVING REFERENCE CELLS, AND RELATED METHOD OF SETTING REFERENCE CURRENT - A method of setting a reference current of a nonvolatile memory device comprises measuring a noise characteristic of each of multiple reference cells, and selecting at least one of the reference cells as a reference cell for generating a reference current according to the measured noise characteristics.02-02-2012
20090135657SEMICONDUCTOR MEMORY - A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.05-28-2009
20120155185MEMORY DEVICE AND CORRESPONDING READING METHOD - An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.06-21-2012
20100172187ROBUST SENSING CIRCUIT AND METHOD - A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches that are coupled to the sensing device and to a target element. The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.07-08-2010
20110103152SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.05-05-2011
20100290290NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.11-18-2010
20100290291SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (11-18-2010
20100208525NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a sense amplifier, first and second bit lines that are connected to the sense amplifier, a first memory cell column that is connected to the first bit line, the first memory cell column being formed by a plurality of MONOS type transistors, a first constant current source that is connected to the second bit line, the first constant current source generating a reference current for the first memory cell column, and a first switch that is provided between the first constant current source and the second bit line, the first switch being formed by a MONOS type transistor.08-19-2010
20090059673Method of Operating an Integrated Circuit for Reading the Logical State of a Memory Cell - In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.03-05-2009
20090059672SELF-TIMED INTEGRATING DIFFERENTIAL CURRENT SENSE AMPLIFIER - A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. Integration continues until a desired voltage or time is reached, resulting in a sufficiently reliable output. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.03-05-2009
20120213008NONVOLATILE MEMORY DEVICE AND PROGRAM VERIFY METHOD THEREOF - A program verify method of the nonvolatile memory device includes supplying a first program verify voltage to a word line coupled to memory cells of a memory cell array, sensing a voltage of a bit line coupled to the memory cells in response to a first sense signal, supplying a second program verify voltage higher than the first program verify voltage to the word line, and sensing a voltage of the bit line in response to a second sense signal having a lower voltage level than the first sense signal.08-23-2012
20100008148Low Noise Sense Amplifier Array and Method for Nonvolatile Memory - In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.01-14-2010
20120262993SENSING SCHEME IN A MEMORY DEVICE - Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.10-18-2012
20100329023SENSE AMPLIFIER APPARATUS AND METHODS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed.12-30-2010
20080298132Sense transistor protection for memory programming - A method and apparatus for protecting a sense transistor in a sense amplifier during memory programming and erase operations, and for increasing the coupling efficiency of the memory device during the programming and erase operations.12-04-2008
20120327717HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.12-27-2012
20110019484Non-Volatile Memory and Method With Improved Sensing Having Bit-Line Lockout Control - In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.01-27-2011
20110235430MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.09-29-2011
20100232229SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell, a bit line, a source line, a source line driver, a sense amplifier, a counter, a detector, a controller. The sense amplifier reads the data by sensing current flowing through the bit line. The counter counts ON memory cells and/or OFF memory cells. The detector detects whether the voltage of the source line has exceeded a reference voltage. The controller controls the number of times of data sensing by the sense amplifier in accordance with the detection result in the detector, and controls a driving force of the source line driver in accordance with the count in the counter.09-16-2010
20100008147SENSING CIRCUIT FOR FLASH MEMORY DEVICE OPERATING AT LOW POWER SUPPLY VOLTAGE - A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a second load element, a second inverting circuit, and a sense amplifier. The first load element includes an end connected with a bit line of a main cell array within the flash memory device. The first inverting circuit includes an input terminal connected with the bit line of the main cell array and an output terminal connected with another end of the first load element. The second load element includes an end connected with a bit line of a reference cell array within the flash memory device. The second inverting circuit includes an input terminal connected with the bit line of the reference cell array and an output terminal connected with another end of the second load element. The sense amplifier compares a voltage of the bit line of the main cell array with a voltage of the bit line of the reference cell array and generates an output signal according to a result of the comparison.01-14-2010
20100182840Nonvolatile Memory Device and Program or Verification Method Using the Same - A nonvolatile memory device includes a bit line sensing signal supply unit configured to output a bit line sensing signal, having a rising voltage level that rises in discrete steps, in response to a control signal, and a bit line sensing unit configured to selectively connect a bit line and a sensing node in response to the bit line sensing signal.07-22-2010
20100202213Current-Mode Sense Amplifying Method - A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current, respectively; duplicating the cell current and the reference current to respectively generate a mirrored cell current via a first current path and a mirrored reference current via a second current path and equalizing a first voltage drop generated as the mirrored cell current flows by the first current path and a second voltage drop generated as the mirrored reference current flows by the second current path; and removing the equalization of the first voltage drop and the second voltage drop and adjusting first voltage drop and the second voltage drop according to a first current flowing by the first current path and a second current flowing by the second current path.08-12-2010
20100202212Non-Volatile Memory With Power-Saving Multi-Pass Sensing - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.08-12-2010
20120243326SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a device includes transistors each with a path connected to a bit line, and circuits each includes a switch, the circuit being connected to the bit line. The device includes a amplifier connected to the transistor and to the circuit, and a latch connected to the amplifier to hold first data before read is carried out on a cell and to hold second data if a current equal to or a larger than a predetermined value flows via the bit line. In the device, the switch is turned on or off depending on data held in another latch located adjacently in a direction of the word lines, to control a connection between the bit line and connected to another bit line the amplifier via the circuit.09-27-2012
20080247239METHOD FOR CURRENT SENSING WITH BIASING OF SOURCE AND P-WELL IN NON-VOLATILE STORAGE - Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.10-09-2008
20080247237SEMICONDUCTOR MEMORY DEVICE IN WHICH SENSE TIMING OF SENSE AMPLIFIER CAN BE CONTROLLED BY CONSTANT CURRENT CHARGE - A semiconductor memory device includes a plurality of sense amplifiers which read data from a plurality of memory cells of a memory cell array, and a sense time generation circuit which controls the sense time of the plurality of sense amplifiers, the sense time generation circuit including a dummy capacitor having substantially the same size as that of a capacitor provided in each of the plurality of sense amplifiers, a control transistor connected to one electrode of the dummy capacitor and a constant-current discharge circuit which controls the control transistor to discharge the dummy capacitor with a constant current. The constant-current discharge circuit includes first and second nMOS transistors which are connected in series and a mirror circuit which generates gate voltage to operate the first and second nMOS transistors in a saturated region by use of the lowest voltage.10-09-2008
20130141984INTERNAL DATA COMPARE FOR MEMORY VERIFICATION - A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.06-06-2013
20130141985METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES - The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.06-06-2013
20130094299Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory - Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.04-18-2013
20130148432SENSE AMPLIFIER WITH OFFSET CURRENT INJECTION - A sense amplifier includes a sense input node, a current mirror circuit to mirror the current on the sense input node, and a result output node. A current source supplies an offset current. The sense amplifier increases the current on the sense input node by the offset current and reduces the offset current from the mirrored current at the result output node.06-13-2013
20130100744Compact Sense Amplifier for Non-Volatile Memory - A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.04-25-2013
20110267891DRIVING CIRCUIT FOR MEMORY DEVICE - An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells for programming the selected memory cells; the first programming voltage requires a first transient period for reaching a first target value thereof. In the solution according to an embodiment of the present invention, the programming means includes means for maintaining the second programming voltage substantially equal to the first programming voltage during a second transient period being required by the second programming voltage to reach a second target value thereof.11-03-2011
20130135940SEMICONDUCTOR MEMORY - A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.05-30-2013
20130176791NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND VERIFICATION CONTROL METHOD FOR THE SAME - A nonvolatile semiconductor memory device includes a memory cell array, a plurality of local sense amplifiers, a global sense amplifier and an address decoder. The address decoder is configured to switch between a first verification and a second verification. The first verification operates the plurality of local sense amplifiers and simultaneously verifies data of a plurality of memory cells connected to the plurality of local sense amplifiers. The second verification stops the plurality of local sense amplifiers, directly connects the local bit line connected to each of the local sense amplifiers with the global bit line, and simultaneously verifies data of the plurality of memory cells connected to the plurality of local sense amplifiers.07-11-2013
20100315878SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL WITH CHARGE ACCUMULATION LAYER - According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a first MOS transistor, and a current source circuit. The bit line transfers data read from the memory cell and/or data to be written to the memory cell. The sense amplifier charges the bit line during a data read and a data write. The first MOS transistor connects the bit line and the sense amplifier together. The current source circuit supplies a constant current to a gate of the first MOS transistor to charge the gate during a data write and/or a data read.12-16-2010
20100315877DATA SENSING MODULE AND SENSING CIRCUIT FOR FLASH MEMORY - A sensing circuit for a flash memory is provided. The sensing circuit includes a first transistor, a detector, and a charge circuit. A drain of the first transistor is coupled to a bias, a gate thereof receives an inverted signal, and a source thereof receives a data. In addition, the drain of the first transistor is further coupled to the detector. Therefore, the detector detects a voltage of the drain of the first transistor. When the voltage of the drain is lower than a threshold voltage, the detector enables a control signal. The charge circuit charges the source of the first transistor when the control signal is enabled, until the voltage of the drain of the first transistor reaches the threshold voltage.12-16-2010
20130155774SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.06-20-2013
20130182507MEMORY SYSTEM TEMPERATURE CALIBRATION - A nonvolatile memory system includes a memory controller chip with at least one temperature sensor that is individually calibrated, at a single temperature, after the nonvolatile memory system is assembled, so that the calibration data is stored outside the memory controller chip, in a nonvolatile memory chip, thus obviating the need for components to store calibration data in the memory controller chip.07-18-2013
20120008410Detection of Word-Line Leakage in Memory Arrays: Current Based Approach - Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.01-12-2012
20120294090Current-Sense Amplifier With Low-Offset Adjustment and Method of Low-Offset Adjustment Thereof - A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.11-22-2012
20130208544FLASH MEMORY WITH READ TRACKING CLOCK AND METHOD THEREOF - The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current.08-15-2013

Patent applications in class Sensing circuitry (e.g., current mirror)