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Multiple pulses (e.g., ramp)

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365 - Static information storage and retrieval

365185010 - FLOATING GATE

365185180 - Particular biasing

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DocumentTitleDate
20130028026Memory and Method for Programming Memory Cells - A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element.01-31-2013
20110194353METHOD OF PROGRAMMING MEMORY CELLS FOR A NON-VOLATILE MEMORY DEVICE - A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.08-11-2011
20110194354NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controller controls in such a manner that a verification operation subsequent to a program operation by which a threshold voltage of a memory cell transistor to be written has become equal to or higher than a verification level for the first time is carried out twice or more at the same verification level, verification operations of the second and subsequent times are carried out after a second program operation which is carried out with the memory cell transistor set in an unselected state.08-11-2011
20110194352PROGRAMMING METHODS AND MEMORIES - Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.08-11-2011
20100157686Method and Apparatus for Programming Nonvolatile Memory - A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.06-24-2010
20100074025Nonvolatile Memory Devices Having Erased-State Verify Capability and Methods of Operating Same - A program method of a nonvolatile memory device includes applying a program voltage to program cells for changing data; verifying the program cells, based on the changed data; and verifying program inhibit cells for maintaining stored data even when the program voltage is applied to the program inhibit cells, based on the stored data.03-25-2010
20100074024PROGRAMMING A MEMORY DEVICE TO INCREASE DATA RELIABILITY - Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.03-25-2010
20130039130PROGRAM METHOD OF NONVOLATILE MEMORY DEVICE - Disclosed is a program method of a nonvolatile memory device including applying a first program voltage to a word line of a memory cell; verifying a variation of a threshold voltage of the memory cell; and applying a second program voltage to a memory cell having a threshold voltage higher than a reference level, the second program voltage being lower in level than the first voltage pulse.02-14-2013
20130033936METHODS TO OPERATE A MEMORY CELL - Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.02-07-2013
20100046301INTELLIGENT CONTROL OF PROGRAM PULSE FOR NON-VOLATILE STORAGE - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.02-25-2010
20090135656NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH DUMMY CELLS AND METHOD OF PROGRAMMING THE SAME - A nonvolatile semiconductor memory device includes a memory cell array, an erase controller and a dummy cell controller. The memory cell array includes multiple cell strings, each including at least two dummy cells having different threshold voltages and normal memory cells. The erase controller performs, in cell block units, an erase operation for the normal memory cells of each cell string and an adjacent dummy cell of the at least two dummy cells positioned nearer the normal memory cells, and performs an erase verify operation for the normal memory cells. The dummy cell controller performs a program operation for each of the adjacent dummy cells within the memory cell array and a program verify operation of the adjacent dummy cells, and performs a program verify operation for remaining dummy cells, which are not adjacent dummy cells, and then a program operation for the remaining dummy cells requiring programming.05-28-2009
20130083606LIFETIME MARKERS FOR MEMORY DEVICES - The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.04-04-2013
20110002174FLASH MEMORY DEVICE AND PROGRAM RECOVERY METHOD THEREOF - A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.01-06-2011
20130088923NONVOLATILE MEMORY DEVICE, SYSTEM, AND PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data.04-11-2013
20090040833NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - Provided are a non-volatile memory device and a programming method. The programming method includes applying a program voltage to a selected word line, applying an elevated pass voltage to word lines adjacent to the selected word line in a plurality of word lines, and applying a pass voltage to remaining word lines in the plurality of word lines.02-12-2009
20110013460DYNAMICALLY ADJUSTABLE ERASE AND PROGRAM LEVELS FOR NON-VOLATILE MEMORY - Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.01-20-2011
20110013459METHOD OF PROGRAMMING/ERASING THE NONVOLATILE MEMORY - A method for programming/erasing a nonvolatile memory uses the multi-stage pulses to program/erase the memory so as to reduce the slow program/erase bit issue. The method applies a first predetermined voltage bias to a memory cell for a predetermined number of times. Each time the voltage bias is applied to the memory cell the memory is verified against a criterion. If the verification failed after the predetermined number of times applying the first predetermined voltage bias, a second predetermined voltage bias is applied to program/erase the nonvolatile memory. If the verification failed after applying the second predetermined voltage bias, a third predetermined voltage bias is applied to program/erase the nonvolatile memory.01-20-2011
20090067251REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.03-12-2009
20120224431PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY - For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the programming operation, and adjusting a program starting voltage level of one or more program pulses applied to the one or more memory cells during a subsequent programming operation in response, at least in part, to the number of program pulses required to program the sample of the one or more memory cells programmed during the prior programming operation.09-06-2012
20120224429METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES - Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS09-06-2012
20100124121METHOD OF ERASING FLASH MEMORY DEVICE - In a method of erasing a flash memory device according to an aspect of this disclosure, an erase operation is performed to lower threshold voltages of memory cells to a voltage level less than a first voltage. A first soft program operation is performed until a threshold voltage of any one of the memory cells reaches a second voltage higher than the first voltage. A second soft program operation is performed until a threshold voltage of any one of the memory cells reaches a third voltage higher than the second voltage.05-20-2010
20090238007METHOD OF SUPPLYING AN OPERATING VOLTAGE OF A FLASH MEMORY DEVICE - A method of supplying an operating voltage of a flash memory device includes supplying an operating voltage to a word line selected according to an input address, and changing a pass voltage according to a change of the operating voltage level. The pass voltage is supplied to unselected word lines other than the selected word line.09-24-2009
20090238006ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO THE NUMBER OF PROGRAMMING OR ERASE FAILURES - Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A number of the memory cells that failed to program or erase is determined and is compared to a certain number that can be different than a number of memory cells to be programmed or erased. The programming voltage pulse or the erase voltage pulse is adjusted in response to the comparison of the number of memory cells that failed to program or erase to the certain number. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase.09-24-2009
20090231924NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF - A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals. Further, the circuit for applying said plurality of pulse signals includes a first circuit for generating a first clock having a first amplitude voltage and a second clock having a second amplitude voltage which is higher than said first amplitude voltage, a second circuit for generating said plurality of said pulse signal having corresponding predetermined voltages based on said first clock or said second clock input from said first circuit respectively, and a third circuit for stopping an input of said first clock and said second clock to said second circuit when said plurality of pulse signals generated by said second circuit reach said corresponding predetermined voltages respectively.09-17-2009
20090231923REDUCTION OF PUNCH-THROUGH DISTURB DURING PROGRAMMING OF A MEMORY DEVICE - In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a V09-17-2009
20090010068Systems for Coarse/Fine Program Verification in Non-Volatile Memory Using Different Reference Levels for Improved Sensing - Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensings. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing.01-08-2009
20090010067COARSE/FINE PROGRAM VERIFICATION IN NON-VOLATILE MEMORY USING DIFFERENT REFERENCE LEVELS FOR IMPROVED SENSING - Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensings. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing.01-08-2009
20120113723MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE - In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.05-10-2012
20120236654PROGRAMMING NON-VOLATILE MEMORY WITH VARIABLE INITIAL PROGRAMMING PULSE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse associated with achieving an intermediate result for a respective programming process is identified, a pulse increment between programming pulses is decreased for the respective programming process while continuing the respective programming process to program non-volatile storage elements to the respective one or more targets and the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process.09-20-2012
20120236653SELF-CHECK CALIBRATION OF PROGRAM OR ERASE AND VERIFY PROCESS USING MEMORY CELL DISTRIBUTION - Subject matter disclosed herein relates to a memory device, and more particularly to write or erase performance of a memory device.09-20-2012
20130163341MULTI-PASS PROGRAMMING IN A MEMORY DEVICE - A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a preprogram level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.06-27-2013
20080291738METHODS AND CIRCUITS FOR GENERATING A HIGH VOLTAGE AND RELATED SEMICONDUCTOR MEMORY DEVICES - Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.11-27-2008
20090040832SOFT PROGRAM METHOD IN A NON-VOLATILE MEMORY DEVICE - A soft program method in a non-volatile memory device for performing a soft program step so as to improve threshold voltage distribution of an erased cell is disclosed. The soft program method in a non-volatile memory device includes performing a soft program for increasing threshold voltages of memory cells by a given level, wherein an erase operation is performed about the memory cells, performing a verifying operation for verifying whether or not a cell programmed to a voltage more than a verifying voltage is existed in each of cell strings, and performing repeatedly the soft program until it is verified that whole cell strings have one or more cell programmed to the voltage more than the verifying voltage.02-12-2009
20100195401METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data.08-05-2010
20120106257NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.05-03-2012
20120127801METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes performing a LSB program operation on memory cells coupled to a selected word line and a word line adjacent to the selected word line; performing a first MSB program operation so that the threshold voltages of the memory cells coupled to the selected word line reach temporary voltages lower than first target voltages; performing a second MSB program operation so that the threshold voltages of the memory cells coupled to the word line adjacent to the selected word line are higher than second target voltages; and performing a third MSB program operation so that the threshold voltages of the memory cells coupled to the selected word line are higher than the first target voltages.05-24-2012
20110280082NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.11-17-2011
20110280083NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.11-17-2011
20100008146Memory device and method of programming thereof - The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a negative pulse having a negative voltage, and a temporal interval existing between subsequent pulses of the plurality of pulses, and controlling at least one of a width of at least one of the temporal intervals and a magnitude of at least one of the plurality of pulses.01-14-2010
20100124123Nonvolatile Memory Device with Incremental Step Pulse Programming - A nonvolatile memory device includes a sense amplifier circuit sensing first data from a memory cell via a bit line and outputting the sensed first data, in response to a read command. A write driver circuit programs the memory cell and stores second data indicating a programming state of the memory cell, in response to a program command. A verification block outputs a result of a comparison between the first and second data in response to a first read command. The second data is updated based on the determination on the programming of the memory cell in response to a second read command applied following the first read command.05-20-2010
20130021849Program Algorithm with Staircase Waveform Decomposed into Multiple Passes - Programming algorithms suitable for non-volatile memory devices are presented, where the usual staircase type of waveform is decomposed into multiple passes. The same pulses are used, but their order is different, being broken down into N subsets of every N-th pulse so that there are N programming passes. For example, in a four pass version the first pass would sequentially have pulses (1, 5, 9, . . . ) of the staircase; the second pass would have pulses (2, 6, 10, . . . ); and so on for the third and fourth passes. By using a large step size for stepping up the program voltage V01-24-2013
20090310419Nonvolatile Memory with Index Programming and Reduced Verify - In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.12-17-2009
20110128790ANALOG SENSING OF MEMORY CELLS IN A SOLID-STATE MEMORY DEVICE - A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.06-02-2011
20090207664Flash Memory Device for Variably Controlling Program Voltage and Method of Programming the Same - Provided is a method of programming the flash memory device including setting increments of program voltages according to data states expressed as threshold voltage distributions of multi-level memory cells. An Increment Step Pulse Programming (ISPP) clock signal corresponds to a loop clock signal and the increments of the program voltages and is generated in response to program pass/fail information. A default level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the loop clock signal. An additional level enable signal is generated by performing a counting operation until reaching the increments of the program voltages, in response to the ISPP clock signal. The program voltage is increased by 1 increment, in response to the default level enable signal. The program voltage is increased by 2 increments, in response to the additional level enable signal.08-20-2009
20120287720SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A semiconductor memory device and a method of programming the same are provided which can improve the program accuracy by classifying cells depending on a program status of memory cells during a program operation to control a bit line program voltage. The method comprises classifying memory cells to be programmed based on program characteristics of the memory cells and sequentially providing word line program voltages having increasing voltage levels and bit line program voltages having decreasing voltage levels to the classified memory cells in a program operation, wherein differently classified two memory cells receive different bit line program voltages, respectively.11-15-2012
20110286279Erase and Programming Techniques to Reduce the Widening of State Distributions in Non-Volatile Memories - Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.11-24-2011
20120008408NON-VOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME - A non-volatile memory device and an operation method of the same are provided. A method for operating a non-volatile memory device includes programming a plurality of memory cells based on a target voltage level, verifying threshold voltage levels of the plurality of memory cells based on a correction voltage level higher than the target voltage level and selecting a memory cell programmed lower than the correction voltage level, and programming the selected memory cell based on the correction voltage level.01-12-2012
20110164455MEMORY CELL OPERATION - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.07-07-2011
20110292734METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a semiconductor device includes performing an initial program operation on all memory cells included in a selected memory cell block to set threshold voltages of all the memory cells to a voltage equal to or greater than 12-01-2011
20100046300REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE - Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.02-25-2010
20090086544COMPENSATION OF NON-VOLATILE MEMORY CHIP NON-IDEALITIES BY PROGRAM PULSE ADJUSTMENT - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.04-02-2009
20100080064BIT LINE BIAS FOR PROGRAMMING A MEMORY DEVICE - Bit line bias for programming a memory device is generally described. In one example, circuitry for bit line bias programming comprises a word line, one or more bit lines coupled with the word line, and one or more cells to be programmed to a target threshold voltage coupled with the word line and the one or more bit lines wherein a program speed of the one or more cells is increased by selectively pre-charging the one or more bit lines such that a single program pulse raises individual threshold voltages of the one or more cells to or above the target threshold voltage.04-01-2010
20120140566PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number of passed memory cells corresponding to a number of pass bits, if, a result of the program verify operation, the program operation failed to program all of the memory cells of the selected page to the target threshold voltage or higher, and making a determination that determines whether the number of pass bits is greater than the first number of pass permission bits, and raising a voltage of a bit line coupled to a failed memory cell, if, as a result of the determination, the number of pass bits is greater than the first number of pass permission bits.06-07-2012
20120140568Programming Memory With Reduced Pass Voltage Disturb And Floating Gate-To-Control Gate Leakage - Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.06-07-2012
20090310421Nonvolatile Memory with Correlated Multiple Pass Programming - A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size, and each successive pass has the staircase pulse train offset from that of the previous pass by a predetermined offset level. The predetermined offset level is less than the common step size and may be less than or equal to the predetermined offset level of the previous pass. Thus, the same programming resolution can be achieved over multiple passes using fewer programming pulses than conventional method where each successive pass uses a programming staircase pulse train with a finer step size. The multiple pass programming serves to tighten the distribution of the programmed thresholds while reducing the overall number of programming pulses.12-17-2009
20090310420Method for Correlated Multiple Pass Programming in Nonvolatile Memory - A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size, and each successive pass has the staircase pulse train offset from that of the previous pass by a predetermined offset level. The predetermined offset level is less than the common step size and may be less than or equal to the predetermined offset level of the previous pass. Thus, the same programming resolution can be achieved over multiple passes using fewer programming pulses than conventional method where each successive pass uses a programming staircase pulse train with a finer step size. The multiple pass programming serves to tighten the distribution of the programmed thresholds while reducing the overall number of programming pulses.12-17-2009
20090310418Method for Index Programming and Reduced Verify in Nonvolatile Memory - In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.12-17-2009
20100124124NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device including a bit line voltage supply unit configured to supply a power source voltage, a second voltage in which a second reference voltage has been subtracted from a third reference voltage, or a third voltage in which a first reference voltage has been subtracted from the third reference voltage according to data stored in a first latch unit, a second latch unit, and a third latch unit included in a page buffer, and a bit line voltage setting unit configured to transfer a voltage of 0 V or an output voltage of the bit line voltage supply unit to a bit line according to the data stored in the first, second, and third latch units.05-20-2010
20100124122METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.05-20-2010
20100124120NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes; a memory cell array including a plurality of memory cells arranged in word lines and bit lines, a high-voltage generator generating a program voltage pulse applied to a selected word line among the word lines, and a pass voltage applied to a non-selected word line, and control logic iteratively increasing the program voltage pulse and adjusting the pass voltage according to a defined increment during a program operation.05-20-2010
20110261623METHOD OF ERASING SEMICONDUCTOR MEMORY DEVICE - A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.10-27-2011
20110149660SENSING FOR MEMORY READ AND PROGRAM VERIFY OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.06-23-2011
20110149659ERASE OPERATIONS AND APPARATUS FOR A MEMORY DEVICE - Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.06-23-2011
20120033500NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY - In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back-and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower-programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.02-09-2012
20100080065NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile semiconductor memory device includes a memory cell and a driving unit. The a memory cell has a semiconductor layer having, a channel, and a source region and a drain region provided on both sides of the channel; a first insulating film provided on the channel; a charge retention layer provided on the first insulating film; and a gate electrode provided on the charge retention layer. The driving unit applies a burst signal having a constant amplitude and a constant frequency between the gate electrode and the semiconductor layer and performs at least one of operations of programming and erasing charge on the charge retention layer.04-01-2010
20090141557SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.06-04-2009
20110170359WORD LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.07-14-2011
20110170358PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.07-14-2011
20090262582Method of Programming Flash Memory Device - Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.10-22-2009
20090285028METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing a program operation on a first page, counting a program pulse application number until the program operation on the first page is completed, comparing the counted program pulse application number and a critical value and resetting a program start voltage based on the comparison result, and performing a program operation on a second page using the reset program start voltage.11-19-2009
20090290423METHOD OF ERASING A NONVOLATILE MEMORY DEVICE - In a method of erasing a nonvolatile memory device, an erase operation is performed on memory cells of a selected block. A first soft program operation is performed on the cells on which the erase operation has been performed. The erase operation and the first soft program operation are repeatedly performed by increasing an erase voltage by a first step voltage until a threshold voltage of the memory cells becomes lower than a first erase verify voltage. When the threshold voltage of the memory cells becomes lower than the first erase verify voltage, a second soft program operation is performed. The second soft program operation is repeatedly performed by increasing a soft program voltage by a second step voltage until a cell is programmed to have a soft program verify voltage.11-26-2009
20090296486Memory device and memory programming method - Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.12-03-2009
20100110797METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY - A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.05-06-2010
20100110796METHOD OF PERFORMING ERASE OPERATION IN NON-VOLATILE MEMORY DEVICE - A method of performing an erase operation in a non-volatile memory device includes a multi-erase operation and a post-erase operation. The multi-erase operation includes multi-erasing multiple memory blocks at the same time using a multi-erase voltage. The post-erase operation includes post-erasing one or more failed memory blocks of the multi-erased memory blocks using a post-erase voltage having sequentially increasing voltage values based on incremental step pulses (ISPs).05-06-2010
20090201741Non-volatile memory cell with injector - In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the source of holes into the charge-storage layer of the charge storage stack. The injector has a barrier potential for holes which is less than an insulating layer of the charge-storage stack which is oriented towards the source of holes. A multi-layer crested barrier injector may have layers of increasing potential barriers for holes from the source to the charge-storage layer. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.08-13-2009
20080291737PROGRAM AND ERASE METHODS FOR NONVOLATILE MEMORY - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.11-27-2008
20080291736NON-VOLATILE STORAGE SYSTEM WITH TRANSITIONAL VOLTAGE DURING PROGRAMMING - To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.11-27-2008
20100208523DYNAMIC SOFT PROGRAM TRIMS - Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.08-19-2010
20090190406RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES - Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.07-30-2009
20100142284DETERMINISTIC-BASED PROGRAMMING IN MEMORY - Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.06-10-2010
20110205803RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES - Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.08-25-2011
20110267890SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.11-03-2011
20090129168METHOD OF OPERATING A FLASH MEMEORY DEVICE - A method of operating a flash memory device wherein the width of threshold voltage distribution of memory cells is adjusted by setting different conditions of a program operation in accordance with levels of threshold voltages of the memory cells. As a result, width of the threshold voltage distribution of memory cells may be narrowed.05-21-2009
20080316832NON-VOLATILE STORAGE SYSTEM WITH INTELLIGENT CONTROL OF PROGRAM PULSE DURATION - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.12-25-2008
20080316833INTELLIGENT CONTROL OF PROGRAM PULSE DURATION - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.12-25-2008
20120069675REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.03-22-2012
20120069674FLASH MEMORY DEVICE AND RELATED PROGRAM VERIFICATION METHOD - A nonvolatile memory device performs a program operation using an incremental pulse programming (ISPP) scheme in which a plurality of program loops alternate between a coarse-fine verify operation, and a fine verify operation according to a value of a program loop counter.03-22-2012
20120069673METHOD AND DEVICE FOR PROGRAMMING DATA INTO NON-VOLATILE MEMORIES - A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control signal.03-22-2012
20120069672NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.03-22-2012
20090003075FLASH MEMORY DEVICES AND PROGRAMMING METHODS THAT VARY PROGRAMMING CONDITIONS IN RESPONSE TO A SELECTED STEP INCREMENT - A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.01-01-2009
20090052256THRESHOLD VOLTAGE DIGITIZER FOR ARRAY OF PROGRAMMABLE THRESHOLD TRANSISTORS - A system includes a voltage generator, current sensing amplifiers, and a control module. The voltage generator outputs a first voltage, which is generated based on received codewords, to a first word line that communicates with N transistors each having programmable threshold voltages, where N is an integer greater than 1. The current sensing amplifiers sense currents through the N transistors via N bit lines, respectively, and generate control signals when current through a corresponding one of the N transistors is greater than or equal to a predetermined current. The control module generates measured values of the threshold voltages of the N transistors by compensating the ones of the codewords based on at least one of a position of the corresponding ones of the N transistors and a temperature.02-26-2009
20130215680AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE - Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.08-22-2013
20090086545Non-Volatile Memory Device and Method of Operating the Same - The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage.04-02-2009
20080273392METHOD OF PROGRAMMING A SELECTED MEMORY CELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.11-06-2008
20090219761CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.09-03-2009
20090257282NON-VOLATILE STORAGE SYSTEM WITH INITIAL PROGRAMMING VOLTAGE BASED ON TRIAL - A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements (which may or may not include the first set).10-15-2009
20090244977VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE FOR NON-VOLATILE STORAGE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process includes programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process.10-01-2009
20090257280NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING SAME - An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch10-15-2009
20090257281METHOD OF PROGRAMMING A FLASH MEMORY DEVICE USING SELF BOOSTING - A method of programming a flash memory device controls a channel boosting level to ensure device properties. The flash memory device is programmed in an Incremental Step Pulse Program (ISPP) manner by applying a program voltage to a selected memory cell and a pass voltage to unselected memory cells. The programming is performed by varying the pass voltage so that a gap of a predetermined range is maintained between a channel voltage and a word line voltage of the unselected memory cell.10-15-2009
20110228610NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A PROGRAMMING METHOD THEREOF - A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.09-22-2011
20100265771METHOD OF PROGRAMMING MEMORY CELLS OF SERIES STRINGS OF MEMORY CELLS - Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after programming each memory cell of the string located between the target memory cell and a first end of the string, and verifying the programming of the target memory cell by applying a bias at a second end of the string opposite the first end and sensing a voltage developed at the first end in response to the bias.10-21-2010
20100002521Method for Programming of Memory Cells, in Particular of the Flash Type, and Corresponding Programming Architecture - A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.01-07-2010
20120033501NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY - Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.02-09-2012
20090052255PROGRAM AND ERASE METHODS FOR NONVOLATILE MEMORY - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying at least one programming pulse, at least one erasing pulse, at least one time delay, at least one soft erase pulse, at least one soft programming pulse and/or at least one verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.02-26-2009
20090290422METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes floating a drain select line, a source select line, a well, and a common source line of the nonvolatile memory device; precharging a program-inhibited bit line; and performing a program operation by applying a program voltage to a selected word line. The select lines and the well are floated to prevent the influence of a voltage applied to a bit line. Accordingly, degradation of the nonvolatile memory device can be prevented.11-26-2009
20100182839Method of Programming Nonvolatile Memory Device - According to a method of programming a nonvolatile memory device, a program operation is performed on a first page by applying a program pulse to the first page. A verification operation is performed on the program operation by applying a verification voltage to the first page. If the program operation for the first page has not been completed, a voltage selected from threshold voltages of the first page is set as a highest threshold voltage. The program operation for the first page is completed by repeatedly performing a program operation and a verification operation on the first page while a voltage level of the program pulse is increased. The sum of a program start voltage for the first page and a difference between the verification voltage and the highest threshold voltage is set as a program start voltage for a second page.07-22-2010
20110235429METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY - A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.09-29-2011
20100157685PROGRAMMING IN A MEMORY DEVICE - Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.06-24-2010
20100220528NAND WITH BACK BIASED OPERATION - Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts09-02-2010
20110058424DATA LINE MANAGEMENT IN A MEMORY DEVICE - Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.03-10-2011
20090273981Methods and apparatuses for programming flash memory using modulated pulses - Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. Embodiments generally comprise a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. Alternative embodiments may include a threshold verifier capable of verifying that the threshold voltage is set within an acceptable voltage range of a target threshold voltage. A pulse width modulator in some apparatus embodiments may modulate the pulse durations early in the sequence when programming fast bits and late in the sequence when programming slow bits. Method embodiments generally comprise generating a sequence of pulses, applying the sequence of pulses to a memory cell to set a threshold voltage of the memory cell, and modulating among pulses in the sequence the parameters of pulse duration, pulse separation time, and step voltage magnitude.11-05-2009
20090040831METHOD OF PROGRAMMING IN A FLASH MEMORY DEVICE - A method of programming in a flash memory device is disclosed. The method includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, verifying whether or not the first memory cell is programmed through a first verifying voltage, and programming the first memory cell using a program voltage increased in sequence by a step voltage than the first program voltage in case that the first memory cell is not programmed programming a second memory cell coupled to an odd bit line by applying the first program voltage to the word line, and verifying whether or not the second memory cell is programmed through a second verifying voltage higher than the first verifying voltage, and programming the second memory cell using a program voltage increased in sequence by the step voltage than the first program voltage in case that the second memory cell is not programmed.02-12-2009
20090073769METHOD AND SYSTEM FOR OPTIMIZING RELIABILITY AND PERFORMANCE OF PROGRAMMING DATA IN NON-VOLATILE MEMORY DEVICES - Methods of managing memory devices, and devices so managed. A value of a parameter, that is used to program one or more memory cells, is adapted to a monitored condition of the cell(s). Either the number of bits per cell is held fixed or the monitored condition is an intrinsic condition of the cell(s). The initial value of the parameter is optimized for those specific cells, relative to a pre-selected criterion, by programming the cell(s) in accordance with candidate values of the parameter.03-19-2009
20100232227NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A non-volatile memory device including a memory cell array; a read/write circuit configured to drive bit lines of the memory cell array with a negative bit line voltage according to data to be programmed; a bit line setup-time measuring circuit configured to measure the bit line setup-time, which may be a function of the amount of data to be programmed, at each ISPP program loop; and a control logic configured to control the program voltage and/or the applied time of a program voltage applied to the selected wordline of the memory cell array based on the measured bit line setup-times measured at each ISPP program loop.09-16-2010
20090109759OPERATING MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells are coupled between the edge cells. The method includes programming a non-edge cell within a first threshold voltage (Vt) distribution. The method also includes programming an edge cell within a second Vt distribution, wherein the first and second Vt distributions correspond to a same one of a number of data states, and wherein the second Vt distribution is different than the first Vt distribution for at least one of the number of data states.04-30-2009
20080291735METHOD FOR USING TRANSITIONAL VOLTAGE DURING PROGRAMMING OF NON-VOLATILE STORAGE - To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.11-27-2008
20080279012Methods of Operating Memory Devices Including Negative Incremental Step Pulse Programming and Related Devices - A memory device may include a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. Moreover, the string selection transistor may be coupled between the string and a bitline, and the ground selection transistor may be coupled between the string and a common source line. During programming, one of the plurality of memory cell transistors in the string may be selected for a program operation so that other memory cell transistors in the string are unselected, and a plurality of negative voltage pulses may be applied to a channel region of the selected memory cell transistor. While applying the plurality of negative voltage pulses to the channel region, a positive pass voltage may be applied to control gate electrodes of the unselected memory cell transistors, and a positive program voltage may be applied to a control gate electrode of the selected memory cell. Related methods and devices are discussed.11-13-2008
20100296344Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.11-25-2010
20130135938NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second signal is applied to a second cell. The driving unit applies a third signal to the gate electrodes of all the memory cells prior to the sequential reading. The third signal has a voltage smaller than the second signal and time duration equal to or more than that of a sum of time duration during which the first signal is applied to all the memory cells. In a period prior to the third signal application, the driving unit performs at least one of applying a fourth signal to the gate electrodes and matching is a potential of the gate electrodes with that of the semiconductor layer.05-30-2013
20100302862Non-volatile Memory Device - The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage.12-02-2010
20100302858DATA LINE MANAGEMENT IN A MEMORY DEVICE - Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.12-02-2010
20100302859NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a memory block including a number of cell strings, a channel voltage detection unit configured to detect channel voltages of the cell strings in which the channel voltages are changed based on voltages supplied to memory cells of the cell strings during a program operation and to generate channel voltage code based on an average channel voltage of the detected channel voltages, and a voltage supply unit configured to change a level of a pass voltage of the voltages supplied to memory cells in which the pass voltage is supplied to the memory cells during the program operation according to the channel voltage code.12-02-2010
20100302860NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, including page buffers each configured to store program data for memory cells or store data read from the memory cells, and a control unit configured to, when a program operation is first performed after power is supplied, count a number of program pulses until a verification operation using a first verification voltage is a pass, compare the counted number and a first number of program pulses, select either the first or second program start voltages according to a result of the comparison, and control the program operation to be performed using the selected program start voltage until the power is off.12-02-2010
20130141982SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to selected memory cells and perform an erase verify operation by supplying an erase verify voltage to the selected memory cells, wherein the peripheral circuit is configured to increase the first erase voltage to a first level at a first rising rate for a first rising period and increase the first erase voltage to a first target level at a second rising rate lower than the first rising rate for a second rising period.06-06-2013
20110242899EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE-VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE - An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase.10-06-2011
20090141556METHOD OF VERIFYING PROGRAMMING OF A NONVOLATILE MEMORY DEVICE - A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation operation for changing a voltage of the bit line is performed. Results of the first read evaluation operation are sensed using a first sensing voltage. A second read evaluation operation for changing the voltage of the bit line is performed again. Results of the second read verify operation are then sensed using the first sensing voltage.06-04-2009
20090067252FUSE DATA ACQUISITION - One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing at least one of the number of fuse circuits in response to detecting that the voltage has reached the threshold level, and reading an output of at least one of the number of fuse circuits at least partially in response to a detected state change of an output of the at least one initialized fuse circuit.03-12-2009
20110019483ADAPTIVE ERASE AND SOFT PROGRAMMING FOR MEMORY - An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.01-27-2011
20110026331PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY - Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.02-03-2011
20110044113NONVOLATILE MEMORY DEVICE, METHOD FOR PROGRAMMING SAME, AND MEMORY SYSTEM INCORPORATING SAME - A nonvolatile memory device performs a program operation on selected memory cells by determining a level of a program voltage based on a degree of deterioration of the memory cells, and executing the program operation using the program voltage.02-24-2011
201102428984-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE - A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.10-06-2011
20110080789AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE - Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.04-07-2011
20090323430PROGRAM ACCELERATION OF A MEMORY DEVICE - Selective program acceleration of a memory device is generally described. In one example, a method includes applying a first bias voltage to one or more bit lines coupled with a plurality of cells to be programmed, applying one or more program pulses to the plurality of cells, verifying the plurality of cells at a target threshold voltage to determine whether one or more cells of the plurality of cells have reached or surpassed the target threshold voltage, identifying slower cells of the plurality of cells, and selectively accelerating a program speed of the slower cells to reduce a programming time of a memory device.12-31-2009
20110134703Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest And/Or Slowest Programming Bits - A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.06-09-2011
20110242900MEMORY CELL SENSING DEVICES AND METHODS - The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter to a digital-to-analog converter (DAC). An output of the DAC can correspond to a ramping voltage provided to a control gate of the memory cell. An output of a second counter can be provided to sensing circuitry coupled to a sense line of the memory cell. Conduction of the sense line in response to the ramping voltage can be sensed, and an output value of the second counter can be determined in response to the sensed conduction of the sense line.10-06-2011
20110242901LIFETIME MARKERS FOR MEMORY DEVICES - The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.10-06-2011
20090323429PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY - Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.12-31-2009
20100054041ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO A RATE OF PROGRAMMING OR ERASING - Memory devices and methods of operating memory devices are provided. In one such embodiment, a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A rate at which programming or erasing is proceeding is determined. The programming voltage pulse or the erase voltage pulse is adjusted at least partially in response to the determined rate. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase.03-04-2010
20100039863MITIGATION OF RUNAWAY PROGRAMMING OF A MEMORY DEVICE - Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.02-18-2010
20100135082MOVING PROGRAM VERIFY LEVEL FOR PROGRAMMING OF MEMORY - Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level, and a subset of the group of cells that are below the next PV level are selected and a next program pulse is applied to the subset of cells to facilitate verifying the cells to pass the next PV level. The moving PV level process can continue until the group of memory elements is verified to pass the target PV level.06-03-2010
20110249503SELECT GATE PROGRAMMING IN A MEMORY DEVICE - Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.10-13-2011
20110249504SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY - In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.10-13-2011
20110249505METHOD OF PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE - A method of programming a semiconductor memory device by applying a program voltage to a selected word line in an incremental step pulse program mode includes raising a voltage of precharging a bit line for program inhibition according to an increase in the program voltage applied to the selected word line.10-13-2011
20100246271ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.09-30-2010
20100246272APPARATUS COMPARING VERIFIED DATA TO ORIGINAL DATA IN THE PROGRAMMING OF A MEMORY ARRAY - Apparatus configured to perform a programming operation on at least one memory cell of the memory array in response to original data, and further configured to perform a comparison of verified data of the at least one memory cell of the memory array to the original data following success of the programming operation. Certain apparatus may be configured to permit skipping the comparison.09-30-2010
20120201082ERASE RAMP PULSE WIDTH CONTROL FOR NON-VOLATILE MEMORY - A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block.08-09-2012
20110255342MEMORY VOLTAGE CYCLE ADJUSTMENT - The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.10-20-2011
20100302861Program and erase methods for nonvolatile memory - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.12-02-2010
20110249506SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to an embodiment includes a plurality of memory cells which electrically rewrite data by controlling the amount of charges accumulated in a floating gate formed on a well through a tunnel insulating film. The semiconductor storage device includes a well control circuit which outputs an erasure voltage to be applied to the well through an output terminal. The semiconductor storage device includes a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal. The semiconductor storage device includes a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit. The semiconductor storage device includes a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit. The semiconductor storage device includes an erase pulse control circuit which sets target voltages of the first pump circuit and the second pump circuit, on the basis of setting values to set a target voltage of the erasure voltage.10-13-2011
20120201083SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.08-09-2012
20090080263REDUCING PROGRAMMING VOLTAGE DIFFERENTIAL NONLINEARITY IN NON-VOLATILE STORAGE - A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.03-26-2009
20120170375Vertical Nonvolatile Memory Devices and Methods of Operating Same - Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).07-05-2012
20120170374NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device programs a memory cell by performing a plurality of program loops each comprising a program operation and a program verifying operation. Where the program verifying operation in one program loop determines that the memory cell has been successfully programmed to a target state, a soft-programming operation is performed in a subsequent program loop to determine whether the memory cell has retained the target state, and if not, increases the threshold voltage of the memory cell.07-05-2012
20120170373SEMICONDUCTOR MEMORY DEVICE AND PROGRAM METHODS THEREOF - Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.07-05-2012
20080266972PROGRAMMING A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is increased by the step voltage. The step voltage for the lowest word line near the source line is lower than the step voltage for the word line closest to the drain line.10-30-2008
20080266970PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY - For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.10-30-2008
20080266971PROGRAMMING A FLASH MEMORY DEVICE - An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step.10-30-2008
20080198660MULTIPLE PASS WRITE SEQUENCE FOR NON-VOLATILE STORAGE - A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting threshold voltage distributions and programs non-volatile storage elements to at least two ending threshold voltage distributions.08-21-2008
20110255344CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.10-20-2011
20080253194FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality of memory cells using a program voltage having an increment decreased according to an increase in the program loop number, wherein the verifying and programming steps constitute a program loop, the program loop being terminated at a point in time when a level of the verify voltage reaches to a voltage range of the second state.10-16-2008
20080253193Non-Volatile Memory with Predictive Programming - In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. A checkpoint is a set of coordinates on the predetermined function determined by a conventional programming mode employing alternating program and verify operations.10-16-2008
20080205156Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation.08-28-2008
20080205155Systems and methods to reduce interference between memory cells - Embodiments of the inventive subject matter provide systems and methods for programming a set of memory cells by inducing a first voltage on the lower page of a first group of memory cells to hold a first least significant bit, and by inducing a second voltage on the lower page of a second group of memory cells to hold a second least significant bit. Once the lower page is programmed, the voltage may be shifted to the upper page of each memory cell into a final range representing one or more most significant bits to be programmed. Each memory cell may store a voltage within a final programmed range representing a binary value.08-28-2008
20080205157Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation.08-28-2008
20110164454NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the stepwise increasing step pulses according to the number of the stepwise increasing step pulses.07-07-2011
20110164457Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation.07-07-2011
20110164456METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES USING INHIBIT VOLTAGES THAT ARE LESS THAN A SUPPLY VOLTAGE - Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less than a nominal programming preparation voltage as used in the conventional art. Programming pulses can be applied to selected word lines of the memory cells to be programmed when the uninhibited bit lines are at 0V.07-07-2011
20110134701MEMORY KINK COMPENSATION - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.06-09-2011
20110134702PROGRAMMING METHODS AND MEMORIES - Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and applying a set of incrementing inhibit pulses to an unselected cell to fine-tune program the selected cell to a second threshold voltage.06-09-2011
20110255343PROGRAMMING IN A MEMORY DEVICE - Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.10-20-2011
20100110795BOOSTING SEED VOLTAGE FOR A MEMORY DEVICE - A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.05-06-2010
20110096608MITIGATION OF RUNAWAY PROGRAMMING OF A MEMORY DEVICE - Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.04-28-2011
20100165742METHODS AND CIRCUITS FOR GENERATING A HIGH VOLTAGE AND RELATED SEMICONDUCTOR MEMORY DEVICES - Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.07-01-2010
20100165741DYNAMIC PASS VOLTAGE - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.07-01-2010
20100165740NONVOLATILE SEMICONDUCTOR MEMORY CAPABLE OF TRIMMING AN INITIAL PROGRAM VOLTAGE FOR EACH WORD LINE - A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a trimming circuit configured to obtain a parameter of an initial program voltage for each word line of the plurality of word lines; an initial Vpgm parameter register configured to receive the parameter of the initial program voltage from the trimming circuit and to store the parameter; and a control circuit configured to perform programming of data to the memory cell array based on the parameter of the initial program voltage stored in the initial Vpgm parameter register, the trimming circuit being arranged in a part of the control circuit.07-01-2010
20100165738Non-Volatile Memory And Method For Sensing With Pipelined Corrections For Neighboring Perturbations - A page of non-volatile multi-level storage elements on a word line WLn is sensed in parallel while compensating for perturbations from a neighboring page on an adjacent word line WLn+1. First, the programmed thresholds of storage elements on WLn+1 are sensed in the time domain and encoded as time markers. This is accomplished by a scanning sense voltage increasing with time. The time marker of a storage element indicates the time the storage element starts to conduct or equivalently when the scanning sense voltage has reached the threshold of the storage element. Secondly, the page on WLn is sensed while the same scanning voltage with an offset level is applied to WLn+1 as compensation. In particular, a storage element on WLn will be sensed at a time indicated by the time marker of an adjacent storage element on WLn+1, the time when the offset scanning voltage develops an appropriate compensating bias voltage on WLn+1.07-01-2010
20100067307METHOD FOR PROGRAMMING AND ERASING AN NROM CELL - A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.03-18-2010
20100067305NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD WITH IMPROVED PASS VOLTAGE WINDOW - A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.03-18-2010
20100067306NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the stepwise increasing step pulses according to the number of the stepwise increasing step pulses.03-18-2010
20100195400NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.08-05-2010
20100027348PROGRAM METHOD OF FLASH MEMORY DEVICE - A program method of a flash memory device includes inputting a first data and a second data to a page buffer coupled to memory cells including an even page and an odd page, pre-programming a first memory cell of the odd page using the first data, programming a second memory cell of the even page using the second data, and programming the pre-programmed first memory cell using the first data.02-04-2010
20120307564METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.12-06-2012
20110051521FLASH MEMORY MODULE AND METHOD FOR PROGRAMMING A PAGE OF FLASH MEMORY CELLS - A flash memory module and a method for programming a page of flash memory cells, the method includes: receiving a cycle count indication indicative of a number of program cycles of the page of memory cells; setting a value of a programming parameter of a programming operation based on the cycle count indication; and programming at least one flash memory cell of the page of flash memory cells by performing the programming operation.03-03-2011
20110051520NONVOLATILE MEMORY DEVICE, DRIVING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME - A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and a ground voltage is applied to the well of the transistor. And, during a second time a second high voltage level is applied to the channel of the transistor, and within the second time interval a first negative voltage is applied to the well of the transistor. The first high voltage level is higher than the second high voltage level, and a voltage applied on the selected wordline is negative within the second time interval.03-03-2011
20100165739NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.07-01-2010
20120099378NONVOLATILE MEMORY AND METHOD FOR VERIFYING THE SAME - A nonvolatile memory device includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage sensing unit configured to apply a verify precharge voltage to the bit line in response to a voltage of a sensing node before a verify operation, a voltage transmission unit configured to apply a voltage of the bit line to the sensing node in a verify operation, and a page buffer configured to determine a voltage of the sensing node in response to data stored therein before a verify operation and to change the data in response to a voltage level of the sensing node in the verify operation.04-26-2012
20100128534Word Line Voltage Boost System and Method for Non-Volatile Memory Devices and Memory Devices and Processor-Based System Using Same - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.05-27-2010
20100103741NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURAL MEMORY CELLS AND A DUMMY CELL COUPLED TO AN END OF A MEMORY CELL - A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.04-29-2010
20110063919MEMORY KINK CHECKING - This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.03-17-2011
20120206972NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.08-16-2012
20110157995NAND MEMORY PROGRAMMING METHOD USING DOUBLE VINHIBIT RAMP FOR IMPROVED PROGRAM DISTURB - A method of applying an inhibit bias to an unselected word line when programming a NAND memory device is provided. The method may include ramping the inhibit bias to the unselected word line to a first predetermined voltage and ramping the inhibit bias to the unselected word line to a second predetermined voltage. Ramping of the inhibit bias to the unselected word line to a first predetermined voltage may occur until a boosted channel reaches a leakage limited saturation potential.06-30-2011
20120044769MULTI-PASS PROGRAMMING IN A MEMORY DEVICE - A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.02-23-2012
20080239824Non-Volatile Memory with Compensation for Variations Along a Word Line - Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.10-02-2008
20120008409REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE - Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.01-12-2012
20120044770NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS flash memory array - A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.02-23-2012
20120008407SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method of programming a semiconductor memory device includes a first program step for performing a program by supplying a first program voltage, having a specific amount, to a selected word line of the semiconductor memory device for a set time and a second program step for performing a program by supplying, to the selected word line, a second program voltage which is a step pulse gradually rising from a start voltage lower than the first program voltage.01-12-2012
20120008406NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a nonvolatile memory device includes programming first memory cells to make threshold voltages of the first memory cells to reach a verification voltage determined based on program data of second memory cells to be programmed, and programming the second memory cells.01-12-2012
20120008405Detection of Broken Word-Lines in Memory Arrays - Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same.01-12-2012
20120044768PROGRAMMING TO MITIGATE MEMORY CELL PERFORMANCE DIFFERENCES - Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and a maximum target voltage is used as a gate step voltage for a second programming voltage. Fast and slow programming memory cells are determined from the distribution resulting from the second programming voltage. An effective gate voltage applied to the control gates of the fast programming memory cells is less than an effective gate voltage applied to the control gates of the slow programming memory cells during the third programming voltage.02-23-2012
20120014184PROGRAMMING NON-VOLATILE MEMORY WITH BIT LINE VOLTAGE STEP UP - Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.01-19-2012
201200141833 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB - A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.01-19-2012
20120057408ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE - A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.03-08-2012
20120026798SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.02-02-2012
20120063232METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.03-15-2012
20120155184FLASH MEMORY DEVICE HAVING DUMMY CELL - A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.06-21-2012
20120155182NON-VOLATILE MEMORY DEVICE AND CACHE PROGRAM METHOD OF THE SAME - A cache programming method for a non-volatile memory device includes programming data for a current programming operation into a memory cell array, determining whether the current programming operation has been performed to a threshold point of program completion, and receiving a data for a next programming operation when the current programming operation has been performed to the threshold point of program completion.06-21-2012
20120155183METHOD OF SOFT PROGRAMMING SEMICONDUCTOR MEMORY DEVICE - An operating method of a semiconductor memory device includes erasing all memory cells of a selected cell block, performing a soft program operation on the erased memory cells by supplying a soft program pulse to word lines of the selected cell block, performing a first verify operation using a first voltage level lower than a target voltage level of the soft program operation, performing a second verify operation using the target voltage level, setting voltages of bit lines, and repeating the soft program operation, the first verify operation, the second verify operation, and an operation of setting the voltages of bit lines while raising the soft program pulse gradually.06-21-2012
20130010540PROGRAMMING METHODS FOR A MEMORY DEVICE - Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a final target programmed state where the partial programming is verified by applying a ramped voltage having a first voltage range (e.g., where the first voltage range is selected in response to program coupling effects from memory cells adjacent to the target memory cell.) A programming operation following the partial programming operation is performed on one or more adjacent memory cells which is then followed by additional programming of the target memory cell to adjust the memory cell from the partially programmed state to the final programmed state. A ramped voltage having a second voltage range different from the first voltage range is utilized to verify the programming of the target memory cell to the final programmed state.01-10-2013
20100172185Method for Operating a Flash Memory Device - A charge trap flash memory device is capable of preventing a data retention fail by ensuring a data retention margin. A method for operating the charge trap flash memory device is provided. A selected memory cell is programmed using a program voltage. The selected memory cell is verified using a first program verify voltage. Date retention states of selected memory cell having passed the program verify step are verified using a retention verify voltage. A read step of determining a program pass or fail by reading data of the selected memory cell having passed the retention verify step is performed using a read voltage.07-08-2010
20100172186PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY - For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.07-08-2010
20110103151Methods of Programming Semiconductor Memory Devices - To program a semiconductor memory device, a plurality of target threshold voltage groups are set by dividing target threshold voltages representing states of memory cells. The target threshold voltage groups are substantially simultaneously programmed by applying a plurality of program voltages to a word line. Program end times for the target threshold voltage groups are adjusted.05-05-2011
20110103150NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING - A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.05-05-2011
20120120729WORD LINE KICKING WHEN SENSING NON-VOLATILE STORAGE - Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced.05-17-2012
20120163094PROGRAMMING METHODS AND MEMORIES - Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and applying a set of incrementing inhibit pulses to an unselected cell to fine-tune program the selected cell to a second threshold voltage.06-28-2012
20120163093NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A programming method of a nonvolatile memory device includes inputting even data and odd data to be programmed into even memory cells coupled to even bit lines and odd memory cells coupled to odd bit lines, respectively, setting a sense signal as a first sense signal or a second sense signal having a lower voltage level than the first sense signal, based on odd data of odd memory cells adjacent to each of the even memory cells to be programmed, programming the even data into the even memory cells by supplying a program voltage, performing a program verify operation on each of the even memory cells in response to the set sense signal, and programming the odd data into the odd memory cells by supplying a program voltage.06-28-2012
20120163092NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.06-28-2012
20100208524SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE - Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.08-19-2010
20110182122DYNAMIC SOFT PROGRAM TRIMS - Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.07-28-2011
20120134214SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A program method of a semiconductor memory device includes performing a least significant bit (LSB) program operation for target LSB program cells of a selected page, increasing the threshold voltages of target most significant bit (MSB) program cells of the selected page before performing an MSB operation for the target MSB program cells, and performing the MSB program operation for the target MSB program cells after the increasing of the threshold voltages of the target MSB program cells.05-31-2012
20090059671Method of programming non-volatile memory device - A method of programming a non-volatile memory device may include performing a first programming operation including applying a program voltage to a memory cell and verifying the memory cell using a first verification voltage. A perturbation pulse may be applied to the memory cell to facilitate thermalization of charges in the memory cell if the memory cell passes the verification using the first verification voltage. The memory cell may be verified using a second verification voltage greater than the first verification voltage after the perturbation pulse is applied.03-05-2009
20090109760DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES - Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.04-30-2009
20120075932CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.03-29-2012
20120176843MEMORIES AND METHODS OF PROGRAMMING MEMORIES - Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.07-12-2012
20100008145METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming nonvolatile memory devices. According to one programming method program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is then verified whether a program has been completed as a result of the program operation. According to another programming method, a program operation is performed by applying a step-shaped dummy program pulse, which has a second pulse width and has been increased by a second step voltage. A program operation is performed by applying a program pulse having a first step voltage and a first pulse width. It is then verified whether a program has been completed as a result of the program operation.01-14-2010
20120218826NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A non-volatile memory device and a program method thereof are disclosed. The non-volatile memory device includes a page buffer section connected to the bit lines further connected to memory cells and where the page buffer section is for controlling a potential of the bit lines in response to control signals, and a program controller configured to perform a comparison of a count of a number of program pulses provided to the memory cells with a target number by which a program pulse of the program pulses is to be provided and output the control signals in accordance with the comparison, wherein the target number is set in accordance with a threshold voltage value of the memory cells and a state to be programmed.08-30-2012
20120224430READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADAPTIVE PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.09-06-2012
20120188824PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.07-26-2012
20120081969PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises applying positive pulses and negative pulses simultaneously to a memory cell array to program at least one memory cell included in the memory cell array.04-05-2012
20120230113RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES - Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.09-13-2012
20110122705METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing an erase operation, counting an erase pulse application number once the erase operation is completed, comparing the counted erase pulse application number and a reference value, defining a post program start voltage based on the comparison result, performing a post program operation and a verify operation using the defined post program start voltage, and performing a program operation on cells on which the post program operation has been completed.05-26-2011
20110122704METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing an erase operation, counting an erase pulse application number once the erase operation is completed, comparing the counted erase pulse application number and a reference, defining a program start voltage based on the comparison result, and performing a program operation using the defined program start voltage.05-26-2011
20110122703PROGRAMMING MEMORY WITH DIRECT BIT LINE DRIVING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING - During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines. Dedicated power supplies can be used to provide the step up to avoid a risk that the unselected bit lines begin floating due to pre-charging of other bit lines The selected bit lines are coupled higher as a function of their proximity to unselected bit lines, and in preparation for applying a program pulse. Coupling may be used for slow and fast programming modes. A dedicated power supply can be provided for driving slow programming mode bit lines at a level which provides coupling compensation.05-26-2011
20110122702PROGRAMMING MEMORY WITH SENSING-BASED BIT LINE COMPENSATION TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING - During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines, and the amount of coupling which is experienced by the selected bit lines is sensed. When a program pulse is applied, voltages of the selected bit lines are set based on the amount of coupling. The bit line voltage is set higher when more coupling is sensed. The amount of coupling experience by a given selected bit line is a function of its proximity to unselected bit lines. One or more coupling thresholds can be used to indicate that a given selected bit line has one or two adjacent unselected bit lines, respectively.05-26-2011
20100329020METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes an initial data setting step of inputting data for program inhibition to a first latch of a page buffer to which memory cells to be programmed with a second threshold voltage distribution are coupled, a first program and verification step of performing program and verification operations, a first data setting step of, when a program pulse is supplied more than N times (where N is a natural number), inputting data for performing a program operation to the first latch of the page buffer to which the memory cells to be programmed with the second threshold voltage distribution are coupled, and a second program and verification step of performing program and verification operations.12-30-2010
20100329022METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels.12-30-2010
20100329021METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes inputting program data to page buffers; performing a program operation and a program verification operation until threshold voltages of memory cells included in a selected page reach a target level according to the program data; when the threshold voltages of the memory cells reach the target level, performing an over-program verification operation to determine over-programmed memory cells in the memory cells; and making a determination of whether error checking and correction (ECC) processing for the over-programmed memory cells is feasible.12-30-2010
20080298131INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISCHARGE RAMP RATE CONTROL AND METHOD THEREFOR - An integrated circuit (12-04-2008
20120327716COMPENSATION OF NON-VOLATILE MEMORY CHIP NON-IDEALITIES BY PROGRAM PULSE ADJUSTMENT - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.12-27-2012
20120268999DYNAMIC PROGRAMMING FOR FLASH MEMORY - A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion.10-25-2012
20110222353SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.09-15-2011
20100246270CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE - A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.09-30-2010
20120127800Pair Bit Line Programming To Improve Boost Voltage Clamping - A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.05-24-2012
20110235428COMPENSATION OF NON-VOLATILE MEMORY CHIP NON-IDEALITIES BY PROGRAM PULSE ADJUSTMENT - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.09-29-2011
20100232228MEMORY DEVICE, MEMORY SYSTEM AND PROGRAMMING METHOD - A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing the distribution voltage and the second verify voltage.09-16-2010
20100232226SOLID STATE STORAGE SYSTEM FOR UNIFORMLY USING MEMORY AREA AND METHOD CONTROLLING THE SAME - A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not.09-16-2010
20110242902NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory cell array including a plurality of memory cells; a plurality of word lines each connected in common to memory cells arranged in a corresponding one of rows among the plurality of memory cells; a voltage generator including a clock signal cycle controller configured to lengthen a cycle of a clock signal every time writing is performed at a stepped-up program voltage to the memory cells connected to a word line selected from the word lines, the voltage generator being configured to generate a desired output voltage by using the clock signal, wherein the clock signal cycle controller performs control in such a way that a ramp up rate for writing at the stepped-up program voltage is kept substantially equal to a ramp up rate for writing at an initial program voltage.10-06-2011
20120087192Non-Volatile Memory Device with Program Current Clamp and Related Method - A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.04-12-2012
20120092932PROGRAMMING METHODS AND MEMORIES - Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.04-19-2012
20100202211NONVOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE SAME - Provided are a nonvolatile memory device and a method for programming the same. The method for programming the nonvolatile memory device includes programming at least one memory cell of the nonvolatile memory device by repeating program loops. A first self-boosting method is applied to at least one of the program loops and a second self-boosting method, different from the first self-boosting method, is applied to at least one other of the program loops.08-12-2010
20120140569MEMORY CELL OPERATION - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.06-07-2012
20120140567NAND STEP UP VOLTAGE SWITCHING METHOD - Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.06-07-2012
20130016564ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICESAANM Ferragina; VincenzoAACI San Genesio ed Uniti (PV)AACO ITAAGP Ferragina; Vincenzo San Genesio ed Uniti (PV) ITAANM Surico; StefanoAACI Bussero (MI)AACO ITAAGP Surico; Stefano Bussero (MI) ITAANM Moioli; GiuseppeAACI Albino (BG)AACO ITAAGP Moioli; Giuseppe Albino (BG) ITAANM Bartoli; SimoneAACI Mandello del Lario (LC)AACO ITAAGP Bartoli; Simone Mandello del Lario (LC) IT - Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.01-17-2013
20120243324NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a certain write voltage to the word line multiple times to set a threshold voltage of the memory cell to a value corresponding to data. The control circuit is configured to control the write voltage such that the write voltage is increased by a first step-up voltage when the write voltage is repeatedly applied in a first period after the write operation starts, and the write voltage is increased by a second step-up voltage lower than the first step-up voltage in a second period after the first period.09-27-2012
20120243323Nonvolatile Memory and Method for Improved Programming With Reduced Verify - A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V09-27-2012
20080225595CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.09-18-2008
20110261624DATA LINE MANAGEMENT IN A MEMORY DEVICE - Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.10-27-2011
20130176789MEMORY ARRAY AND METHOD FOR PROGRAMMING MEMORY ARRAY - A method for programming a memory array is provided. The memory array includes a memory cell string composed of a first transistor, a plurality of memory cells and a second transistor connected in series, and the method for programming the memory array includes following steps. In a setup phase, a switching memory cell in the memory cells is turned off, and a first voltage and a second voltage are applied to a first source/drain and a second source/drain of the switching memory cell. In a programming phase, a bit line connected to the memory cell string is floating, and a ramp signal is provided to a word line electrically connected to the switching memory cell.07-11-2013
20120250418Natural Threshold Voltage Distribution Compaction In Non-Volatile Memory - In a non-volatile memory system, a multi-phase programming operation is performed in which a drain-side select gate voltage (Vsgd) can be adjusted in different programming phases to accommodate different bit line bias (Vbl) levels. A higher Vbl can be used when Vsgd is higher to avoid unnecessary stress on the SGD transistor and reduce power consumption. For example, Vsgd can be higher in an earlier program phase than in a later program phase. The higher Vbl, which is not based on programming speed, can be is applied when the Vth of a storage element is between lower and upper verify levels of target data states, or throughout a programming phase, or at other times. The higher Vbl is an additional slow down measure which can be implemented in addition to a programming speed-based slow down measure such as a further raised Vbl which is applied to faster-programming storage elements.10-04-2012
20130135937PROGRAMMING MEMORY CELLS USING SMALLER STEP VOLTAGES FOR HIGHER PROGRAM LEVELS - Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.05-30-2013
20080247236PROGRAM METHOD OF FLASH MEMORY DEVICE - A method for operating a flash memory device includes applying a first program voltage Vp10-09-2008
20110216600DRAIN SELECT GATE VOLTAGE MANAGEMENT - Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.09-08-2011
20080198661NON-VOLATILE STORAGE APPARATUS WITH VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process include programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process.08-21-2008
20110235427Channel Hot Electron Injection Programming Method and Related Device - A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.09-29-2011
20110249507SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.10-13-2011
20110255341PROGRAMMING METHODS FOR A MEMORY DEVICE - Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a final target programmed state where the partial programming is verified by applying a ramped voltage having a first voltage range (e.g., where the first voltage range is selected in response to program coupling effects from memory cells adjacent to the target memory cell.) A programming operation following the partial programming operation is performed on one or more adjacent memory cells which is then followed by additional programming of the target memory cell to adjust the memory cell from the partially programmed state to the final programmed state. A ramped voltage having a second voltage range different from the first voltage range is utilized to verify the programming of the target memory cell to the final programmed state.10-20-2011
20100290289OPERATING MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells are coupled between the edge cells. The method includes programming a non-edge cell within a first threshold voltage (Vt) distribution. The method also includes programming an edge cell within a second Vt distribution, wherein the first and second Vt distributions correspond to a same one of a number of data states, and wherein the second Vt distribution is different than the first Vt distribution for at least one of the number of data states.11-18-2010
20120275233SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE - Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.11-01-2012
20120275232SEMICONDUCTOR DEVICE AND ERASE METHODS THEREOF - An erase method of a semiconductor device includes performing an operation comprised of supplying an erase pulse to erase the memory cells of a memory block, performing an erase verify operation for detecting memory cells of the memory block having threshold voltages dropped to a target erase voltage, from among the memory cells, performing a pre-program operation on the memory cells having the threshold voltages dropped to the target erase voltage, if, as a result of the erase verify operation, the memory block comprises memory cells having the threshold voltages higher than the target erase voltage and the memory cells having the threshold voltages dropped to the target erase voltage, and repeating the operation of supplying an erase pulse, the erase verify operation, and the pre-program operation until the threshold voltages of all the memory cells drop to the target erase voltage.11-01-2012
20120275231METHOD, APPARATUS, AND MANUFACTURE FOR FLASH MEMORY WRITE ALGORITHM FOR FAST BITS - A method, apparatus, and manufacture for a memory device is provided. The memory device includes memory cells that each store two bits, and a memory controller. During write operations, for each bit in each memory cell that is to be programmed, the memory controller determines whether both bits of the memory cell are being programmed. While controlling an application of programming pulses to the memory cell to program the bit, if both bits of the memory cell are being programmed, the memory controller causes the application of each programming pulse to the bit to occur for a standard duration. Otherwise, the memory controller causes the application of each programming pulse to the bit to occur for a reduced duration. The reduced duration is less than three-fourths of the standard duration.11-01-2012
20130176790Charge Cycling By Equalizing the Source and Bit Line Levels Between Pulses During No-Verify Write Operations for NAND Flash Memory - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.07-11-2013
20120281480SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.11-08-2012
20120281479Detection of Broken Word-Lines in Memory Arrays - Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.11-08-2012
20110286280Pulse Control For NonVolatile Memory - This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.11-24-2011
20110310672Threshold Voltage Digitizer for Array of Programmable Threshold Transistors - A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as the ramp voltage is being applied, generating a respective control signal in response to sensing a predetermined threshold current along a respective bitline in the memory array, wherein each transistor in the memory array is in communication with a respective bitline in the memory array; and for each transistor in the memory array, latching a current value of the incrementing digital code in response to the respective control signal corresponding to the transistor being generated. The current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor.12-22-2011
20110310671REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING - A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.12-22-2011
20120020166NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In one embodiment, a nonvolatile semiconductor storage device includes a plurality of memory cells, and a setting part in which a setting value for prescribing a relation between a program voltage to be applied to the memory cells and a loop number of application processes of the program voltage is set to change the program voltage according to the loop number. The device further includes a voltage controller configured to program data into the memory cells by applying the program voltage depending on the loop number to the memory cells, using the setting value. The device further includes a counter configured to count a maximum value or an average value of final loop numbers in the memory cells, where the final loop numbers are loop numbers in the respective memory cells at time when data programming is completed. The device further includes a setting change part configured to, in response to a change of the counted maximum value or average value from a predetermined maximum value or average value, perform a setting process for canceling the change of the maximum value or average value.01-26-2012
20130194875STRUCTURE AND METHOD FOR HEALING TUNNEL DIELECTRIC OF NON-VOLATILE MEMORY CELLS - A semiconductor device comprises an array of memory cells. Each of the memory cells includes a tunnel dielectric, a well region including a first current electrode and a second current electrode, and a control gate. The first and second current electrodes are adjacent one side of the tunnel dielectric and the control gate is adjacent another side of the tunnel dielectric. A controller is coupled to the memory cells. The controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric.08-01-2013
20090290424METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES - Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.11-26-2009
20120081970SEMICONDUCTOR MEMORY APPARATUS AND PROGRAM VERIFICATION METHOD - A non-volatile memory apparatus includes a memory cell array, a power supply configured to generate an operation voltage according to an operation mode and provide the memory cell array with the operation voltage, and a controller configured to provide the memory cell array with a first verification voltage and a second verification voltage in a program verification operation, detect a high speed program cell by the first verification voltage and the second verification voltage from selected memory cells to be programmed and set the high speed program cell to be in a program inhibition state, and detect a low speed program cell by the second verification voltage.04-05-2012
20130208543NON-VOLATILE MEMORY DEVICE AND ISPP PROGRAMMING METHOD - A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition.08-15-2013

Patent applications in class Multiple pulses (e.g., ramp)