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365 - Static information storage and retrieval

365185010 - FLOATING GATE

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Class / Patent application numberDescriptionNumber of patent applications / Date published
365185110 Bank or block architecture 395
365185170 Logic connection (e.g., NAND string) 294
365185090 Error correction (e.g., redundancy, endurance) 133
365185080 With volatile signal storage device 70
365185140 Program gate 38
365185160 Virtual ground 11
365185100 Extended floating gate 5
20100157669Floating Gate Inverter Type Memory Cell And Array - A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell. In this case, the NMOS inverter transistor functions as a tunneling capacitor for programming and erasing the cell, and the PMOS inverter transistor functions as a tunneling capacitor for erasing the cell.06-24-2010
20120236635Logic-Based Multiple Time Programming Memory Cell - A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.09-20-2012
20090207655MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE - A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.08-20-2009
20080232162One time programming cell structure and method of fabricating the same - A One Time Programming (OTP) cell structure, a method of fabricating an OTP structure, and a method of programming a OTP cell structure. The OTP structure comprises a semiconductor substrate; an n Metal-Oxide-Semiconductor (nMOS) programming structure formed on the substrate; wherein respective electrical contacts to a source of the nMOS programming structure and to a p-bulk of the substrate are separated for individual biasing of the source and the p-bulk of the substrate.09-25-2008
20110157972FTP MEMORY DEVICE PROGRAMMABLE AND ERASABLE AT CELL LEVEL - An embodiment of non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory includes at least one sector of a plurality of memory cells; each sector includes a storage region of a first type of conductivity and a further storage region of a second type of conductivity. Each memory cell includes a first region and a second region of the second type of conductivity, which are formed in the storage region for defining a storage transistor of floating gate MOS type of the first type of conductivity; the memory cell likewise includes a further first region and a further second region of the first type of conductivity, which are formed in the further storage region for defining a further storage transistor of floating gate MOS type of the second type of conductivity. The memory cell also includes a common floating gate of the storage transistor and the further storage transistor. The memory device further includes programming means for programming each memory cell individually by programming the corresponding floating gate through the corresponding storage transistor, and erasing means for erasing each memory cell individually by erasing the corresponding floating gate through the corresponding further storage transistor.06-30-2011
365185070 Cross-coupled cell 3
20090147577NON-VOLATILE SEMICONDUCTOR LATCH USING HOT-ELECTRON INJECTION DEVICES - The invention concerns semiconductor latches capable of memorizing any programmed information even after power supply has been removed. Used is a 0.6 m BiCMOS EPROM process but it is applicable in any other process having hot electron injection devices like EPROM, Flash EEPROM. Suggested is a bi-stable latch circuit having a pair of cross-coupled branches (I,II), each branch including a complementary driver and a load connected between a drain line and a source line and a non-volatile memory cell having a program transistor and a read transistor, at least one of said drivers and loads including said read transistor, said driver and load of said branch connected in series at a respective output node, said read transistor and program transistor having a common floating gate and separate control gates, said control gate of said program transistor connected to a program voltage, the drain of said program transistor connected to a respective input node, said control gate of said read transistor in said branch connected to said output node of the other branch (II).06-11-2009
20090003063METHOD AND DEVICE FOR DEMULTIPLEXING A CROSSBAR NON-VOLATILE MEMORY - A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.01-01-2009
20110002167PUSH-PULL PROGRAMMABLE LOGIC DEVICE CELL - A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a source, and a drain. A stress transistor has a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit. Where one of the first or second potentials is a bit line, an isolation transistor is coupled between the other of the second potentials and one of the non-volatile transistors.01-06-2011
365185060 Segregated columns 1
20110267882MEMORY ARRAY WITH INVERTED DATA-LINES PAIRS - At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.11-03-2011
Entries
DocumentTitleDate
20090168517Read and volatile NV standby disturb - A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.07-02-2009
20110194349NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a nonvolatile semiconductor memory device includes a substrate provided with a memory cell part and sense amplifiers on a surface of the substrate, first isolation regions and first device regions disposed in the substrate under the memory cell part, and second isolation regions and second device regions disposed in the substrate under the sense amplifiers. The device further includes a plurality of interconnects disposed on the substrate in the sense amplifiers, extending in a first direction parallel to the surface of the substrate, being adjacent to one another in a second direction perpendicular to the first direction, and arranged in the same interconnect layer. At least one of the second device regions includes first and second stripe portions extending in the first direction, being adjacent in the second direction, and having stripe shapes, and a connecting portion disposed to connect the first stripe portion and the second stripe portion. The device further includes a source contact disposed on the connecting portion, and electrically connected to one of the interconnects.08-11-2011
20090122609SEMICONDUCTOR DEVICE - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.05-14-2009
20100008141Strap-Contact Scheme for Compact Array of Memory Cells - A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the array. The strap-contact corridor comprises strap-contact cells, which provide electrical interconnection between control-gate lines, erase gate lines, common-source lines, and word-lines and their respective straps.01-14-2010
20130077401SEMICONDUCTOR MEMORY DEVICE - A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.03-28-2013
20100046291Process and Temperature Tolerant Non-Volatile Memory - A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.02-25-2010
20100103736NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.04-29-2010
20090237995Scaleable memory Systems Using Third Dimension Memory - A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays and optionally a control node that allows data access to be controlled by an external memory controller or by the embedded controller. The memory circuits can be chained together to increase memory capacity. The memory arrays can be two-terminal cross-point arrays that may be stacked upon one another.09-24-2009
20090154240NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction06-18-2009
20090154241NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.06-18-2009
20100329008NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a Y decoder unit comprising decoders, each selecting one or more of the page buffers in response to address signals and outputting a first or second control signal to the selected page buffers in response to the operation mode; a mode selection unit outputting first and second operation selection signals for selecting the operation mode; and an I/O control unit comprising I/O control circuits, each detecting data, inputted and output through the first and second I/O lines, and outputting the detected data or coupling one of the first and second I/O lines to a data line.12-30-2010
20120182801Memory Architecture of 3D NOR Array - A 3D memory device includes a plurality of ridge-shaped stacks of memory cells. Word lines are arranged over the stacks of memory cells. Bit lines structures are coupled to multiple locations along the stacks of memory cells. Source line structures are coupled to multiple locations along each of the semiconductor material strips of the stacks. The bit line structures and the source line structures are between adjacent ones of the word lines.07-19-2012
20130051142MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE - Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device.02-28-2013
20080316821NONVOLATILE STORAGE DEVICE AND BIAS CONTROL METHOD THEREOF - A nonvolatile storage device having a memory cell array composed of a plurality of memory cells. The plurality of memory cells include a bit line to which the drain terminals of the plurality of memory cells that have noncovalent connected gate terminals are commonly connected and a source line to which the source terminals of the plurality of memory cells that have commonly connected gate terminals are commonly connected and which extend perpendicularly to the bit line. The memory cell also includes a first source selector switch for connecting the source line to a source bias line.12-25-2008
20090040824SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of a word lines. The word lines have a set of odd word lines and a set of even word lines. The odd and the even word lines are located from a first end region to a second end region through the cell region located between the first and the second end regions. The odd word lines are divided in the first end region and the even word lines are divided in the second end region to form dummy word line portions.02-12-2009
20090091976Integrated Circuit with Switching Unit for Memory Cell Coupling, and Method for Producing an Integrated Circuit for Memory Cell Coupling - An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.04-09-2009
20090091975Non-volatile memory device and operation method of the same - Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor.04-09-2009
20090290416NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire connected to a cell well line of a memory cell, a third wire which supplies a power supply voltage to a circuit arranged outside of a region of the cell array, a fourth wire and a fifth wire being arranged in a row direction within the cell array region, and the first wire, the second wire and the third being formed in a layer above a layer in which the bit line within the cell array is formed, the fourth wire and the fifth wire being formed in the layer in which the bit line within the cell array region is formed.11-26-2009
20090279357NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF TESTING THE SAME - A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.11-12-2009
20120224424NONVOLATILE MEMORY DEVICE, METHOD FOR FABRICATING THE SAME, AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes bit and source lines alternately arranged parallel to each other and even strings and odd strings alternately arranged between the bit lines and the source lines and each including drain selection transistors, memory transistors, and a source selection transistor. The drain selection transistors include a first drain selection transistor with the same structure as the memory transistors and a second drain selection transistor with the same structure as the source selection transistor. The nonvolatile memory device further includes an even drain selection line connected to the first drain selection transistors of the even strings and the second drain selection transistors of the odd strings and an odd drain selection line connected to the second drain selection transistors of the even strings and the first drain selection transistors of the odd strings.09-06-2012
20090231916NON-VOLATILE MEMORY DEVICE - A non-volatile memory device increases a number of word lines and a storage capacity using a multi level cell. The non-volatile memory device addresses a problem of self-boosting not being adequately generated due to the increased number of word lines. The non-volatile memory device includes a memory cell array configured to have first memory cells for storing first bit information coupled to third word lines except a first word line adjacent to a drain select line and a second word line adjacent to a source select line, and second memory cells coupled to the first word line and the second word line. The second memory cells store second bit information that is smaller than the first bit information.09-17-2009
20090010062Bit line decoder architecture for NOR-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes R first sub-decoders, R isolation circuits, a second sub-decoder, and a sensing circuit. The R first sub-decoders communicate with R memory sub-arrays of the memory array, respectively, where R is an integer greater than 1. The R isolation circuits each have first ends that communicate with the R first sub-decoders, respectively, and second ends. The second ends of a first of the R isolation circuits communicate with corresponding the second ends of (R-01-08-2009
20090010061Bit line decoder architecture for NOR-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes a first sub-decoder, a control module, and an isolation circuit. The first sub-decoder is adjacent to the memory array and includes D control devices arranged in a first of two levels of the bit line decoder. The D control devices selectively communicate with a first set of S of B bit lines of the memory array, where log01-08-2009
20090010059Memory Arrangement, Particularly for the Non-Volatile Storage of Uncompressed Video and/or Audio Data - When recording uncompressed video and/or audio data using a digital video recorder, there is the need for a robust memory arrangement based on non-volatile, integrated circuits which is able to be fitted directly on the video camera without a long external cable connection and which is also able to be used for shots under difficult conditions, particularly action shots. The inventive memory arrangement involves the use of a number of non-volatile memory chips which are connected together with a favorable level of circuit complexity. To be able to cope with the high data rate for the incoming video and/or audio data, a plurality of parallel supply buses are provided. Each supply bus has an associated number of memory chips. In this case, the memory word length of the memory chips is greater than the bus width of a data/address bus. A supply bus with high-quality multiplexing has a respective associated number of demultiplexer/driver circuits which match the bus width of the supply bus to the memory word length of the memory chips. There are respectively as many downstream memory chips per demultiplexer/driver circuit as prescribed by a value X, the value X being limited by the memory technology used, namely by the maximum number of circuits which can be connected, also called the “fan-out” value. The memory chips used are preferably NAND Flash EPROM memory chips.01-08-2009
20080298125SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including an element region which is surrounded by an element isolation insulation layer, a transistor including a gate electrode which is provided on the element region, and a source region and a drain region which are provided in the first element region, a first auxiliary wiring layer and a second auxiliary wiring layer which extend in a channel length direction and are provided on the element isolation insulation layer such that the first transistor is interposed between the first auxiliary wiring layer and the second auxiliary wiring layer, and a control circuit which sets, while the first transistor is in an ON state, the first auxiliary wiring layer and the second auxiliary wiring layer at a first voltage of the same polarity as a gate voltage of the first transistor that is in the ON state.12-04-2008
20120236642INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.09-20-2012
20100027334EEPROM CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT - An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.02-04-2010
20110128786MEMORY DEVICE - A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.06-02-2011
20100265769SEMICONDUCTOR MEMORY DEVICE - An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.10-21-2010
20090251963Non-volatile memory device and method of manufacturing the same - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.10-08-2009
20090147576FLOATING GATE WITH UNIVERSAL ETCH STOP LAYER - Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.06-11-2009
20100128531NONVOLATILE NAND-TYPE MEMORY DEVICES INCLUDING CHARGE STORAGE LAYERS CONNECTED TO INSULATING LAYERS - A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.05-27-2010
20090141554MEMORY DEVICE HAVING SMALL ARRAY AREA - Memory arrays can be implemented including word lines connected to memory transistors and corresponding select transistors. Each memory transistor is also connected to an array select transistor. Each select transistor is also connected to a bit line. The memory transistors are arranged such that they define bytes of data. A well line is connected to each portion of the semiconductor substrate that defines an array of bytes.06-04-2009
20090310410NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.12-17-2009
20090016107Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.01-15-2009
20100128530FLASH MEMORY DEVICE AND LAYOUT METHOD OF THE FLASH MEMORY DEVICE - Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation. A first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.05-27-2010
20090080254Gated Diode Nonvolatile Memory Cell Array - A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.03-26-2009
20120033495SEMICONDUCTOR DEVICE - A semiconductor device is provided which comprises a nonvolatile memory capable of storing complementary data and performing a more accurate blank check than ever before.02-09-2012
20100080058SEMICONDUCTOR DEVICE - The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.04-01-2010
20090201729Memory device and memory device heat treatment method - A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.08-13-2009
20090109752MEMORY CELL HEIGHTS - Embodiments of the present disclosure provide methods, arrays, devices, modules, and systems for memory cell heights. One array of memory cells includes a number of semiconductor pillars having a number of charge storage nodes, each of the charge storage nodes being associated with a respective number of pillars and separated from the respective pillars by a dielectric. The array also includes a number of conductively coupled gates, each of the number of gates being associated with a respective one of the number of storage nodes. At least two pillars in the array have different heights.04-30-2009
20090296470NONVOLATILE MEMORY - A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which are connected in series. A gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the second word line, one of source and drain regions of the first memory transistor is connected to the first bit line, and one of source and drain regions of the second memory transistor is connected to the second bit line. Each of the first bit line and the second bit line is provided in common for memory cells in columns which are adjacent to each other.12-03-2009
20120170368NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a nonvolatile memory device and a method for fabricating the same, which can secure the structural stability of a three-dimensional nonvolatile memory device. The nonvolatile memory device includes one or more columnar channel plugs, a plurality of word lines and a plurality of dielectric layers stacked alternately to surround the columnar channel plug, a memory layer disposed between the word line and the columnar channel plug, a plurality of word line connection portions, each of the word line connection portions connecting ends of word lines of a common layer from among the plurality of word lines, and a plurality of word line extension portions extending from the word line connection portions.07-05-2012
20090003059SEGMENTED BIT LINE FOR FLASH MEMORY - A memory device including segmented bit lines with memory cells coupled to a data cache is provided. A segmented bit line includes a bias transistor to selectively connect the bit line to a source line. Further, a physical implementation showing a segmentation pattern of the memory device is also provided.01-01-2009
20090003061Select gate transistors and methods of operating the same - Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate, a control gate, and a dielectric disposed between the floating gate and the control gate. Such a memory array also includes a plurality of select gates, wherein each select gate is coupled to each of the plurality of columns and each select gate includes a floating gate, a control gate, and an inter-gate dielectric layer. Each select gate of such a memory array also includes a switch electrically coupled between the floating gate and the control gate of the select gate and configured to switchably couple the floating gate and control gate of the select gate.01-01-2009
20110205795MEMORY DEVICE - With a serial interface memory device of this invention, a read-out rate of data is increased, while an increase in a size of a circuit is suppressed. An EEPROM is provided with a memory cell array storing data, a row address decoder and a column address decoder that select an address of the memory cell array in accordance with an address signal serially inputted in synchronization with a clock, sense amplifiers SA08-25-2011
20090168518CHIP SELECT CONTROLLER AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME - A chip select controller for a non-volatile memory device includes a first chip enable signal transfer unit, a second chip enable signal transfer unit, a first chip select pad, a second chip select pad, a third chip select pad and a chip select unit. The first chip enable signal transfer unit buffers first and second chip enable signals according to a control signal. The second chip enable signal transfer unit buffers third and fourth chip enable signals according to the control signal. The first chip select pad is configured to transfer a first chip select signal. The second chip select pad is configured to transfer a second chip select signal. The third chip select pad is configured to transfer the second chip select signal. The chip select unit addresses a specific chip according to the first chip select signal and the second chip select signal.07-02-2009
20080279002METHODS OF READING DATA INCLUDING COMPARING CURRENT AND PREVIOUS SECTION ADDRESSES AND RELATED DEVICES - A memory device may include a memory cell array arranged in a plurality of sections of memory cells, with each section of memory cells including a plurality of sub-sections of memory cells. Operation of the memory device may include providing a current memory address for a current read operation from a controller, and the current memory address may include a current section address portion and a current sub-section address portion. The current section address portion and a previous section address portion of a previous read operation may be compared. When the current and previous section address portions are different, a wait signal may be enabled at the controller. While enabling the wait signal at the controller, a section of data may be copied from the memory cell array to a section buffer, with the section of data being copied from a section of memory cells defined by the current section address portion of the current memory address. After copying the section of data to the section buffer, a sub-section of the data from the section of data in the section buffer may be transmitted to the controller. Related systems and devices are also discussed.11-13-2008
20080291725Memory cell array and semiconductor memory - A memory cell array includes a plurality of memory cells disposed in matrix, a plurality of word lines extending to the column direction wherein the gates in the memory cells disposed in each column are commonly connected to one of the word lines, a plurality of sub bit lines extending to the row direction wherein the source in the memory cells disposed in a first row and the drain in the memory cells disposed in a second row, which is adjacent to the first row, are commonly connected to one of the sub bit lines, and a plurality of pairs each having a source selector and a drain selector wherein each pair is disposed at one of the locations, which sandwich the word lines, alternatively, and which are located at both ends of the sub bit lines, which are adjacent to each other.11-27-2008
20080247231NAND FLASH MEMORY DEVICE - A NAND flash memory device includes: a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells; a plurality of word lines that are connected to the plurality of memory cells; a plurality of bit lines that are connected to the plurality of memory cells; and a read-write control section that applies a voltage selectively to the plurality of word lines and the plurality of bit lines, wherein each of the plurality of NAND memory cell units includes a first select gate transistor and a second select gate transistor; and wherein the read-write control section sets an voltage level applied to word lines, so that the voltage level becomes lower than a predetermined voltage level applied to other word lines connected to control gate electrodes of memory cells.10-09-2008
20080253183SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.10-16-2008
20080279003MULTIPLE INDEPENDENT SERIAL LINK MEMORY - An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.11-13-2008
20080266951NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD - A non-volatile memory device, related memory system, and program method for the non-volatile memory device are disclosed. In the method, memory cells in a memory cell array are accessed through a plurality of word lines by applying a program voltage to a selected word line, wherein the selected word line is not adjacent to an outmost word line, applying a first reduced pass voltage to word lines adjacent to the selected word line, and applying a second reduced pass voltage to the outermost word lines.10-30-2008
20090310409Nonvolatile Semiconductor Memory - A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.12-17-2009
20080266954Transition areas for dense memory arrays - A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.10-30-2008
20080266953SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE - A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.10-30-2008
20080266952MEMORY ARRAY ARCHITECTURE FOR A MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY ARRAY ARCHITECTURE - A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.10-30-2008
20090027965ROW SELECTOR CIRCUIT FOR ELECTRICALLY PROGRAMMABLE AND ERASABLE NON VOLATILE MEMORIES - The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.01-29-2009
20090027964SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL WORD LINES ARRANGED AT NARROW PITCH AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n−1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines.01-29-2009
20090161427NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.06-25-2009
20120069655NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.03-22-2012
20090010060Bit line decoder architecture for nor-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes D control devices and a control module. The D control devices selectively communicate with (D−1) bit lines of the memory array and are arranged in first and second levels of the bit line decoder. (D−2) of the D control devices are arranged in the first level, and two of the D control devices are arranged in the second level. log01-08-2009
20090040823FLASH MEMORY - A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash memory. The sawtooth gate conductor line results in select gate transistors having different select gate lengths and produces at least one depletion-mode select transistor at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.02-12-2009
20090251965NONVOLATILE MEMORY DEVICE INCLUDING CIRCUIT FORMED OF THIN FILM TRANSISTORS - A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.10-08-2009
20090052245CMOS Logic Compatible Non-Volatile Memory Cell Structure, Operation, And Array Configuration - The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance with the present invention comprises a program transistor with a program transistor source as a first program terminal; a select transistor with a select transistor gate as a select terminal and a select transistor drain as a second program terminal; and an erase transistor with an erase transistor source and an erase transistor drain connected as an erase terminal, wherein the erase transistor shares a floating gate with the program transistor and the drain program transistor is connected to the select transistor source. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided.02-26-2009
20090086540METHOD OF OPERATING NON-VOLATILE MEMORY ARRAY - A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-−2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation.04-02-2009
20090190401Memory device employing NVRAM and flash memory cells - A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows, which may correspond to page units including flash memory cells and NVRAM cells.07-30-2009
20090251964NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to the present invention is a NAND-type flash memory which is electrically capable of programming/erasing. The nonvolatile semiconductor memory device has at least 3 or more memory cell columns in which a plurality of memory cells are connected in series, and these memory cell columns are adjacent to each other via a shallow trench isolation. And, a programming operation is performed individually to each of these memory cell columns. In this manner, a programming-prevent voltage is surely provided at on at least one side of both surfaces of the semiconductor substrate which are adjacent via a shallow trench isolation to the surface of the semiconductor substrate under the programming-prevented memory cell. Therefore, a miss-programming to an unselected memory cell can be largely reduced.10-08-2009
20090129161Nonvolatile Memory Devices that Support Virtual Page Storage Using Odd-State Memory Cells - A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of physical memory cells, respectively, and collectively as an additional block of virtual memory cells. The first and second blocks of memory cells and the additional block of virtual memory cells may be read independently to provide a total of three blocks of read data.05-21-2009
20100149873PUSH-PULL FPGA CELL - A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.06-17-2010
20100014353FLASH MEMORY DEVICE WITH SWITCHING INPUT/OUTPUT STRUCTURE - In a flash memory device with switching I/O structure for applying in flash memory products, depending on actual need for input and/or output pins, other pins may be flexibly switched to input, output, or bi-directional pins through software and/or hardware and/or CAM access. Therefore, data input and/or output rate may be changed through switching the I/O structure. Moreover, after the I/O configuration, the switched other pins may start data input/output immediately after the flash memory is started to operate, without the need of waiting for several input/output phases.01-21-2010
20120195121NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.08-02-2012
20100259981Trap-charge non-volatile switch connector for programmable logic - A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.10-14-2010
20100188900ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS - An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.07-29-2010
20090046511REGULATION OF BOOST-STRAP NODE RAMP RATE USING CAPACITANCE TO COUNTER PARASITIC ELEMENTS IN CHANNEL - Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read operations within a desired period of time. Each sector can be associated with a decoder subcomponent and associated regulator subcomponent. Parasitic resistance and capacitance elements can increase the further in distance a sector and associated decoder component are from a booster component, which is utilized to increase the voltage at a boost-strap node within each decoder subcomponent to facilitate performing read operations. To counter the parasitic elements, each regulator subcomponent can include one or more capacitors, where the number of capacitors and total capacitance value can be determined based on the distance the associated decoder subcomponent is from the booster component.02-19-2009
20080279001OPERATING METHOD OF NON-VOLATILE MEMORY - A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed on the substrate and a first gate dielectric layer disposed between the gate and the substrate. The memory cell includes a pair of floating gate disposed on the substrate, a control gate disposed on the upper surface of the floating gates, an inter-gate dielectric layer disposed between the floating gate and the control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a second gate dielectric layer disposed between the bottom of the control gate and the substrate.11-13-2008
20100238727NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.09-23-2010
20110110155STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE - A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).05-12-2011
20100254190NONVOLATILE MEMORY DEVICE HAVING DIFFERENT TYPES OF METAL LINES - Provided is a nonvolatile memory device, including a memory cell array region, a decoder and an interface region. The memory cell array region includes multiple word lines. The decoder supplies multiple voltages to the word lines through multiple first type metal lines formed of a first metal and multiple second type metal lines formed of a second metal. The interface region connects the first type metal lines to first word lines in a first group, and connects the second type metal lines to second word lines in a second group. The first type metal lines are sequentially disposed to correspond with a positioning order of the first word lines in the first group, and the second type metal lines are sequentially disposed to correspond with a positioning order of the second word lines in the second group.10-07-2010
20110058419MULTI-CHIP ASSEMBLY WITH OPTICALLY COUPLED DIE - Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.03-10-2011
201100584183D NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction.03-10-2011
20100254191SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY - A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.10-07-2010
20090116284MEMORY APPARATUS AND METHOD THEREOF FOR OPERATING MEMORY - A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced.05-07-2009
20090273976SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.11-05-2009
20100195391SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M08-05-2010
20120243315SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.09-27-2012
20120243314NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate. The plurality of first conductive layers are electrically connected to gates of the memory cells. The second conductive layer is electrically connected to a gate of the dummy transistor. The third conductive layer is electrically connected to a gate of the back gate transistor. The second conductive layer is short-circuited with the third conductive layer.09-27-2012
20110032763SEMICONDUCTOR DEVICES INCLUDING FIRST AND SECOND BIT LINES - In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line.02-10-2011
20080310228Memory with correlated resistance - Methods, systems, and devices are disclosed, such as a method of operating a memory device. In certain embodiments, such a method includes writing a plurality of data values to a plurality of data locations. The plurality of data locations may be coupled to one another in a series, and the plurality of data values may be sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.12-18-2008
20100220527Non-volatile FIFO with third dimension memory - A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that require non-volatile data storage can also be implemented as registers or the like using the BEOL non-volatile third dimension memory cells so that power to the FIFO can be cycled and data is retained. The BEOL non-volatile third dimension memory cells can be configured in a single layer of memory or in multiple layers of memory. An IC that includes the FIFO can also include one or more other memory types that are emulated using the BEOL non-volatile third dimension memory cells and associated FEOL circuitry configured for data operations on those memory cells.09-02-2010
20090109753NONVOLATILE SEMICONDUCTOR MEMORY - A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories.04-30-2009
20080291726BANDGAP ENGINEERED SPLIT GATE MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.11-27-2008
20080266949INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES - A floating gate memory cell's channel region (10-30-2008
20100302848TRANSISTOR HAVING PERIPHERAL CHANNEL - Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel region is formed around a perimeter of the source/drain region. Such transistors should facilitate a reduction in edge effect and leakage as the channel of the transistor is not bordering on an isolation region. Additionally, the use of a source/drain region extending through a channel region facilitates high-power, high-voltage operation.12-02-2010
20100309723SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.12-09-2010
20100309722SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.12-09-2010
20100322002EEPROM DEVICE - An EEPROM device which prevents disturbance phenomena when writing data on a memory cell. The device includes an on/off switch element for selectively connecting between an individual source line and a common source line in response to a control signal supplied via a control terminal.12-23-2010
20110249498THREE-DIMENSIONALLY STACKED NONVOLATILE SEMICONDUTOR MEMORY - A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.10-13-2011
20110019473MEMORY ARRAY AND METHOD OF OPERATING ONE OF A PLURALITY OF MEMORY CELLS - An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.01-27-2011
20120134209Single-Transistor EEPROM Array and Operation Methods - A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.05-31-2012
20110044107Nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device has a drawing wiring drawn out from one end of a gate electrode and connected to a terminal, and has another drawing wiring drawn out from the other end of the gate electrode and connected to a terminal. Lengths of the two drawing wirings are set different from each other.02-24-2011
20110044108FLASH MEMORY DEVICE AND PROGRAM METHOD OF FLASH MEMORY DEVICE USING DIFFERENT VOLTAGES - A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.02-24-2011
20100149874NON-VOLATILE MEMORY APPARATUS AND METHOD WITH DEEP N-WELL - An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.06-17-2010
20090016108NONVOLATILE SEMICONDUCTOR MEMORY - A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.01-15-2009
20090016106SUB VOLT FLASH MEMORY SYSTEM - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.01-15-2009
20110249497STACKED PACKAGE OF SEMICONDUCTOR DEVICE - Provided is a nonvolatile memory device. The nonvolatile memory device includes a substrate including a first region and a second region, which are spaced from each other. A string line group is disposed on the substrate in the first region, and a bias interconnection group is disposed above the substrate in the second region. The bias interconnection group includes a string select bias interconnection, cell bias interconnections, and a ground select bias interconnection, which are respectively electrically connected to a string select line, word lines, and a ground select line within the string line group. The string select bias interconnection is disposed between the ground select bias interconnection and the cell bias interconnections within the bias interconnection group.10-13-2011
20110249499Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.10-13-2011
20090213655MEMORY SYSTEM WITH USER CONFIGURABLE DENSITY/PERFORMANCE OPTION - The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the desired memory performance and/or memory density. The user configurable density/performance option can be adjusted with special read/write operations or a configuration register having a memory density configuration bit for each memory block.08-27-2009
20110075481NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.03-31-2011
20120147673SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.06-14-2012
20120201079SEMICONDUCTOR MEMORY DEVICE IN WHICH CAPACITANCE BETWEEN BIT LINES IS REDUCED, AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first bit lines and second bit lines are arranged in different layers.08-09-2012
20090016105NONVOLATILE MEMORY UTILIZING MIS MEMORY TRANSISTORS CAPABLE OF MULTIPLE STORE OPERATIONS - A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.01-15-2009
20100097858THREE-DIMENSIONALLY STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.04-22-2010
20100097859Nonvolatile memory device - A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.04-22-2010
20080247232SEMICONDUCTOR STORAGE DEVICE AND ELECTRONIC EQUIPMENT THEREFOR - A semiconductor storage device includes a first memory cell for storing two kinds of states, a second memory cell for storing two kinds of states, and a sense amplifier for detecting a potential difference between voltages equivalent to readout currents of the first and second memory cells, respectively. Either one of information data “0” or data “1”, which is stored in combination of the first and second memory cells, is read out by detecting the potential difference equivalent to the readout current difference between the first and second memory cells.10-09-2008
20090021981NONVOLATILE MEMORY DEVICE INCLUDING CIRCUIT FORMED OF THIN FILM TRANSISTORS - A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.01-22-2009
20080285346Decoder, memory system, and physical position converting method thereof - A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.11-20-2008
20080285345SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.11-20-2008
20080285344Integrated Circuits; Methods for Manufacturing an Integrated Circuit; Memory Modules; Computing Systems - Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.11-20-2008
20080266950DATA PATH CIRCUIT IN A FLASH MEMORY DEVICE - A data output circuit in an NAND flash memory device is disclosed. The data path circuit in a flash memory includes at least one switching means configured to output one or more internal address signals in accordance with a data output control signal, and one or more data output circuit configured to output data when a specific internal address signal is outputted through the switching means.10-30-2008
20080247230Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout - A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.10-09-2008
20080205145MEMORY CONTROLLER CONTROLLING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DEVICE - A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.08-28-2008
20110134695SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.06-09-2011
20100284221Nonvolatile memory device and method for controlling word line or bit line thereof - A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.11-11-2010
20100329007Pointer Based Column Selection Techniques in Non-Volatile Memories - Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. to control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.12-30-2010
20120147674Nonvolatile Memory Devices that Utilize Dummy Word Line Segments to Inhibit Dishing During Fabrication - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction06-14-2012
20080219052ALWAYS-EVALUATED ZERO STANDBY-CURRENT PROGRAMMABLE NON-VOLATILE MEMORY - In an integrated circuit device, a continuous-output, zero-standby-current non-volatile storage cell is formed by P-MOS and N-MOS transistor elements coupled in series between first and second power supply nodes (e.g., V09-11-2008
20110096600SEMICONDUCTOR MEMORY DEVICE REDUCING RESISTANCE FLUCTUATION OF DATA TRANSFER LINE - According to one embodiment, a semiconductor memory device includes first and second memory cell blocks and an interconnect rerouting unit provided therebetween. The first memory cell block includes first interconnects and second interconnects provided in each space between the first interconnects. The second memory cell block includes a plurality of third interconnects provided on lines extending from the first interconnects and a plurality of fourth interconnects provided on lines extending from the second interconnects. A width and a thickness of the second and fourth interconnects are smaller than a width and a thickness of the first and second interconnects. Each of the first to fourth interconnects is connected to one end of first to fourth cell units including memory cells. The interconnect rerouting unit connects one of the fourth interconnects to one of the first interconnects and connects one of the third interconnects to the second interconnects.04-28-2011
20110188309SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first circuit unit having first and second interconnects, a second circuit unit having third and fourth interconnects, and an intermediate unit provided therebetween and having first and second transistors juxtaposed to each other along a direction perpendicular to a direction from the first circuit unit toward the second circuit unit. A high impurity concentration region in a first connection region of one diffusion layer of the first transistor is connected to the first interconnect, and other diffusion layer is connected to the third interconnect. A distance from the first connection region to a gate is longer than a distance from the second connection region to a gate. An midpoint region with a narrower width than the first connection region is provided between the gate and the first connection region of the one diffusion layer of the first transistor.08-04-2011
20100020608NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.01-28-2010
201100515123D MEMORY DEVICES DECODING AND ROUTING SYSTEMS AND METHODS - 3D memory devices are disclosed, such as those that include multiple two-dimensional tiers of memory cells. Each tier may be fully or partially formed over a previous tier to form a memory device having two or more tiers. Each tier may include strings of memory cells where each of the strings are coupled between a source select gate and a drain select gate such that each tier is decoded using the source/drain select gates. Additionally, the device can include a wordline decoder for each tier that is only coupled to the wordlines for that tier.03-03-2011
20090003060High density NOR flash array architecture - In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions.01-01-2009
20120099374NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a substrate including device regions extending in a first direction, a memory cell array region including a plurality of memory cells disposed on the device regions, bit lines extending in the first direction, a sense amplifier circuit connected to ends of the bit lines, and bit line contacts connecting device regions to bit lines. The memory cell array region includes first to N-th regions where N is an integer of two or more, and a K-th region is located at a greater distance from the sense amplifier circuit than a (K−1)-th region, where K is an arbitrary integer of 2 to N. Contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−1)-th region, each device region having constant width in the memory cell array region.04-26-2012
20100124114Semiconductor Device and Layout Method for the Semiconductor Device - Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).05-20-2010
20120206963SEMICONDUCTOR ASSOCIATIVE MEMORY DEVICE - According to one embodiment, a semiconductor associative memory device comprises a retrieval block having retrieval word strings arranged in a column direction, each of the retrieval word strings includes memory cells arranged in a row direction between a word input terminal and a word output terminal, each of the memory cells having a first input terminal, a second input terminal, and an output terminal, wherein in each retrieval word string, the second input terminal of one of the memory cells is used as the word input terminal, and each of other memory cells is connected to the output terminal of adjacent memory cell by the second input terminal, wherein the first input terminals of the memory cells in the same column are connected.08-16-2012
20120008391VOLTAGE SWITCH CIRCUIT AND NONVOLATILE MEMORY DEVICE USING THE SAME - A voltage switch circuit includes a positive voltage supply circuit configured to supply a positive voltage to a control node in response to an enable signal, a negative voltage supply circuit configured to supply a negative voltage to the control node in response to a negative voltage enable signal, a control signal generation circuit configured to generate the negative voltage enable signal in response to the enable signal, and a switch circuit configured to transfer an input voltage with a positive potential or a negative potential to an output node in response to a potential of the control node.01-12-2012
201203005473-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines.11-29-2012
20120300546APPARATUS AND METHODS INCLUDING A BIPOLAR JUNCTION TRANSISTOR COUPLED TO A STRING OF MEMORY CELLS - Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.11-29-2012
20090135649Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V05-28-2009
20120106252NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A nonvolatile semiconductor memory device includes a first region, a second region, and a plurality of word lines. The first region includes a plurality of electrically-rewritable memory transistors. The second region is located around the first region. The plurality of word lines are connected to the gates of the plurality of memory transistors respectively. The plurality of word lines includes interconnection portions and connection portions respectively. The interconnection portions extend in a first direction to head from the first region to the second region and are arrayed in a second direction orthogonal to the first direction with a first distance therebetween. The connection portions are extending from the interconnection portions, located in the second region, and electrically connected to contacts, respectively. The ends of the plurality of connection portions are formed along straight lines extending in the second direction.05-03-2012
20120155170NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.06-21-2012
20100172178Semiconductor device manufacturing method and semiconductor integrated circuit device - A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.07-08-2010
20100172176Semiconductor Device, a Method of Using a Semiconductor Device, a Programmable Memory Device, and Method of Producing a Semiconductor Device - A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.07-08-2010
20100172177MEMORY DEVICE HAVING SUB-BIT LINES AND MEMORY SYSTEM - A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.07-08-2010
20120250409SEMICONDUCTOR MEMORY AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.10-04-2012
20100290285Flash Memory Device Using Double Patterning Technology and Method of Manufacturing the Same - Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.11-18-2010
20100290284Single-Transistor EEPROM Array and Operation Methods - An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.11-18-2010
20100246263Non-volatile Memory Device - This patent relates to a non-volatile memory device and a driving method thereof. The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate are electrically isolated from each other, and a plurality of word lines formed between the source select line and the drain select line.09-30-2010
20120127793MEMORY ARRAYS - A memory array includes a control gate, where every memory cell coupled to a first side of the control gate is within a first row of memory cells and every memory cell coupled to a second side of the control gate is within a second row of memory cells, and where the first row of memory cells is successively adjacent to the second row of memory cells. The memory array also includes alternating first and second bit lines, where each of the memory cells of the first row of memory cells is coupled to a respective one of the first bit lines, where each of the memory cells of the second row of memory cells is coupled to a respective one of the second bit lines, and wherein the first bit lines are different from the second bit lines.05-24-2012
20090059665Semiconductor Memory - A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.03-05-2009
20090059664Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same - In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.03-05-2009
20120170369NONVOLATILE MEMORY DEVICES - Nonvolatile memory devices including memory cell arrays with first bit line regions and common source tapping regions which are alternately disposed on a substrate along a direction, a page buffer including second bit line regions aligned with the first bit line regions and page buffer tapping regions aligned with the common source tapping regions, and a plurality of bit lines spaced apart from one another and extending to the second bit line regions from the first bit line regions.07-05-2012
20120176839NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.07-12-2012
20080205144NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.08-28-2008
20090073767CONTROL GATE LINE ARCHITECTURE - A non-volatile storage system that includes less word line drivers than word lines by having a limited set of individually controllable drivers for a subset of unselected word lines requiring word line by word line control, and have the remaining word lines connected to a common source.03-19-2009
20120314497SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.12-13-2012
20120081958NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME - Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.04-05-2012
20120230105Semiconductor Integrated Circuit - In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.09-13-2012
20090003062Non-volatile semiconductor device - A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.01-01-2009
20110122695PROGRAMMING MEMORY WITH BIT LINE FLOATING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING - During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of its target data state, after which the bit line is floated so that programming speed is slowed. The verify level which triggers the floating can be a target verify level of a data state that is one or more states below the target data state. Or, the verify level which triggers the floating can be an offset verify level of the target data state. An option is to raise the bit line voltage before it floats, to enter a slow programming mode, in which case there is a double slow down.05-26-2011
20100329009SMART CARD CAPABLE OF SENSING LIGHT - A smart card is foamed of a memory having light-sensing cells to sense externally supplied light and generate a detection signal in response to the externally supplied light being sensed by the light-sensing cells, and a reset control circuit generating a reset signal in response to the detection signal, the reset signal operating to reset the smart card.12-30-2010
20110032762MULTI-DOT FLASH MEMORY - According to one embodiment, a multi-dot flash memory includes an active area, a floating gate arranged on the active area via a gate insulating film and having a first side and a second side facing each other in a first direction, a word line arranged on the floating gate via an inter-electrode insulating film, a first bit line arranged on the first side of the floating gate via a first tunnel insulating film and extending in a second direction intersecting the first direction, and a second bit line arranged on the second side of the floating gate via a second tunnel insulating film and extending in the second direction. The active area has a width in the first direction narrower than that between a center of the first bit line and a center of the second bit line.02-10-2011
20110038210Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same - In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.02-17-2011
20120087189Non-Volatile Memory Device - A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.04-12-2012
20120087188STRUCTURE AND INHIBITED OPERATION OF FLASH MEMORY WITH SPLIT GATE - A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities.04-12-2012
20120287712SEMICONDUCTOR DEVICE - A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn.11-15-2012
20100202201MEMORY ARRAY WITH INVERTED DATA-LINE PAIRS - At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.08-12-2010
20130016559NAND FLASH MEMORY SYSTEM AND METHOD PROVIDING REDUCED POWER CONSUMPTIONAANM SONG; JONG-UKAACI SEOULAACO KRAAGP SONG; JONG-UK SEOUL KRAANM JANG; SOON-BOKAACI SEOULAACO KRAAGP JANG; SOON-BOK SEOUL KRAANM KIM; YOUNG-WOOKAACI GUNPO-SIAACO KRAAGP KIM; YOUNG-WOOK GUNPO-SI KRAANM KIM; HYUN-JINAACI SUWON-SIAACO KRAAGP KIM; HYUN-JIN SUWON-SI KR - A NAND flash memory device comprises a NAND flash memory comprising a first pad and a plurality of second pads. The first pad comprises a first receiver configured to receive a first signal. The second pads comprise a plurality of respective second receivers configured to receive a plurality of respective second signals. The second receivers are selectively powered, i.e., turned on or off, according to a logic level of the first signal.01-17-2013
20110157984BLOCK DECODER OF SEMICONDUCTOR MEMORY DEVICE - A block decoder of a semiconductor memory device includes a control signal generation circuit configured to generate an initial control signal and a block selection control signal in response to memory block selection addresses, an output node control circuit configured to set up an initial voltage of an output node in response to the initial control signal, and a block selection signal generation circuit configured to generate a block selection signal by raising a potential of the output node in response to the block selection control signal and the initial voltage of the output node.06-30-2011
20130135930NONVOLATILE MEMORY APPARATUS AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory apparatus includes a a memory cell array, a page buffer unit connected to bit lines of the memory cell array through a high voltage switching unit, a first interconnection configured to connect a high voltage switch of the high voltage switching unit, connected to an even bit line, to the page buffer unit, and formed at a first layer, and a second interconnection configured to connect a high voltage switch of the high voltage switching unit, connected to an odd bit line, to the page buffer unit, and formed at a second layer different from the first layer.05-30-2013
20120243313SEMICONDUCTOR MEMORY ARRAY AND METHOD FOR PROGRAMMING THE SAME - The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.09-27-2012
20080239807Transition areas for dense memory arrays - A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.10-02-2008
20080232166CONTENT DATA STORAGE DEVICE AND ITS CONTROL METHOD - A content data storage device which stores content data in nonvolatile memories from which data is erasable in units of blocks includes a bus width conversion unit converting a transmission bus to buses of a plurality of systems, a storage unit including a plurality of sets of memories, a plurality of switching units selectively switching between derivation of the content data and derivation of command signals and addresses, a controller configuring to perform (i) conversion control, (ii) state control, (iii) supply control, and (iv) switching control, the controller controlling the operation for reading and writing the content data with reference to the nonvolatile memories, and, a plurality of switch on and off units selectively switching on or off the content data, the command signals and the addresses.09-25-2008
20080225591NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers.09-18-2008
20080225590APPARATUS AND METHOD FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES - A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.09-18-2008
201301767813D Memory Array with Read Bit Line Shielding - A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.07-11-2013
20130176782MEMORY DEVICE HAVING SUB-BIT LINES AND MEMORY SYSTEM - A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.07-11-2013
20130094295MEMORY DEVICE IN PARTICULAR EXTRA ARRAY CONFIGURED THEREIN FOR CONFIGURATION AND REDUNDANCY INFORMATION - Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.04-18-2013
20130100736MAPPING BETWEEN TWO BUSES USING SERIAL ADDRESSING BITS - A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.04-25-2013
20110267881MEMORY ARRAY - A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read.11-03-2011
20130128664MEMORY MODULE FOR SIMULTANEOUSLY PROVIDING AT LEAST ONE SECURE AND AT LEAST ONE INSECURE MEMORY AREA - A memory module has at least one secure and at least one insecure memory area, separate write/read electronic units for each of the memory areas and at least one shared analog circuit part such as a voltage supply circuit for supplying the write/read electronic units and/or the memory areas.05-23-2013
20080198655Integrated circuit, method of reading data stored within a memory device of an integrated circuit, method of writing data into a memory device of an integrated circuit, memory module, and computer program - A memory device comprises a plurality of memory cells, each of which comprising a first electrode, a second electrode and an active material arranged between the first electrode and the second electrode, wherein the memory cells are grouped into memory cell groups, each memory cell group defining a memory cell group area and being configured such that corresponding first electrodes are individually addressable, and corresponding second electrodes are commonly addressable via a common select device provided within the memory cell group area of the memory cell group.08-21-2008
201301557713D NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal patterns; and a diffusion barrier layer interposed between the barrier metal patterns and the charge blocking layer.06-20-2013
20090080253DEVICE, SYSTEM, AND METHOD OF BIT LINE SELECTION OF A FLASH MEMORY - Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state. Other embodiments are described and claimed.03-26-2009
20130182504PAGE BUFFER CIRCUIT AND NONVOLATILE MEMORY DEVICE HAVING THE SAME - A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.07-18-2013
20110280072NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.11-17-2011
20110286269Non-Volatile Electronic Memory Device With NAND Structure Being Monolithically Integrated On Semiconductor - A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.11-24-2011
20110305083NONVOLATILE MEMORY DEVICE - A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.12-15-2011
20110310665Nonvolatile Memory Device - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.12-22-2011
20120020158SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).01-26-2012
20120020157Novel high-temperature non-volatile memory design - A method for fabricating a high temperature integrated circuit includes forming a drain/source diffusion and forming a buried diffusion implant containing the drain/source diffusion in a substrate to separate the drain/source diffusion from the substrate and an edge of a field isolation layer to decreases leakage current occurring with high voltage and high temperature. A nonvolatile memory array driver circuit with multiple driver transistors separated by anti-leakage transistors connected to prevent excess junction leakage current at elevated temperatures. Another nonvolatile memory array driver circuit has a high voltage blocking transistor connected to two anti-leakage transistors connected such that a source of the first anti-leakage transistor is connected to a drain of the high voltage blocking transistor and a drain of the second anti-leakage transistor is connected to prevent excess junction leakage current at elevated temperatures.01-26-2012
20130208542EMBEDDED SOLID STATE DISK AS A CONTROLLER OF A SOLID STATE DISK - A Solid State Disk (SSD) includes a plurality of nonvolatile memory devices storing data, and an embedded solid state disk controlling the plurality of nonvolatile memory devices. The SSD uses an embedded SSD (eSSD) as a controller. Thus, the SSD can be embodied in a small area. Also, since the SSD does not need an additional process for manufacturing a controller, manufacturing cost per unit may be reduced.08-15-2013

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