Entries |
Document | Title | Date |
20080198651 | NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION - A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device. | 08-21-2008 |
20080198652 | Memory Device Programming Using Combined Shaping And Linear Spreading - A method for data storage includes accepting data for storage in a memory ( | 08-21-2008 |
20080198653 | CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT - A circuit arrangement includes a nonvolatile memory cell having a continuously variable characteristic that can be read out. A programming unit is coupled to the memory cell and designed to apply an analog signal to the memory cell in order to vary the characteristic, if the characteristic lies within a predetermined range of values, in such a way that the characteristic lies outside the predetermined range of values. A supply voltage unit is provided for providing a supply voltage. A changeover unit is coupled to the supply voltage unit and to the programming unit and designed to trigger the application of the analog signal to the memory cell if the supply voltage is interrupted. | 08-21-2008 |
20080198654 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L | 08-21-2008 |
20080205136 | READ METHOD OF MEMORY DEVICE - A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a N | 08-28-2008 |
20080205137 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter. | 08-28-2008 |
20080205138 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array. | 08-28-2008 |
20080205139 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each having a plurality of threshold levels corresponding to a plurality of programming data respectively; a voltage generator circuit which generates a plurality of programming voltage pulses and a plurality of verify voltage pulses which are applied to said nonvolatile memory cells; a counter circuit which counts the number of times said programming voltage pulse is applied to corresponding said nonvolatile memory cell; a storage circuit which stores data corresponding to said plurality of verify voltage pulses which are set for each of corresponding said threshold levels and the number of times said programming voltage pulse is applied, the number of times said programming voltage pulse is applied being standards for switching a plurality of said verify voltage pulses; a comparison circuit which compares the number of times said programming voltage pulse is applied with said standards and generates a comparison result; a control circuit which controls said plurality of verify voltage pulses step by step based on said comparison result. | 08-28-2008 |
20080205140 | Bit line structure for a multilevel, dual-sided nonvolatile memory cell array - A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected in a cross connective columnar bit line structure such that each column of the dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of bit lines. The first of the associated pair of bit lines is further connected to a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells. | 08-28-2008 |
20080205141 | Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell - A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate along with positive drain and source voltage to inject hot carriers of holes to two charge trapping regions, one of a plurality of threshold adjustment voltages representing a portion of the multiple data bits to the drain and source regions to set the hot carrier charge levels to the two charge trapping regions. The erasing circuit provides a very large positive erase voltage to tunnel the electrons from cell's channel to whole trapping layer including the two charge trapping regions. The reading circuit generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages representative of multiple data bits, generates a drain voltage level to activate the charge-trapping nonvolatile memory cell. | 08-28-2008 |
20080212367 | METHOD OF OPERATING A FLASH MEMORY DEVICE - In a method of operating a flash memory device including a memory cell array having a Multi-Level Cell (MLC) for storing plural bit data, a first memory block included in the MLC is selected. First to M | 09-04-2008 |
20080212368 | DATA VERIFICATION METHOD AND SEMICONDUCTOR MEMORY - A semiconductor memory device storing multi-bit write data and a related method of verifying data programmed to a memory cell are disclosed. The method compares a write data reference bit selected from the write data with a corresponding external data bit indicative of an intended write data bit value, and verifies a target bit selected from the write data only upon a positive comparison between the write data reference bit and the corresponding external data bit. | 09-04-2008 |
20080212369 | METHOD OF MANAGING A MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS - A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are read by reading respective ternary strings written in respective pairs of three-level cells and decoding each read ternary string in a corresponding string of three bits according to the coding scheme. A pair of adjacent bits, belonging to at least one of a same initial string and two initial adjacent strings, are programmed by identifying pairs of three-level cells to be programmed that encode the strings of three bits and programming each pair of three-level cells. | 09-04-2008 |
20080219049 | ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY WITH N-BITS PER CELL - An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of the memory cells are preferably arranged in a matrix of rows and columns disposed substantially in a rectangle, with a plurality of word lines coupled with memory gate electrodes intersecting a first side of the rectangle substantially perpendicularly, a plurality of bit lines coupled with memory drain-source current paths intersecting a second side of the rectangle substantially perpendicularly (the second side also substantially perpendicularly intersecting the first side), a row select circuit being disposed at the first side for coupling with the word lines, and peripheral circuitry including a column select circuit and a sense circuit being disposed at the second side. | 09-11-2008 |
20080219050 | REDUCTION OF BACK PATTERN DEPENDENCY EFFECTS IN MEMORY DEVICES - A method for operating a memory that includes multiple analog memory cells includes storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels. After storing the data, second storage values are read from at least some of the cells, including at least one interfered cell that belongs to a group of cells. A Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell is detected and canceled. The second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, are processed so as to reconstruct the data. | 09-11-2008 |
20080219051 | SYSTEM THAT COMPENSATES FOR COUPLING DURING PROGRAMMING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location). | 09-11-2008 |
20080225589 | Memory page boosting method, device and system - A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells. | 09-18-2008 |
20080232163 | MEMORY STORAGE TECHNIQUE FOR A BI-DIRECTIONALLY PROGRAMMABLE MEMORY DEVICE - According to some embodiments, a memory device is disclosed. The memory device includes a memory array with a programming region to store data. The programming region includes a plurality of memory cells and has an associated flag bit. Logic is coupled to the memory array. The logic is to compare data stored in the programming region to a desired programmed value, and to determine a number of changing bits. The logic may further set or clear the associated flag bit, depending on the number of changing bits. | 09-25-2008 |
20080232164 | METHOD FOR PROGRAMMING A MULTILEVEL MEMORY - A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises programming the bits of the memory having a Vt level lower than the first PV level of the targeted programmed state such that at least one bit of them has a Vt level larger than a second PV level corresponding to a targeted programmed state, wherein the second PV level of the targeted programmed state is larger than the corresponding first PV level; and programming only the bits of the memory with a Vt level lower than the first PV level of the targeted programmed state such that each of them has a Vt level larger than the first PV level of the targeted programmed state. | 09-25-2008 |
20080232165 | Method for modifying data more than once in a multi-level cell memory location within a memory array - A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in the upper page by storing a value of one in each of the bits. One or more bits in the lower page are then programmed such that a one is stored in the one or more bits of the lower page. One or more bits in the upper page are then programmed such that a one is stored in the one or more bits of the upper page. The one or more bits in the upper page are then reprogrammed such that the value in the one or more bits of the upper page transitions from a one to a zero. The transition from a one to a zero in the one or more bits of the upper page is used to mark for performance of a block management function the block. | 09-25-2008 |
20080239804 | Method for reading multiple-value memory cells - A read method for multiple-value information in a semiconductor memory such as a nonvolatile semiconductor memory is introduced. The method includes obtaining a first data from a selected multiple-value memory cell by applying a first voltage to a control gate of the selected multiple-value memory cell. A second data from the selected multiple-value memory cell is obtained by applying a second voltage to the control gate of the selected multiple-value memory cell. A first bit of the plurality of bits stored in the selected multiple-value memory cell is then obtained by performing a predetermined calculation on the first data and the second data. A second bit of the plurality of bits is obtained from the selected multiple-value memory cell by applying a third voltage to the control gate of the selected multiple-value memory cell. | 10-02-2008 |
20080239805 | NONVOLATILE SEMICONDUCTOR MEMORY AND DATA READING METHOD - A nonvolatile semiconductor memory according to the present invention includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section for, when performing 4-value data programming, read or erasure with respect to at least one of the plurality of memory cells, selecting and applying a voltage to a corresponding word line and a corresponding bit line among the plurality of word lines and the plurality of bit lines; wherein the data reading and programming control section includes an adjacent memory cell data reading section for reading, at a reading voltage of a predetermined reading voltage level, whether or not data is programmed in a lower page of a second memory cell adjacent to a first memory cell in the memory cell array, and generating adjacent memory cell state data which represents a data state of the second memory cell; an adjacent memory cell data memory section for storing the adjacent memory cell state data generated by the adjacent memory cell data reading section; a reading voltage level control section for defining a plurality of predetermined reading voltage verify levels for reading data from the first memory cell based on the adjacent memory cell state data; a data reading section for reading the data from the first memory cell at a plurality of reading voltages corresponding to the plurality of predetermined reading voltage verify levels; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section. | 10-02-2008 |
20080239806 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 10-02-2008 |
20080253181 | METHOD FOR PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE - A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels. | 10-16-2008 |
20080253182 | NAND FLASH MEMORY DEVICE AND PROGRAMMING METHOD - A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program. | 10-16-2008 |
20080259684 | Programming a NAND flash memory with reduced program disturb - When a memory device receives two or more pluralities of bits from a host to store in a nonvolatile memory, the device first stores the bits in a volatile memory. Then, in storing the bits in the nonvolatile memory, the device raises the threshold voltages of some cells of the volatile memory to values above a verify voltage. While those threshold voltages remain substantially at those levels, the device raises the threshold voltages of other cells of the volatile memory to values below the verify voltage. In the end, every cell stores one or more bits from each plurality of bits. Preferably, all the cells share a common wordline. A data storage device operates similarly with respect to storing pluralities of bits generated by an application running on the system. | 10-23-2008 |
20080259685 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data program control section which programs a plurality of first multi-bits data each having a first number of bits, or a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, to said plurality of memory cell arrays, a page buffer circuit which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said word lines from said plurality of memory cell arrays, a data transfer section which transfers said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said second number of bits from said page buffer circuit synchronized with a second clock signal having a cycle which is twice that of a first clock signal, and a data output section which receives said data from said data transfer section and outputs externally said data in synchronization with said first clock signal. | 10-23-2008 |
20080259686 | NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND LSB READ METHOD - A non-volatile memory device and system as well as a LSB read method are disclosed. The LSB read method includes reading LSB data from a memory cell during a main LSB read operation making reference to a flag cell threshold voltage, determining whether the LSB data contains an error, and if the LSB data contains an error re-reading the LSB data during a LSB recover-read operation without making reference to the flag cell threshold voltage. | 10-23-2008 |
20080266945 | ADAPTIVE DETECTION OF THRESHOLD LEVELS IN MEMORY - Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location. | 10-30-2008 |
20080266946 | METHOD OF MANAGING A MULTILEVEL MEMORY DEVICE AND RELATED DEVICE - A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels. | 10-30-2008 |
20080266947 | Bit-Symbol Recognition Method and Structure for Multiple-Bit Storage in Non-Volatile Memories - Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell. | 10-30-2008 |
20080266948 | Memory system, program method thereof, and computing system including the same - Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device. | 10-30-2008 |
20080273384 | Non-volatile multilevel memory cells with data read of reference cells - Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell. | 11-06-2008 |
20080273385 | NAND step up voltage switching method - Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired. | 11-06-2008 |
20080273386 | MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION - An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch. | 11-06-2008 |
20080285342 | Method of Programming a Nonvolatile Memory Cell and Related Memory Array - A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties. | 11-20-2008 |
20080285343 | Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups - Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an i | 11-20-2008 |
20080291724 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits. | 11-27-2008 |
20080298124 | PARALLEL PROGRAMMING OF MULTIPLE-BIT-PER-CELL MEMORY CELLS BY CONTROLLING PROGRAM PULSEWIDTH AND PROGRAMMING VOLTAGE - Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operation reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing. During or at the end of write operations, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly. | 12-04-2008 |
20080304317 | SOLID STATE MEMORY UTILIZING ANALOG COMMUNICATION OF DATA VALUES - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. This analog signal may then be processed to convert it to a digital representation of the individual bits of the bit pattern represented by the analog signal. Such memory devices may be incorporated into bulk storage devices, and may utilize form factors and communication protocols of hard disk drives (HDDs) and other traditional bulk storage devices for transparent replacement of such traditional bulk storage devices in electronic systems. | 12-11-2008 |
20080304318 | MULTI-LEVEL-CELL TRAPPING DRAM - A memory device having at least one multi-level memory cell is disclosed, and each multi-level memory cell configured to store n multiple bits, where n is an integer, wherein the multiple bits are stored in a charge storage layer trapping charge carriers injected by application of a voltage to set or reset a threshold voltage V | 12-11-2008 |
20080304319 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 12-11-2008 |
20080304320 | MEMORY CELL AND METHOD OF PROGRAMMING THE SAME - A method of programming a memory cell is described. The memory cell includes a gate with a charge trapping layer isolated from a substrate for storing data with a first region and a second region separated from the first region. The method of programming the memory cell includes applying a first voltage arrangement with a first gate voltage for programming the first region and applying a second voltage arrangement with a second gate voltage for programming the second region. The first gate voltage is greater than the second gate voltage. | 12-11-2008 |
20080310222 | PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate. | 12-18-2008 |
20080310223 | Method for programming a multilevel memory - A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K | 12-18-2008 |
20080310224 | Coarse and fine programming in a solid state memory - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage. | 12-18-2008 |
20080310225 | Programming of a solid state memory utilizing analog communication of bit patterns - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes preprogramming erased memory cells that are to be programmed to a known V | 12-18-2008 |
20080310226 | Multi-Bit Flash Memory Devices Having a Single Latch Structure and Related Programming Methods, Systems and Memory Cards - Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed. | 12-18-2008 |
20080310227 | SEMICONDUCTOR MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier. | 12-18-2008 |
20080316812 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 12-25-2008 |
20080316813 | MULTI-LEVEL CELL SERIAL-PARALLEL SENSE SCHEME FOR NON-VOLATILE FLASH MEMORY - A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme. | 12-25-2008 |
20080316814 | PROGRAM-VERIFY SENSING FOR A MULTI-LEVEL CELL (MLC) FLASH MEMORY DEVICE - According to some embodiments, a method and apparatus for program verify sensing disclosed. During a program verify sensing operation, a tracking signal may be generated to match a sense amplifier signal. A data stream from a sequence generator may be held at a pass/hold logic until the tracking signal reaches a trip point. The data stream may be subsequently latched at a main latch with the sense amplifier signal. | 12-25-2008 |
20080316815 | METHODS OF PROGRAMMING MULTILEVEL CELL NONVOLATILE MEMORY - A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block. | 12-25-2008 |
20080316816 | SYSTEMS FOR PROGRAMMING MULTILEVEL CELL NONVOLATILE MEMORY - A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block. | 12-25-2008 |
20080316817 | Method and system for programming non-volatile memory cells based on programming of proximate memory cells - A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed. | 12-25-2008 |
20080316818 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING - A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage. | 12-25-2008 |
20080316819 | FLASH MEMORY DEVICE CAPABLE OF STORING MULTI-BIT DATA AND SINGLE-BIT DATA - There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included. | 12-25-2008 |
20080316820 | Method of programming memory device - Provided is a method of programming a memory device. The method includes performing a program voltage applying operation; and performing a verifying operation, wherein a plurality of verifying operations are consecutively performed after a program voltage applying operation. | 12-25-2008 |
20090003054 | DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line. | 01-01-2009 |
20090003055 | METHOD FOR PROGRAMMING MULTI-LEVEL CELL FLASH MEMORY DEVICE - A method for programming an MLC flash memory device minimizes interference between adjacent cells during a program operation, such that threshold voltage distribution becomes narrow and uniform. According to the method, an auxiliary program operation is performed on memory cells to be programmed, such that a majority of the memory cells have a positive threshold voltage. An LSB of a particular memory cell is programmed to a predetermined level, and data of the programmed LSB is sensed. An MSB of the particular memory cell is programmed to a predetermined level according to the sensed data of the LSB. | 01-01-2009 |
20090003056 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation. | 01-01-2009 |
20090003057 | NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-LEVEL CELLS USING MODIFIED READ VOLTAGES AND METHODS OF OPERATING THE SAME - Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed. | 01-01-2009 |
20090003058 | FLASH MEMORY DEVICE AND METHOD FOR ADJUSTING READ VOLTAGE OF FLASH MEMORY DEVICE - A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field. | 01-01-2009 |
20090010057 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND MEMORY SYSTEM - A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2 | 01-08-2009 |
20090010058 | MULTI-BIT NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND METHOD OF FABRICATING THE SAME - A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes. | 01-08-2009 |
20090016102 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTI-VALUE INFORMATION - To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information. | 01-15-2009 |
20090016103 | MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM - A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result. | 01-15-2009 |
20090016104 | Nonvolatile semiconductor memory device and programming method thereof - A programming method of a multi-bit flash memory device includes programming multi-bit data into selected memory cells through pluralities of programming loops. In each programming loop, an increment of a programming voltage applied to the selected memory cells is varied in accordance with a result of program-verification for each data state of the multi-bit data and reading-verification for a data state is skipped when the program-verification indicates that data state has passed. | 01-15-2009 |
20090027959 | PROGRAMMING MULTILEVEL CELL MEMORY ARRAYS - Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first portion of a programming operation if a second or a fourth data state is desired, while memory cells remain in the first Vt distribution if the first or a third data state is desired. During a second portion of the programming operating, if the third data state is desired, those memory cells are shifted from the first Vt distribution to a third Vt distribution higher than the second Vt distribution and, if the fourth data state is desired, those memory cells are shifted from the second Vt distribution to a fourth Vt distribution higher than the third Vt distribution. | 01-29-2009 |
20090027960 | Cell deterioration warning apparatus and method - Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device. | 01-29-2009 |
20090027961 | Non-volatile memory cell programming method - A non-volatile memory cell programming method is provided. A memory cell programming method of programming 2-bit data in a memory cell having 4 threshold voltage distributions may comprise: a first program operation of programming a first bit of the 2-bit data in the memory cell by applying a first programming voltage to the memory cell; a second program operation of programming a second bit of the 2-bit data in the memory cell by applying a second programming voltage to the memory cell; and a stabilization operation of applying a stabilization voltage having an electric field opposite in polarity to an electric field formed by the first and second programming voltages to the memory cell after one of the first and second program operations that corresponds to a higher one of the first and second programming voltages is performed. | 01-29-2009 |
20090027962 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK - A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode. | 01-29-2009 |
20090027963 | HIGH PERFORMANCE MULTI-LEVEL NON-VOLATILE MEMORY DEVICE - Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and charge blocking layer for high speed programming/erasure. Charge retention is enhanced by utilization of nano-crystals and/or bulk trapping materials in a composite non-conductive trapping layer and a high K dielectric insulating layers. The band-gap engineered gate-stack with asymmetric direct tunneling or crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage high speed tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. Memory cell embodiments of the present invention allow multiple levels of bit storage in a memory cell through multiple charge centroids and/or multiple threshold voltage levels. | 01-29-2009 |
20090034329 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SUPPRESSING PEAK CURRENT - A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule. | 02-05-2009 |
20090034330 | WORD LINE VOLTAGE GENERATOR AND FLASH MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF GENERATING WORD LINE VOLTAGE THEREOF - A word line voltage generator that generates a word line voltage, which is selectively changed depending on a temperature, a flash memory device including the word line voltage generator, and a method of generating the word line voltage. The word line voltage generator includes a read voltage generator and a controller. The read voltage generator generates a read voltage or a verify voltage based on one of reference voltages in response to an enable control signal and supplies the read voltage or the verify voltage to one of a plurality of global word lines in response to a row decoding signal, during a read operation or a read operation for program verification, of the flash memory device. The controller generates one of the reference voltages in response to a read control signal or a verify control signal. When a temperature is varied, the read voltage generator changes the level of the read voltage or the verify voltage in reverse proportion to the temperature. | 02-05-2009 |
20090034331 | NAND MEMORY DEVICE COLUMN CHARGING - Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations. | 02-05-2009 |
20090040821 | LOW POWER MULTIPLE BIT SENSE AMPLIFIER - A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data. | 02-12-2009 |
20090040822 | FLASH MEMORY DEVICE HAVING SINGLE PAGE BUFFER STRUCTURE AND RELATED PROGRAMMING OPERATIONS - A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided. | 02-12-2009 |
20090046508 | Programming methods for multi-level flash EEPROMs - A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage. | 02-19-2009 |
20090046509 | TECHNIQUE TO IMPROVE AND EXTEND ENDURANCE AND RELIABILITY OF MULTI-LEVEL MEMORY CELLS IN A MEMORY DEVICE - A novel technique to improve and extend endurance and reliability of a memory device utilizing multi-level cells is disclosed. As a memory device ages, it's reliability deteriorates. Prior to the memory device becoming completely unreliable, the memory device transitions from a multi-level cell operating mode to a reduced capacity operating mode. When operating in the multi-level cell mode, the memory system stores multiple bits per cell. The memory system stores fewer bits per cell when operating in the reduced capacity. The transition between modes is achieved by setting all bits of a particular memory page to a specific value, for example, either a logic “1” or a logic “0.” | 02-19-2009 |
20090046510 | Apparatus and method for multi-bit programming - Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell. | 02-19-2009 |
20090052240 | Flash Memory Device and Method of Programming the Same - A flash memory device may include a memory cell array, a page buffer unit, and a switching element. The page buffer unit may include first and second latches and is configured to program data into the memory cell array and read data from the memory cell array. The switching element enables the first latch during a verify operation of a first program based on a first verify voltage, and enables or disables the first latch in order to execute a verify operation of a second program based on a second verify voltage lower than the first verify voltage depending on whether data to be programmed has been stored in the second latch. | 02-26-2009 |
20090052241 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node. | 02-26-2009 |
20090052242 | NAND TYPE NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes n-numbered memory cells (n is an integer of not less than 3) and a driver which applies a first voltage to a control gate electrode of a selected first memory cell in the n-numbered memory cells, applies a second voltage lower than the first voltage to a control gate electrode of a second memory cell adjacent to the first memory cell, and applies a third voltage lower than the second voltage to control gate electrodes of third memory cells other than the first and second memory cells at the time of programming. The first, second and third voltages have values not less than a value for turning on the n-numbered memory cells regardless of their threshold voltages. | 02-26-2009 |
20090052243 | Method of controlling a memory cell of non-volatile memory device - A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells. | 02-26-2009 |
20090052244 | MULTILEVEL STORAGE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE ENABLING HIGH-SPEED DATA READING AND HIGH-SPEED DATA WRITING - A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2 | 02-26-2009 |
20090059662 | MULTI-LEVEL CELL MEMORY DEVICES AND METHODS USING SEQUENTIAL WRITING OF PAGES TO CELLS SHARING BIT BUFFERS - An apparatus includes a nonvolatile memory including a plurality of memory cells, each configured to store data having at least two bits and a control circuit configured to write data to a first memory cell connected to a wordline of the nonvolatile memory and to then write data to a second memory cell that is connected to wordline and shares a bit buffer with the first memory cell. | 03-05-2009 |
20090067235 | Test circuit and method for multilevel cell flash memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 03-12-2009 |
20090067236 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state, and means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential. | 03-12-2009 |
20090067237 | MULTI-BIT DATA MEMORY SYSTEM AND READ OPERATION - Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data. | 03-12-2009 |
20090067238 | NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION - The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations. | 03-12-2009 |
20090067239 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 03-12-2009 |
20090067240 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 03-12-2009 |
20090073762 | METHODS OF OPERATING MULTI-BIT FLASH MEMORY DEVICES AND RELATED SYSTEMS - Methods of operating a non-volatile multi-bit memory device can include programming multi-bit memory cells included in one page of the device with page data including an error detection code based on the page data and determining the validity of the page data using the error detection code read from the multi-bit memory cells in response to an error during programming of the multi-bit memory cells, wherein the multi-bit memory cells in the one page are configured to store a single bit of the page data. | 03-19-2009 |
20090073763 | METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell. | 03-19-2009 |
20090073764 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE CAPABLE OF HIGH-SPEED WRITING - A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation. | 03-19-2009 |
20090073765 | NON-VOLATILE MEMORY DEVICE AND METHOD HAVING BIT-STATE ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 03-19-2009 |
20090073766 | SEMICONDUCTOR MEMORY DEVICE WHICH GENERATES VOLTAGES CORRESPONDING TO A PLURALITY OF THRESHOLD VOLTAGES - A memory cell MC stores a plurality of bits of data using threshold levels | 03-19-2009 |
20090080247 | USING MLC FLASH AS SLC BY WRITING DUMMY DATA - A method for storing data includes designating, in a memory array including cells configured for writing a first number of bits per cell, a group of the cells to which input data are to be written at a second number of bits per cell, smaller than the first number. Dummy data that are independent of the input data are stored in a first set of one or more bits of the cells in the group. The input data are written to a second set of at least one other bit of the cells in the group. | 03-26-2009 |
20090080248 | DATA STORAGE AND PROCESSING ALGORITHM FOR PLACEMENT OF MULTI - LEVEL FLASH CELL (MLC) VT - A wireless device that includes a memory device having an engine to execute a voting algorithm to average a memory cell data sensing result over time to provide a charge placement in the memory cell. | 03-26-2009 |
20090080249 | Non-volatile memory cell endurance using data encoding - A method and apparatus for storing an n-bit (for n>=2) data block in an array of non-volatile memory cells utilizes a predetermined n+k-bit (for k>=1) encoding selected to reduce the number of programmed cells required to store the n-bit data block. | 03-26-2009 |
20090080250 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF - A multi-valued nonvolatile semiconductor storage device and an operation method thereof capable of setting a plurality of positive levels having positive threshold voltages and a plurality of negative levels having negative threshold voltages for storing information in a charge storage layer is provided. According to one aspect, there is provided a nonvolatile semiconductor storage device which comprises a storage element provided on a first surface of a semiconductor layer and including a charge storage layer provided with a plurality of positive levels having positive threshold voltages and a plurality of negative levels having negative threshold voltages to store information, and a back electrode provided on a second surface of the semiconductor layer to be opposite to the storage element, the back electrode being configured to apply a voltage which converts information stored in the negative level of the charge storage layer to information having a positive threshold voltage. | 03-26-2009 |
20090080251 | NAND FLASH MEMORY DEVICES AND METHODS OF LSB/MSB PROGRAMMING THE SAME - Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register. | 03-26-2009 |
20090080252 | SEMICONDUCTOR MEMORY DEVICE - A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array. | 03-26-2009 |
20090086539 | NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices and systems. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of single level non-volatile memory cells and a number of multiple level non-volatile memory cells, where a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell. | 04-02-2009 |
20090091974 | Methods of programming non-volatile memory cells - A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit. | 04-09-2009 |
20090097311 | NON-EQUAL THRESHOLD VOLTAGE RANGES IN MLC NAND - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Threshold voltage ranges of the memory cells have a larger range size for ranges that include lower threshold voltages and a smaller range size for ranges that include higher threshold voltages since program disturb is lower at higher threshold voltages. | 04-16-2009 |
20090097312 | CONTROLLED RAMP RATES FOR METAL BITLINES DURING WRITE OPERATIONS FROM HIGH VOLTAGE DRIVER FOR MEMORY APPLICATIONS - Systems and methods that control the switching transition times or profile of a ramped voltage write signal used for programming or erasing at least a wordline of an array of multi-bit and/or multi-level flash memory cells are provided. In one embodiment, this goal is accomplished by applying a ramped or otherwise controlled profile write voltage to the flash memory cells in order to avoid disturb issues to the unselected (non-targeted) neighboring memory cells, which preserves the existing state of the neighboring cells while keeping the design as compact and manageable as possible yet maintains a high write speed. The systems and method are applicable to, and reliable for various memory technologies, since the size of the steps or other such functional transitions of the ramped voltage profile can be adjusted or trimmed to any level of resolution required. | 04-16-2009 |
20090097313 | PAGE BUFFER, MEMORY DEVICE HAVING THE PAGE BUFFER AND METHOD OF OPERATING THE SAME - A page buffer includes a first latch coupled between a sensing node and a data input/output node for storing data to be programmed. The sensing node is coupled to a bit line corresponding to an MLC selected for programming. The data input/output node receives/outputs data. A second latch is coupled to the sensing node for performing a program, verifying or read operation. A first switching means is coupled between the first latch and the sensing node for transmitting data stored in the first latch to the bit line through the sensing node when the program operation is performed. A second switching means is coupled to a first node of the second latch and the sensing node for verifying a first program operation. A third switching means is coupled between a second node of the second latch and the sensing node for verifying a second program operation. | 04-16-2009 |
20090097314 | PAGE BUFFER AND MULTI-STATE NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode. | 04-16-2009 |
20090103357 | FAST SINGLE PHASE PROGRAM ALGORITHM FOR QUADBIT - Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline. | 04-23-2009 |
20090103358 | REDUCING PROGRAMMING ERROR IN MEMORY DEVICES - A method for storing data in an array ( | 04-23-2009 |
20090103359 | Apparatus and method of multi-bit programming - Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory. | 04-23-2009 |
20090103360 | Multi-Bit Flash Memory Device and Program and Read Methods Thereof - The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped. | 04-23-2009 |
20090103361 | LEVEL VERIFICATION AND ADJUSTMENT FOR MULTI-LEVEL CELL (MLC) NON-VOLATILE MEMORY (NVM) - Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a ‘gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy. | 04-23-2009 |
20090109743 | MULTILEVEL MEMORY CELL OPERATION - One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a reference cell to a Vt level at least as great as an uppermost Vt level of the number of different Vt levels, performing a read operation on the reference cell, and determining a number of read reference voltages used to determine a particular program state of the memory cell based on the read operation performed on the reference cell. | 04-30-2009 |
20090109744 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes programming at least one of the memory cells to one of a number of states. The method also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. The method further includes sensing non-erased states of the memory cells using at least one common voltage level. | 04-30-2009 |
20090109745 | NON-VOLATILE MULTILEVEL MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states. | 04-30-2009 |
20090109746 | MEMORY CELL PROGRAMMING - One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least in part, on the one of the first number of states and the second cell to one of a fourth number of states based, at least in part, on the one of the second number of states. | 04-30-2009 |
20090109747 | FRACTIONAL BITS IN MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for programming memory cells. One method embodiment includes storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. The method also includes storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2 | 04-30-2009 |
20090109748 | Apparatus and method of multi-bit programming - Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may include: a first control unit that allocates any one of 2 | 04-30-2009 |
20090109749 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area including a plurality of memory cells each configured to store n-bit data on the basis of a threshold voltage, and a controller which sets 2 | 04-30-2009 |
20090109750 | SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping latter for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory, as non-volatile memory when power to the device is interrupted. | 04-30-2009 |
20090109751 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive. | 04-30-2009 |
20090122603 | INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING - A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 05-14-2009 |
20090122604 | METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING RELATED APPLICATION DATA - A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 05-14-2009 |
20090122605 | INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE MULTIPLE-TIME PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING - A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 05-14-2009 |
20090122606 | FLASH MEMORY DEVICE HAVING MULTI-LEVEL CELL AND READING AND PROGRAMMING METHOD THEREOF - There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations. | 05-14-2009 |
20090122607 | ERASE OPERATION IN A FLASH DRIVE MEMORY - A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The parasitic capacitance between the target cells and the adjacent cells causes the threshold voltage of the target cell to increase to a new threshold voltage with the programming of the adjacent cells. A difference between the new threshold voltage and the first threshold voltage is determined. If the difference is greater than or equal to a predetermined threshold, the target cell is soft programmed until the difference is less than the predetermined threshold. | 05-14-2009 |
20090122608 | MEMORY VOLTAGE CYCLE ADJUSTMENT - The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles. | 05-14-2009 |
20090129149 | Nonvolatile semiconductor memory device for writing multivalued data - A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching. | 05-21-2009 |
20090129150 | METHOD FOR OPERATING MEMORY - A memory operating method includes the following steps. First, a memory including a charge storage structure is provided. Next, first type charges are injected into the charge storage structure such that a threshold level of the memory is higher than an erase level. Then, second type charges are injected into the charge storage structure such that the threshold level of the memory is lower than a predetermined bit level. Next, first type charges are injected into the charge storage structure such that the threshold level of the memory approximates to or is equal to the predetermined bit level. | 05-21-2009 |
20090129151 | READ METHOD FOR MLC - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Cell reads are performed multiple times and the read threshold voltages averaged to more closely approximate actual threshold voltage and to compensate for random noise. | 05-21-2009 |
20090129152 | PROGRAM AND READ METHOD FOR MLC - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Program and read operations are performed in opposite directions to allow for subtraction of impact of subsequently programmed cells on target cells being read. | 05-21-2009 |
20090129153 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 05-21-2009 |
20090129154 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures. | 05-21-2009 |
20090129155 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell. | 05-21-2009 |
20090129156 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit. | 05-21-2009 |
20090129157 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THRESHOLD VALUE IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method for controlling a threshold value in a nonvolatile semiconductor memory device, includes: performing writing at least once on at least one of the memory cells to be adjusted to a state other than an erased state with an applied voltage that does not cause excess writing, with verify reading being not performed; and performing verify reading by applying a verify voltage corresponding to a target threshold value of the memory cell after the writing is performed on the at least one of the memory cells to be adjusted to the state other than the erased state, and, when the threshold value of the memory cell is determined to be lower than the target threshold value, repeating the writing with the applied voltage that does not cause excess writing and the verify reading until the threshold value of the memory cell becomes equal to or higher than the target threshold value. | 05-21-2009 |
20090129158 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NAND-TYPE FLASH MEMORY AND THE LIKE - A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential. | 05-21-2009 |
20090129159 | READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. | 05-21-2009 |
20090129160 | READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. | 05-21-2009 |
20090135648 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTILEVEL DATA - In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell. | 05-28-2009 |
20090141552 | MEMORY SYSTEM - A memory system includes a nonvolatile memory including a plurality of memory cells, each memory cell being configured to store n levels (n is a natural number of not less than 3) in accordance with a threshold voltage, and a converter which encodes input data in the form of a bit string, records the encoded data in the nonvolatile memory, and limits a difference between levels which adjacent memory cells can take to not more than a predetermined level lower than the n levels. | 06-04-2009 |
20090141553 | SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line. | 06-04-2009 |
20090147572 | METHOD, APPARATUS, AND SYSTEM FOR ERASING MEMORY - Methods, apparatus, and systems may operated such as to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. One such pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored in the plurality of multiple level memory cells, and erasing the plurality of multiple level memory cells of the memory block based on a result from verifying the charge stored in the plurality of multiple level memory cells. | 06-11-2009 |
20090147573 | FASTER PROGRAMMING OF MULTI-LEVEL NON-VOLATILE STORAGE THROUGH REDUCED VERIFY OPERATIONS - Programming speed for multi-level non-volatile storage elements is increased by reducing the number of verify operations. In one approach, verify operations are initially performed for the highest state less frequently than for other, lower states based on a recognition that a wider threshold voltage distribution for the highest state can be tolerated. After a number of additional programming pulses are applied, the frequency with which the verify operations are performed for the highest state increases. For example, for a four-level device in which state C is the highest state, C-state verify operations can be started when a first B-state element has been programmed and an additional number of program pulses have been applied. The C-state verify operations can be performed after every other program pulse until a certain number of C-state elements have been fully programmed, after which the C-state verify operations can be performed after every program pulse. | 06-11-2009 |
20090147574 | Flash Memory Device for Determining Most Significant Bit Program - A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed. | 06-11-2009 |
20090147575 | NOR FLASH MEMORY DEVICE WITH A SERIAL SENSING OPERATION AND METHOD OF SENSING DATA BITS IN A NOR FLASH MEMORY DEVICE - In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed. | 06-11-2009 |
20090154233 | NAND TYPE MEMORY AND PROGRAMMING METHOD THEREOF - A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring. | 06-18-2009 |
20090154234 | READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS - Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated. | 06-18-2009 |
20090154235 | REDUCED STATE QUADBIT - A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell. | 06-18-2009 |
20090154236 | Systems and methods for discrete channel decoding of LDPC codes for flash memory - Embodiments include systems and methods for soft encoding and decoding of data for flash memories using Log-Likelihood Ratios (LLRs). The LLRs are computed from statistics determined by observation of flash memory over time. In some embodiments, the write, retention and read transition probabilities are computed based on the observed statistics. These probabilities are used to compute the LLRs. During a read operation, a device reads the voltage of a cell of the flash memory. The level of the output is determined from the voltage. The level determines which LLRs to compute and transmit to a soft decoder. | 06-18-2009 |
20090154237 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area. | 06-18-2009 |
20090154238 | PROGRAMMING MULTILEVEL CELL MEMORY ARRAYS - Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first portion of a programming operation if a second or a fourth data state is desired, while memory cells remain in the first Vt distribution if the first or a third data state is desired. During a second portion of the programming operating, if the third data state is desired, those memory cells are shifted from the first Vt distribution to a third Vt distribution higher than the second Vt distribution and, if the fourth data state is desired, those memory cells are shifted from the second Vt distribution to a fourth Vt distribution higher than the third Vt distribution. | 06-18-2009 |
20090154239 | NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS - A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association with 2 | 06-18-2009 |
20090161425 | METHOD OF DETERMINING A FLAG STATE OF A NON-VOLATILE MEMORY DEVICE - In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n flag state information about n flag cells, resetting an entire flag state information value, sequentially reading first to n flag state information, increasing the entire flag state information value depending on a read result of the first to n flag state information, and determining a flag state by comparing the entire flag state information value and a critical value. | 06-25-2009 |
20090161426 | MEMORY PROGRAMMING METHOD AND DATA ACCESS METHOD - A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed. | 06-25-2009 |
20090168513 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH IMPROVED RELIABILITY - The reliability of multiple level cells in a memory device should be increased by programming the ends of the series strings of memory cells differently than the remaining quantity of memory cells of the series string. The end cells closest to select gate source and select gate drain transistors can be programmed as single level cells while the remaining cells of the string are programmed as multiple level cells. Another embodiment can program only one or more cells at the source end of the series string as single level cells. Still another embodiment can skip programming of the cells at either only the source end or both the source end and the drain end of the series string. | 07-02-2009 |
20090168514 | SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH MEMORY CELLS HAVING CHARGE STORAGE LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell, a source line, and a source line control circuit. The memory cell includes a charge storage layer and a control gate and is capable of holding 2 levels or more levels of data. The source line is electrically connected to a source of the memory cell. The source line control circuit detects a current passed to the source line and controls a potential of the source line in accordance with a detected current amount in a reading operation or a verification operation of the data. | 07-02-2009 |
20090168515 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 07-02-2009 |
20090168516 | Method for Generating Soft Bits in Flash Memories - Information stored as physical states of cells of a memory is read by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells according to the first set. Then, at least some of the references are set to respective members of a second set of values, and the physical states of the cells are read according to the second set. At least one member of the second set is different from any member of the first set, so that the two readings together read the physical states of the cells with higher resolution than the first reading alone. | 07-02-2009 |
20090175075 | FLASH MEMORY STORAGE APPARATUS, FLASH MEMORY CONTROLLER, AND SWITCHING METHOD THEREOF - A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data. | 07-09-2009 |
20090175076 | Memory device and method for estimating characteristics of multi-bit cell - Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell. | 07-09-2009 |
20090175077 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers. | 07-09-2009 |
20090175078 | APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB - The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process. | 07-09-2009 |
20090175079 | STRUCTURES AND METHODS TO STORE INFORMATION REPRESENTABLE BY A MULTIPLE-BIT BINARY WORD IN ELECTRICALLY ERASABLE, PROGRAMMABLE READ-ONLY MEMORY (EEPROM) - Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply. Using the distinctive threshold voltage associated with the different stored charges, the output voltage from the drain is distinctively recognized and converted back to the original n-bit word. A similar method for a PFET EEPROM is also disclosed. | 07-09-2009 |
20090175080 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 07-09-2009 |
20090185415 | CELL OPERATION MONITORING - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation. | 07-23-2009 |
20090185416 | SYSTEM THAT COMPENSATES FOR COUPLING BASED ON SENSING A NEIGHBOR USING COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location). | 07-23-2009 |
20090185417 | Apparatus and method of memory programming - A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells. | 07-23-2009 |
20090185418 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES - Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal. | 07-23-2009 |
20090185419 | PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME - A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation. | 07-23-2009 |
20090185420 | PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME - A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation. | 07-23-2009 |
20090190396 | Memory device and method of reading memory data - A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage. | 07-30-2009 |
20090190397 | Memory device and data reading method - A memory device and a memory data reading method are provided. The memory device may include: a multi-bit cell array; a programming unit that stores N data pages in a memory page in the multi-bit cell array; and a control unit that divides the N data pages into a first group and second group, reads data of the first group from the memory page, and determines a scheme of reading data of the second group from the memory page based on the read data of the first group. | 07-30-2009 |
20090190398 | Method of programming data in a NAND flash memory device and method of reading data in the NAND flash memory device - A method of programming data in a NAND flash memory device including at least one even bitline and at least one odd bitline, the method including programming N-bit data into first cells coupled to the at least one even bitline or the at least one odd bitline and programming M-bit data into second cells coupled to the other of the at least one even bitline and the at least one odd bitline, where N is a natural number greater than one and M is a natural number greater than N. | 07-30-2009 |
20090190399 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY - In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level. | 07-30-2009 |
20090190400 | NON-VOLATILE MEMORY DEVICE WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions. | 07-30-2009 |
20090196097 | Device for reading memory data and method using the same - Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage. | 08-06-2009 |
20090196098 | Multiple-Level Memory with Analog Read - A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers. | 08-06-2009 |
20090196099 | PAGE BUFFER CIRCUIT OF MEMORY DEVICE AND PROGRAM METHOD - A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data. | 08-06-2009 |
20090201725 | MULTI-LEVEL MEMORY CELL PROGRAMMING METHODS - A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage. | 08-13-2009 |
20090201726 | NON-VOLATILE SEMICONDUCTOR STORAGE SYSTEM - In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value. | 08-13-2009 |
20090201727 | READ METHOD OF MEMORY DEVICE - A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a N | 08-13-2009 |
20090201728 | Erase Method of Flash Memory Device - Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation. | 08-13-2009 |
20090207656 | OPERATING METHOD OF MEMORY - An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state. | 08-20-2009 |
20090207657 | MULTI LEVEL INHIBIT SCHEME - Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed. | 08-20-2009 |
20090207658 | OPERATING METHOD OF MEMORY DEVICE - An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array | 08-20-2009 |
20090207659 | Memory device and memory data read method - Provided are memory devices and memory data read methods. A method device may include: a multi-bit cell array; a decision unit that may detect threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages, using a first decision value; an error detector that may detect an error bit of the first data; and a determination unit that may determine whether the decision unit decides second data from the detected threshold voltages using a second decision value, based on a number of detected error bits, the second decision value being different from the first decision value. Through this, it is possible to reduce time spent for reading data stored in the multi-bit cell. | 08-20-2009 |
20090207660 | PROGRAM METHOD OF FLASH MEMORY DEVICE - Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation. | 08-20-2009 |
20090207661 | SEGMENTED BITSCAN FOR VERIFICATION OF PROGRAMMING - A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed. | 08-20-2009 |
20090213651 | TWO-BIT NON-VOLATILE FLASH MEMORY CELLS AND METHODS OF OPERATING MEMORY CELLS - A method for erasing a plurality of two-bit memory cells, each two-bit memory cell comprises a first bit and a second bit. A reference voltage is applied to a first bit line and a second bit line, the first bit line being associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell. Then a control activation voltage is applied to a first bit line select and a second bit line select, each bit line associated with the first bits and the second bits of each memory cell, respectively. Then an operating voltage is applied to a plurality of word lines associated with each two-bit memory cell, wherein the operating voltage is between 14 and 20 volts. | 08-27-2009 |
20090213652 | PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE - Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse. | 08-27-2009 |
20090213653 | PROGRAMMING OF ANALOG MEMORY CELLS USING A SINGLE PROGRAMMING PULSE PER STATE TRANSITION - A method for data storage in analog memory cells includes defining multiple programming states for storing data in the analog memory cells. The programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells. The data is stored in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse. | 08-27-2009 |
20090213654 | PROGRAMMING ANALOG MEMORY CELLS FOR REDUCED VARIANCE AFTER RETENTION - A method includes defining a nominal level of a physical quantity to be stored in analog memory cells for representing a given data value. The given data value is written to the cells in first and second groups of the cells, which have respective first and second programming responsiveness such that the second responsiveness is different from the first responsiveness, by applying to the cells in the first and second groups respective, different first and second patterns of programming pulses that are selected so as to cause the cells in the first and second groups to store respective levels of the physical quantity that fall respectively in first and second ranges, such that the first range is higher than and the second range is lower than the nominal level. The given data value is read from the cells at a later time. | 08-27-2009 |
20090219758 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2 | 09-03-2009 |
20090219759 | DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line. | 09-03-2009 |
20090231914 | Memory devices and methods - Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit. | 09-17-2009 |
20090231915 | Reading array cell with matched reference cell - A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity. | 09-17-2009 |
20090237992 | SEMICONDUCTOR MEMORY DEVICE HAVING STACKED GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell, a bit line, a source line, a detection circuit, and a sense amplifier. The memory cell holds or more levels of data. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The detection circuit detects a current flowing through the source line during a read operation and a verify operation on the data. The sense amplifier reads the data by sensing a current flowing through the bit line during the read operation and the verify operation. Whether or not the sense amplifier reads the same data plural times is determined according to a current amount detected by the detection circuit. | 09-24-2009 |
20090237993 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD - The nonvolatile semiconductor memory device related to the present invention includes a plurality of memory cells, a read/program circuit which supplies a program voltage and a program verification voltage to the plurality of memory cells and desired data is programmed, supplies a first program verification voltage to the plurality of memory cells and then supplies a second program verification voltage to the plurality of memory cells when programming the data, and a read/program control circuit which determines memory cells which reach a first data program state and memory cells which do not reach the first data program state when supplying the first program verification voltage, and determines memory cells which reach a second data program state and memory cells which do not reach the second data program state when supplying the second program verification voltage, and supplies a program control voltage which changes the program operation state for each memory cell. | 09-24-2009 |
20090237994 | Iterative Memory Cell Charging Based on Reference Cell Value - Systems and methods, including computer software for writing to a memory device include applying charge to each of multiple memory cells for storage of a selected data value in each memory cell. The memory cells include a first reference memory cell, and each data value is selected from a group of possible data values. Each possible data value has a corresponding target voltage level, and the first reference memory cell has a corresponding predetermined first reference target voltage level. The voltage level in the first reference memory cell is detected. A determination is made whether the voltage level in the first reference memory cell is less than the first reference target voltage level. Additional charge is applied to the memory cells upon the determination that the voltage level in the first reference memory cell is less than the first reference target voltage. | 09-24-2009 |
20090244968 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a select transistor, a memory cell transistor, a select gate line, a word line, and a row decoder. The memory cell transistor includes a charge accumulation layer and a control gate, and a current path one end of which is connected to a current path in the select transistor. The select gate line and word line are connected to a gate and the control gate of the select transistor and memory cell transistor. The row decoder includes a transfer circuit which transfers a voltage to the select gate line and includes a first switch including a first MOS transistor of a depression type. The first MOS transistor includes a current path one end of which is connected to the select gate line, and transfers a first voltage provided to the other end of the current path to the select gate line. | 10-01-2009 |
20090244969 | SEMICONDUCTOR MEMORY DEVICE COMPRISING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF ERASING DATA THEREOF - A semiconductor memory device includes a memory cell, a bit line, a source line, and a sense amplifier. The memory cell has a stacked gate including a charge accumulation layer and a control gate. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The sense amplifier, during erase verification to determine whether or not a threshold voltage of the memory cell in an erased state is at a threshold level, reads the data from the memory cell and senses the data with a first voltage applied to the control gate of the memory cell, with a positive second voltage higher than the first voltage applied to the semiconductor substrate and the source line, and with a third voltage higher than the second voltage applied to the bit line. | 10-01-2009 |
20090262577 | MULTI-LEVEL CELL FLASH MEMORY - Most drivers of flash memories used for embedded systems are often designed to use power from batteries, but not from a commercial power supply, and therefore are required to be protected against power failures. In addition, if a power failure occurs in the middle of programming a cell, the driver of an MLC flash memory may corrupt not only data in a page subjected to the program operation but also data already stored in the other pages in the same cell, which is an unrecoverable problem. According to the present invention, in order to write data into a block, the driver of the MLC flash memory has steps for preparing another block and writing identical data into corresponding pages of the two blocks alternately and makes it possible to write the data without data loss even if a power discontinuity or power failure occurs. | 10-22-2009 |
20090262578 | Use of Data Latches in Cache Operations of Non-Volatile Memories - Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused. | 10-22-2009 |
20090268516 | METHOD FOR ADAPTIVE SETTING OF STATE VOLTAGE LEVELS IN NON-VOLATILE MEMORY - A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user. | 10-29-2009 |
20090268517 | NON-VOLATILE MEMORY WITH ADAPTIVE SETTING OF STATE VOLTAGE LEVELS - A non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user. | 10-29-2009 |
20090268518 | Novel Multi-State Memory - Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data. | 10-29-2009 |
20090273973 | MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION - An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch. | 11-05-2009 |
20090273974 | Nonvolatile Memory, Verify Method Therefor, and Semiconductor Device Using the Nonvolatile Memory - Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier ( | 11-05-2009 |
20090273975 | NON-VOLATILE MULTILEVEL MEMORY CELLS WITH DATA READ OF REFERENCE CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell. | 11-05-2009 |
20090279356 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell string and a dummy bit line and whose gate is connected to a first selective gate line; a second dummy selective transistor connected between the other end of the dummy cell string and the cell source line and whose gate is connected to a second selective gate line, wherein at a time of writing in a selected memory cell, a voltage of a first dummy bit line selected is driven to a different voltage from a voltage of an unselected bit line, and any of the dummy cell transistors connected to the first dummy bit line is written. | 11-12-2009 |
20090285020 | METHOD OF PROGRAMMING A MULTI LEVEL CELL IN A NON-VOLATILE MEMORY DEVICE - In a method of programming a multi level cell, program speed increases as a program operation/erase operation is repeatedly performed. Particularly, in an ISPP method of reducing a program start voltage, much time may be required to finish a first verifying operation in an initial step where a few program operations/erase operations are performed. Accordingly, a blind verifying method may be applied in accordance with the number of the program operation/erase operations. | 11-19-2009 |
20090285021 | NON-VOLATILE MEMORY DEVICE AND METHOD OF VERIFYING A PROGRAM OPERATION IN THE SAME - A page buffer in a non-volatile memory device for performing a program operation for a multi level cell having m bits includes first register to mth registers, a first data transmitting circuit configured to transmit data stored in a first node or a second node of the first register to a sensing node in accordance with a first data transmitting signal or a second data transmitting signal, and (m-1) sensing node discharging circuits configured to couple the sensing node to ground in accordance with data stored in a first node or a second node of each of the second to mth registers, and a first sensing node discharge signal or a second sensing node discharge signal. | 11-19-2009 |
20090285022 | Memory programming method - A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage. | 11-19-2009 |
20090285023 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page. | 11-19-2009 |
20090285024 | FLASH MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A verify voltage may be changed into a plurality of voltage levels based upon a logic state of each of the memory cells and characteristics or logic states of other memory cells (e.g., adjacent) to each of the memory cells. | 11-19-2009 |
20090290414 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page. | 11-26-2009 |
20090290415 | CARD CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits. | 11-26-2009 |
20090296466 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage. | 12-03-2009 |
20090296467 | NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - Disclosed is a program method of a non-volatile memory device. The program method includes performing a least significant bit (LSB) program operation, during which an LSB program number is stored, and performing a most significant bit (MSB) program operation in a threshold voltage state order determined according to the LSB program number. | 12-03-2009 |
20090296468 | METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY CELLS BASED ON PROGRAMMING OF PROXIMATE MEMORY CELLS - A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed. | 12-03-2009 |
20090296469 | Alternate Row-Based Reading And Writing For Non-Volatile Memory - A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines. | 12-03-2009 |
20090303789 | DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT - Memory devices and methods are disclosed, such as those facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition. Memory devices and methods are also disclosed providing a means for determining initial programming pulse conditions for a population of memory cells based on the number of lower page data values being programmed to a logical 0 or a logical 1 data state. | 12-10-2009 |
20090303790 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - The present invention provides a semiconductor memory device that can minimize the widening of the threshold voltage distribution of cell transistors during a data erasing operation. The semiconductor memory device includes:
| 12-10-2009 |
20090303791 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 12-10-2009 |
20090303792 | METHOD FOR PROGRAMMING A MULTILEVEL MEMORY - A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K | 12-10-2009 |
20090310406 | M+L BIT READ COLUMN ARCHITECTURE FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs a row of non-volatile multi-level memory cells (MLC) in a single program operation to minimize disturb within the pages of the row, while verifying each memory cell page of the row separately. In one embodiment of the present invention, the memory device utilizes data latches to program M-bits of data into each cell of the row and then repurposes the data latches during the subsequent page verify operations to read M+L bits from each cell of the selected page at a higher threshold voltage resolution than required. In sensing, the increased threshold voltage resolution/granularity allows interpretations of the actual programmed state of the memory cell and enables more effective use of data encoding and decoding techniques such as convolutional codes where additional granularity of information is used to make soft decisions reducing the overall memory error rate. | 12-17-2009 |
20090310407 | SENSING AGAINST A REFERENCE CELL - Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states. | 12-17-2009 |
20090310408 | Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed. | 12-17-2009 |
20090316478 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first to third memory cell units each including a first select transistor, a second select transistor and a plurality of memory cell transistors which are connected in series in a first direction between the first select transistor and the second select transistor, the first and second select transistors of the respective memory cell transistors being disposed to neighbor in a second direction crossing the first direction. Those of the memory cell transistors, which neighbor the first and second select transistors, are used as select memory cell transistors. | 12-24-2009 |
20090316479 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF LOWERING A WRITE VOLTAGE - A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with input data. The control circuit supplies a first voltage to a word line of a selected cell in a write operation, and supplies a second voltage to at least one word line adjacent to the selected cell. Thereafter, the control circuit changes a voltage of the at least one word line adjacent to the selected cell from the second voltage to a third voltage (second voltage12-24-2009 | |
20090316480 | METHODS OF STORING MULTIPLE DATA-BITS IN A NON-VOLATILE MEMORY CELL - Methods of storing multiple data-bits in a non-volatile memory cell are carried out by trapping carriers in a composite trapping layer formed over a tunnel insulator layer. The composite trapping layer contains a plurality of band engineered sub-layers providing a plurality of charge trapping layers. | 12-24-2009 |
20090316481 | READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS - Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated. | 12-24-2009 |
20090316482 | METHOD OF PROGRAMMING A MULTI-LEVEL MEMORY DEVICE - Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed. | 12-24-2009 |
20090323414 | Method and Device for Storing Data - In one aspect a method of storing data in an integrated circuit may include identifying a group of storage sites from a plurality of storage sites; selecting a plurality of storage levels, each storage level being assignable to a storage site in the group of storage sites; and assigning a unique storage level to each of the storage sites in the group of storage sites, each unique storage level assigned from the plurality of storage levels. | 12-31-2009 |
20090323415 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 12-31-2009 |
20090323416 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS - Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used. | 12-31-2009 |
20100002503 | Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell. | 01-07-2010 |
20100002504 | Mulitple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same - A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an M | 01-07-2010 |
20100002505 | READING METHOD FOR MLC MEMORY AND READING CIRCUIT USING THE SAME - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages. | 01-07-2010 |
20100002506 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page. | 01-07-2010 |
20100002507 | FLASH MEMORY DEVICE REDUCING NOISE OF COMMON SOURCE LINE, PROGRAM VERIFY METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed. | 01-07-2010 |
20100002508 | FLASH MEMORY DEVICE CONTROLLING COMMON SOURCE LINE VOLTAGE, PROGRAM-VERIFY METHOD, AND MEMORY SYSTEM - Disclosed is a flash memory device and a program-verify method. The flash memory device includes; a plurality of memory cells connected between a bit line and a common source line, and a data input/output circuit connected to the bit line and configured to store program data for a selected one of the plurality memory cells. The data input/output circuit maintains the program data during a program-verify operation and controls a voltage level on the bit line in accordance with the program data. | 01-07-2010 |
20100002509 | INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION - Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation. | 01-07-2010 |
20100002510 | NAND TYPE FLASH MEMORY AND WRITE METHOD OF THE SAME - A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor. | 01-07-2010 |
20100008138 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - According to an aspect of a method of programming a nonvolatile memory device, a first program operation command is input, and a program operation is executed according to a program start voltage stored in a program start voltage storage unit. Here, a program voltage, which is applied at a time point at which a memory cell programmed higher than a verify voltage while the program operation is performed occurs for the first time, is updated to a program start voltage. | 01-14-2010 |
20100008139 | Memory devices having volatile and non-volatile memory characteristics and methods of operating the same - Multi-bit semiconductor memory devices having both volatile and nonvolatile memory characteristics and methods of operating the same are disclosed, the semiconductor memory device including a floating body on an upper region of a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode and a charge trap layer between the floating body and the gate electrode, where first bit data is written in one of the charge trap layer and the floating body, and second bit data is written in one of the charge trap layer and the floating body in which first bit data is not written. | 01-14-2010 |
20100008140 | NONVOLATILE MEMORY DEVICES SUPPORTING MEMORY CELLS HAVING DIFFERENT BIT STORAGE LEVELS AND METHODS OF OPERATING THE SAME - Nonvolatile memory devices include a memory cell array including a first memory cell and an adjacent second memory cell and a data input/output circuit configured to operate the first memory cell as an m-bit cell and to operate the second memory cell as an n-bit cell, wherein m is not equal to n. The first and second memory cells may be adjacent cells connected to same word line or to the same bit line. The memory cell array may include a third memory cell adjacent the first memory cell and the data input/output circuit may be further configured to operate the third memory cell as a k-bit cell. The first and second memory cells may be connected to the same word line and the first and third memory cells may be connected to the same bit line. The data input/output circuit may be configured to operate the first memory cell as a j-bit cell responsive to detecting a number of erase operations for the first memory cell meeting a predetermined criterion, wherein j is less than n. In some embodiments, j may be equal to m. | 01-14-2010 |
20100014349 | PROGRAMMING NON-VOLATILE STORAGE USING BINARY AND MULTI-STATE PROGRAMMING PROCESSES - A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block (target block) of multi-state data using a multi-state programming process, where the target block has been previously programmed with binary data X times (or less than X times). | 01-21-2010 |
20100014350 | NAND FLASH MEMORY - A NAND flash memory according to examples of the invention includes a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction and first and second transfer transistor blocks disposed in order in the first direction at one end in a second direction intersecting with the first direction of the memory cell array. An address allocation to the word lines in the first NAND block is inverted against an address allocation to the word lines in the third NAND block. | 01-21-2010 |
20100014351 | SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS - An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states. | 01-21-2010 |
20100014352 | NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION - The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations. | 01-21-2010 |
20100020599 | MULTI-LEVEL FLASH MEMORY - A multi-level flash memory comprises a semiconductor substrate, a gate structure having a lower block positioned in the semiconductor substrate and an upper block positioned on the semiconductor substrate, and a plurality of storage structures separated by the gate structure. The upper block connects to the lower block of the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site. | 01-28-2010 |
20100020600 | PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A programming method of a non-volatile memory device having a drain select transistor, a source select transistor, and a plurality of memory cells connected between the drain select transistor and the source select transistor includes applying a program voltage, which increases stepwise according to a repetition of a program cycle, to a selected memory cell and applying a pass voltage, which decreases in inverse proportion to change of the program voltage, to some of unselected memory cells. | 01-28-2010 |
20100020601 | Multi-Bit Flash Memory Devices and Methods of Programming and Erasing the Same - A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero. | 01-28-2010 |
20100020602 | NON-VOLATILE MEMORY DEVICES AND PROGRAMMING METHODS FOR THE SAME - The non-volatile memory device includes a plurality of memory cells. Each of the memory cells is configured to achieve one of a plurality of states, and each of the states represents different multi-bit data. In one embodiment, the method of programming includes simultaneously programming (1) a first memory cell from a first selected state to a second selected state and (2) a second memory cell from a third selected state to a refined third selected state. The refined third selected state has a higher verify voltage than the third selected state. | 01-28-2010 |
20100020603 | NONVOLATILE SEMICONDUCTOR MEMORY AND DATA WRITING METHOD FOR NONVOLATILE SEMICONDUCTOR MEMORY - A method having the steps of applying the same gate voltage to each of gate terminals of a plurality of memory cells via word lines to designate the memory cells as a write target, and simultaneously applying a write voltage that corresponds to each write data across drain-source terminals of two or more memory cells that are write targets via bit lines to write simultaneously a plurality of data elements having mutually different data values to the memory cells. | 01-28-2010 |
20100020604 | SHIFTING REFERENCE VALUES TO ACCOUNT FOR VOLTAGE SAG - A system and method, including software implemented techniques, can be used to adjust for sag in stored data values. Charge is applied to multiple memory cells, and each memory cell is charged to a target voltage corresponding to a data value. The memory cells include a reference cell that is charged to a predetermined voltage. A voltage level in the reference cell is detected, and voltage levels from a group of memory cells are also detected. An adjustment is performed based upon the difference between the detected voltage level in the reference cell and the predetermined voltage. | 01-28-2010 |
20100020605 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive. | 01-28-2010 |
20100020606 | WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME - A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device. | 01-28-2010 |
20100027332 | FLASH MEMORY PROGRAMMING - A method, device and system are provided for programming a flash memory device, the method including executing a bit line setup operation, and executing a channel pre-charge operation simultaneously with the bit line setup operation, the channel pre-charge operation including applying a channel pre-charge voltage to all word lines; and the device including a voltage generator disposed for providing each of a program voltage, a read voltage, a pass voltage, and a channel pre-charge voltage, a high-voltage switch connected to the voltage generator and disposed for switchably providing one of the program voltage, read voltage, pass voltage, or channel pre-charge voltage, and control logic connected to the high-voltage switch and disposed for simultaneously executing a bit line setup operation and a channel pre-charge operation, the channel pre-charge operation comprising controlling the high-voltage switch to apply the channel pre-charge voltage to both selected and unselected word lines of the device. | 02-04-2010 |
20100027333 | Nonvolatile Semiconductor Memory Device - A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area. | 02-04-2010 |
20100034019 | SYSTEMS AND METHODS FOR PERFORMING A PROGRAM-VERIFY PROCESS ON A NONVOLATILE MEMORY BY SELECTIVELY PRE-CHARGING BIT LINES ASSOCIATED WITH MEMORY CELLS DURING THE VERIFY OPERATIONS - A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation. | 02-11-2010 |
20100034020 | SEMICONDUCTOR MEMORY DEVICE INCLUDING CHARGE STORAGE LAYER AND CONTROL GATE - A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality of memory cells includes a control gate and is configured to hold two-or-higher-level data. Each of signal lines is electrically connected with a gate or one end of a current path of each of the memory cells. Each of signal lines has a line width which differs depending on each interval between the memory cells adjacent to each other. The control unit controls a voltage applied to each of the signal lines in accordance with the line width of each of the signal lines. | 02-11-2010 |
20100039858 | FAST PROGRAMMING MEMORY DEVICE - In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state. | 02-18-2010 |
20100039859 | System and Method for Programming Cells in Non-Volatile Integrated Memory Devices - A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed. | 02-18-2010 |
20100054036 | Methods of precharging non-volatile memory devices during a programming operation and memory devices programmed thereby - Embodiments are directed to a method of programming a semiconductor memory device, the memory device including: a plurality of memory cell transistors arranged in a plurality of transistor strings; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the transistor strings; and a plurality of bit lines, each bit line connected to at least one of the transistor strings, the method comprising: applying a first voltage, and then applying a programming voltage to a selected word line corresponding to the selected memory cell transistor; and in advance of applying the first voltage to the selected word line, applying a second voltage to at least one neighboring word line that neighbors the selected word line, the neighboring word line connected to a neighboring, unselected memory cell transistor of the selected transistor string, to ensure precharging of a channel region of another, unselected transistor string between a first, unselected transistor of the unselected transistor string connected to the neighboring word line and a second, unselected transistor of the unselected transistor string connected to the selected word line, the first, unselected transistor neighboring the second, unselected transistor in the unselected transistor string. | 03-04-2010 |
20100054037 | FLASH MEMORY DEVICE WITH MULTI LEVEL CELL AND BURST ACCESS METHOD THEREIN - A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits. | 03-04-2010 |
20100061148 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF - A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels. | 03-11-2010 |
20100061149 | Non-Volatile Semiconductor Memory - A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells. | 03-11-2010 |
20100067296 | COMPENSATING FOR COUPLING DURING PROGRAMMING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location). | 03-18-2010 |
20100074004 | HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN - Flash memory systems and methodologies are provided herein for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, thereby creating a single program and erase entity. Logical cell erase, program, and/or read can be accomplished by using two channel regions in union. This combination can allow for single logical cell erasure in a flash device and the use of a high voltage state as an erased state. A default erased state can be a high voltage state. As a result, program operations can be performed by changing a voltage state of the single program and erase entity to a low voltage state, and erase operations can be performed by changing a voltage state of the single program and erase entity to a high voltage state. | 03-25-2010 |
20100074005 | EEPROM EMULATION IN FLASH DEVICE - Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase entities can allow for logical cell erase and program in either direction of a low voltage state or a high voltage state on a single bit or variable bit length basis. By employing the single program and erase entity, the subject innovation can provide a cost-effective approach to emulating electrically EEPROM in a flash device. | 03-25-2010 |
20100074006 | DYNAMIC ERASE STATE IN FLASH DEVICE - Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring drain/source regions of two adjacent physical memory cells. The dynamic erase state can involve an indicator bit that indicates an erase direction of a low voltage state or a high voltage state. The single logical cell erasure can be performed by changing a voltage state of a single program and erase entity according to the indicated erase direction. By employing the indicator bit with the single program and erase entity decoding scheme, the methods and systems can reduce erase time and/or a number of cycles, thereby increasing system reliability, efficiency, and/or durability. | 03-25-2010 |
20100074007 | FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL - Flash memory systems and methods are provided for facilitating a single logical cell erasure in a flash memory device. Logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis with conventional technologies. Various operations can be performed on a flash device on a basis of the single program and erase entity. | 03-25-2010 |
20100074008 | SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES - Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting a specific ground scheme at sector level. The sector configure registers can select a decoding scheme from multiple virtual ground decoding schemes including a conventional dual bit decoding scheme and a single program and erase entity decoding scheme. Since the single program and erase entity decoding scheme can emulate EEPROM functionality in a flash device, the combination of the conventional dual bit decoding scheme and the single program and erase entity decoding scheme can provide both dual bit high density storage and EEPROM emulation in a single flash device. | 03-25-2010 |
20100074009 | QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL - Flash memory systems and methodologies are provided herein for facilitating single logical cell erasure and quad or more bit storage in a flash device. The single logical cell erasure can be accomplished by employing a single program and erase entity as a single logical cell. The single program and erase entity is a combination of neighboring drain/source regions of two adjacent physical memory cells. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis. The memory cells can contain four or more data states, and each of the two adjacent memory cells in the single program and erase entity can be programmed independently from each other. As a result, the single program and erase entity can store four or more bits. | 03-25-2010 |
20100074010 | MEMORY DEVICE REFERENCE CELL PROGRAMMING METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed. | 03-25-2010 |
20100074011 | Non-volatile memory device and page buffer circuit thereof - A non-volatile memory device includes a cell array including a plurality of memory cells, a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state, and a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop. | 03-25-2010 |
20100074012 | Least significant bit page recovery method used in multi-level cell flash memory device - A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device is provided. The method includes setting first through n | 03-25-2010 |
20100080056 | SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages. | 04-01-2010 |
20100085807 | SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE - A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on. | 04-08-2010 |
20100085808 | READ METHOD FOR MLC - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Cell reads are performed multiple times and the read threshold voltages averaged to more closely approximate actual threshold voltage and to compensate for random noise. | 04-08-2010 |
20100085809 | MULTI-BIT FLASH MEMORY AND READING METHOD THEREOF - A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data. | 04-08-2010 |
20100091566 | NAND FLASH MEMORY - In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor. | 04-15-2010 |
20100091567 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 04-15-2010 |
20100097855 | Non-volatilization semiconductor memory and the write-in method thereof - Task: to decrease the number of times of the verifying process and shorten the time to program. | 04-22-2010 |
20100097856 | FLASH MEMORY AND ASSOCIATED METHODS - In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period. | 04-22-2010 |
20100097857 | Predictive Programming in Non-Volatile Memory - In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level. | 04-22-2010 |
20100103733 | PROGRAMMING NON-VOLATILE MEMORY WITH VARIABLE INITIAL PROGRAMMING PULSE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse associated with achieving an intermediate result for a respective programming process is identified, a pulse increment between programming pulses is decreased for the respective programming process while continuing the respective programming process to program non-volatile storage elements to the respective one or more targets and the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process. | 04-29-2010 |
20100103734 | PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results. | 04-29-2010 |
20100103735 | MEMORY DEVICE AND PROGRAM METHOD THEREOF - Provided are a flash memory system and a driving method thereof. A flash memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, and a control logic. The control logic performs control for one-bit information to be stored in the plurality of memory cells. The control logic controls storing data in the plurality of memory cells multiple times without an erasion operation. Accordingly, the flash memory device does not execute an erasion operation, increasing an operation speed. | 04-29-2010 |
20100110787 | MEMORY CELL READOUT USING SUCCESSIVE APPROXIMATION - A method for operating a memory ( | 05-06-2010 |
20100110788 | DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY - Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array. | 05-06-2010 |
20100110789 | MEMORY DEVICE BIASING METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device. | 05-06-2010 |
20100110790 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline. | 05-06-2010 |
20100118605 | SEMICONDUCTOR STORAGE DEVICE ADAPTED TO PREVENT ERRONEOUS WRITING TO NON-SELECTED MEMORY CELLS - A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation. | 05-13-2010 |
20100118606 | Methods of programming non-volatile memory devices and memory devices programmed thereby - In a method of programming a non-volatile memory device, and in a device incorporating the same, the memory device includes: a plurality of memory cell transistors arranged in a plurality of transistor strings, wherein a transistor string includes a plurality of memory cell transistors arranged in series; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the different transistor strings; and a plurality of bit lines, each bit line connected to one of the transistor strings. The method comprises: applying a first voltage to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; and applying a second voltage to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor. | 05-13-2010 |
20100118607 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 05-13-2010 |
20100124108 | PROGRAMMING METHODS AND MEMORIES - Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used. | 05-20-2010 |
20100124109 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTI LEVEL DATA - A memory cell array is configured so that a plurality of memory cells which are connected to a word line and a bit line store one value out of n values (n is a natural number of 2 or more) in one memory cell and are arranged in a matrix. A control circuit controls electronic potentials of the word line and the bit line in response to input data to write data in the memory cells. When writing data in the first memory cell of the memory cell array, the control circuit varies a writing level on the basis of writing data to write in a second memory cell adjacent to the first memory cell. | 05-20-2010 |
20100124110 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit. | 05-20-2010 |
20100124111 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile semiconductor memory device comprises: a memory cell array including a plurality of memory cell units each including memory cells, a plurality of bit lines, and a common source line; a sense amplifier operative to read data from a selected memory cell; a control circuit operative to control a read operation of the sense amplifier; and a cell source monitoring circuit operative to detect a voltage of the common source line, compare the detected voltage of the common source line with a reference voltage, and output a read control signal. The sense amplifier is configured to read data from the selected memory cell through at least two cycles. The control circuit is configured to perform control to determine whether the data reading is to be ended after a first reading cycle or a second reading cycle is to be carried out, based on the read control signal. | 05-20-2010 |
20100124112 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a plurality of cells for storing data on a basis of charges stored nonvolatilly, a write unit for writing and erasing data on the cell by injecting or extracting charges into or from the cell, a comparator for comparing the voltage produced by a selected cell to be read out with a threshold, a read unit for outputting read data on the basis of the comparison result by the comparator, and a threshold update unit for updating the threshold of the comparator according to the voltage produced by the selected cell. | 05-20-2010 |
20100124113 | SEMICONDUCTOR MEMORY WRITE METHOD - A semiconductor memory write method which, when writing data at a threshold voltage level in a memory cell, is configured to perform two write operations including a preliminary data write operation of writing temporary data at a threshold voltage level lower than that of the data at the threshold voltage level, and a final data write operation of additionally writing final data at the threshold voltage level, includes making at least one of a write time of the preliminary data write operation, a word-line waiting time of verify read, and a bit-line waiting time of verify read, shorter than that of the final data write operation. | 05-20-2010 |
20100128523 | MULTI-PASS PROGRAMMING IN A MEMORY DEVICE - A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further. | 05-27-2010 |
20100128524 | MULTI-PHASE PROGRAMMING OF MULTI-LEVEL MEMORY - Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed using learned drain voltages as initial drain voltages where drain voltage levels are varied during each program pulse to facilitate programming memory cells to respective intrinsic verify voltage levels based on respective data levels. A second programming phase is performed using ending drain voltages from the first programming phase as initial drain voltages where gate voltage levels are varied during each program pulse to facilitate programming memory cells to respective final verify voltage levels based on respective data levels. | 05-27-2010 |
20100128525 | ALL-BIT-LINE ERASE VERIFY AND SOFT PROGRAM VERIFY - Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased. | 05-27-2010 |
20100128526 | MULTI-LEVEL NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which changes a set up term of the selected word line and the non-selected word line based on a value of the selected read potential, wherein the value of the selected read potential is selected from two or more potentials. | 05-27-2010 |
20100128527 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a data memory cell array having multi level memory cells divided into two groups, a write sequence memory cell array configured to store a write sequence indicating in which of the two groups the multi level data was written first, and a write time memory cell array configured to store the number of write operations performed on the memory cells. The memory device further includes a control circuit configured to control a program operation by determining allocation of data corresponding to a minimum physical voltage distribution causing a reaction of the memory cells, such that a shift of a first minimum physical voltage causing a reaction due to the first write operation and a shift of a second minimum physical voltage causing a reaction due to the second write operation are equal regardless of write sequence. | 05-27-2010 |
20100128528 | MEMORY CELL PROGRAMMING - One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least in part, on the one of the first number of states and the second cell to one of a fourth number of states based, at least in part, on the one of the second number of states. | 05-27-2010 |
20100128529 | NAND STEP VOLTAGE SWITCHING METHOD - Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired. | 05-27-2010 |
20100135078 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 06-03-2010 |
20100135079 | MULTILEVEL STORAGE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE ENABLING HIGH-SPEED DATA READING AND HIGH-SPEED DATA WRITING - A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2 | 06-03-2010 |
20100142269 | MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS - A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access. | 06-10-2010 |
20100142270 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM STORING MULTILEVEL DATA - A first memory cell stores data of k bits in one cell. A second memory cell stores data of h bits (h06-10-2010 | |
20100142271 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING A SHIFT OF THRESHOLD VOLTAGE - A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels. | 06-10-2010 |
20100142272 | METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP - In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC. | 06-10-2010 |
20100142273 | PROGRAMMING METHODS FOR MULTI-LEVEL MEMORY DEVICES - A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage. | 06-10-2010 |
20100142274 | MULTILEVEL MEMORY CELL OPERATION - One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a reference cell to a Vt level at least as great as an uppermost Vt level of the number of different Vt levels, performing a read operation on the reference cell, and determining a number of read reference voltages used to determine a particular program state of the memory cell based on the read operation performed on the reference cell. | 06-10-2010 |
20100149867 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a nonvolatile memory which includes a block having a plurality of memory cell groups, each of the memory cell groups being electrically connected to a plurality of bit lines and electrically connected to a common word line, each memory cell being recordable of a plurality of bits, a first register which stores information obtained by correcting first data to be written to a first word line, and a control circuit which sets a set potential in the first register and writes the bits to a write target first memory cell at a time using the information in the first register, the set potential being obtained by subtracting, from a target potential to be finally set in the first memory cell, a potential increase which is generated by setting a potential in an unwritten second memory cell adjacent to the first memory cell. | 06-17-2010 |
20100149868 | Access method of non-volatile memory device - Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected sub-distribution from among a plurality of sub-distributions according to a distance of the threshold voltage variation of the first memory cell, the plurality of sub-distributions corresponding to a target distribution of the second memory cell. | 06-17-2010 |
20100149869 | MULTI-LEVEL CELL FLASH MEMORY DEVICE AND READ METHOD - A method of reading data of a multi-level cell (MLC) flash memory device is disclosed. The method includes reading a least significant bit (LSB) and a most significant bit (MSB) of the data programmed to a plurality of memory cells. Reading each of the LSB and MSB includes; reading a MSB flag indicating whether or not the MSB for memory cells in a page of memory cells has been programmed, performing a first read with respect to a plurality of first bit lines, setting a target voltage in view of the read value of the MSB flag, applying the target voltage to a plurality of second bit lines, and performing a second read with respect to the plurality of second bit lines. | 06-17-2010 |
20100149870 | NON-VOLATILE SEMICONDUCTOR MEMORY, AND THE METHOD THEREOF - A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array | 06-17-2010 |
20100149871 | Reading method of nonvolatile semiconductor memory device - Reading methods of a nonvolatile semiconductor memory device are described herein. Methods may include supplying, to a word line, one of a voltage corresponding to a highest reading level or a voltage having a level higher than a first reading level of a read operation to be performed on the word line, and subsequently supplying a voltage of the first reading level to the word line and performing the read operation. | 06-17-2010 |
20100149872 | Nonvolatile memory device and method for operating the same - Methods for operating a nonvolatile memory device including multi-level cells configured to store at least n logic states, where n is equal to or greater than four are provided. The methods may include selecting at least one read voltage for a read operation based on information set at a portion of an address of the respective one of the multi-level cells, and determining multi-level data stored in the respective multi-level cell using the at least one selected read voltage. | 06-17-2010 |
20100157671 | DATA REFRESH FOR NON-VOLATILE STORAGE - Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element. | 06-24-2010 |
20100157672 | Wordline Temperature Compensation - A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature compensated wordline signal(s) to the nonvolatile memory. The temperature compensated wordline signals change as the temperature dependent read window changes. | 06-24-2010 |
20100157673 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME - A non-volatile semiconductor memory device capable of preventing reading failure during the occurrence of the FG-FG coupling effect is disclosed. The non-volatile semiconductor memory device includes a memory cell array, each cell of which stores at least two bits, such as LSB and MSB, using different threshold voltages. In addition, the device includes a control circuit for controlling the data-reading operation of the memory cell array. When the reading operation of the memory cells of a first word line is performed, the memory cells of a second word line adjacent to the first word line are examined to determine whether the writing operation of the MSB is performed. If the writing operation of the MSB is performed, a pre-charge voltage of the bit lines connecting to the memory cells of the first word line is reduced to a predetermined voltage for canceling out the raising of the threshold voltage caused by the coupling effect between gate electrodes. | 06-24-2010 |
20100157674 | Two Levels of Voltage Regulation Supplied for Logic and Data Programming Voltage of a Memory Device - Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection of flash memory cells to be supplied with power from the first input during a write operation. | 06-24-2010 |
20100157675 | PROGRAMMING ORDERS FOR REDUCING DISTORTION IN ARRAYS OF MULTI-LEVEL ANALOG MEMORY CELLS - A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order. | 06-24-2010 |
20100165730 | READING MEMORY CELLS USING MULTIPLE THRESHOLDS - A method for operating a memory ( | 07-01-2010 |
20100165731 | MEMORY DEVICE AND OPERATING METHOD - A method of operating a memory device includes; defining a plurality of read levels, using the plurality of read levels to determine electrical property differences between first and second memory cells adjacent dispose along a common word line, and determining read data stored in the first and second memory cells in relation to the determination of electrical property differences between the first and second memory cells. | 07-01-2010 |
20100172175 | MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 07-08-2010 |
20100177563 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 07-15-2010 |
20100182832 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower pages and an upper page. One method includes programming a first lower page, programming a second lower page, programming a third lower page, programming an upper page, and reprogramming the upper page of a cell. | 07-22-2010 |
20100188899 | NONVOLATILE ANALOG MEMORY - A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor. a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage. | 07-29-2010 |
20100195385 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of sequentially performing a LSB program operation and an MSB program operation of a nonvolatile memory device, wherein the nonvolatile memory device comprises multi-level memory cells each configured to store two pieces of bit information and page buffers each coupled to a bit line coupled with the memory cells and configured to comprise a first latch coupled to first and second nodes and a second latch coupled to third and fourth nodes, the method including inputting data of MSBs to the second and fourth nodes and setting data of the second and fourth nodes according to a state of data of LSBs stored in the memory cells, and precharging the bit line according to a combination of data stored in the first and second latches and performing the MSB program operation according to a state of a LSB program operation stored in the memory cells. | 08-05-2010 |
20100195386 | PAGE BUFFER CIRCUIT AND NONVOLATILE MEMORY DEVICE - A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node. | 08-05-2010 |
20100195387 | NON-VOLATILE MEMORY DEVICE AND ISPP PROGRAMMING METHOD - A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition. | 08-05-2010 |
20100195388 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes sequentially programming first to (n−1) | 08-05-2010 |
20100195389 | FLASH MEMORY DEVICE AND METHODS PROGRAMMING/READING FLASH MEMORY DEVICE - Multilevel flash memory and methods of programming/reading flash memory are disclosed. The multilevel flash memory device comprises a status detector configured to detect whether or not a target memory cell is programmed to an erase state, and a control logic unit controlling a program voltage applied to a neighboring memory cell adjacent to the target memory cell and to be programmed to one of a plurality of standard program states, such that the neighboring memory cell is programmed to a corresponding one of a plurality of correction program states different from the one of the plurality of standard program states. | 08-05-2010 |
20100195390 | MEMORY DEVICE WITH NEGATIVE THRESHOLDS - A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read reference levels is negative. After storing the data, second storage values are read from the cells using the read reference levels, so as to reconstruct the stored data. In another disclosed method, data is stored in the memory by mapping the data to first storage values selected from a set of the nominal storage values, and writing the first storage values to the cells. The set of nominal storage values is defined such that at least one of the nominal storage values is negative. | 08-05-2010 |
20100202197 | OPERATION METHODS OF NONVOLATILE MEMORY DEVICE - An operation method includes performing a first program operation and a first program verification operation on an even page memory cell group wherein the first program operation is performed such that the even page memory cell group is programmed to have a threshold voltage less than a target threshold voltage, performing a second program operation and a second program verification operation on an odd page memory cell group neighboring the even page memory cell group when the first verification operation is passed, performing a third program operation and a third program verification operation on the even page memory cell group when the second verification operation is passed, wherein the third program operation is performed such that the even page memory cell group is programmed to have a threshold voltage which is equal to or higher than the target threshold voltage. | 08-12-2010 |
20100202198 | Semiconductor memory device and data processing method thereof - Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states. | 08-12-2010 |
20100202199 | TRACKING CELLS FOR A MEMORY SYSTEM - Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading. | 08-12-2010 |
20100202200 | Power Line Compensation for Flash Memory Sense Amplifiers - In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current. | 08-12-2010 |
20100208519 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME - First and second data retaining circuits retain data read from memory cell and threshold voltage information indicating where in one of plural threshold voltage distributions threshold voltage of memory cell is located. Calculation device executes calculations among data retained in first and second data retaining circuit and data read by sense amplifier. | 08-19-2010 |
20100214837 | NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES - A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage. | 08-26-2010 |
20100220525 | NON-VOLATILE MEMORY DEVICE AND ERASE AND READ METHODS THEREOF - An erase method of a non-volatile memory device includes first erasing memory cells of a non-volatile memory device with a first erase voltage; in response to a judgment that the erasure of at least one of the memory cells has failed, determining an amount of voltage to add to the first erase voltage, the amount being based on a threshold voltage distribution of the first erased memory cells; and second erasing the memory cells with a second erase voltage, the second erase voltage being higher than the first erase voltage by the determined amount. | 09-02-2010 |
20100220526 | NONVOLATILE MEMORY DEVICE, SYSTEM, AND PROGRAMMING METHOD - A nonvolatile memory device stores program data in a first address area, determines whether the first address area is a most significant address area and whether the program data is reliable data, and upon determining that the first address area is not a most significant address area and that the program data is reliable data, additionally stores the program data in a second address area. | 09-02-2010 |
20100226170 | Non-volatile Memory Array Having Circuitry To Complete Programming Operation In The Event Of Power Interrupt - An electrically programmable non-volatile memory device comprises a memory circuit which includes an array of non-volatile memory cells. Each memory cell is capable of being programmed. A programming circuit can generate a programming signal to program one or more of the memory cells. A voltage detector circuit is connected to a voltage source which outputs a certain voltage. The voltage detector circuit detects when the certain voltage has decreased to a certain level, and in response thereto, the voltage detector provides an output signal to the memory controller to complete the on-going programming command sequence and to power down itself. An auxiliary voltage source maintains voltage to the memory circuit for a period of time sufficient for the programming circuit to complete the programming of the one or more of the memory cells, when the certain voltage is at or below the certain level. | 09-09-2010 |
20100226171 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes receiving a program command, performing program and verification operations in response to each of a number of program pulse, and performing an n number of program operations, where n is a positive integer and at least one verification operation for the n program operations has been omitted. | 09-09-2010 |
20100226172 | METHOD OF READING DATA AND METHOD OF INPUTTING AND OUTPUTTING DATA IN NON-VOLATILE MEMORY DEVICE - A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address. | 09-09-2010 |
20100226174 | MULTIPLE BIT PER CELL NON VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME - A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an M | 09-09-2010 |
20100226175 | MEMORY DEVICES AND METHODS OF WRITING DATA TO MEMORY DEVICES UTILIZING ANALOG VOLTAGE LEVELS - Memory devices, and methods of writing data to memory devices, utilizing analog voltage levels indicative of threshold voltages and desired threshold voltages of memory cells. | 09-09-2010 |
20100226176 | Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations - Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles. | 09-09-2010 |
20100226177 | NON-VOLATILE MULTILEVEL MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states. | 09-09-2010 |
20100232221 | NONVOLATILE MEMORY DEVICE AND METHOD OF READING SAME - A method of reading a nonvolatile memory device comprises sensing data stored in memory cells adjacent to selected memory cells to identify adjacent aggressor cells, and performing separate precharge operations on bitlines connected to selected memory cells having adjacent aggressor cells and on bitlines connected to selected memory cells having adjacent non-aggressor cells. | 09-16-2010 |
20100232222 | MEMORY PAGE BOOSTING METHOD, DEVICE AND SYSTEM - A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells. | 09-16-2010 |
20100238723 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell. During writing of information to a plurality of the memory cells connected to an identical word line, the control circuit is configured to apply, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written. | 09-23-2010 |
20100238724 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor memory device includes a memory cell array including a plurality of memory cells, a first data latch circuit, a second data latch circuit, an arithmetic circuit, a counter circuit, and a controller. And controller compares the number (N) counted by the counter circuit with a reference number (M), and performs control to output flag information outside if N≧M. | 09-23-2010 |
20100238725 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF PROGRAMMING DATA THEREIN - Each of the memory cells stores multiple bits of data by way of a threshold voltage distribution having a negative value and representing an erase state, and a plurality of threshold voltage distributions each having a value higher than the threshold voltage distribution representing the erase state and representing a programming state. In a data programming operation, a control circuit applies a certain verify voltage to a control gate of one of the memory cells to be written to obtain a threshold voltage distribution higher than the threshold voltage distribution representing the erase state, thereby confirming the programming state of the memory cells. The control circuit also applies, in a data programming operation, a certain verify voltage to a control gate of one of the memory cells maintained in the erase state, thereby adjusting a lower limit value of the threshold voltage distribution representing the erase state. | 09-23-2010 |
20100238726 | FLASH MEMORY WITH MULTI-BIT READ - A memory device is described that comprises determining which read data state of more than 2 | 09-23-2010 |
20100246257 | FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION - Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times. | 09-30-2010 |
20100246258 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory cells, a voltage generator configured to generate voltages to program the plurality of memory cells, and a control logic component configured to control the voltage generator to provide a plurality of program voltages to selected memory cells during successive iterations of a program loop. Wherein where memory cells corresponding to one logic state are judged to be program passed during a current iteration of the program loop, the control logic component controls the voltage generator such that a program voltage corresponding to the one logic state is skipped during subsequent iterations of the program loop. | 09-30-2010 |
20100246259 | FLASH MEMORY DEVICE, PROGRAMMING METHOD AND MEMORY SYSTEM - Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a programming voltage to the selection word line. | 09-30-2010 |
20100246260 | NONVOLATILE MEMORY DEVICE, SYSTEM, AND PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data. | 09-30-2010 |
20100246261 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 09-30-2010 |
20100246262 | METHODS AND CONTROL CIRCUITRY FOR PROGRAMMING MEMORY CELLS - Methods of programming memory cells and control circuitry for memory arrays facilitate a reduction of program disturb. A memory cell is shifted from a first data state to a second data state if it is desired to alter a first digit of a data value of the memory cell. If it is desired to alter a second digit of the data value of the memory cell, the memory cell is shifted to a third data state if the memory cell is in the first data state and shifted to a fourth data state if the memory cell is in the second data state. The first, second, third and fourth data states correspond to respective non-overlapping ranges of threshold voltages. The threshold voltages corresponding to the fourth data state are greater than the threshold voltages corresponding to the third data state. | 09-30-2010 |
20100254187 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a cell array including a plurality of nonvolatile memory cells electrically connected to a common word line, each memory cell storing a plurality of bits including a plurality of potential ranks, and a controller measuring a potential of the memory cell for each potential rank and changing a lower limit and upper limit of the potential rank based on the measurement result. | 10-07-2010 |
20100254188 | METHOD FOR PROGRAMMING NONVOLATILE MEMORY DEVICE - A method programs a nonvolatile memory device to program memory cells from one or more first logic states to two or more second logic states. In the method, a number of program voltages are provided to a selected word line, and verify voltages corresponding to the second logic states are provided to the selected word line. The number of the program voltages provided to the selected word line varies according to the threshold voltage difference between each of the first logic states and each of the second logic states. | 10-07-2010 |
20100254189 | Apparatus and method of memory programming - A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells. | 10-07-2010 |
20100259979 | Self Limiting Method For Programming A Non-volatile Memory Cell To One Of A Plurality Of MLC Levels - A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end, a floating gate insulated from a first portion of the channel region and adjacent to the second region, a first control gate adjacent to the floating gate and insulated therefrom, and insulated from a second portion of the channel region, and adjacent to the first region, a second control gate capacitively coupled to the floating gate, and positioned over the floating gate. A method programming the cell to one of a plurality of MLC states comprises applying a current source to the first region. A first voltage is applied to the first control gate sufficient to turn on the second portion of the channel region. A second voltage is applied to the second region, sufficient to cause electrons to flow from the first region towards the second region. A third voltage is applied to the second control gate sufficient to cause electrons in the channel region to be injected onto the floating gate. The third voltage is applied uninterrupted until the floating gate is programmed to the one state. | 10-14-2010 |
20100259980 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. | 10-14-2010 |
20100265766 | BANDGAP ENGINEERED CHARGE TRAPPING MEMORY IN TWO-TRANSISTOR NOR ARCHITECTURE - A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric stack comprises a bandgap engineered, tunneling dielectric layer contacting one of the gate (for gate injection tunneling) and the channel surface (for channel injection tunneling). The dielectric stack of the memory cell also includes a charge trapping dielectric layer on the tunneling dielectric layer and a blocking dielectric layer. | 10-21-2010 |
20100265767 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF FABRICATING THE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF WRITING DATA ON THE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film. | 10-21-2010 |
20100265768 | SEMICONDUCTOR STORAGE APPARATUS, CONTROL APPARATUS AND CONTROL METHOD - A semiconductor storage apparatus comprising: a plurality of cells that store data; a threshold determination section that determines, based on management information that is used to manage data, a binary or multiple-valued form by which values are written to a plurality of the individual cells and determines a threshold based on the determined form of values that are to be written to a plurality of the individual cells; and a write section that writes the data to a plurality of the cells on the basis of the threshold determined by the threshold determination section. | 10-21-2010 |
20100271875 | Compensating for Variations in Memory Cell Programmed State Distributions - Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined. | 10-28-2010 |
20100271876 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND MEMORY SYSTEM - A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2 | 10-28-2010 |
20100271877 | METHOD, APPARATUS, AND SYSTEM FOR ERASING MEMORY - Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example of applying such a pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored in the plurality of multiple level memory cells, and erasing the plurality of multiple level memory cells of the memory block based on a result from verifying the charge stored in the plurality of multiple level memory cells. | 10-28-2010 |
20100277977 | NAND FLASH MEMORY - A NAND flash memory includes a semiconductor substrate, a well region in the semiconductor substrate, memory cells connected in series in the well region, a discharge circuit connected to the well region, a word line connected to the memory cells, and a control circuit which controls potentials of the well region and the word line. The control circuit set the well region to a first potential, and set the word line to a second potential lower than the first potential, in an erase operation. The discharge circuit comprises a constant current source with a constant discharge speed independent on a temperature, and discharges the well region after the erase operation. | 11-04-2010 |
20100277978 | FLASH MEMORY DEVICE HAVING IMPROVED READ OPERATION SPEED - Provided is a flash memory device. The flash memory device includes: a memory cell storing multi-bit data; a reference bias voltage supply circuit generating a reference bias voltage; an sense amplifier sensing the multi-bit data stored in the memory cell using the reference bias voltage; and a control circuit controlling the reference bias voltage supply circuit. The control circuit controls the reference bias voltage supply circuit to allow the reference bias voltage to be developed according to a change of a main word line voltage applied to the memory cell during a read operation. | 11-04-2010 |
20100277979 | MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM - A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result. | 11-04-2010 |
20100277980 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 11-04-2010 |
20100277981 | NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells. | 11-04-2010 |
20100284219 | MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE - Methods for multiple level program verify, memory devices, and memory systems are disclosed. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold. | 11-11-2010 |
20100284220 | OPERATION METHOD OF NON-VOLATILE MEMORY - An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels. | 11-11-2010 |
20100290282 | METHOD AND SYSTEM FOR ADAPTIVELY FINDING REFERENCE VOLTAGES FOR READING DATA FROM A MLC FLASH MEMORY - A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, information about an initial threshold voltage distribution is firstly provided. A first threshold voltage in the initial threshold voltage distribution is then associated with a second threshold voltage in a shifted threshold voltage distribution to be determined, such that the information corresponding to the first threshold voltage is approximate to the information corresponding to the second threshold voltage. Accordingly, initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to difference between the first threshold voltage and the second threshold voltage, thereby resulting in new reference voltage or voltages for reading the data from the MLC flash memory. | 11-18-2010 |
20100290283 | Programming Method for Flash Memory Device - Provided is a programming method that increases writing performance of a flash memory device. The programming method for a flash memory device that includes a plurality of banks including a plurality of memory cells for storing multi-bit data includes the following: programming a most significant bit (MSB) page with respect to banks of a first bank group; programming a least significant bit (LSB) page with respect to banks of a second bank group; programming the MSB page with respect to the banks of the second bank group; and programming the LSB page with respect to the banks of the first bank group. | 11-18-2010 |
20100302845 | MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME - The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits. | 12-02-2010 |
20100302846 | CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY - A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell. | 12-02-2010 |
20100302847 | MULTI-LEVEL NAND FLASH MEMORY - According to one embodiment, a multi-level NAND flash memory executes a writing of an upper data to a LM flag. When an address of a flag assigns a bad column, a data transfer control circuit and a address control circuit control a write operation of upper data in the flag by an operation of transmitting the upper data of the flag from the bad column data hold circuit to the data latch circuit, reading the lower data of the flag from a redundancy column storing the flag into the data latch circuit, generating an address of a redundancy column storing the flag based on the address of the flag, and forcefully inverting the lower data of the flag in the data latch circuit by using the address of the redundancy column storing the flag. | 12-02-2010 |
20100309719 | Folding Data Stored in Binary Format Into Multi-State Format Within Non-Volatile Memory Devices - Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. | 12-09-2010 |
20100309720 | Structure and Method for Shuffling Data Within Non-Volatile Memory Devices - Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process. | 12-09-2010 |
20100309721 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cells, a bit line, a sense amplifier, a memory circuit and an arithmetic circuit. The memory cells store multiple values in one memory cell. The bit line connected with the memory cells. The sense amplifier supplies a write voltage to the bit line. The memory circuit stores one of write data that is to be written in the memory cell and the number of writes. The arithmetic circuit changes the write data stored in the memory circuit to the number of writes and updates the number of writes. The arithmetic circuit controls the write voltage supplied from the sense amplifier based on the write data, and sets the number of writes in accordance with the write data stored in the memory circuit upon confirmation that each memory cell has reached a predetermined threshold voltage. | 12-09-2010 |
20100315872 | Multilevel Cell Memory Devices Having Reference Point Cells - Embodiments of the disclosure include multilevel memory cell devices that utilize reference point cells to determine the states of other cells. Embodiments of the disclosure also include methods of storing data to and retrieving data from multilevel memory cell devices utilizing reference point cells. In one embodiment, a multilevel memory cell device includes user data cells, a reference point cell, and a controller. The user data cells each has one of a plurality of states. The reference point cell has a first state. The controller determines the states of the user data cells based at least in part on the first state of the reference point cell. | 12-16-2010 |
20100315873 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises receiving program data, detecting logic states of the received program data, identifying adjusted margins to be applied to programmed memory cells based on the absence of one or more logic states in the detected logic states, and programming the program data in selected memory cells using the adjusted margins. | 12-16-2010 |
20100321997 | Method And System For Obtaining A Reference Block For A MLC Flash Memory - A method and system for obtaining a reference block on which reference voltages may be found for a MLC flash memory are disclosed. A first block and a second block are provided in the flash memory. A memory controller alternatively controls one of the first and the second blocks to act as the reference block and the other one as a cycle block in a respective period, during which the reference block stays idle and the cycle block is subjected to program/erase cycles. | 12-23-2010 |
20100321998 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises pre-programming multi-bit data in a plurality of multi-level memory cells, reading the pre-programmed multi-bit data from the plurality of multi-level cells based on state group codes indicating state groups of the plurality of multi-level cells, and re-programming the read multi-bit data to the plurality of multi-level cells. | 12-23-2010 |
20100321999 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline. | 12-23-2010 |
20100322000 | PROGRAMMING METHODS FOR THREE-DIMENSIONAL MEMORY DEVICES HAVING MULTI-BIT PROGRAMMING, AND THREE-DIMENSIONAL MEMORY DEVICES PROGRAMMED THEREBY - In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states. | 12-23-2010 |
20100322001 | INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING AND SEPARATE READ/WRITE PATHS - A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Different source/drain regions can be used for program and read operations. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 12-23-2010 |
20100329004 | DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level. | 12-30-2010 |
20100329005 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines. | 12-30-2010 |
20100329006 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEMORIZING MULTIVALUED DATA - In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2 | 12-30-2010 |
20110002165 | FLASH MEMORY - A flash memory according to a present embodiment includes a memory cell array. The memory cell array includes a plurality of memory cells. Each of the memory cells can store n-bit data (n is an integer equal to or larger than 2). A plurality of word line are connected to gate terminals of the memory cells. A plurality of bit lines are connected to the memory cells. Sense amplifiers are configured to detect data stored in the memory cells via the bit lines. A data latch circuit of m×n bits can store n-bit data stored in each of m memory cells (m is an integer equal to or larger than 2) connected to one of the word lines. A multi-level interface can simultaneously transfer data of two or more bits between the data latch circuit and outside. | 01-06-2011 |
20110002166 | TWO-BIT NON-VOLATILE FLASH MEMORY ARRAY - A memory array comprises a semiconductor substrate, two-bit memory cells, word lines, a gate voltage source, bit lines and bit line control cells. The memory cells have a first and a second source/drain regions, each memory cell includes a dielectric trapping layer, and the dielectric trapping layer is disposed between a first oxide layer and a gate layer. The word lines are coupled to the gate layer. The gate voltage source is coupled to the word lines and configured to apply erase voltages between 14 and 20 volts to the word lines. The bit lines are in electrical communication with the first and the second source/drain regions. The bit line control cells are disposed at the beginning and end of each bit line, the bit line control cells are configured to control the electrical communication of each bit line with the first and the second source/drain regions. | 01-06-2011 |
20110007562 | Dynamic wordline start voltage for nand programming - The present invention discloses a method of programming an MLC NAND flash memory device comprising: selecting a start value for a program voltage for a lower page; incrementing said program voltage to program said lower page; verifying a threshold voltage; determining said program voltage to achieve a desired value for said threshold voltage; applying an offset to said program voltage; and obtaining a start value for said program voltage for an upper page. | 01-13-2011 |
20110007563 | NONVOLATILE MEMORY DEVICE, SYSTEM, AND RELATED METHODS OF OPERATION - A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells. | 01-13-2011 |
20110007564 | FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME - A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages. | 01-13-2011 |
20110007565 | MULTILEVEL SEMICONDUCTOR MEMORY, WRITE/READ METHOD THERETO/THEREFROM AND STORAGE MEDIUM STORING WRITE/READ PROGRAM - A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2 | 01-13-2011 |
20110007566 | MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE - Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read. | 01-13-2011 |
20110013450 | METHOD FOR ADAPTIVE SETTING OF STATE VOLTAGE LEVELS IN NON-VOLATILE MEMORY - A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user. | 01-20-2011 |
20110013451 | NON-VOLATILE MEMORY DEVICE WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions. | 01-20-2011 |
20110019470 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, in which a multi-bit region including multi-bit memory cells that store data of two or more bits and a region including memory cells that store data of bits that are less than the bits of the data stored in the multi-bit memory cells are installed, is provided, which can perform a high-speed writing and lengthen the life span of the product without increasing the storage capacity of the region of the memory cells storing the data of bits that are less than the bits of the data in the multi-bit memory cells. The semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i01-27-2011 | |
20110019471 | Nonvolatile Memory with Correlated Multiple Pass Programming - A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size, and each successive pass has the staircase pulse train offset from that of the previous pass by a predetermined offset level. The predetermined offset level is less than the common step size and may be less than or equal to the predetermined offset level of the previous pass. Thus, the same programming resolution can be achieved over multiple passes using fewer programming pulses than conventional method where each successive pass uses a programming staircase pulse train with a finer step size. The multiple pass programming serves to tighten the distribution of the programmed thresholds while reducing the overall number of programming pulses. | 01-27-2011 |
20110019472 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A nonvolatile semiconductor memory device and a programming method thereof are provided. The programming method includes first programming a cell among a plurality of adjacent memory cells to the highest threshold voltage distribution corresponding to a data state, and subsequently programming the other adjacent cells to the lower threshold voltage distributions corresponding to second and third data states. The second data state and the third data state may have the second highest threshold voltage distribution and the third highest threshold voltage distribution, respectively, or the third highest threshold voltage distribution and the second highest threshold voltage distribution, respectively. | 01-27-2011 |
20110026325 | METHOD OF PROGRAMMING A MULTI LEVEL CELL - A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 02-03-2011 |
20110032758 | NONVOLATILE MEMORY DEVICE OUTPUTTING ANALOG SIGNAL AND MEMORY SYSTEM HAVING THE SAME - A memory system and a nonvolatile memory device therein are disclosed. The memory system comprises a memory device outputting a plurality of analog signals during a read operation, a converter to convert the plurality of analog signals into binary data, and a memory controller to operate an error correction operation on the binary data. The error correction operation uses a soft decision algorithm. | 02-10-2011 |
20110032759 | MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line. | 02-10-2011 |
20110032760 | METHOD OF READING DATA IN SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER - According to one embodiment, a method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns includes reading flag data from the memory cells associated with one of the columns into associated one of the latch circuits, selecting one of the latch circuits sequentially, while shifting one of the latch circuits to be selected, and reading the flag data from one of the latch circuits selected in an N | 02-10-2011 |
20110032761 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-10-2011 |
20110038204 | METHOD AND APPARATUS FOR INCREASING MEMORY PROGRAMMING EFFICIENCY THROUGH DYNAMIC SWITCHING OF SENSE AMPLIFIERS - A method and apparatus are described that efficiently program charge-trapping memory cells by dynamically switching sense amplifiers and corresponding drivers depending upon data to be programmed. When a number of sense amplifier/drivers can be operated simultaneously, cells to be programmed to a same level are selected and programmed simultaneously employing up to the number of simultaneously operable sense amplifier/drivers. | 02-17-2011 |
20110038205 | Method Of Reducing Bit Error Rate For A Flash Memory - A method of reducing coupling effect in a flash memory is disclosed. A neighboring page is read, and a flag is set active if the neighboring page is an interfering page. Data are read from the neighboring page at least two more times using at least two distinct read voltages respectively. The threshold-voltage distributions associated with an original page and the neighboring page are transferred according to the read data and the flag. | 02-17-2011 |
20110038206 | SEMICONDUCTOR STORAGE DEVICE TO CORRECT THRESHOLD DISTRIBUTION OF MEMORY CELLS BY REWRITING AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor storage device includes a first cell, a second cell, a bit line, a first buffer, a second buffer, and a controller. The bit line transfers the data to the first cell and the second cell. The first buffer holds write data to the first cell and the second cell. The second buffer holds read data from the first cell. The controller controls first writing and rewriting executed for the first cell and second writing executed for the second cell. The write data in the first buffer is updated each time a second write signal is given. The controller executes the first writing based on the write data held by the first buffer. The controller performs the second writing based on the write data updated in the first buffer. The controller executes the rewriting based on the read data held by the second buffer. | 02-17-2011 |
20110038207 | FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME - The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through N | 02-17-2011 |
20110038208 | METHOD OF READING DUAL-BIT MEMORY CELL - A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value. | 02-17-2011 |
20110038209 | Method and System for Adaptively Finding Reference Voltages for Reading Data from a MLC Flash Memory - A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, a first total number of cells of the flash memory above a first threshold voltage in a shifted threshold voltage distribution is provided. Search to find a second threshold voltage such that a second total number of the cells above the second threshold voltage is approximate to the first total number. An initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to a voltage difference between the second threshold voltage and the first threshold voltage, thereby resulting in a new reference voltage or voltages for reading the data from the MLC flash memory. | 02-17-2011 |
20110044100 | FLASH MEMORY CELL AND METHOD FOR OPERATING THE SAME - A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate, a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, a second doped region disposed in the semiconductor substrate at a second side of the first charge-trapping region, a first dielectric layer separating the semiconductor substrate from the first charge-trapping region and the second charge-trapping region, a first conductor disposed above the first charge-trapping region, and a second dielectric layer separating the first charge-trapping region from the first conductor, wherein the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region. | 02-24-2011 |
20110044101 | METHOD AND SYSTEM OF FINDING A READ VOLTAGE FOR A FLASH MEMORY - A method and system of finding a read voltage for a flash memory is disclosed. Data are read from array cells of the flash memory with a default read voltage, and a recorded state bit number that is recorded during programming is also read. Determine an optimal read voltage if the readout data do not pass the error correction control (ECC). Data are then re-read from the array cells of the flash memory with the determined optimal read voltage. | 02-24-2011 |
20110044102 | SELECTIVE MEMORY CELL PROGRAM AND ERASE - Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed. | 02-24-2011 |
20110044103 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises: a memory cell array configured by a plurality of first and second lines and a plurality of memory cells, each of the memory cells being selected by the first and second lines and being configured to store multiple-bit data in a nonvolatile manner; a data bus configured to transmit write data to be written to the plurality of memory cells, the write data being configured by a plurality of unit data; a column selection unit configured by a plurality of data latches, each of the data latches being configured to directly receive the unit data inputted from the data bus and to retain the unit data; and a control unit configured to control activation/non-activation of the data latches. During a programming operation, for each unit data inputted to the column selection unit, the control unit activates one of the data latches corresponding to a certain one of the memory cells where the unit data is to be stored. | 02-24-2011 |
20110044104 | NONVOLATILE MEMORY DEVICE AND SYSTEM, AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through N | 02-24-2011 |
20110044105 | NONVOLATILE MEMORY DEVICE AND SYSTEM, AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory cells includes executing first through (N−1) | 02-24-2011 |
20110044106 | NONVOLATILE SEMICONDUCTOR MEMORY AND DATA READING METHOD - A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming control section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section. | 02-24-2011 |
20110051510 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH TRANSFERS A PLURALITY OF VOLTAGES TO MEMORY CELLS AND METHOD OF WRITING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, a bit line, and a voltage generator. The memory cell array includes each of a plurality of memory cells. Each of the memory cells includes a charge storage layer and a control gate and is capable of holding two or more levels of data. The bit line is capable of transferring data to the memory cells in a one-to-one correspondence. The voltage generator carries out a verify operation by applying a verify voltage to the memory cells after performing first writing by applying a first voltage and then a second voltage lower than the first voltage to the control gate. | 03-03-2011 |
20110051511 | DIGITAL FILTERS WITH MEMORY - A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter. | 03-03-2011 |
20110058414 | MEMORY WITH MULTIPLE REFERENCE CELLS - A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels. | 03-10-2011 |
20110058415 | Systems and Methods for Increasing Bit Density in a Memory Cell - Various embodiments of the present invention provide systems, methods and circuits for memory utilization. As one example, a memory system is disclosed that includes a memory bank and a memory access controller circuit. The memory bank includes a number of default memory cells and a number of redundant memory cells. The memory access controller circuit is operable to access a usable memory space including both the combined default memory cells and the redundant memory cells. | 03-10-2011 |
20110058416 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SUPPRESSING PEAK CURRENT - A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule. | 03-10-2011 |
20110058417 | SENSING MEMORY CELLS - Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory cells to one of a number of states. The method also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. The method further includes sensing non-erased states of the memory cells using at least one common voltage level. | 03-10-2011 |
20110063905 | MULTI-VALUED ROM USING CARBON-NANOTUBE AND NANOWIRE FET - A multivalued memory device which includes a first multivalued memory transistor and a second multivalued memory transistor, wherein each transistor has a channel made from at least one carbon nanotube or nanowire, wherein data is stored by varying the number of carbon nanotubes or nanowires used in the channel, wherein the channel is the at least one carbon nanotube or nanowire which allows current to flow through it. | 03-17-2011 |
20110063906 | MEMORY ADAPTED TO PROGRAM A NUMBER OF BITS TO A MEMORY CELL AND READ A DIFFERENT NUMBER OF BITS FROM THE MEMORY CELL - A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell. | 03-17-2011 |
20110063907 | FRACTIONAL BITS IN MEMORY CELLS - Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2 | 03-17-2011 |
20110063908 | Nonvolatile Memory, Verify Method Therefor, and Semiconductor Device Using the Nonvolatile Memory - Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier ( | 03-17-2011 |
20110069544 | METHOD AND APPARATUS FOR PROGRAMMING A MULTI-LEVEL MEMORY - A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV | 03-24-2011 |
20110069545 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell. | 03-24-2011 |
20110069546 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells to store N-value data (N being an integer equal to or larger than 3); and a writing circuit configured to repeatedly execute a writing cycle on a plurality of memory cells until data writing is finished. The writing circuit divides the pulse width of the writing pulse into a plurality of sections to change the pulse height among the sections such that the respective sections provide writing voltages for writing different target threshold levels, and brings the bit line connected to the memory cell to be written with any of the target threshold levels into a selected state synchronously to the section for applying the writing voltage for writing that target threshold level. | 03-24-2011 |
20110069547 | SENSING AGAINST A REFERENCE CELL - Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states. | 03-24-2011 |
20110069548 | DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY - Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array. | 03-24-2011 |
20110075478 | NONVOLATILE MEMORY DEVICE AND SYSTEM, AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2 | 03-31-2011 |
20110075479 | MULTI-LEVEL CELL COPYBACK PROGRAM METHOD IN A NON-VOLATILE MEMORY DEVICE - A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation. | 03-31-2011 |
20110075480 | Non-Volatile Memory With Improved Sensing By Reducing Source Line Current - One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked. | 03-31-2011 |
20110080784 | NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF - An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1 | 04-07-2011 |
20110080785 | SEMICONDUCTOR MEMORY DEVICE, AND MULTI-CHIP PACKAGE AND METHOD OF OPERATING THE SAME - Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The controller is configured to control a first data storing operation for storing an input data to the single level cell section and control a second data storing operation for storing the input data stored in the single level section to the multi level cell section during an idle time. | 04-07-2011 |
20110080786 | DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT - Memory devices and methods are disclosed, such as those facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition. Memory devices and methods are also disclosed providing a means for determining initial programming pulse conditions for a population of memory cells based on the number of lower page data values being programmed to a logical 0 or a logical 1 data state. | 04-07-2011 |
20110085378 | Memory and Operation Method Therefor - In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage. | 04-14-2011 |
20110085379 | NONVOLATILE MEMORY DEVICE AND SYSTEM AND RELATED METHOD OF OPERATION - A nonvolatile memory device detects a first memory cell to be successfully programmed in a program operation for multiple memory cells connected to a wordline, and then detects a number of program loops required to successfully program the remaining memory cells connected to the wordline. An initial program voltage of subsequent program operations is then adjusted based on the detected number of loops. | 04-14-2011 |
20110085380 | Method of Programming a Memory - A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an n | 04-14-2011 |
20110090734 | METHODS AND APPARATUS FOR STORING DATA IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE WITH CROSS-PAGE SECTORS, MULTI-PAGE CODING AND PER-PAGE CODING - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 04-21-2011 |
20110090735 | EXPANDED PROGRAMMING WINDOW FOR NON-VOLATILE MULTILEVEL MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include negative Vt levels. The method includes applying a read voltage to a word line of a selected cell while applying a pass voltage to word lines of unselected cells, applying a boost voltage to a source line coupled to the selected cell, applying a voltage greater than the boost voltage to a bit line of the selected cell, and sensing a current variation of the bit line in response to the selected cell changing from a non-conducting state to a conducting state. | 04-21-2011 |
20110090736 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense. | 04-21-2011 |
20110096598 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS - Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used. | 04-28-2011 |
20110096599 | MULTI LEVEL INHIBIT SCHEME - Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed. | 04-28-2011 |
20110103144 | STRUCTURES AND METHODS OF TRIMMING THRESHOLD VOLTAGE OF A FLASH EEPROM MEMORY - A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density. | 05-05-2011 |
20110103145 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 05-05-2011 |
20110110153 | DATA STATE-DEPENDENT CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY - In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states. | 05-12-2011 |
20110110154 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltage from an initial state of the memory cell to a target state, and applying at least one of the determined verify voltages to the memory cell to verify whether the memory cell is programmed to the target state. | 05-12-2011 |
20110116312 | NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS READ, PROGRAM AND ERASE - One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a source-side multiplexer, a drain-side multiplexer, a source-side sense amplifier, and a drain-side write driver. A first binary value is stored in a first bit in the memory cell by trapping or releasing a first electric charge in the first insulating spacer. The first bit is read by sensing the resistive change in the cell transistor or by sensing the threshold voltage change in the cell transistor. | 05-19-2011 |
20110116313 | READ METHOD FOR MLC - Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Cell reads are performed multiple times and the read threshold voltages averaged to more closely approximate actual threshold voltage and to compensate for random noise. | 05-19-2011 |
20110116314 | METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING RELATED APPLICATION DATA - A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 05-19-2011 |
20110116315 | Nonvolatile Semiconductor Memory Device - A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area. | 05-19-2011 |
20110122690 | METHOD FOR PROGRAMMING MULTI-LEVEL CELL AND MEMORY APPARATUS - A method for programming a multi-level cell and a memory apparatus are described, wherein each cell has two storage sites. The method includes making the first storage site have a first Vt level and the second storage site have a second Vt level. The first Vt level is selected from M Vt levels. When the first Vt level is the i-th level among the M Vt levels, the second Vt level is selected from n | 05-26-2011 |
20110122691 | POWER MANAGEMENT OF MEMORY SYSTEMS - A memory system that includes a memory array and a memory controller manages power consumption by maintaining a variable credit value that reflects the amount of power available to the memory system. The variable credit value may be increased periodically up to a limit. When a power-consuming operation is performed, the variable credit value is reduced to reflect the power used. | 05-26-2011 |
20110122692 | PROGRAMMING NON-VOLATILE MEMORY WITH A REDUCED NUMBER OF VERIFY OPERATIONS - A method and non-volatile storage system are provided in which programming speed is increased by reducing the number of verify operations, while maintaining a narrow threshold voltage distribution. A programming scheme performs a verify operation at an offset level, before a verify level of a target data state is reached, such as to slow down programming. However, it is not necessary to perform verify operations at both the offset and target levels at all times. In a first programming phase, verify operations are performed for a given data state only at the target verify level. In a second programming phase, verify operations are performed for offset and target verify levels. In a third programming phase, verify operations are again performed only at the target verify level. Transitions between phases can be predetermined, based on programming pulse number, or adaptive. | 05-26-2011 |
20110122693 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 05-26-2011 |
20110128784 | NON-VOLATILE MEMORY DEVICE - An electronic memory device is presented. The device comprises at least one basic unit (FIG. | 06-02-2011 |
20110134693 | APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB - The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process. | 06-09-2011 |
20110134694 | High Voltage Generation And Control In Source-Side Injection Programming Of Non-Volatile Memory - Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used. | 06-09-2011 |
20110141808 | Methods and Apparatus for Programming Multiple Program Values Per Signal Level in Flash Memories - Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance. | 06-16-2011 |
20110141809 | PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data. | 06-16-2011 |
20110141810 | READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. | 06-16-2011 |
20110141811 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region. | 06-16-2011 |
20110149650 | Data Transfer Flows for On-Chip Folding - A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations. | 06-23-2011 |
20110149651 | Non-Volatile Memory And Method With Atomic Program Sequence And Write Abort Detection - A program operation in a non-volatile memory is segmented at predefined junctures into smaller segments for execution over different times. The predefined junctures are such that they allow unambiguous identification when restarting the operation in a next segment so that the operation can continue without having to restart from the very beginning of the operation. This is accomplished by requiring the programming sequence of each segment to be atomic, that is, to only terminate at a predetermined type of programming step. In a next segment, the terminating programming step is identified by detecting a predetermined pattern of ECC errors across a group of programmed wordlines. | 06-23-2011 |
20110157980 | TECHNIQUE TO REDUCE FG-FG INTERFERENCE IN MULTI BIT NAND FLASH MEMORY IN CASE OF ADJACENT PAGES NOT FULLY PROGRAMMED - A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that have not been programmed. | 06-30-2011 |
20110157981 | FLASH MEMORY SYSTEM HAVING CROSS-COUPLING COMPENSATION DURING READ OPERATION - A method for reading an addressed cell of a memory system comprises applying at least two different voltage levels to a control gate of a memory cell in an array of memory cells, wherein the memory cell is adjacent to and in electrical field communication with the addressed memory cell. A threshold voltage of the addressed memory cell is measured at each of the at least two different applied voltage levels. At least two of the measured threshold voltages of the addressed memory cell are converted to one or more bit values stored in the addressed memory cell. The bit values are provided to a host of the memory system. An apparatus implementing the method is also disclosed. | 06-30-2011 |
20110157982 | Novel High Speed High Density NAND-Based 2T-NOR Flash Memory Design - A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip. | 06-30-2011 |
20110157983 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures. | 06-30-2011 |
20110164449 | PROGRAMMING BASED ON CONTROLLER PERFORMANCE REQUIREMENTS - Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit. | 07-07-2011 |
20110170347 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ACCURATE READING EVEN WHEN ERASURE LEVEL CHANGES - According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are adjacent to each other, and the second and third memory cells are adjacent to each other. Data is stored into the memory cells in an order of the first, second, and third memory cells. When reading data from the second memory cells, the controller reads data from the first and third memory cells, and changes read conditions for the second memory cell in accordance with the read data. | 07-14-2011 |
20110170348 | ANALOG INTERFACE FOR A FLASH MEMORY DIE - A flash disk controller includes an input operable to receive analog signals from a flash memory die. The flash memory die includes multiple flash memory cells. The analog signals represent data values stored in the flash memory cells. An analog-to-digital conversion module is coupled to the input to convert received analog signals into digital data. A control module selects memory cells from which the input receives analog signals. | 07-14-2011 |
20110176361 | METHOD AND APPARATUS FOR INCREASING MEMORY PROGRAMMING EFFICIENCY THROUGH DYNAMIC SWITCHING OF BIT LINES - A method of efficiently programming charge-trapping memory cells includes sense amplifiers being dynamically connected to cells to be programmed, by switching bit lines. The method increases a number of cells that can be programmed simultaneously, such that an optimal use of sense amplifier resources is obtained. | 07-21-2011 |
20110176362 | SEMICONDUCTOR STORAGE DEVICE CAPABLE OF REDUCING ERASURE TIME - According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is monitored, and an erase voltage is set based on the monitored results. Thus, the erase voltage can be precisely set without depending on the threshold voltage distribution of the memory cell before the erasure. | 07-21-2011 |
20110176363 | JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES - A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. | 07-21-2011 |
20110182119 | APPARATUS, SYSTEM, AND METHOD FOR DETERMINING A READ VOLTAGE THRESHOLD FOR SOLID-STATE STORAGE MEDIA - An apparatus, system, and method are disclosed for determining a read voltage threshold for solid-state storage media. A data set read module reads a data set from storage cells of solid-state storage media. The data set is originally stored in the storage cells with a known bias. A deviation module determines that a read bias for the data set deviates from the known bias. A direction module determines a direction of deviation for the data set. The direction of deviation is based on a difference between the read bias of the data set and the known bias. An adjustment module adjusts a read voltage threshold for the storage cells of the solid-state storage media based on the direction of deviation. | 07-28-2011 |
20110182120 | NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-LEVEL CELLS USING MODIFIED READ VOLTAGES AND METHODS OF OPERATING THE SAME - Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed. | 07-28-2011 |
20110194346 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 08-11-2011 |
20110194347 | Nonvolatile Memory Devices Having Improved Read Reliability - Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages. | 08-11-2011 |
20110194348 | DYNAMIC AND ADAPTIVE OPTIMIZATION OF READ COMPARE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION - A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points. | 08-11-2011 |
20110199822 | METHOD AND APPARATUS FOR CONTROLLING PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE - A method of managing a page buffer of a non-volatile memory device comprises programming least significant bit (LSB) page data from an LSB page buffer into a page of memory cells, and retaining the LSB page data in the LSB page buffer until most significant bit (MSB) page data corresponding to the LSB page data is programmed in the page. | 08-18-2011 |
20110199823 | PRELOADING DATA INTO A FLASH STORAGE DEVICE - Programmer's data that is transferred from a programming device ( | 08-18-2011 |
20110205793 | METHOD FOR ACCESSING MULTI-LEVEL NON-VOLATILE MEMORY CELL - A method for accessing a multi-level non-volatile memory cell includes the following steps: determining at least one target word line voltage according to a target bit to be read from a plurality of bits stored in the multi-level non-volatile memory cell; and applying the at least one target word line voltage to the multi-level non-volatile memory cell in order to determine the target bit. Herein the at least one target word line voltage includes at most 2 | 08-25-2011 |
20110216587 | NONVOLATILE MEMORY DEVICE, METHODS OF PROGRAMING THE NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - Embodiments of the inventive concept provide a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a read/write circuit, and a backup circuit. The memory cell array includes a first memory block including a first word line having first memory cells and a second word line having second memory cells. Each of the first memory cells and second memory cells configured to store first-bit data and second-bit data. The read/write circuit is configured to program data into the first and second memory cells and read data stored in the first and second memory cells. The backup circuit is configured to, after first-bit data are programmed into the first word line, but before second-bit data are programmed into the first word line, store first-bit data stored in the second memory cells of the second word line | 09-08-2011 |
20110216588 | MULTI-BIT CELL MEMORY DEVICES USING ERROR CORRECTION CODING AND METHODS OF OPERATING THE SAME - A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits. | 09-08-2011 |
20110216589 | FLASH MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a memory device and a data converting device. The memory device includes a memory cell array which includes a plurality of memory cells. The data converting device includes an encoding device. The encoding device converts input data into converted data by changing a bandwidth corresponding to the input data, and provides the converted data to the memory device. Accordingly, the memory system is capable of improving the reliability of programmed data by changing the bandwidth corresponding to data to be programmed. A method of storing data in a memory system is also disclosed. | 09-08-2011 |
20110216590 | NONVOLATILE MEMORY DEVICE USING INTERLEAVING TECHNOLOGY AND PROGRAMMMING METHOD THEREOF - A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2 | 09-08-2011 |
20110222341 | MULTI-LEVEL CELL PROGRAMMING SPEED IMPROVEMENT THROUGH PROGRAM LEVEL EXCHANGE - A method of storing data in a multi-level charge-trapping memory array is described. An incidence-of-occurrence (i.e., frequency) analysis is performed on data to be programmed to identify data words combining a high programming voltage with a high frequency of occurrence. Those words are reassigned in order to reduce programming time. | 09-15-2011 |
20110222342 | DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern. | 09-15-2011 |
20110222343 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline. | 09-15-2011 |
20110222344 | METHOD FOR MODIFYING DATA MORE THAN ONCE IN A MULTI-LEVEL CELL MEMORY LOCATION WITHIN A MEMORY ARRAY - A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function. | 09-15-2011 |
20110222345 | Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase. | 09-15-2011 |
20110228601 | MLC SELF-RAID FLASH DATA PROTECTION SCHEME - A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data. | 09-22-2011 |
20110235413 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention sets the lower limit of an intermediate distribution in a page writing operation such that an amount of shift from a first threshold voltage distribution to a second threshold voltage distribution is substantially equal to an amount of shift from the intermediate distribution to a fourth threshold voltage distribution, and raises the lower limit of the intermediate distribution as the number of times writing has been executed increases. When the threshold voltage distribution of a second memory cell adjoining a reading target first memory cell and subject to data write after the first memory cell is the second or fourth threshold voltage distribution, the control circuit executes control of applying a second reading pass voltage higher than the first reading pass voltage to the second memory cell. | 09-29-2011 |
20110235414 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a memory cell array, a controller. A memory cell array comprises bit lines, and memory cells configured to store different states, i.e., m values or n values. When storing the n values in a memory cell, the controller performs a first method of applying a bit-line voltage to a first bit line connected to the memory cell, and setting a second bit line adjacent to the first bit line at 0 V, in a read operation and in a verify operation. When storing the m values in the memory cell, the controller performs a second method of applying the bit-line voltage to all the bit lines in a read operation, and setting the first bit line and the second bit line at the bit-line voltage or 0 V in a verify operation, in accordance with whether the write is complete. | 09-29-2011 |
20110242889 | PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results. | 10-06-2011 |
20110242890 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining | 10-06-2011 |
20110249495 | NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICES HAVING THE NON-VOLATILE MEMORY DEVICE - A non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels. One of the plurality of states of the second group of states includes at least one of the plurality of states of the first group of states. | 10-13-2011 |
20110249496 | PROGRAM METHOD OF MULTI-BIT MEMORY DEVICE AND DATA STORAGE SYSTEM USING THE SAME - Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels. | 10-13-2011 |
20110255336 | SEMICONDUCTOR MEMORY DEVICE - A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory cells are connected in series between the bit lines and a source to constitute cell string. The word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage. The writing stage includes a plurality of writing loops. The writing loops respectively includes a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell. | 10-20-2011 |
20110261618 | Off-Die Charge Pump that Supplies Multiple Flash Devices - A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump. | 10-27-2011 |
20110261619 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF LOWERING A WRITE VOLTAGE - A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with input data. The control circuit supplies a first voltage to a word line of a selected cell in a write operation, and supplies a second voltage to at least one word line adjacent to the selected cell. Thereafter, the control circuit changes a voltage of the at least one word line adjacent to the selected cell from the second voltage to a third voltage (second voltage10-27-2011 | |
20110273932 | NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells. | 11-10-2011 |
20110273933 | ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERSION WINDOW ADJUSTMENT BASED ON REFERENCE CELLS IN A MEMORY DEVICE - An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array. | 11-10-2011 |
20110280068 | JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE - Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells. | 11-17-2011 |
20110280069 | ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE - Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator. | 11-17-2011 |
20110280070 | NONVOLATILE MEMORY DEVICE, SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND READ OPERATION OF NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory cell array, a page buffer, and a control circuit. The memory cell array comprises multi-level cells configured to store hard decision data bits. The page buffer is configured to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline during a first read operation, to set first soft decision data bits according to the first read operation, and to sense one or more hard decision data bits from each of the multi-level cells in response to a second read voltage applied to the selected wordline in a second read operation. The control circuit is configured to control the first read operation and the second read operation to be performed in succession. | 11-17-2011 |
20110280071 | CARD CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits. | 11-17-2011 |
20110286267 | Pattern-Sensitive Coding of Data for Storage in Multi-Level Memory Cells - A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits. | 11-24-2011 |
20110286268 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 11-24-2011 |
20110292724 | NONVOLATILE MEMORY DEVICE, SYSTEM AND PROGRAMMING METHOD WITH DYNAMIC VERIFICATION MODE SELECTION - Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition. | 12-01-2011 |
20110292725 | FLASH MEMORY DEVICE AND SYSTEM WITH PROGRAM SEQUENCER, AND PROGRAMMING METHOD - A programming method for a nonvolatile memory device includes performing a LSB programming operation programming all LSB logical pages, and thereafter performing a MSB programming operation programming all MSB logical pages, wherein during the LSB programming operation a selected MLC is programmed to a negative intermediate program state. A program sequence for the LSB and MSB programming operations may be sequential or non-sequential in relation to an order arranged of word lines. | 12-01-2011 |
20110292726 | Nonvolatile Memory Device Capable Of Reducing Read Disturbance And Read Method Thereof - Provided are a nonvolatile memory device and a read method of the same. The read method applying one of a plurality of unselected read voltages to unselected wordlines adjacent to a selected word line. The voltage applied to the unselected word lines being based on which of a plurality of selected read voltages is applied to the selected wordline. | 12-01-2011 |
20110292727 | SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS - An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states. | 12-01-2011 |
20110292728 | INTEGRATED CIRCUIT OF DEVICE FOR MEMORY CELL - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages. | 12-01-2011 |
20110299333 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described. | 12-08-2011 |
20110299334 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array connected to word lines and bit lines, and formed by arranging a plurality of memory cells in a matrix, each memory cell storing one of n values (n is a natural number of not less than 2), and a control circuit configured to write data in the memory cells by controlling potentials of the word lines and the bit lines in accordance with input data. The control circuit performs a write verify operation a plurality of number of times by changing a voltage level, stores data of the voltage level at which verify pass occurs, and determines a write voltage based on the stored data of the voltage level. | 12-08-2011 |
20110299335 | Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed. | 12-08-2011 |
20110305081 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises programming target memory cells among a plurality of memory cells connected to a wordline, performing a first sensing operation on the plurality of memory cells, and selectively performing a second sensing operation on the target memory cells based on a result of the first sensing operation. | 12-15-2011 |
20110305082 | METHODS AND APPARATUS FOR SOFT DATA GENERATION FOR MEMORY DEVICES - Methods and apparatus are provided for soft data generation for memory devices. At least one soft data value is generated for a memory device, by obtaining at least one hard read value; and generating the soft data value associated with the at least one hard read value based on statistics for reading the hard read value. The hard read value may be one or more of data bits, voltage levels, current levels and resistance levels. The generated soft data value may be one or more of (i) a soft read value that is used to generate one or more log likelihood ratios, and (ii) one or more log likelihood ratios. The statistics comprise one or more of bit-based statistics and cell-based statistics. The statistics may also optionally comprise pattern-dependent disturbance of at least one aggressor cell on the target cell, as well as location-specific statistics. At least one soft data value can be generated for a memory device, by obtaining a soft read value; and generating the soft data value associated with the soft read value based on statistics for reading the soft read value, wherein the statistics comprise one or more of location-specific statistics and pattern-dependent statistics. | 12-15-2011 |
20110317487 | MULTIPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME - A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an M | 12-29-2011 |
20120002469 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells selected by word lines and bit lines, each memory cell being capable of storing N-bit data, a set of n-th bits of a plurality of memory cells selected by one of the word lines constituting an n-th physical page, and a predetermined number of the bit lines constituting one column; and a data writing unit that divides each of first to N-th input data of the length of the physical page or less input from the outside into unit data of the length of the column, changes at least a portion of the order of unit data of the first to N-th input data of a predetermined column in the predetermined column before data writing, and performs writing. | 01-05-2012 |
20120002470 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to an embodiment includes a data write portion, the data write portion includes, in a write loop, a first operation mode of sequentially performing a program operation and a first verify operation, and a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation, and the data write portion includes, in the first verify operation, precharging a bit-line connected to the first memory cell and a bit-line connected to a second memory cell adjacent to the first memory cell and verifying data of the first memory cell, then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell, precharging the bit-line connected to the first memory cell and verifying data of the first memory cell. | 01-05-2012 |
20120008387 | METHOD OF TWICE PROGRAMMING A NON-VOLATILE FLASH MEMORY WITH A SEQUENCE - A method of twice programming a multi-bit per cell non-volatile memory with a sequence is disclosed. At least one page at a given word line is firstly programmed with program data by a controller of the non-volatile memory, and at least one page at a word line preceding the given word line is secondly programmed with the same program data by the controller. | 01-12-2012 |
20120008388 | NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF - An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting a main voltage distribution group and a plurality of secondary voltage distribution groups, wherein each of the main voltage distribution group and the secondary voltage distribution groups includes N threshold-voltage distribution curves, and N is an integer greater than 2; selecting a first operation level and a second operation level according to a programming command; programming the first storage position according to the threshold-voltage distribution curve corresponding to the first operation level in the main voltage distribution group; selecting one of the secondary voltage distribution groups according to the first operation level and programming the second storage position according to the threshold-voltage distribution curve corresponding to the second operation level in the selected secondary voltage distribution group. | 01-12-2012 |
20120008389 | NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF PERFORMING READ OPERATIONS - Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has a negative threshold voltage the read operation applies a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal. | 01-12-2012 |
20120008390 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes memory blocks each including a plurality of groups of memory cells programmable in multiple levels and a control circuit configured to make a determination of whether a specific memory block treated a bad block, from among the memory blocks, is programmable in a single level and to control the specific memory block according to a result of the determination so that the specific memory block is usable as a single level cell block. | 01-12-2012 |
20120020153 | Nonvolatile Memory Devices with Highly Reliable Programming Capability and Methods of Operating Same - Programming methods of a non-volatile memory device by which a programming error is less likely to occur. A programming method may involve applying a precharge voltage to a program inhibit cell at a different time according to the threshold voltage of the program inhibit cell. A programming method may involve applying a different level of precharge voltage to a program inhibit cell according to the threshold voltage of the program inhibit cell. | 01-26-2012 |
20120020154 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes memory cells storing data in a nonvolatile manner, word lines connected to the memory cells and including a first word line and a second word line which is n-th (n is an integer of 1 or more) from the first word line, and a control circuit configured to control a voltage of a word line to write data to a memory cell so that data are written in order from the first word line to the second word line. In a write sequence of the first word line, the control circuit applies a writing voltage to the second word line before writing a memory cell connected to the first word line. | 01-26-2012 |
20120020155 | MULTIPAGE PROGRAM SCHEME FOR FLASH MEMORY - A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The selected wordline connected to the cells to be programmed is driven with predetermined program profiles at different time intervals, where each predetermined program profile is configured for shifting an erase threshold voltage to a specific threshold voltage corresponding to a specific logic state. A multi-page bitline controller biases each bitline to enable or inhibit programming during each of the time intervals, in response to the combination of specific logic states of the bits belonging to each page of data that are associated with that respective bitline. | 01-26-2012 |
20120020156 | METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES PERFORMING THE METHOD - A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell. | 01-26-2012 |
20120026790 | Non-volatile memory device including block state confirmation cell and method of operating the same - Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell. | 02-02-2012 |
20120026791 | Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations - Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles. | 02-02-2012 |
20120026792 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE - Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example. | 02-02-2012 |
20120033492 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method. In one embodiment, a data storage device comprises a flash memory. First, the flash memory is directed to read a plurality of programming voltage values for data programming. The programming voltage values are then adjusted to obtain a plurality of adjusted programming voltage values according to difference bits between a plurality of stored data patterns corresponding to the programming voltage values. The adjusted programming voltage values are then sent to the flash memory. The flash memory is then directed to perform data programming according to the adjusted programming voltage values, wherein the data programmed according to the adjusted programming voltage values has a lower error bit rate than that of the data programmed according to the programming voltage values. | 02-09-2012 |
20120033493 | ERASE COMPLETION RECOGNITION - Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively coupled to the at least one erase status memory cell, the control module configured to perform operations on the main memory array based at least in part on the value stored in the at least one erase status memory cell. Other embodiments may be described and claimed. | 02-09-2012 |
20120033494 | DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level. | 02-09-2012 |
20120039120 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM - A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer. | 02-16-2012 |
20120039121 | PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE - Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results. | 02-16-2012 |
20120039122 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2 | 02-16-2012 |
20120039123 | MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE - The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels. | 02-16-2012 |
20120039124 | Non-Volatile Memory and Method With Improved Sensing Having Bit-Line Lockout Control - In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level. | 02-16-2012 |
20120039125 | Nonvolatile Memory with Correlated Multiple Pass Programming - A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size, and each successive pass has the staircase pulse train offset from that of the previous pass by a predetermined offset level. The predetermined offset level is less than the common step size and may be less than or equal to the predetermined offset level of the previous pass. Thus, the same programming resolution can be achieved over multiple passes using fewer programming pulses than conventional method where each successive pass uses a programming staircase pulse train with a finer step size. The multiple pass programming serves to tighten the distribution of the programmed thresholds while reducing the overall number of programming pulses. | 02-16-2012 |
20120044761 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method of 4-bit MLC programming a nonvolatile memory device includes inputting an m | 02-23-2012 |
20120044762 | REJUVENATION OF ANALOG MEMORY CELLS - A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the memory cells in the group to meet the given storage quality level, is applied to the identified group. Data is stored in the rejuvenated group of the memory cells. | 02-23-2012 |
20120044763 | Non-Volatile Memory and Semiconductor Device - There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. | 02-23-2012 |
20120057404 | MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 03-08-2012 |
20120063224 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a source line connected to first and second cell units, a cell-source driver setting the source line on a fixed potential in a programming, a data latch circuit temporary storing program data, a hookup circuit connecting one of the first and second bit lines to the data latch circuit, and connecting the other one of the first and second bit lines to the source line, in the programming, a level detection circuit detecting a potential level of the source line, and a control circuit determining a completion of a charge of the first and second bit lines when the potential level of the source line is larger than a threshold value, and making a charge time of the first and second bit lines variable, in the programming. | 03-15-2012 |
20120063225 | READING DATA FROM MEMORY CELLS INCLUDING STORING CHARGES TO ANALOG STORAGE DEVICES - Methods of reading data from memory cells. Such methods include subjecting an analog storage device to a voltage level indicative of a threshold voltage of a memory cell to store a charge to the analog storage device, and generating an analog voltage from the stored charge. | 03-15-2012 |
20120063226 | SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE - Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected data is loaded into a second data cache. After a read operation of programmed columns of memory cells, the read data is compared to the expected data and error bit indicators are stored in the second data cache in the error bit locations. The second data cache is masked with the mask data so that only those error bits that are unmasked are counted. If the number of unmasked error bit indicators is greater than a threshold, the memory block is marked as unusable. | 03-15-2012 |
20120069652 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate, a floating body to store data in volatile memory and a floating gate or trapping layer configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell. | 03-22-2012 |
20120069653 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines each connected to nonvolatile memory cells; and a control circuit. When executing the data reading operation, the control circuit applies to a selected word line connected to a selected memory cell a first voltage obtained by adding a first adjusting voltage to an intermediate voltage between adjoining two of the threshold voltage distributions; applies to first non-selected word lines adjoining the selected word line a second voltage obtained by subtracting a second adjusting voltage from a reading pass voltage; applies to second non-selected word lines adjoining the first non-selected word lines a third voltage obtained by adding the second adjusting voltage to the reading pass voltage; and applies to third non-selected word lines, the third non-selected word lines being non-selected word lines except the first and second non-selected word lines, the reading pass voltage. | 03-22-2012 |
20120069654 | MEMORY DEVICE AND METHOD FOR ESTIMATING CHARACTERISTICS OF MULTI-BIT PROGRAMMING - Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell. | 03-22-2012 |
20120075930 | REUSE OF INFORMATION FROM MEMORY READ OPERATIONS - A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation. | 03-29-2012 |
20120099372 | Sequence Detection for Flash Memory With Inter-Cell Interference - A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells. | 04-26-2012 |
20120099373 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes sequentially programming first to (n−1) | 04-26-2012 |
20120106246 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF WRITING THE SAME, AND SEMICONDUCTOR DEVICE - A control circuit is configured to be able to perform a rough write process, a foggy write process, and a fine write process. The rough write process moves, for a memory cell to be provided with a plurality of second threshold voltage distributions, a first threshold voltage distribution in the positive direction to generate a third threshold voltage distribution. The foggy write process does not move, for a memory cell finally to be provided with first data, the third threshold voltage distribution, and moves, for a memory cell finally to be provided with second data different from the first data, the first threshold voltage distribution or the third threshold voltage distribution in the positive direction to generate a plurality of fourth threshold voltage distributions. The fine write process moves the fourth threshold voltage distributions in the positive direction to generate the second threshold voltage distributions. | 05-03-2012 |
20120106247 | FLASH MEMORY DEVICE INCLUDING FLAG CELLS AND METHOD OF PROGRAMMING THE SAME - Provided is a flash memory device and a method of programming the same. The flash memory device includes a memory cell array, a first judgment circuit and a second judgment circuit. The memory cell array includes multiple main cells and multiple flag cells. The first judgment circuit judges program pass of the main cells, and the second judgment circuit judges program pass of the flag cells by applying a more strict judgment reference than the first judgment circuit. | 05-03-2012 |
20120106248 | NON-VOLATILE MULTILEVEL MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states. | 05-03-2012 |
20120106249 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 05-03-2012 |
20120106250 | METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES - Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching. | 05-03-2012 |
20120106251 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES - Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal. | 05-03-2012 |
20120113714 | METHOD FOR PROGRAMMING A MULTI-STATE NON-VOLATILE MEMORY (NVM) - A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage. | 05-10-2012 |
20120113715 | Non-Volatile Memory With Improved Sensing By Reducing Source Line Current - One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked. | 05-10-2012 |
20120113716 | Structure and Method for Shuffling Data Within Non-Volatile Memory Devices - Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process. | 05-10-2012 |
20120113717 | SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ECC EFFICIENCY - Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells. | 05-10-2012 |
20120120726 | VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE FOR NON-VOLATILE STORAGE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process includes programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process. | 05-17-2012 |
20120127791 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF PROGRAMMING SAME - A nonvolatile memory device is programmed using an incremental step pulse programming method comprising a plurality of program loops. Some program loops use a one step verification operation, and other program loops use a two step verification operation. | 05-24-2012 |
20120127792 | SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS - In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range. | 05-24-2012 |
20120134207 | Non-Volatile Memory Device And Read Method Thereof - In one embodiment, the method for reading memory cells in an array of non-volatile memory cells includes reading data from a memory cell using a set of hard decision voltages and at least a first set of soft decision voltages based on a single read command. | 05-31-2012 |
20120134208 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND READ METHOD THEREOF - A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell. | 05-31-2012 |
20120140558 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit applies a write pulse voltage to a selected word line to perform a write operation to 1-page memory cells along the selected word line. The circuit then performs a verify read operation to confirm whether the data write to the 1-page memory cells is completed. According to the result of the verify read operation, a step-up operation is performed out to raise the write pulse voltage by a step-up voltage. The control circuit changes the amount of the step-up voltage according to a distribution width of a first threshold voltage distribution generated in process of the write operation to the memory cells. | 06-07-2012 |
20120140559 | SELECTIVE MEMORY CELL PROGRAM AND ERASE - Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed. | 06-07-2012 |
20120147669 | NON-VOLATILE MEMORY DEVICE AND A METHOD FOR OPERATING THE DEVICE - A method for operating a non-volatile memory device includes programming a memory cell and not programming a flag cell during first to n | 06-14-2012 |
20120147670 | SEMICONDUCTOR STORAGE DEVICE ADAPTED TO PREVENT ERRONEOUS WRITING TO NON-SELECTED MEMORY CELLS - A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation. | 06-14-2012 |
20120147671 | OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE - A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation. | 06-14-2012 |
20120147672 | FRACTIONAL BITS IN MEMORY CELLS - Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2 | 06-14-2012 |
20120155166 | Alternate Page By Page Programming Scheme - An alternate page by page scheme for the multi-state programming of data into a non-volatile memory is presented. Pages of data are written a page at a time onto word lines of the memory. After all of the pages of data are written to a first level of resolution onto one word line, the memory goes back to the adjacent word line (on which all of the pages of data have previously been written the first level of resolution) and refines the accuracy with which the data had been written on this preceding word line. This can reduce the effects on the data of capacitive coupling between the word lines. | 06-21-2012 |
20120155167 | NON-VOLATILE STORAGE DEVICE, INFORMATION PROCESSING SYSTEM AND WRITE CONTROL METHOD OF NON-VOLATILE STORAGE DEVICE - A non-volatile storage device has a non-volatile memory, a capacity determination part configured to determine whether data amount stored into the non-volatile memory exceeds a first threshold value, an area dividing determination part configured to provide a first storage area for writing one bit data to one memory cell and a second storage area for writing multiple bit data to one memory cell in storage areas of the non-volatile memory, a first write control part configured to write data into the first storage area by a first writing mode until the capacity determination part determines that the first threshold value has been exceeded, a data selector configured to select data that frequency of access does not reach a predetermined reference value among data stored into the non-volatile memory when the capacity determination part determines that the first threshold value has been exceeded, and a second write control part configured to temporarily save data selected by the data selector from the first storage area to write the saved data to the second storage area by a second writing mode. | 06-21-2012 |
20120155168 | NEGATIVE VOLTAGE GENERATOR, DECODER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM USING NEGATIVE VOLTAGE - A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage, an oscillator configured to generate an oscillation clock, a charge pump configured to generate a negative voltage in response to a pump clock, and a voltage detector. The voltage detector is configured to detect the negative voltage by comparing a division voltage, obtained by voltage dividing the direct current voltage, with the reference voltage, and to generate the pump clock corresponding to the detected negative voltage based on the oscillation clock. | 06-21-2012 |
20120155169 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device storing plural data bits in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data. In a first write operation processing data in the first unit, logic of one of the higher-order and the lower-order bit is fixed, and two multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the memory cell in a pseudo binary state. In a second write operation processing data in a second unit larger than the first unit, plural input data bits in a multivalued state and parity data for error correction in the second unit are stored in the memory cell. | 06-21-2012 |
20120163076 | SINGLE CHECK MEMORY DEVICES AND METHODS - Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells. | 06-28-2012 |
20120163077 | MULTI-LEVEL CELL NOR FLASH MEMORY DEVICE - A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate. | 06-28-2012 |
20120163078 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SUPPRESSING PEAK CURRENT - A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule. | 06-28-2012 |
20120163079 | Programming Orders for Reducing Distortion Based on Neighboring Rows - A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order. | 06-28-2012 |
20120163080 | Reducing Distortion Using Joint Storage - A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order. | 06-28-2012 |
20120170363 | METHOD FOR INCREASING PROGRAM SPEED AND CONTROL READ WINDOWS FOR MULTI-LEVEL CELL NON-VOLATILE MEMORY - A method of programming a memory device comprising a plurality of bits that each have a plurality of program states in which each program state has a corresponding program verify (PV) level may include applying a first sequence of program shots to program fastest bits of the memory device utilizing a bias voltage having a maximum value corresponding to a respective program state being programmed, lowering the bias voltage to apply a second sequence of program shots to program fast bits of the memory device up to N program shots, and increasing the bias voltage for program shots greater than N to program slow bits of the memory device. | 07-05-2012 |
20120170364 | Method Of Programming A Nonvolatile Memory Device - In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data. | 07-05-2012 |
20120170365 | NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING THE SAME, AND METHODS OF PROGRAMMING NON-VOLATILE MEMORY DEVICES - A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string select line. The method includes programming a first sub-block of the memory block, determining in the non-volatile memory device when a reference word line is programmed during programming of the first sub-block, and partial erasing a second sub-block of the memory block upon determining that the reference word line is programmed during programming of the first sub-block. | 07-05-2012 |
20120170366 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells. | 07-05-2012 |
20120170367 | SEMICONDUCTOR DEVICE AND METHOD OF GENERATING VOLTAGES USING THE SAME - A semiconductor device includes a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address; a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal; and a voltage generation circuit for outputting voltages distributed in response to the enable signals. | 07-05-2012 |
20120176837 | MEMORY CELL SENSING USING NEGATIVE VOLTAGE - Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage. | 07-12-2012 |
20120176838 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage. | 07-12-2012 |
20120182797 | SENSE OPERATION IN A MEMORY DEVICE - Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell. | 07-19-2012 |
20120182798 | Non-Volatile Semiconductor Memory - A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. | 07-19-2012 |
20120182799 | DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY - Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array. | 07-19-2012 |
20120182800 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING A SHIFT OF THRESHOLD VOLTAGE - A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels. | 07-19-2012 |
20120188821 | METHOD FOR ACHIEVING FOUR-BIT STORAGE USING FLASH MEMORY HAVING SPLITTING TRENCH GATE - The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased. | 07-26-2012 |
20120195117 | SEMICONDUCTOR SYSTEM AND DATA PROGRAMMING METHOD - A data programming method includes the steps of determining whether a threshold voltage distribution of a memory cell, where a first bit value of writing data was programmed, has deviated from a targeted first voltage range, correcting the first bit value through an error correction code if the threshold voltage distribution of the memory cell has deviated from the first voltage range, and programming a corrected first bit value and a second bit value of the writing data to the memory cell. | 08-02-2012 |
20120195118 | SEMICONDUCTOR MEMORY APPARATUS, DATA PROGRAMMING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory apparatus includes: a memory unit including a first memory group and a second memory group; and a control unit configured to control input data to be programmed into selected memory cells of the first memory group such that one-bit data is programmed into each of the memory cells of the first memory group when the size of the input data is smaller than a size of data which may be stored into the first memory group during a programming mode, and control the input data programmed in the first memory group to be reprogrammed into selected memory cells of the second memory group during a standby mode after the programming mode, such that multi-bit data are programmed into each of the memory cells of the selected second memory group. | 08-02-2012 |
20120195119 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation. | 08-02-2012 |
20120195120 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit controls erase operation to erase data of memory transistors, correction write operation, and correction write verify operation. In the correction write operation, a erase threshold level of a memory transistor is moved to a positive threshold level after the erase operation. In the correction write verify operation, whether or not a threshold level of the result of the correction write operation reaches a first value is determined. In the correction write operation, the control circuit executes the correction write operation with respect to plural memory units connected to a common one of the bit lines as a group. The control circuit sequentially executes the correction write verify operation with respect to plural memory units in which the correction write operation is executed. | 08-02-2012 |
20120201077 | NONVOLATILE SEMICONDUCTOR MEMORY AND CONTROL METHOD THEREOF - According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to perform an operation process based on a scan result of the bit scan circuit, and a control circuit to control an operation of writing data according to a first mode in which a voltage used for an upper-data writing is calculated during a lower-data writing and a second mode used a voltage based on setting information. The bit scan circuit scans the number of to-be-written memory cells before starting writing and the processing unit compares the number of to-be-written memory cells with a criterion and determines one of the first and second modes for the writing based on a result of comparison. | 08-09-2012 |
20120201078 | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N - A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set. | 08-09-2012 |
20120206962 | METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS - A memory chip includes memory cells storing data to be read; at least one reference cell having a reference cell current level and a reference gate voltage adjuster to adjust, for each reference cell, a reference gate voltage level to compensate for a shift of the reference cell current level from an original current level. | 08-16-2012 |
20120218818 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes a page region including a plurality of normal cells and a plurality of auxiliary cells, a detecting unit configured to output a pass signal when at least one cell is programmed with a voltage higher than a reference voltage among program target cells of the page region, a count storing unit configured to store a count in the plurality of auxiliary cells during a first program operation for the page region, wherein the count indicates a total number of program pulses applied to the at least one cell until the pass signal is outputted from the detecting unit, and a voltage setting unit configured to set a program start voltage for a second program operation of the page region based on the count stored in the plurality of auxiliary cells. | 08-30-2012 |
20120224420 | SEMICONDUCTOR MEMORY DEVICE AND DECODING METHOD - A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio. | 09-06-2012 |
20120224421 | SYSTEM AND METHOD OF DECODING DATA FROM MEMORY BASED ON SENSING INFORMATION AND DECODED DATA OF NEIGHBORING STORAGE ELEMENTS - Systems and methods to decode data stored in a data storage device are disclosed. Data bits stored in a first group of storage elements are decoded using data in a second group of storage elements together with physical characteristics of the second group of storage elements to aid in the decoding of the first group of storage elements. | 09-06-2012 |
20120224422 | Nonvolatile Semiconductor Memory Device - A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area. | 09-06-2012 |
20120224423 | PROGRAMMING AND ERASURE SCHEMES FOR ANALOG MEMORY CELLS - A method for data storage, in a memory that includes multiple analog memory cells, includes setting a parameter of an iterative process applied to a group of the memory cells based on one or more data values stored in at least one of the memory cells in the memory. The iterative process is performed in the group of the memory cells in accordance with the set parameter. | 09-06-2012 |
20120230104 | NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF - Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read operation and a data recover read scheduler controlling a data recover read operation and configured to control the page buffer circuit at a read request. One of the normal read scheduler and the data recover read scheduler is selected according to selection information provided from an external device. | 09-13-2012 |
20120236641 | ASYMMETRIC LOG-LIKELIHOOD RATIO FOR MLC FLASH CHANNEL - Disclosed is an system and method for reading a flash memory cell with an adjusted read level. A current read level is adjusted to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1. | 09-20-2012 |
20120243310 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 09-27-2012 |
20120243311 | Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells - Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell. | 09-27-2012 |
20120243312 | SEMICONDUCTOR MEMORY DEVICE COMPRISING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF ERASING DATA THEREOF - A semiconductor memory device includes a memory cell, a bit line, a source line, and a sense amplifier. The memory cell has a stacked gate including a charge accumulation layer and a control gate. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The sense amplifier, during erase verification to determine whether or not a threshold voltage of the memory cell in an erased state is at a threshold level, reads the data from the memory cell and senses the data with a first voltage applied to the control gate of the memory cell, with a positive second voltage higher than the first voltage applied to the semiconductor substrate and the source line, and with a third voltage higher than the second voltage applied to the bit line. | 09-27-2012 |
20120250408 | MEMORY SYSTEM, CONTROLLER, AND METHOD FOR CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory system includes nonvolatile memory having a plurality of memory cells of storage capacity of a specified number of bits equal to or greater than two bits, and a number-of-rewrites management table managing numbers of rewrites of the memory cells. The memory system of the embodiment includes a controller writing to the memory cells in a number of bits in accordance with a write request of a host, dividing the memory cells into groups in dependence on storage capacity after the numbers of rewrites of the memory cells managed by the number-of-rewrites management table exceed a specified number, and writing to the memory cells of the group corresponding to storage capacity of the number of bits in accordance with the write request of the host. | 10-04-2012 |
20120257451 | NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells. | 10-11-2012 |
20120268988 | NONVOLATILE MEMORY DEVICE INCLUDING MEMORY CELL ARRAY WITH UPPER AND LOWER WORD LINE GROUPS - A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group. | 10-25-2012 |
20120268989 | NOVEL HIGH SPEED HIGH DENSITY NAND-BASED 2T-NOR FLASH MEMORY DESIGN - A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip. | 10-25-2012 |
20120268990 | SELECTIVE RE-PROGRAMMING OF ANALOG MEMORY CELLS - A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states. After initially storing the data, a second group of the analog memory cells, which potentially cause interference to the first group, is programmed. After programming the second group, the first group is selectively re-programmed with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset. | 10-25-2012 |
20120275220 | THREE-DIMENSIONAL MULTI-BIT NON-VOLATILE MEMORY AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately arranged gate stack regions and channel region spaces; gate dielectric layers for discrete charge storage; periodically arranged channel regions; source doping regions and drain doping regions symmetrically arranged to each other; bit lines led from the source doping regions and the drain doping regions; and word lines led from the gate stack regions. The gate dielectric layers for discrete charge storage can provide physical storage spots to achieve single-bit or multi-bit operations, so as to achieve a high storage density. According to the present disclosure, the localized charge storage characteristic of the charge trapping layer and characteristics such as a longer effective channel length and a higher density of a vertical memory structure are utilized, to provide multiple storage spots in a single memory cell. Therefore, the storage density is improved while good performances such as high speed are ensured. | 11-01-2012 |
20120275221 | MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells. | 11-01-2012 |
20120281471 | Memory Page Buffer - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 11-08-2012 |
20120281472 | Highly Compact Non-Volatile Memory and Method thereof - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness. | 11-08-2012 |
20120281473 | CARD CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits. | 11-08-2012 |
20120287710 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SPEEDING UP WRITE OPERATION - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, write circuit, memory unit, and voltage generation unit. A plurality of strings is arranged in the memory cell array, each of which includes a plurality of memory cells connected to word lines. The write circuit selects a first string selected as a sample from the memory cell array, and writes data to the memory cell. The memory unit holds, for each word line, the number of write operations to each memory cell of the first string. When data is written to each memory cell of a second string other than the first string, the voltage generation unit generates an initial write voltage based on the number of write operations, which corresponds to the selected word line and is read out from the memory unit. | 11-15-2012 |
20120287711 | FLASH MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A flash memory device includes a memory cell array, a temperature sensing unit, and a control unit. The memory cell array is configured to store a plurality of pieces of configuration data corresponding to respective temperature levels of the flash memory device, the pieces of configuration data indicative of respective operation parameter values of the flash memory device. The temperature sensing unit is configured to measure an ambient temperature of the flash memory device and to generate temperature level data. The a control unit is configured to receive the temperature level data from the temperature sensing unit, to read a piece of configuration data corresponding to the temperature level data from among the plurality of pieces of configuration data stored in the memory cell array, and to set operation parameters of the flash memory device according to an operation parameter value indicated by the read piece of configuration data. | 11-15-2012 |
20120307559 | DATA MODULATION FOR GROUPS OF MEMORY CELLS - Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of M number of programmed states, where M is greater than a minimum number of programmed states needed to store N/G units of data in one memory cell, and where the programmed state of each memory cell of the group is one of the combination of programmed states. | 12-06-2012 |
20120314495 | APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB - The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process. | 12-13-2012 |
20120314496 | NONVOLATILE MEMORY DEVICES HAVING IMPROVED READ RELIABILITY - Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages. | 12-13-2012 |
20120320671 | MEMORY DEVICE WITH REDUCED SENSE TIME READOUT - A method for data storage includes providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout configurations is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout configuration. | 12-20-2012 |
20120320672 | MEMORY DEVICE READOUT USING MULTIPLE SENSE TIMES - A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations. | 12-20-2012 |
20120320673 | DATA STORAGE SYSTEM HAVING MULTI-LEVEL MEMORY DEVICE AND OPERATING METHOD THEREOF - A method for a data storage system is disclosed. The method includes providing a memory cell array, and providing N blocks in a first region of the memory cell array, N being an integer greater than 1. Each cell of each block of the N blocks is configured to store no more than N−1 bits of data. The method further includes providing a block in the second region of the memory cell array. Each cell of the block in the second region is configured to store N bits of data. The method additionally includes configuring the data storage system so that when data is programmed to the memory cell array, N pages of the data are initially stored in N respective blocks of the first region of the memory cell array, and then the N pages of the data are stored in the block of the second region. | 12-20-2012 |
20120320674 | MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION - An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch. | 12-20-2012 |
20120320675 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges. | 12-20-2012 |
20120327711 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME - A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile memory device using the selected read voltage. | 12-27-2012 |
20130003455 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH ADVANCED MULTI-PAGE PROGRAM OPERATION - A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. | 01-03-2013 |
20130003456 | SCALABLE MULTI-FUNCTIONAL AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE - A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO | 01-03-2013 |
20130003457 | APPARATUS, SYSTEM, AND METHOD FOR USING MULTI-LEVEL CELL SOLID-STATE STORAGE AS REDUCED-LEVEL CELL SOLID-STATE STORAGE - A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. Each MLC memory element is capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit. The restricted number of programming states includes a first state which is an erase state. The restricted number of programming states also includes a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements. | 01-03-2013 |
20130003458 | NAND ARCHITECTURE MEMORY WITH VOLTAGE SENSING - A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier. | 01-03-2013 |
20130010537 | DEVICES AND METHODS OF PROGRAMMING MEMORY CELLS - Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data. | 01-10-2013 |
20130016558 | METHOD OF STORING DATA IN NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICEAANM Ahn; Jung-RoAACI Suwon-siAACO KRAAGP Ahn; Jung-Ro Suwon-si KRAANM Lee; Bong-YongAACI Suwon-siAACO KRAAGP Lee; Bong-Yong Suwon-si KRAANM Lee; Hae-BumAACI Suwon-siAACO KRAAGP Lee; Hae-Bum Suwon-si KRAANM Kim; Eui-DoAACI Ansan-siAACO KRAAGP Kim; Eui-Do Ansan-si KRAANM Jang; Houng-KukAACI Hwaseong-siAACO KRAAGP Jang; Houng-Kuk Hwaseong-si KRAANM Shin; Kyung-JunAACI Hwaseong-siAACO KRAAGP Shin; Kyung-Jun Hwaseong-si KRAANM Yoon; Tae-HyunAACI SeoulAACO KRAAGP Yoon; Tae-Hyun Seoul KR - In a method of storing data in a nonvolatile memory device, a program operation is performed on target memory cells among a plurality of memory cells based on a program voltage. A verification operation is performed on the target memory cells based on a verification voltage to determine whether all of the target memory cells are completely programmed. The verification voltage is changed depending on the program operation. | 01-17-2013 |
20130021846 | LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM - A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module. | 01-24-2013 |
20130021847 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block. | 01-24-2013 |
20130028017 | DETERMINING AND TRANSFERRING DATA FROM A MEMORY ARRAY - Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell. | 01-31-2013 |
20130028018 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - In method of programming a nonvolatile memory device, multi-bit data are loaded into a plurality of page buffers. Multi-level cells included in a multi-level cell block are programmed to a plurality of intermediate program states including a first intermediate program state and a second intermediate program state which is higher than the first intermediate program state based on the multi-bit data. Whether the multi-level cells are programmed to the plurality of intermediate program states is verified. Cell group information for the first intermediate program state is generated by checking whether a result of the verification for the second intermediate program state satisfies a predetermined criterion. The multi-level cells are programmed to a plurality of target program states corresponding to the multi-bit data based on the cell group information. | 01-31-2013 |
20130028019 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i01-31-2013 | |
20130033933 | ADJUSTING OPERATIONAL PARAMETERS FOR MEMORY CELLS - Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit configured to perform one or more reading operations on a set of memory cells to determine an upper bound of the threshold voltages of the set of memory cells. The device may further include a parameter adjustment unit configured to adjust one or more operational parameters for the set of memory cells based, at least in part, on the determined upper bound of the threshold voltages. Other techniques and devices are also provided. | 02-07-2013 |
20130039126 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of | 02-14-2013 |
20130044542 | METHOD OF SORTING A MULTI-BIT PER CELL NON-VOLATILE MEMORY AND A MULTI-MODE CONFIGURATION METHOD - A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block. | 02-21-2013 |
20130051141 | THRESHOLD VOLTAGE COMPENSATION IN A MULTILEVEL MEMORY - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. | 02-28-2013 |
20130064013 | NON-VOLATILE MULTI-LEVEL MEMORY DEVICE AND DATA READ METHOD - A non-volatile memory device, a data read method thereof and a recording medium are provided. The method includes receiving a data read command for a first word line in a memory cell array, reading data from a second word line adjacent to the first word line, and reading data from the first word line using a different voltage according to a state of the data read from the second word line. The number of read voltages used to distinguish an erased state and a first programmed state is greater than the number of read voltages used to distinguish a second programmed state and a third programmed state. | 03-14-2013 |
20130070524 | ON CHIP DYNAMIC READ FOR NON-VOLATILE STORAGE - Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die. | 03-21-2013 |
20130070525 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a control circuit controlling a read operation of applying a read voltage to a selected memory cell to read data, and a write verify operation of applying a verify voltage to the selected memory cell. In a first case, the control circuit sets a voltage to a first write verify voltage and a first read voltage. In a second case in which the memory cells deteriorate more than in the first case, the control circuit sets a voltage to a second write verify voltage and a second read voltage. The control circuit sets a difference between a maximum value of the first write verify voltage and a maximum value of the first read voltage to be more than a difference between a maximum value of the second write verify voltage and a maximum value of the second read voltage. | 03-21-2013 |
20130070526 | FLASH MEMORY AND READING METHOD OF FLASH MEMORY - A reading method of a flash memory, the reading method including: sensing hard data of a first target page by using a first hard read voltage; and generating soft data of the first target page by using at least one pair of, that is, two, first soft read voltages whose voltage levels are different from a voltage level of the first hard read voltage, while the flash memory performs a first operation on the hard data. | 03-21-2013 |
20130077400 | MEMORY DEVICE AND CONTROL METHOD OF MEMORY DEVICE - A memory card includes: a plurality of memory cells; a CPU core; and an ECC unit configured to perform soft decision decoding. If decoding based on an LLR acquired from a first LLR table fails, the memory card measures a threshold voltage distribution centered on a first HB read voltage with a highest voltage. If a first shift value as a difference between a least frequent voltage of the threshold voltage distribution and the first HB read voltage is “negative”, the memory card performs decoding based on an LLR acquired from the second LLR table. If the first shift value is “positive”, the memory card performs decoding based on an LLR acquired from a third LLR table. | 03-28-2013 |
20130088917 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device is programmed by performing a plurality of program loops each comprising sequentially applying first through n-th program pulses (n>1) to a selected wordline connected to a page of memory cells to be programmed, and incrementing each of the first through n-th program pulses prior to a next program loop, wherein the first through n-th program pulses are used to program selected memory cells to respective first through n-th program states, and during application of an i-th program pulse among the first through n-th program pulses (1 | 04-11-2013 |
20130094288 | CATEGORIZING BIT ERRORS OF SOLID-STATE, NON-VOLATILE MEMORY - Bit errors affecting cells of a solid-state, non-volatile memory are assigned to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells. A reference voltage used to access the respective cells is adjusted to manage the respective bit errors of the first category. Additional corrective measures are taken to manage the respective bit errors of the second category. | 04-18-2013 |
20130094289 | DETERMINATION OF MEMORY READ REFERENCE AND PROGRAMMING VOLTAGES - Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions. | 04-18-2013 |
20130094290 | SHIFTING CELL VOLTAGE BASED ON GROUPING OF SOLID-STATE, NON-VOLATILE MEMORY CELLS - Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells. | 04-18-2013 |
20130094291 | SEMICONDUCTOR MEMORY DEVICE - At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data. | 04-18-2013 |
20130094292 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF THE SAME - A method is provided for programming a multi-level cell flash memory device. The programming method includes programming a first memory cell of the multi-level call flash memory device to one of first through i-th program states, wherein i is a positive integer, by applying a first program pulse to the first memory cell in a first type programming operation, and programming a second memory cell to one of i+1-th through j-th program states, wherein j is an integer equal to or greater than three, by applying a second program pulse to the second memory cell in a second type programming operation. At least one of a second step voltage, a second bit-line forcing voltage and a second verification operation of the second type programming operation is different from a first step voltage, a first bit-line forcing voltage, and a first verification operation of the first type programming operation, respectively. | 04-18-2013 |
20130094293 | MEMORY DEVICE AND METHOD OF READING DATA FROM MEMORY DEVICE - A method is provided for reading data from memory cells, including at least one victim cell and at least one aggressor cell, using an element graph. The method includes defining function nodes corresponding to probability density functions with respect to a first physical characteristic of the at least one victim cell and a second physical characteristic of the at least one aggressor cell, defining variable nodes corresponding to at least one first data value stored in the at least one victim cell and at least one second data value stored in the at least one aggressor cell, and defining edges connecting the function nodes and the variable nodes. | 04-18-2013 |
20130094294 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE - Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory cells to judge an erase state and at least one program state; performing a state read operation in which the at least one program state is read using a plurality of state read voltages; and programming the program data in the memory cells using a plurality of verification voltages having different levels according to a result of the state read operation. Also disclosed are methods using a plurality of verification voltages selected based on factors which may affect a threshold voltage shift or other characteristic representing the data of a memory cell after programming. | 04-18-2013 |
20130107623 | MEMORY CELL SENSING | 05-02-2013 |
20130107624 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF | 05-02-2013 |
20130107625 | Flash Memory Apparatus and Method for Controlling Flash Memory Apparatus | 05-02-2013 |
20130114338 | VOLTAGE SUPPLY CONTROLLER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM - A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied. | 05-09-2013 |
20130121072 | METHOD FOR NON-VOLATILE MEMORY WITH BACKGROUND DATA LATCH CACHING DURING READ OPERATIONS - Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles. | 05-16-2013 |
20130128662 | NONVOLATILE MEMORY DEVICE AND METHOD OF READING DATA IN NONVOLATILE MEMORY DEVICE - A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs. | 05-23-2013 |
20130128663 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICE - A method for programming a non-volatile memory device includes: providing a non-volatile memory device including data cells capable of storing N-bit data (N is a natural number) and a monitoring cell capable of monitoring whether the N-bit data has been programmed into the data cells; performing a first programming operation for the data cells while inhibiting programming of the monitoring cell; and performing a second programming operation for the monitoring cell while inhibiting programming of the data cells, wherein the second programming operation is performed differently from the first programming. | 05-23-2013 |
20130135926 | APPARATUS HAVING INDICATIONS OF MEMORY CELL DENSITY AND METHODS OF THEIR DETERMINATION AND USE - Methods and apparatus utilizing indications of memory cell density facilitate management of memory density of a memory device. By permitting each of a plurality of portions of a memory array of the memory device to be assigned a corresponding memory cell density determined through an evaluation of those portions of the memory array, better performing portions of the memory array may not be hindered by lesser performing portions of the memory array. | 05-30-2013 |
20130135927 | SYSTEMS AND METHODS OF DECODING DATA USING SOFT BITS AT A NON-BINARY DECODER THAT USES PROBABILISTIC DECODING - A method includes reading a representation of a codeword stored in a multi-level-cell (MLC) memory by comparing cell threshold voltages in the MLC memory to hard bit thresholds to generate hard bit values and to soft bit thresholds to generate soft bit values. The hard bit values and the soft bit values are provided to a non-binary decoder that uses probabilistic decoding to obtain decoded data. | 05-30-2013 |
20130135928 | SEMICONDUCTOR MEMORY DEVICE, READING METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME - A reading method of a semiconductor memory device having a multi-level memory cell includes the steps of: reading flag data indicating whether the most significant bit (MSB) of data programmed in the multi-level memory cell is programmed or not; storing the read flag data; reading the least significant bit (LSB) of the data programmed in the multi-level memory cell, based on the read flag data; and reading the MSB of the data programmed in the multi-level memory cell based on the stored flag data. | 05-30-2013 |
20130135929 | METHOD OF PROGRAMMING MULTI-LEVEL CELLS IN NON-VOLATILE MEMORY DEVICE - A method of programming a multi-level cells (MLC) commonly coupled to a word line in a non-volatile memory device includes shadow-programming first MLC to a first shadow state, shadow-programming second MLC to a second shadow state less than the first shadow state, and then main-programming the first MLC from the first shadow state to a first final state and main-programming the second MLC from the second shadow state to the second final state less than the first final state. | 05-30-2013 |
20130141972 | DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern. | 06-06-2013 |
20130141973 | NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION - A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell. | 06-06-2013 |
20130141974 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises pre-programming multi-bit data in a plurality of multi-level memory cells, reading the pre-programmed multi-bit data from the plurality of multi-level cells based on state group codes indicating state groups of the plurality of multi-level cells, and re-programming the read multi-bit data to the plurality of multi-level cells. | 06-06-2013 |
20130148424 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 06-13-2013 |
20130148425 | ON CHIP DYNAMIC READ FOR NON-VOLATILE STORAGE - Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die. | 06-13-2013 |
20130148426 | SENSE OPERATION IN A MEMORY DEVICE - Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell. | 06-13-2013 |
20130155768 | Method for Operating a High Density Multi-Level Cell Non-Volatile Flash Memory Device - A localized trapping multi-level memory cell operating method includes the following steps. First, a localized trapping memory cell with the initial threshold voltage of ˜2.5V is provided. Next, an erasing operation is performed to obtain a negative threshold level which has the uniform distribution along the channel region. Taking into account the over-erasure issue in the erasing course, a programming operation is performed to precisely adjust the threshold voltage to a predetermined level of −2V˜−1V. Then, with the negative voltage as a new initial state, corresponding programming operation is performed and electrons are locally injected the storage layer. By controlling the quantity of injected electrons, the MLC storage is achieved. | 06-20-2013 |
20130155769 | Non-Volatile Memory And Method With Improved First Pass Programming - A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced. | 06-20-2013 |
20130155770 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array having a plurality of bit lines and a plurality of word lines intersecting each other and a plurality of nonvolatile memory cells; and a page buffer for each bit line including a latch configured to store one of data to be written to a first nonvolatile memory cell selected by each word line and data read from the first nonvolatile memory cell, wherein before reading out data, the page buffer configured to store in a replica capacitor a voltage value of a word line adjacent to the selected word line when a second nonvolatile memory cell is turned on, the replica capacitor including a first capacitor and a second capacitor connected in parallel, and the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell according to the voltage value. | 06-20-2013 |
20130163329 | MEMORY SYSTEM - Provided is a non-volatile semiconductor storage device according to one embodiment including: a memory cell array where memory cells capable of storing data of three or more levels are arrayed; a flag cell which is provided in an access prevention area where external access to the memory cell array is prevented; a flag data generating unit which generates flag data which is to be written in the flag cell based on a written state of the memory cell array; and an access prevention cancelling unit which permits external reading of the flag data based on an externally applied command. | 06-27-2013 |
20130170293 | HYBRID MULTI-LEVEL CELL PROGRAMMING SEQUENCES - A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC. | 07-04-2013 |
20130170294 | MULTIPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME - A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M-1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an M | 07-04-2013 |
20130176776 | Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Program to Verify Transition - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level. | 07-11-2013 |
20130176777 | Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Verify to Program Transition - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level. | 07-11-2013 |
20130176778 | CELL-LEVEL STATISTICS COLLECTION FOR DETECTION AND DECODING IN FLASH MEMORIES - Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level statistics are optionally generated substantially simultaneously with a reading of the read values, for example, as part of a read scrub process. The cell-level statistics can be used to convert the read values for the plurality of bits to a reliability value for a bit among the plurality of bits. | 07-11-2013 |
20130176779 | INTER-CELL INTERFERENCE CANCELLATION IN FLASH MEMORIES - Inter-cell interference cancellation is provided for flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized threshold voltage values for at least one target cell of the flash memory device; obtaining one or more hard decision read values for at least one aggressor cell of the target cell; determining an aggressor state of the at least one aggressor cell; determining an interference amount based on the aggressor state; determining an adjustment to the quantized threshold voltage values based on the determined interference amount; and adjusting the quantized threshold voltage values based on the determined adjustment. The quantized threshold voltage values for at least one target cell are optionally re-used from a previous soft read retry operation. The adjusted quantized threshold voltage values are optionally used to determine reliability values and are optionally applied to a soft decision decoder and/or a buffer. | 07-11-2013 |
20130176780 | DETECTION AND DECODING IN FLASH MEMORIES WITH ERROR CORRELATIONS FOR A PLURALITY OF BITS WITHIN A SLIDING WINDOW - Methods and apparatus are provided for detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and decoding the plurality of bits using a binary decoder. The non-binary log likelihood ratio captures one or more of intra-page correlations and/or intra-cell correlations. A least significant bit and a most significant bit of a given cell can be independently converted and/or jointly converted to the non-binary log likelihood ratio. | 07-11-2013 |
20130182503 | METHOD, MEMORY CONTROLLER AND SYSTEM FOR READING DATA STORED IN FLASH MEMORY - An exemplary method for reading data stored in a flash memory is disclosed. The flash memory comprises a plurality of memory cells and stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of 2N voltage states. The method includes: controlling the flash memory to perform at least one read operation upon the memory cell to obtain at least one binary digit for representing a bit of the N bits data; generating a codeword for representing the bit of the N bits data according to the at least one binary digit, wherein the codeword is different from the at least one binary digit; providing the codeword to an error correction decoder for performing an error correction operation. | 07-18-2013 |
20130194864 | IMPLEMENTING ENHANCED DATA WRITE FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING - A method and apparatus are provided for implementing enhanced performance for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A voltage baseline of a prior write is identified, and a data write uses the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding for data being written to the MLC memory responsive to the identified voltage baseline. | 08-01-2013 |
20130194865 | IMPLEMENTING ENHANCED DATA READ FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING - A method and apparatus are provided for implementing enhanced data read for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data read back for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, higher voltage and lower voltage levels are compared, and respective data values are identified responsive to the compared higher voltage and lower voltage levels. | 08-01-2013 |
20130194866 | ACCESSING METHOD AND A MEMORY USING THEREOF - A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current. | 08-01-2013 |
20130201759 | COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage. | 08-08-2013 |
20130208539 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, and a control circuit. A first memory cell stores first data of n bits, a second memory cell stores second data used to determine whether data of k bits is stored in the first memory cell, and the control circuit performs first determination of determining data read from the data of the second memory cell, performs second determination of determining data read from the second memory cell by supplying the first word line with a second read voltage different from the first read voltage, and outputs either one of a result obtained by reading the data stored in the first memory cell at the first read voltage and a result obtained by reading the data stored in the first memory cell at the second read voltage, based on a result of the second determination. | 08-15-2013 |
20130208540 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - An instruction to perform an erase on a group of one or more memory cells is sent. An indication that the erasure of the group of memory cells is unsuccessful is received. In response to receiving the indication that the erasure of the group of memory cells is unsuccessful, the value of a voltage threshold, associated with the group of memory cells, is changed to a new voltage threshold and the new voltage threshold and identification information associated with the group of memory cells is stored. | 08-15-2013 |
20130208541 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 08-15-2013 |
20130215678 | Method, Memory Controller and System for Reading Data Stored in Flash Memory - An exemplary method for reading data stored in a flash memory. The method comprises: controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain a first binary digit for representing a bit of the N bits data; performing an error correction hard decode according to the first binary digit; controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable result; and performing an error correction soft decode according to the first binary digit and the second binary digit. | 08-22-2013 |
20130223143 | NONVOLATILE MEMORY DEVICE HAVING ADJUSTABLE PROGRAM PULSE WIDTH - A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line. | 08-29-2013 |
20130223144 | ACCESSING AN NROM ARRAY - A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method. | 08-29-2013 |
20130223145 | APPARATUS CONFIGURED TO PROGRAM A MEMORY CELL TO A TARGET THRESHOLD VOLTAGE REPRESENTING A DATA PATTERN OF MORE THAN ONE BIT - Memory devices and bulk storage devices configured to program a memory cell to a target threshold voltage representing a data pattern of more than one bit and read the data pattern of more than one bit of the memory cell in a single read operation by generating a signal that is representative of an actual threshold voltage of the memory cell. | 08-29-2013 |
20130223146 | REFERENCE VOLTAGE OPTIMIZATION FOR FLASH MEMORY - A system including a reference voltage module to generate one or more reference voltages used to determine states of a plurality of memory cells of a nonvolatile memory. The memory cells have a threshold voltage distribution. A divider module selects, in response to a change in the threshold voltage distribution, a voltage range within which to update one of the reference voltages, and divide the voltage range into a plurality of regions. A counting module counts a number of the memory cells having threshold voltages within each of the plurality of regions. An update module selects one of the plurality of regions having the threshold voltages of a smallest number of the memory cells, and updates the one of the reference voltages to a voltage value associated with the selected one of the plurality of regions to compensate for the change in the threshold voltage distribution. | 08-29-2013 |
20130229868 | Saving of Data in Cases of Word-Line to Word-Line Short in Memory Arrays - Technique of operating a non-volatile memory are presented so that in case data that would otherwise be lost in the case of a word line to word line short is preserved. Before writing a word line, the data from a previously written adjacent is word line is read back and stored in data latches associated with the corresponding bit lines, but that are not being used for the data to be written. If a short occurs, as the data for both word lines is still in the latches, it can be written to a new location. This technique can also be incorporated into cache write operations and for a binary write operation inserted into a pause of a multi-state write. | 09-05-2013 |
20130229869 | ACCESSING MEMORY USING REFERENCE VOLTAGES - Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of reference voltages that are near an integral reference voltage to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results. | 09-05-2013 |
20130235660 | LOCAL SELF-BOOST USING A PLURALITY OF CUT-OFF CELLS ON A SINGLE SIDE OF A STRING OF MEMORY CELLS - Methods for local self-boost of a selected memory cell channel, memory devices, and systems are disclosed. One such method generates a cut-off channel under each of a plurality of memory cells on one of either a source side or a drain side of a selected memory cell. | 09-12-2013 |
20130235661 | STRUCTURES AND METHODS OF HIGH EFFICIENT BIT CONVERSION FOR MULTI-LEVEL CELL NON-VOLATILE MEMORIES - Structures and methods of converting Multi-Level Cell (MLC) Non-Volatile Memory (NVM) into multi-bit information are disclosed. In MLC NVM system, multi-bit information stored in NVM cell is represented by the states of NVM cell threshold voltage levels. In this disclosure, “P” states of NVM cell threshold voltage levels are divided into “N” groups of threshold voltage levels. Each group contains “M” states of multiple threshold voltage levels of NVM cells, where P=N×M. The “M” states of NVM cell threshold voltage levels in each group are sensed and resolved by applying one correspondent gate voltage to the group. By applying “N” multiple gate voltages, the whole “P” states of NVM cell threshold voltage levels can be sensed and efficiently converted into storing bits in the MLC NVM cells. | 09-12-2013 |
20130235662 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a control circuit executes a first page writing operation, a first verify operations, a second page writing operation, a second verify operations, a step-up operation. The control circuit executes the first page writing operation which forms an intermediate distribution, and a first read operation which reads data form the intermediate distribution by using a determine voltage higher than a first verify voltage with a first value, and changes a second verify voltage based on the result of the first read operation. | 09-12-2013 |
20130235663 | VOLTAGE MODE SENSING FOR LOW POWER FLASH MEMORY - Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits. | 09-12-2013 |
20130235664 | Non-Volatile Memory Systems and Methods - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. | 09-12-2013 |
20130235665 | METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY CELLS BASED ON PROGRAMMING OF PROXIMATE MEMORY CELLS - A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed. | 09-12-2013 |
20130242652 | Enhanced Multilevel Memory - Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories. | 09-19-2013 |
20130242653 | FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME - A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages. | 09-19-2013 |
20130250677 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND PROGRAM METHOD OF THE SAME - Disclosed is a method for programming a nonvolatile memory device, which includes memory cells arranged in a plurality of rows. The programming method includes alternately selecting word lines to program data at a first page portion and a second page portion associated with the memory cells. After the first and second page portions are programmed, the method includes programming data at a third page portion associated with the memory cells according to an order in which word lines are arranged. The word lines may be sequentially selected one by one from a word line adjacent to a ground selection line. | 09-26-2013 |
20130250678 | PAGE BUFFER, MEMORY DEVICE COMPRISING PAGE BUFFER, AND RELATED METHOD OF OPERATION - A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node. | 09-26-2013 |
20130250679 | NAND STEP UP VOLTAGE SWITCHING METHOD - Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired. | 09-26-2013 |
20130250680 | METHODS OF PROGRAMMING SEMICONDUCTOR MEMORY DEVICES - To program a semiconductor memory device, a plurality of target threshold voltage groups are set by dividing target threshold voltages representing states of memory cells. The target threshold voltage groups are substantially simultaneously programmed by applying a plurality of program voltages to a word line. Program end times for the target threshold voltage groups are adjusted. | 09-26-2013 |
20130250681 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 09-26-2013 |
20130250682 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 09-26-2013 |
20130258772 | Non-Volatile Memory and Method Having a Memory Array with a High-Speed, Short Bit-Line Portion - A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions. | 10-03-2013 |
20130258773 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH TRANSFERS A PLURALITY OF VOLTAGES TO MEMORY CELLS AND METHOD OF WRITING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, a bit line, and a voltage generator. The memory cell array includes each of a plurality of memory cells. Each of the memory cells includes a charge storage layer and a control gate and is capable of holding two or more levels of data. The bit line is capable of transferring data to the memory cells in a one-to-one correspondence. The voltage generator carries out a verify operation by applying a verify voltage to the memory cells after performing first writing by applying a first voltage and then a second voltage lower than the first voltage to the control gate. | 10-03-2013 |
20130272065 | Off-Die Charge Pump that Supplies Multiple Flash Devices - A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump. | 10-17-2013 |
20130279248 | Data Retention in Nonvolatile Memory with Multiple Data Storage Formats - In a nonvolatile memory that stores data in two or more different data storage formats, such as binary and MLC, a separation scheme is used to distribute blocks containing data in one data storage format (e.g. binary) so that they are separated by at least some minimum number of blocks using another data storage format (e.g. MLC). | 10-24-2013 |
20130279249 | OPERATING METHOD OF MEMORY SYSTEM INCLUDING NAND FLASH MEMORY, VARIABLE RESISTANCE MEMORY AND CONTROLLER - An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory. | 10-24-2013 |
20130279250 | NONVOLATILE MEMORY DEVICE WITH FLAG CELLS AND USER DEVICE INCLUDING THE SAME - A nonvolatile memory device includes a flag cell configured to store flag information, a plurality of dummy cells adjacent to the flag cell, and program control logic configured to control a program operation on the flag cell and a dummy program operation on the plurality of dummy cells. When the program operation on the flag cell is performed, the program control logic performs the dummy program operation on at least one of the plurality of dummy cells. | 10-24-2013 |
20130279251 | NOVEL SHIELDING 2-CYCLE HALF-PAGE READ AND PROGRAM SCHEMES FOR ADVANCED NAND FLASH DESIGN - The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period. | 10-24-2013 |
20130279252 | DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT - Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition. | 10-24-2013 |
20130286731 | MEMORY DEVICE, MEMORY CONTROL DEVICE, AND MEMORY CONTROL METHOD - A memory device includes: a plurality of nonvolatile memory sections configured to allow one memory cell to record data of a plurality of bits, and to include a corresponding number of pages to the plurality of bits in accordance with a plurality of the memory cells as a write control unit; and a control section configured to control writing and reading data to and from the plurality of nonvolatile memory sections, wherein among the plurality of nonvolatile memory sections, if data is written into one of the nonvolatile memory sections, the data is written for each page in sequence from a low-order page to a high-order page, and when the data is written into the low-order page, control is performed such that the data to be written into the low-order page is written into any area of the other of the nonvolatile memory sections at same timing. | 10-31-2013 |
20130286732 | FLASH MEMORY DEVICES HAVING MULTI-BIT MEMORY CELLS THEREIN WITH IMPROVED READ RELIABILITY - Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation. | 10-31-2013 |
20130286733 | METHOD OF PROGRAMMING/READING A NON-VOLATILE MEMORY WITH A SEQUENCE - A method of programming/reading a multi-bit per cell non-volatile memory with a sequence is disclosed. A plurality of less-significant-bit pages are programmed, and a plurality of consecutive most-significant-bit pages of a plurality of consecutive word lines are programmed one after the other in a consecutive order. The most-significant-bit pages through all word lines in at least one memory block of the non-volatile memory are programmed or read after the less-significant-bit pages through all the word lines in the at least one memory block are programmed or read. | 10-31-2013 |
20130294157 | READING DATA FROM MULTI-LEVEL CELL MEMORY - A method at a data storage device includes determining a first hard bit of a first logical page, the first hard bit corresponding to a particular cell of the MLC memory. A second hard bit of a second logical page is sensed. The second hard bit corresponds to the particular cell. The first hard bit is used as a soft bit of the second logical page to provide reliability information during a decode operation of the second logical page. | 11-07-2013 |
20130294158 | MULTI-LEVEL CELL MEMORY DEVICES AND METHODS OF STORING DATA IN AND READING DATA FROM THE MEMORY DEVICES - A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream. | 11-07-2013 |
20130294159 | DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY - Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array. | 11-07-2013 |
20130301352 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE METHOD - A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other. | 11-14-2013 |
20130308380 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND READING METHOD THEREOF - Provided are a semiconductor memory device has improved read disturbance characteristics as well as improved retention characteristics at a high temperature, and a reading method thereof. The non-volatile semiconductor memory device includes at least one bit line; and a cell string configured to be coupled with the bit line respectively, and include normal memory cells and dummy memory cells that are alternately coupled with each other, where normal data are programmed and read to and from the normal memory cells, and dummy memory cells are programmed with dummy data. | 11-21-2013 |
20130308381 | NON-VOLATILE MEMORY AND METHODS WITH SOFT-BIT READS WHILE READING HARD BITS WITH COMPENSATION FOR COUPLING - A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”. | 11-21-2013 |
20130314988 | SYSTEMS AND METHODS OF UPDATING READ VOLTAGES - A method includes, in a data storage device that includes a non-volatile memory, reading first data values from memory elements of the non-volatile memory using a set of reference voltages that includes a first reference voltage, and determining a first error count associated with the first reference voltage. The method includes reading second data values from the group of memory elements using a set of modified reference voltages that includes a modified first reference voltage, and determining a modified error count associated with the modified first reference voltage. The method includes updating the set of reference voltages to include the first reference voltage or the modified first reference voltage based on a comparison of the error count to the modified error count. | 11-28-2013 |
20130314989 | MEMORY SYSTEM - A memory system includes nonvolatile memory cells each configured to store more than one bit of data, dummy memory cells adjacent to the nonvolatile memory cells, and a control section that applies a read voltage to the nonvolatile memory cells while a first voltage is applied to a gate of the dummy memory cells, when data of the nonvolatile memory cells are read out. The first voltage is higher than a second voltage for turning on the nonvolatile memory cells whose data are not read during the read out. | 11-28-2013 |
20130314990 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, the control circuit applies a pass potential to a first word line and a preliminary read-out potential to a second word line. The control circuit reads the data from the first memory cell transistor at a first condition when the second memory cell transistor has been switched to the ON state and at a second condition when the second memory cell transistor has been switched to an OFF state, by the applying of the preliminary read-out potential. The first condition enables the discrimination of the value of the first memory cell transistor in the case where a threshold distribution of the first memory cell transistor is relatively low. The second condition enables the discrimination of the value of the first memory cell transistor in the case where the threshold distribution of the first memory cell transistor is relatively high. | 11-28-2013 |
20130322170 | MEMORY CELL SENSING - This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data. | 12-05-2013 |
20130322171 | METHODS OF OPERATING NONVOLATILE MEMORY DEVICES THAT SUPPORT EFFICIENT ERROR DETECTION - Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells. | 12-05-2013 |
20130322172 | PROGRAMMING METHODS FOR THREE-DIMENSIONAL MEMORY DEVICES HAVING MULTI-BIT PROGRAMMING, AND THREE-DIMENSIONAL MEMORY DEVICES PROGRAMMED THEREBY - In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states. | 12-05-2013 |
20130329491 | Hybrid Memory Module - A hybrid. memory module. The module includes at least two heterogeneous memory devices and a memory buffer in communication with the memory devices to read data from any one of the memory devices and write the data to any other of the memory devices. | 12-12-2013 |
20130329492 | FLASH MEMORY CONTROL METHOD, CONTROLLER AND ELECTRONIC APPARATUS - A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element. | 12-12-2013 |
20130329493 | Natural Threshold Voltage Distribution Compaction In Non-Volatile Memory - In a non-volatile memory system, a programming operation is performed in which faster-programming storage elements are distinguished from slower-programming storage elements. In one approach, the distinguishing is achieved by applying programming pulses to a target word line, determining when a specified number of the non-volatile storage elements reach a defined verify level, and counting a number of the programming pulses after the specified number of the non-volatile storage elements reach the defined verify level. Upon completion of the counting, the non-volatile storage elements can be read using a read voltage. The storage elements having a threshold voltage above or below the read voltage are the faster- or slower-programming storage elements, respectively. The number of the programming pulses can be set based on a natural threshold voltage distribution of the non-volatile storage elements. | 12-12-2013 |
20130336057 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A method of programming selected memory cells to a plurality of target states comprises applying a first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to at least one target state, applying a program voltage to the selected memory cells, and applying a second verification voltage lower than the first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to the at least one target state, wherein the second verification voltage is provided in a specified program loop and subsequent program loops. The second verification voltage is set such that a number of slow bits in the at least one target state is different from the number of slow bits in another target state. | 12-19-2013 |
20130336058 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches. | 12-19-2013 |
20130343125 | APPARATUS AND METHODS FOR CARRYING OUT OPERATIONS IN A NON-VOLATILE MEMORY CELL HAVING MULTIPLE MEMORY STATES - Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states are disclosed. One of the methods is a method for programming N bits in a non-volatile memory cell configured to store up to N+1 bits, where N is an integer greater than zero. The method for programming includes programming N bits of data in the cell. The method for programming also includes programming an additional bit of data that is a logical function of the N bits of data in the cell. The cell is configured to provide 2N+1 threshold voltage ranges for bit storage and, in accordance with the logical function: i) a first set of 2N threshold voltage ranges of the 2N+1 threshold voltage ranges are used to store the N bits of data; and ii) a remaining second set of 2N threshold voltage ranges alternating with the first set are unused. | 12-26-2013 |
20140003142 | NONVOLATILE MEMORY DEVICE PERFORMING GARBAGE COLLECTION | 01-02-2014 |
20140003143 | FRACTIONAL BITS IN MEMORY CELLS | 01-02-2014 |
20140016409 | MULTIPLE STEP PROGRAMMING IN A MEMORY DEVICE - A method for multiple step programming programs data to an even page of memory cells. The even page of memory cells is read into a page buffer and the uncertain data is removed. An odd page of memory cells is programmed and the data from the even page data from the page buffer is reprogrammed to the even page of memory cells without the uncertain data. | 01-16-2014 |
20140016410 | MEMORY DEVICE AND METHOD ADJUSTING READ VOLTAGE ACCORDING TO VARYING THRESHOLD VOLTAGE DISTRIBUTIONS - A memory device comprises a memory cell that is in one of an erase state and first through N-th program states (N>2). The memory device can be read by determining a first read voltage between the erase state and the first program state based on variations of respective threshold voltage distributions of the erase state and the first program state, and determining one among second through N-th read voltages based on variations in respective threshold voltage distributions of two adjacent program states among the first through N-th program states, and determining remaining read voltages among the second through N-th read voltages based on the one read voltage. | 01-16-2014 |
20140016411 | DEVICES AND METHODS OF PROGRAMMING MEMORY CELLS - Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data. | 01-16-2014 |
20140022841 | Memory System with Unverified Program Step - In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps. | 01-23-2014 |
20140022842 | DATA STORAGE DEVICE COMPRISING NONVOLATILE MEMORY CHIPS AND CONTROL METHOD THEREOF - A storage device is provided which includes a plurality of memory chips each nonvolatile memory cells divided into a first memory region and a second memory region; and a memory controller configured to buffer data provided from the exterior and to control the plurality of memory chips to perform a buffer-program operation and a main-program operation. The buffered data is stored at the first memory region at the buffer-program operation and data stored at the first memory region is written at the second memory region at the main-program operation. During a main-program operation of a first memory chip among the plurality of memory chips, the memory controller buffers data to be written at a second memory chip. | 01-23-2014 |
20140022843 | Protection Against Data Corruption for Multi-Level Memory Cell (MLC) Flash Memory - A system including a controller in communication with a memory. The memory includes memory cells arranged in memory blocks. Each memory cell is capable of storing a plurality of bits. Each memory block defines a plurality of pages. A page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block. The controller is configured to write data to selected pages in one or more memory blocks. The system includes circuitry configured to write data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data. The predetermined number is based on one or more of a number of pages in each memory block and a number of bits in the plurality of bits. | 01-23-2014 |
20140029336 | SYSTEMS AND METHODS OF UPDATING READ VOLTAGES - A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment. | 01-30-2014 |
20140029337 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 01-30-2014 |
20140029338 | STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N - A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set. | 01-30-2014 |
20140036587 | Structure and Method for Narrowing Voltage Threshold Distribution In Non-Volatile Memories - Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding calibration element are part of a common memory array within an integrated circuit, and therefore, are in close proximity to each other. The calibration element may store a parameter used to modify the threshold voltage of the storage element. | 02-06-2014 |
20140036588 | METHOD OF PROGRAMMING A MULTI-LEVEL MEMORY DEVICE - Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed. | 02-06-2014 |
20140043897 | AGGREGATING DATA LATCHES FOR PROGRAM LEVEL DETERMINATION - In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results. | 02-13-2014 |
20140043898 | Common Line Current for Program Level Determination in Flash Memory - In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory. | 02-13-2014 |
20140043899 | MOSFET HAVING MEMORY CHARACTERISTICS - A method for performing a programming operation to a first memory bit and a second memory bit of a device is described. The method includes applying a pulse train voltage to a metal gate of the device and grounding a substrate of the device. By floating/grounding a drain of the device and/or by floating/grounding the source of the device, the first memory and the second memory bit are programmed. The pulse train voltage includes 10 to 1000 pulses. One pulse includes a peak voltage and a base voltage. The peak voltage ranges from 0.5 V to 10 V. A duration of the peak voltage ranges from 1 nanosecond to 1 millisecond. The base voltage is 0 V. A duration of the base voltage ranges from 1 nanosecond to 1 millisecond. | 02-13-2014 |
20140043900 | STORAGE DEVICE AND CONTROL METHOD OF NONVOLATILE MEMORY - According to one embodiment, a storage device includes a nonvolatile memory including physical sectors each of which comprises memory cells commonly connected to a word line, each of the memory cells being capable of storing data of not less than 2 bits, each of the physical sectors including pages corresponding to the number of bits storable in the memory cell, and a controller configured to receive a first write command and to write data associated with the first write command to the nonvolatile memory. In a write process using the first write command, the controller is configured to skip an upper page of a physical sector whose lower page is write-accessed by a second write command prior to the first write command. | 02-13-2014 |
20140043901 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD WITH VARIABLE MEMORY CELL STATE DEFINITIONS - A method operating a nonvolatile memory device includes successively programming a memory cell without physically erasing the memory cell. Each successive programming of the memory cell uses a different erase state region to indicate an erase state for the memory cell. | 02-13-2014 |
20140043902 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a storage unit with multiple memory cells that store data, and a bit-line switch circuit. The bit-line switch circuit is connected to a word line that is connected to the bit line, the source line, and the control gate of the memory cell, which is connected to both ends of the string, in order to write and to read out data from each memory cell. The bit-line wiring that is connected to the bit-line switch circuit is arrayed via a disconnection part into a high potential side wiring part including the bit-line wiring on the high potential side and a low potential side wiring part including the bit-line wiring on the low potential side. In the disconnection part is a dummy wiring part that is in a floating state. | 02-13-2014 |
20140043903 | MEMORY DEVICE HAVING VARIABLE READ VOLTAGE AND RELATED METHODS OF OPERATION - A method of determining a read voltage of a memory device comprises performing a plurality of read operations with respective different read voltages on a first group of storage regions of the memory device using a first error correction rate, wherein the plurality of read operations are performed to distinguish between a pair of adjacent logic states of memory cells in the first group of storage regions, detecting a read voltage level, among the different read voltages, at which a minimum number of erroneous bits is generated in the at least one read operation, and determining a read voltage for a second group of storage regions to which a second error correction rate is applied, based on the detected read voltage level, wherein the first error correction rate is higher than the second error correction rate. | 02-13-2014 |
20140043904 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A memory system performs a first sensing operation to sense whether multi-level cells assume an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line. It then supplies a pre-charge voltage to bit lines corresponding to multi-level cells that have been sensed as assuming the off-cell state in response to the first read voltage, and it performs a second sensing operation with the supplied pre-charge voltage to sense whether each of the multi-level cells that have been sensed as assuming the off-cell state assumes an on-cell state or an off-cell state in response to a second read voltage applied to the selected word line. | 02-13-2014 |
20140050023 | MEMORY DEVICE HAVING COLLABORATIVE FILTERING TO REDUCE NOISE - An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal. | 02-20-2014 |
20140050024 | DATA READING METHOD, AND CIRCUIT, REWRITABLE NON-VOLATILE MEMORY MODULE AND MEMORY STORAGE APPARATUS USING THE SAME - A data reading method for a rewritable non-volatile memory module, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes applying a bias for reading data to a target word line electrically connected to a target memory cell and applying a bias for selecting bit lines to a target bit line electrically connected to the target memory cell. The method also includes applying a first bias to at least one word line adjacent to the target word line and applying a second bias to other word lines, and the first bias is lower than the second bias. The method further includes outputting a corresponding value according to a conduction state of a channel of the target memory cell. Accordingly, the method can effectively increase the gate controllability of the memory cell to prevent read errors. | 02-20-2014 |
20140056066 | READ THRESHOLD ESTIMATION IN ANALOG MEMORY CELLS USING SIMULTANEOUS MULTI-VOLTAGE SENSE - A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds. | 02-27-2014 |
20140056067 | THRESHOLD OPTIMIZATION FOR FLASH MEMORY - Described embodiments provide enhanced read accuracy of a multi-level cell (MLC) flash memory. A read request for desired cells is received by a media controller of the memory. The media controller sets m thresholds to initial values, each threshold corresponding to a cell voltage level of the memory, and measures the cell voltage level of a given cell. For each of the desired cells of the memory, the media controller iteratively, until the measured cell voltage level converges on one of the thresholds, compares the measured cell voltage level to the thresholds. If the measured cell voltage level does not converge on one of the thresholds, the media controller updates the thresholds, remeasures the cell voltage level and compares the remeasured cell voltage level to the updated thresholds. Once the measured cell voltage level converges on a threshold, the media controller determines a binary level of the cell. | 02-27-2014 |
20140056068 | CONFIGURING STORAGE CELLS - Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes determining a usage history for a set of storage cells of a solid-state storage medium. A method includes adjusting a voltage threshold for a set of storage cells by an amount based at least in part on a usage history. A method includes configuring a set of storage cells to use an adjusted voltage threshold. | 02-27-2014 |
20140063939 | DIRECT MULTI-LEVEL CELL PROGRAMMING - A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage. | 03-06-2014 |
20140063940 | ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE - Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches. | 03-06-2014 |
20140063941 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells and memory strings. When lower-page data is first written into a memory string, all memory cells corresponding to the lower-page data are made write-target, a program-verifying level of first ones of the write-targeted memory cells is a first threshold level, and a program-verifying level of second ones of the write-targeted memory cells is a second threshold level. The first threshold level corresponds to data associated with the lowest threshold level and is higher than a third threshold level. The second threshold level is higher than the first threshold level. | 03-06-2014 |
20140071751 | SOFT ERASURE OF MEMORY CELLS - Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value. | 03-13-2014 |
20140071752 | NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system. | 03-13-2014 |
20140071753 | APPARATUS AND METHOD FOR STORING DATA IN TERMINAL - Provided is an apparatus and method for storing data in a terminal are provided. The apparatus includes a processor for sending a first command to a memory to instruct storage of data in a Single-Level Cell (SLC) area of the memory if a function requiring high-speed storage of large amounts of data is selected; and the memory for storing received data in the SLC area regardless of a size of the data, upon receiving the first command from the processor. | 03-13-2014 |
20140071754 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction. | 03-13-2014 |
20140092682 | METHOD FOR PROGRAMMING AND READING FLASH MEMORY BY STORING LAST PROGRAMMING PAGE NUMBER - The invention is to provide a method for programming and reading a flash memory, storing the last programming page in a block while programming the flash memory, judging the programming times in the cell of the block by means of the last programming page and the order and distribution of the page in the predefined page distribution list of the block while reading the flash memory, and selecting the predefined voltage based on the judged programming times to implement the reading process for raising reading performance. | 04-03-2014 |
20140098607 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 04-10-2014 |
20140104943 | ACCELERATED SOFT READ FOR MULTI-LEVEL CELL NONVOLATILE MEMORIES - A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. For example, the given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page. | 04-17-2014 |
20140104944 | PROGRAMMING BASED ON CONTROLLER PERFORMANCE REQUIREMENTS - Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit. | 04-17-2014 |
20140112069 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method and device for a flash memory. According to the method, the flash memory obtains write data to be written to the flash memory, directs the flash memory to write a data page of the write data to a strong page of a target pair page of a target block, and directs the flash memory to write first predetermined data to a weak page of the target pair page for extending the data duration of the strong page of the target pair page. | 04-24-2014 |
20140112070 | MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND COMPUTING SYSTEM INCLUDING THE SAME - Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device. | 04-24-2014 |
20140119113 | Threshold Acquisition and Adaption in NAND Flash Memory - A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell. The method can further include performing at least one threshold voltage adjustment iteration. | 05-01-2014 |
20140119114 | CENTER READ REFERENCE VOLTAGE DETERMINATION BASED ON ESTIMATED PROBABILITY DENSITY FUNCTION - Embodiments include systems, methods, and apparatuses to estimate respective first and second cumulative density functions (CDFs) for values of a plurality of non-volatile memory (NVM) cells in a page of memory. The CDFs may be based at least in part on one or more decoder outputs of codewords for data stored in the page. Based at least in part on the CDFs, first and second probability density functions (PDFs) may be estimated for the values of the page of memory. A center read reference voltage may then be determined for reading a cell in the page. The center read reference voltage may be based at least in part on the first and second PDFs. | 05-01-2014 |
20140119115 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes first memory blocks configured to store m-bit data per cell and second memory blocks configured to store n-bit data per cell. The memory controller is configured to control the nonvolatile memory device to close an open word line generated in a second memory block of the second memory blocks when a program operation is performed on the second memory block. | 05-01-2014 |
20140119116 | DATA WRITING METHOD AND DATA STORAGE DEVICE FOR ADJUSTING PROGRAMMING VOLTAGE VALUES - A data storage device and method including a controller configured to adjust a plurality of programming voltage values for programming most significant bits (MSB) of a plurality of stored data patterns of the memory cells of the flash memory to obtain a plurality of adjusted programming voltage values, wherein the controller is configured to determine a plurality of neighboring data pairs having the stored data patterns corresponding to the programming voltage values neighboring to each other, determine a plurality of difference bits between the stored data patterns of the neighboring data pairs, determine a plurality of target neighboring data pairs with the difference bits corresponding to the most significant bits from the neighboring data pairs, and adjust the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns of the target neighboring data pairs. | 05-01-2014 |
20140126286 | SINGLE-LEVEL CELL ENDURANCE IMPROVEMENT WITH PRE-DEFINED BLOCKS - Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide in MLC blocks may improve data retention. A thinner IPD may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks. | 05-08-2014 |
20140126287 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 05-08-2014 |
20140126288 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 05-08-2014 |
20140126289 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 05-08-2014 |
20140133225 | DATA COMPENSATING METHOD FOR FLASH MEMORY - A data compensating method for a flash memory is provided. Firstly, a first threshold voltage distribution curve of the cells of the flash memory with a first storing state is acquired. Then, a second threshold voltage distribution curve of the cells of the flash memory with a second storing state is acquired. Then, a first occurrence probability of a first type ICI pattern of the first storing state is calculated according to a statistic voltage range and the first threshold voltage distribution curve. A second occurrence probability of the first type ICI pattern of the second storing state is acquired according to the statistic voltage range and the second threshold voltage distribution curve. During a read cycle, storing states of central cells corresponding to the first type ICI pattern are compensated according to the first occurrence probability and the second occurrence probability. | 05-15-2014 |
20140133226 | ERASING PHYSICAL MEMORY BLOCKS OF NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 05-15-2014 |
20140140130 | SEMICONDUCTOR MEMORY DEVICE FOR AND METHOD OF APPLYING TEMPERATURE-COMPENSATED WORD LINE VOLTAGE DURING READ OPERATION - A semiconductor memory device configured to apply a temperature-compensated word line voltage to a word line during a data read operation includes a memory cell array including a plurality of word lines, a plurality of non-volatile memory cells connected to the word lines, and a word line voltage application unit configured to apply a temperature-compensated read voltage to a selected word line and to apply a temperature-compensated pass voltage to at least one unselected word line during a read operation. | 05-22-2014 |
20140146605 | REFRESH METHOD FOR FLASH MEMORY AND RELATED MEMORY CONTROLLER THEREOF - A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space. | 05-29-2014 |
20140146606 | PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY - Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories. | 05-29-2014 |
20140153329 | NONVOLATILE MEMORY DEVICE COMPRISING PAGE BUFFER AND OPERATION METHOD THEREOF - A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set. | 06-05-2014 |
20140153330 | METHOD FOR OPERATING NON-VOLATILE MEMORY DEVICE AND MEMORY CONTROLLER - An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage. | 06-05-2014 |
20140153331 | MULTI-LEVEL CELL MEMORY DEVICE AND OPERATING METHOD THEREOF - According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch. | 06-05-2014 |
20140160842 | Adaptive Operation of Multi Level Cell Memory - A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode. | 06-12-2014 |
20140160843 | NON-VOLATILE MULTILEVEL MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states. | 06-12-2014 |
20140177334 | CIRCUIT FOR SENSING MLC FLASH MEMORY - A circuit for sensing a multi-level cell (MLC) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch. Each of the first decoding units provides a timing information and includes a controlled transistor to allow a current to pass therethrough, and a capacitor to be charged by the current or to discharge through the controlled transistor. The second decoding unit provides a latch signal and includes a controlled transistor to allow a current to pass therethrough, the magnitude of the current being associated with data in an MLC, and a capacitor to be charged by the current or to discharge through the controlled transistor. The data latch, in response to the timing information from each of the first decoding units and the latch signal from the second decoding unit, determines the data in the MLC. | 06-26-2014 |
20140177335 | NONCONSECUTIVE SENSING OF MULTILEVEL MEMORY CELLS - The present disclosure includes apparatuses and methods for nonconsecutive sensing of multilevel memory cells. A number of methods include sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC. | 06-26-2014 |
20140185376 | METHOD AND SYSTEM FOR ASYNCHRONOUS DIE OPERATIONS IN A NON-VOLATILE MEMORY - A mass storage memory system and method of operation is disclosed. The memory includes an interface adapted to receive data from a host, a plurality of flash memory die and a controller, where the controller is configured to receive a first command and read or write data synchronously across the plurality of die based on a first command, and to receive a second command and read or write data asynchronously and independently in each die based on a second command. The controller may program data in a maximum unit of programming for an individual one of the plurality of flash memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die. | 07-03-2014 |
20140185377 | MULTI-LEVEL CELL MEMORY DEVICE AND METHOD OF OPERATING MULTI-LEVEL CELL MEMORY DEVICE - A read method of a multi-level cell memory device includes receiving a first read command, and reading first and second hard decision data by performing first and second hard decision read operations using a first hard decision read voltage and a second hard decision read voltage, respectively, the second hard decision read voltage being higher than the first hard decision read voltage. The method further includes selecting one of the first and second hard decision read voltages, reading first soft decision data by performing a first soft decision read operation using a plurality of soft decision read voltages having voltage levels which are different from that of the selected one of the first and second hard decision read voltages, and providing the first soft decision data to a memory controller for first error correction code (ECC) decoding. | 07-03-2014 |
20140185378 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2″ pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits. | 07-03-2014 |
20140192593 | FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME - A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages. | 07-10-2014 |
20140198567 | DYNAMIC ADJUSTMENT OF READ VOLTAGE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION - A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read. | 07-17-2014 |
20140198568 | NON-VOLATILE MEMORY SYSTEMS AND METHODS - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. | 07-17-2014 |
20140198569 | FLASH MEMORY, FLASH MEMORY SYSTEM AND OPERATING METHOD OF THE SAME - A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells. | 07-17-2014 |
20140198570 | PROGRAMMING MULTIBIT MEMORY CELLS - A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities. | 07-17-2014 |
20140211561 | PROGRAMMING NON-VOLATILE STORAGE SYSTEM WITH MULTIPLE MEMORY DIE - A system and methods for programming a set of data onto non-volatile memory elements, maintaining copies of the data pages to be programmed, as well as surrounding data pages, internally or externally to the memory circuit, verifying programming correctness after programming, and upon discovering programming error, recovering the safe copies of the corrupted data to be reprogrammed in alternative non-volatile memory elements. Additionally, a system and methods for programming one or more sets of data across multiple die of a non-volatile memory system, combining data pages across the multiple die by means such as the XOR operation prior to programming the one or more sets of data, employing various methods to determine the correctness of programming, and upon identifying data corruption, recovering safe copies of data pages by means such as XOR operation to reprogram the pages in an alternate location on the non-volatile memory system. | 07-31-2014 |
20140211562 | FLASH MEMORY AND ASSOCIATED PROGRAMMING METHOD - A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage. | 07-31-2014 |
20140211563 | HOT CARRIER GENERATION AND PROGRAMMING IN NAND FLASH - A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting. | 07-31-2014 |
20140211564 | LEVEL-ESTIMATION IN MULTI-LEVEL CELL MEMORY - The memory cells storing a group of codewords are read to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword. The components of each read signal are ordered according to signal level to produce an ordered read signal. Correspondingly-positioned components of the ordered read signals are then ordered according to signal level to produce ordered component sets for respective component positions in a said ordered read signal. Each ordered component set is partitioned into subsets corresponding to respective memory cell levels, wherein the subsets of the ordered component sets contain respective numbers of components dependent on predefined probabilities of occurrence of different symbol values at different positions in a said codeword whose symbols are ordered according to symbol value. The reference signal level is determined in dependence on the signal components in the subsets corresponding to that memory cell level. | 07-31-2014 |
20140211565 | METHODS OF PROGRAMMING MULTI-LEVEL CELL NONVOLATILE MEMORY DEVICES AND DEVICES SO OPERATING - To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line. | 07-31-2014 |
20140219018 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits. | 08-07-2014 |
20140219019 | SOLID STATE DRIVE AND DATA ERASING METHOD THEREOF - A data erasing method of a solid state drive is provided. The solid state drive includes a memory module. The memory module includes a block. A data to be erased is stored in the block. The data erasing method includes steps of performing a first erasing operation to erase the block, programming the block after the first erasing operation, and performing a second erasing operation to erase the block. | 08-07-2014 |
20140219020 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode. | 08-07-2014 |
20140233309 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k−1 levels (k≦n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing. | 08-21-2014 |
20140233310 | High-Resolution Readout of Analog Memory Cells - A method includes storing data in an analog memory cell by writing an analog value into the memory cell. After storing the data, the data stored in the memory cell is read by discharging electrical current to flow through the memory cell, during a predefined time interval, while applying a variable voltage to a gate of the memory cell. A fraction of the predefined time interval, during which the variable voltage allows the electrical current to flow through the memory cell, is estimated. The stored data is estimated based on the estimated fraction. | 08-21-2014 |
20140233311 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 08-21-2014 |
20140233312 | SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of | 08-21-2014 |
20140241055 | Method and System for Reducing the Complexity of Electronically Programmable Nonvolatile Memory - Embodiments relate to memory devices and methods for firmly programming at least a portion of a plurality of electronically programmable and erasable nonvolatile memory cells in a processing of the nonvolatile memory devices. | 08-28-2014 |
20140241056 | REDUCED COMPLEXITY RELIABILITY COMPUTATIONS FOR FLASH MEMORIES - Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2̂M possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages V | 08-28-2014 |
20140241057 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not. The control circuit is configured to, in the read operation, be capable of executing the read operation targeting the memory cell transistors connected to a portion of the plurality of bit lines, and not execute a charging operation in those other of the bit lines where the connected memory cell transistors are not targeted by the read operation. | 08-28-2014 |
20140241058 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SAME - According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions, the memory cell being connected between a bit line and a source line. The control circuit, in at least one of a write verify operation and a read operation on a selected memory cell, applies to the control gate a control gate voltage to determine the threshold of the selected memory cell, the control gate voltage having a plurality of values respectively corresponded to the plurality of threshold distributions, and sets a voltage between the bit line and the source line based on the control gate voltage. | 08-28-2014 |
20140247655 | MULTI-LEVEL CELL (MLC) NON-VOLATILE MEMORY DATA READING METHOD AND APPARATUS - Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells. | 09-04-2014 |
20140247656 | Pulse Control For NonVolatile Memory - A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 09-04-2014 |
20140247657 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data. | 09-04-2014 |
20140254262 | INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE - Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells. | 09-11-2014 |
20140254263 | Write Sequence Providing Write Abort Protection - In a multi-level cell (MLC) nonvolatile memory array, data is assigned sequentially to the lower and upper page of a word line, then both lower and upper pages are programmed together before programming a subsequent word line. Word lines of multiple planes are programmed together using latches to hold data until all data is transferred. Tail-ends of data of write commands are stored separately. | 09-11-2014 |
20140254264 | Defect Or Program Disturb Detection With Full Data Recovery Capability - A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches. | 09-11-2014 |
20140254265 | Flash Memory Cells, NAND Cell Units, Methods of Forming NAND Cell Units, and Methods of Programming NAND Cell Unit Strings - Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell (MLC) devices, and pass voltage applied to the control gates of the first gate types may be utilized to reduce programming voltages utilized to reach memory states of the MLC devices. Some embodiments include NAND cell units, and some embodiments include methods of forming NAND cell units. Also, some embodiments include methods of programming NAND cell unit string gates in which programming voltage applied to a first string gate is held below a threshold, and pass voltage applied to an adjacent string gate is increased and utilized to program the first string gate. | 09-11-2014 |
20140254266 | DIRECT MULTI-LEVEL CELL PROGRAMMING - A data storage device includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage. | 09-11-2014 |
20140269051 | PROGRAMMING SCHEMES FOR 3-D NON-VOLATILE MEMORY - A method includes providing data for storage in a memory, which includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections. The data is stored in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section. | 09-18-2014 |
20140269052 | SYSTEM AND METHOD OF DETERMINING READING VOLTAGES OF A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a memory according to a first technique and determining a second read threshold voltage of the set of storage elements of the memory according to a second technique. The first read threshold voltage is different from the second read threshold voltage, and the first technique is different from the second technique. | 09-18-2014 |
20140269053 | NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE - A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone. | 09-18-2014 |
20140269054 | NON-VOLATILE MEMORY AND METHOD OF OPERATION THEREOF - A method of altering threshold voltage distribution of a non-volatile MLC memory before the memory is programmed according to a pre-designated coding table. The method includes grouping a plurality of cells which are pre-designated to have the same first bit voltage in a same main state and then grouping the cells in a selected main state into a same sub state if they have the same pre-designated second bit voltage. The method further has a step by elevating the first bit voltage of the cells with highest pre-designated second bit voltage to a voltage which is greater than the voltage of the pre-designated highest main state. | 09-18-2014 |
20140269055 | SEMICONDUCTOR MEMORY DEVICE - Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read voltage candidates to read storage data from the cells, counts a distribution of voltages stored in the cells for each read voltage candidate, specifies a minimum read voltage candidate where a sum of the counting exceeds an expected number, and uses the specified candidate as a read voltage to distinguish a first storage data item corresponding to the expected number and an adjacent second storage data item. | 09-18-2014 |
20140269056 | SOLID STATE DRIVE ENCOUNTERING POWER FAILURE AND ASSOCIATED DATA STORAGE METHOD - A solid state drive and its associated data storage method are provided. The data storage method comprising steps of: receiving data-for-writing from a host, and transforming the data-for-writing to data-for-storage; comparing a supply voltage and a predetermined voltage; and when the supply voltage is lower than the predetermined voltage, proceeding a strong-page programming procedure for storing the data-for-storage to a blank area of a multi-level cell flash memory. | 09-18-2014 |
20140269057 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage. | 09-18-2014 |
20140269058 | Non-volatile Memory Program Algorithm Device And Method - A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold. | 09-18-2014 |
20140269059 | SHIFTING CELL VOLTAGE BASED ON GROUPING OF SOLID-STATE, NON-VOLATILE MEMORY CELLS - Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells. | 09-18-2014 |
20140286093 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a NAND string and a sense amplifier. The NAND string includes a memory cell transistor to be capable of holding any of three or more levels of values. The NAND string includes one end connected to a bit line and the other end connected to a source line. The sense amplifier connects the bit line. A first voltage is applied to the source line when a first read voltage is applied to a selected word line connected to a selected memory cell transistor. A second voltage is applied to the source line when a second read voltage is applied to the selected word line. The first voltage is higher than the second voltage. The first read voltage is the lowest voltage of a plurality of read voltage. The second read voltage is higher than the first read voltage. | 09-25-2014 |
20140286094 | DATA MODULATION FOR GROUPS OF MEMORY CELLS - Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of M number of programmed states, where M is greater than a minimum number of programmed states needed to store N/G units of data in one memory cell, and where the programmed state of each memory cell of the group is one of the combination of programmed states. | 09-25-2014 |
20140301141 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF - A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels. | 10-09-2014 |
20140307506 | Off-Die Charge Pump that Supplies Multiple Flash Devices - A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump. | 10-16-2014 |
20140313823 | NONVOLATILE MEMORY DEVICE, SYSTEM AND PROGRAMMING METHOD WITH DYNAMIC VERIFICATION MODE SELECTION - Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition. | 10-23-2014 |
20140313824 | DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory. The operating method of the data storage device includes storing data in the buffer memory, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the program pattern. | 10-23-2014 |
20140313825 | DRAIN SELECT GATE VOLTAGE MANAGEMENT - Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed. | 10-23-2014 |
20140313826 | OFF-DIE CHARGE PUMP THAT SUPPLIES MULTIPLE FLASH DEVICES - A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump. | 10-23-2014 |
20140321202 | DEFECTIVE BLOCK MANAGEMENT - In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations. | 10-30-2014 |
20140321203 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for accessing a memory includes: utilizing a Flash memory to perform a plurality of sensing operations with a plurality of different sensing voltages respectively corresponding to the plurality of sensing operations; according to the plurality of sensing operations, generating a first digital value of a Flash cell of the Flash memory; according to the plurality of sensing operations and the first digital value, generating at least a second digital value of the Flash cell; and obtaining soft information of the Flash cell according to the second digital value. The first digital value and the second digital value are used for determining information of a same bit stored in the Flash cell, a number of possible bit(s) of the Flash cell directly corresponds to a number of possible states of the Flash cell, and the obtained soft information is used for performing soft decoding. | 10-30-2014 |
20140321204 | METHOD AND APPARATUS FOR OPTIMIZING REFERENCE VOLTAGES IN A NONVOLATILE MEMORY - A system including a divider module, a read module, a counting module, and a reference voltage setting module. The divider module is configured to select a voltage range in which to adjust a reference voltage used to read memory cells of nonvolatile memory, and to divide the voltage range into a plurality of bins, where each of the bins is defined by a pair of voltages. The read module is configured to perform a plurality of read operations by applying, to the memory cells, the voltages defining the bins. The counting module is configured to generate, in each of the read operations, counts of a number of memory cells having threshold voltages in each of the bins. The reference voltage setting module is configured to adjust, based on the counts, the reference voltage to a voltage selected from one or more voltages associated with the bins. | 10-30-2014 |
20140328123 | Minimal Maximum-Level Programming - A method for writing data, the method may include evaluating current levels of multiple memory cells that belong to a certain set of memory cells or receiving an indication about the current levels of the multiple memory cells; encoding a new data unit to provide an encoded data unit to be written to the multiple memory cells while minimizing an amount of changes in levels of the maximum cell level among the multiple memory cells required for storing the encoded data unit; and writing the encoded data unit to the multiple memory cells. | 11-06-2014 |
20140334228 | LINEARLY RELATED THRESHOLD VOLTAGE OFFSETS - Threshold voltage offsets for threshold voltages are determined. The threshold voltage offsets may be linearly related by a non-zero slope. The threshold voltages are shifted using their respective threshold voltage offsets. The threshold voltages that are shifted by their respective threshold voltage offsets are used to read data from multi-level memory cells. | 11-13-2014 |
20140340964 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage11-20-2014 | |
20140340965 | SELECTIVE RE-PROGRAMMING OF ANALOG MEMORY CELLS - A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states. After initially storing the data, a second group of the analog memory cells, which potentially cause interference to the first group, is programmed. After programming the second group, the first group is selectively re-programmed with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset. | 11-20-2014 |
20140347923 | THRESHOLD VOLTAGE CALIBRATION USING REFERENCE PATTERN DETECTION - A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A V | 11-27-2014 |
20140347924 | DATA STORAGE IN ANALOG MEMORY CELLS ACROSS WORD LINES USING A NON-INTEGER NUMBER OF BITS PER CELL - A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows. | 11-27-2014 |
20140347925 | INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE - Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells. | 11-27-2014 |
20140355340 | UPDATING READ VOLTAGES - A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data. In another embodiment, storage elements of the memory are sensed using a set of candidate read voltages to generate sensing data that is transferred to a memory accessible to the controller. The multiple representations of data may be generated based on the sensing data to emulate results of reading the storage elements using a different combination of candidate reading voltages. | 12-04-2014 |
20140355341 | READ THRESHOLD ESTIMATION IN ANALOG MEMORY CELLS USING SIMULTANEOUS MULTI-VOLTAGE SENSE - A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds. | 12-04-2014 |
20140355342 | DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT - Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition. | 12-04-2014 |
20140369118 | CONFIGURING STORAGE CELLS - Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes determining a usage history for a set of storage cells of a solid-state storage medium. A method includes adjusting a voltage threshold for a set of storage cells by an amount based at least in part on a usage history. A method includes configuring a set of storage cells to use an adjusted voltage threshold. | 12-18-2014 |
20150016186 | METHODS AND APPARATUSES FOR DETERMINING THRESHOLD VOLTAGE SHIFT - Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells programmed to the first number of data states and determining changes in threshold voltage for memory cells at each data state of a second number of data states by searching threshold voltage data of memory cells programmed to the second number of data states within a range of threshold voltages, wherein the range is shifted from a previous range based on the changes in threshold voltage for memory cells programmed to the first number of data states. | 01-15-2015 |
20150016187 | ASYMMETRIC LOG-LIKELIHOOD RATIO FOR FLASH CHANNEL - Disclosed is a system and method for reading a flash memory cell with an adjusted read level. A current read level is set to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1. | 01-15-2015 |
20150023097 | PARTIAL REPROGRAMMING OF SOLID-STATE NON-VOLATILE MEMORY CELLS - Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state. | 01-22-2015 |
20150023098 | OPERATION METHOD OF MULTI-LEVEL MEMORY - An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level. | 01-22-2015 |
20150023099 | DIRECT MULTI-LEVEL CELL PROGRAMMING - A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage. | 01-22-2015 |
20150029789 | NONVOLATILE MEMORY DEVICE INCLUDING MEMORY CELL ARRAY WITH UPPER AND LOWER WORD LINE GROUPS - A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group. | 01-29-2015 |
20150036426 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAM VERIFYING THE SAME - A program method of a three-dimensional nonvolatile memory device is provided which includes executing at least one program loop including an operation of programming selected memory cells of a selected string turned on by a selected string selection transistor and an operation of verifying whether programming of the memory cells is passed; and applying a negative counter voltage to a selected word line connected to the selected memory cells of the selected string at least once during an interval of the verify operation where there are turned on string selection transistors of unselected strings connected through the same bit line as that of the selected string. | 02-05-2015 |
20150036427 | INCREMENTALLY PROGRAMMABLE NON-VOLATILE MEMORY - An array of programmable non-volatile devices, such as a nominal OTP cell, is adapted such that a V | 02-05-2015 |
20150036428 | METHOD OF OPERATING INCREMENTALLY PROGRAMMABLE NON-VOLATILE MEMORY - An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a V | 02-05-2015 |
20150043275 | MULTI-PULSE PROGRAMMING FOR MEMORY - Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed. | 02-12-2015 |
20150043276 | SYSTEMS AND METHODS OF STORING DATA - A method includes, when using a binary cache in an multi-level cell (MLC) flash memory splitting a codeword corresponding to a data page into multiple data pages and storing the multiple data pages into multiple single level cell (SLC) pages of the binary cache for subsequent storage into a single wordline of the MLC flash memory. | 02-12-2015 |
20150049545 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF PROGRAMMING SAME - A method of programming a nonvolatile memory device comprises performing an N-th program loop based on state data stored in data latches according to a default state ordering, determining whether conversion of the default state ordering is required according to a predetermined criterion, as a consequence of determining that conversion of the default state ordering is required, converting all or part of the state data stored in the data latches from the default state ordering to another state ordering, and performing a (N+1)th program loop based on the converted state data. | 02-19-2015 |
20150070986 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array configured having NAND strings arranged therein; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to apply a verify voltage to a selected word line, apply a read pass voltage that renders conductive an unselected memory cell regardless of cell data to an unselected word line, and apply a bit line voltage of a certain value to a selected bit line, thereby executing a write verify operation that determines whether a selected memory cell has a desired threshold voltage or not. The control circuit is configured capable of changing a voltage value of the bit line voltage based on a position of the selected word line among the plurality of word lines relative to the NAND string. | 03-12-2015 |
20150070987 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method of a semiconductor memory device includes, in an n-th program loop, applying a first program pulse to a first memory cell group, applying a second program pulse to a second memory cell group, and determining first fast cells and first slow cells in the first memory cell group, and in an n+1-th program loop, applying a third program pulse, which is increased by a step voltage from the first program pulse, to the first fast cells in the first memory cell group, and applying a fourth program pulse, which is increased by the step voltage from the second program pulse, to the first slow cells in the first memory cell group and the second memory cell group. | 03-12-2015 |
20150070988 | SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND OPERATING METHOD THEREOF - There are a semiconductor device including: a plurality of memory blocks including a plurality of pages; peripheral circuits configured to perform a least significant bit read operation and a most significant bit read operation of a selected page included in a selected block; and a control circuit including a least significant bit read-retry table and a most significant bit read-retry table which have a plurality of indexes, and configured to control the peripheral circuits to store an index used when error correction is possible among the least significant bit read-retry table in the least significant bit read operation and perform the most significant bit read operation by first selecting the stored index among the most significant bit read-retry table. | 03-12-2015 |
20150070989 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation. | 03-12-2015 |
20150078078 | APPARATUS AND METHOD OF STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150078079 | APPARATUS AND METHOD OF STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150078080 | NAND ARRAY HIARCHICAL BL STRUCTURES FOR MULTIPLE-WL AND ALL-BL SIMULTANEOUS ERASE, ERASE-VERIFY, PROGRAM, PROGRAM-VERIFY, AND READ OPERATIONS - Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1(top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred V | 03-19-2015 |
20150078081 | Trimmable Reference Generator For Sense Amplifier - A trimmable current reference generator for use in a sense amplifier is disclosed | 03-19-2015 |
20150078082 | Non-volatile Memory Device With Current Injection Sensing Amplifier - A non-volatile memory device with a current injection sensing amplifier is disclosed. | 03-19-2015 |
20150078083 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a write control unit that performs a first write operation with respect to a first threshold distribution, a first verify operation on the first threshold distribution, and a second write operation on the basis of a result of the first verify operation, and then starts a third write operation with respect to a second threshold distribution. | 03-19-2015 |
20150078084 | GENERATING READ THRESHOLDS USING GRADIENT DESCENT AND WITHOUT SIDE INFORMATION - A first bit position of a cell in solid state storage is read where a sorting bit is obtained using the read of the first bit position. A second bit position of the cell is read for a first time, including by setting a first read threshold associated with the second bit position to a first value and setting a second read threshold associated with the second bit position to a second value. The second bit position of the cell is read for a second time, including by setting the first read threshold to a third value and setting the second read threshold to a fourth value. A new value for the first read threshold and for the second read threshold is generated using the sorting bit, the first read, and the second read. | 03-19-2015 |
20150085571 | UPDATING READ VOLTAGES - A data storage device includes a controller that is configured to determine a first read voltage for a first page of a non-volatile memory (e.g., a lower page of a Multi-Level Cell flash memory device). The controller is also configured to determine a second read voltage for a second page (e.g., an upper page) of the non-volatile memory by applying an offset value to the first read voltage. The controller is also configured to store data identifying the first read voltage and the second read voltage. | 03-26-2015 |
20150085572 | STORAGE OF READ THRESHOLDS FOR NAND FLASH STORAGE USING LINEAR APPROXIMATION - A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. The slope and the y intercept are stored with a block identifier associated with the block. | 03-26-2015 |
20150085573 | UPDATING READ VOLTAGES - A method performed at a data storage device includes adjusting a first read voltage and a second read voltage to form sets of read voltages. First representations of data are read from a logical page in the non-volatile memory according to the sets of read voltages. The first representations of the data correspond to multiple values of the first read voltage and the second read voltage. The first representations of the data are stored in a memory and second representations of the data are generated based on the first representations. A value of the first read voltage is selected based on syndrome weights corresponding to the second representations. | 03-26-2015 |
20150092487 | Solving MLC NAND paired page program using reduced spatial redundancy - Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring the data, using less than a full back up storage. | 04-02-2015 |
20150092488 | FLASH MEMORY SYSTEM ENDURANCE IMPROVEMENT USING TEMPERATURE BASED NAND SETTINGS - Methods and apparatus to improve flash memory system endurance using temperature based flash memory settings are described. In one embodiment, memory controller logic applies one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device. Other embodiments are also disclosed and claimed. | 04-02-2015 |
20150092489 | FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POINTS OF CELL VOLTAGE DISTRIBUTIONS USING HISTOGRAMS - Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations. | 04-02-2015 |
20150103595 | BIT LINE AND COMPARE VOLTAGE MODULATION FOR SENSING NONVOLATILE STORAGE ELEMENTS - In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed. | 04-16-2015 |
20150103596 | CODING METHOD AND DECODING METHOD IN MEMORY SYSTEM - Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern. | 04-16-2015 |
20150103597 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY SYSTEM - An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions. | 04-16-2015 |
20150109859 | ELECTRONIC DEVICE WITH SOLID STATE DRIVE AND ASSOCIATED CONTROL METHOD - An electronic device with a solid state drive and associated control method are provided. The electronic device includes: a host; a power supply component, for providing electric power to the host and the solid state drive; and the solid state drive including a control unit electrically connected to the host through a bus, a cache memory electrically connected to the control component, and a flash memory electrically connected to the control component. When a remaining power of the power supply component decreases to a threshold value, the host controls the solid state drive to enter a data secure mode and disables the cache memory; and when the remaining power of the power supply component is above the threshold value, the host controls the solid state drive to enter a high performance mode and enables the cache memory. | 04-23-2015 |
20150117098 | POWER DROP PROTECTION FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory. A method includes programming a first page at a word line of the non-volatile memory. While programming a second page at the word line, first storage elements of the word line are selectively programmed in response to a power drop at the data storage device to increase a state separation that separates data values of the first page. | 04-30-2015 |
20150117099 | Selection of Data for Redundancy Calculation By Likely Error Rate - Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low. | 04-30-2015 |
20150117100 | STORAGE DEVICE AND RELATED PROGRAMMING METHOD - A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through a dummy pattern program operation, and thereafter performing a continuous writing operation on the memory block. | 04-30-2015 |
20150124525 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device comprises a memory cell array comprising memory cells coupled to word lines and bit lines, a voltage generator suitable for generating a drive voltage to be applied to a selected word line, and a control logic suitable for detecting the number of pulses of a program voltage received from the memory cell array in a program operation, storing bias information corresponding to the detected number of pulses in a register, and controlling a level of the program voltage for a subsequent program operation based on the bias information. | 05-07-2015 |
20150124526 | NONVOLATILE MEMORY DEVICE, SYSTEM AND PROGRAMMING METHOD WITH DYNAMIC VERIFICATION MODE SELECTION - Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition. | 05-07-2015 |
20150131374 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - The present invention relates to a semiconductor device, including memory blocks suitable for storing data, peripheral circuits suitable for refreshing the memory blocks, and a control circuit suitable for controlling the peripheral circuits to change data stored in a first memory block among the memory blocks and refresh the first memory block with changed data, and an operating method thereof. | 05-14-2015 |
20150131375 | METHOD OF DRIVING NONVOLATILE MEMORY DEVICES - A method of driving a nonvolatile memory device, includes; forward shifting threshold voltages of nonvolatile memory cells by executing a first program loop with respect to the nonvolatile memory cells, and thereafter, reverse shifting the threshold voltages of the nonvolatile memory cells, and again forward shifting the threshold voltages of the nonvolatile memory cells by executing a second program loop with respect to the nonvolatile memory cells. | 05-14-2015 |
20150131376 | THRESHOLD ESTIMATION USING BIT FLIP COUNTS AND MINIMUMS - A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on the group of solid state storage cells at a second threshold that corresponds to an upper bound for the given bin. A minimum is determined using the bit flip counts corresponding to the plurality of bins and the minimum is used to estimate an optimal threshold. | 05-14-2015 |
20150146484 | MEMORY SYSTEM INCLUDING MULTI-LEVEL MEMORY CELLS AND PROGRAMMING METHOD USING DIFFERENT PROGRAM START VOLTAGES - A method of programming multi-level memory cells includes defining a first program start voltage and a second program start voltage higher than the first program start voltage, programming first memory cells among the MLC to the first program state using a program operation that begins programming of the first memory cells at the first program start voltage, and programming second memory cells among the MLC to the second program state using a program operation that begins programming of the second memory cells at the second program start voltage. | 05-28-2015 |
20150146485 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected level of the program voltage. | 05-28-2015 |
20150294723 | NONVOLATILE MEMORY SYSTEM, METHOD OF OPERATING THE SAME AND METHOD OF MANUFACTURING THE SAME - An operating method of a nonvolatile memory system including first and second. areas is provided. Data stored in the first area is migrated to the second area when a first booting operation is performed. The data stored in the second area is reprogrammed. The first booting operation is a booting operation performed when the nonvolatile memory system is first powered on after mounted on a printed circuit board. The reprogramming is a program operation performed on the data stored in the second area without performing an erasing operation on the data stored in the second area. | 10-15-2015 |
20150302920 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell. | 10-22-2015 |
20150303922 | HIGH VOLTAGE SWITCH CIRCUIT AND NONVOLATILE MEMORY INCLUDING THE SAME - A high voltage switch circuit includes a high voltage switch suitable for transferring a voltage of an input terminal to an output terminal in response to a voltage of a control node; a first transistor suitable for electrically connecting a first node and the control node in response to an inverted activation signal; a second transistor suitable for supplying a first high voltage to the first node in response to an activation signal; a third transistor connected in parallel to the second transistor, and operable in response to the control node; a discharge transistor suitable for discharging the control node; and a first level shifter suitable for changing a swing level of a preliminary activation signal, and generating the activation signal and the inverted activation signal. | 10-22-2015 |
20150310905 | Field Effect Transistor Constructions And Methods Of Programming Field Effect Transistors To One Of At Least Three Different Programmed States - A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed. | 10-29-2015 |
20150318037 | SNR ESTIMATION IN ANALOG MEMORY CELLS - A method includes programming a group of analog memory cells by writing respective analog values into the memory cells in the group. After programming the group, the analog values are read from the memory cells in the group using a set of read thresholds so as to produce readout results. Respective optimal positions for the read thresholds in the set are identified based on the readout results. A noise level in the readout results is estimated based on the identified optimal positions of the read thresholds. | 11-05-2015 |
20150332758 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to an embodiment, a controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines. | 11-19-2015 |
20150332759 | Systems and Methods for Lower Page Writes - In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order. | 11-19-2015 |
20150340086 | THRESHOLD VOLTAGE ANALYSIS - Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells. | 11-26-2015 |
20150340100 | FLASH COMMAND THAT REPORTS A COUNT OF CELL PROGRAM FAILURES - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units. The memory units may each have a size less than a total size of the memory. The memory units may include a plurality of cells. The controller may be configured to issue a plurality of program operations to write to one or more of the cells. The controller may be configured to implement a polling status command after each of the program operations to verify programming of each of the cells. A response to each of the polling status commands may be used to report a number of the cells that failed to be programmed. | 11-26-2015 |
20150340369 | 3D INDEPENDENT DOUBLE GATE FLASH MEMORY - A memory device configurable for independent double gate cells, storing multiple bits per cell includes multilayer stacks of conductive strips configured as word lines. Active pillars are disposed between pairs of first and second stacks, each active pillar comprising a vertical channel structure, a charge storage layer and an insulating layer. The insulating layer in a frustum of an active pillar contacts a first arcuate edge of a first conductive strip in a layer of the first stack and a second arcuate edge of a second conductive strip in a same layer of the second stack. A plurality of insulating columns serve, with the active pillars, to divide the stacks of word lines into even and odd lines contacting opposing even and odd sides of each active pillar. The active pillar can be generally elliptical with a major axis parallel with the first and second conductive strips. | 11-26-2015 |
20150348617 | HIGHLY COMPACT NON-VOLATILE MEMORY AND METHOD THEREOF - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness. | 12-03-2015 |
20150348618 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 12-03-2015 |
20150348620 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell. | 12-03-2015 |
20150348621 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD THEREOF - This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of NAND cell units arranged therein, each of the NAND cell units being configured having a plurality of memory cells connected in series therein. A bit line is connected to one end of the NAND cell unit, and a source line is connected to the other end of the NAND cell unit. A sense amplifier circuit is connected to the bit line. The sense amplifier circuit comprises: a first switch circuit connected between a power supply voltage terminal and a sense node; a sense amplifier connected to the sense node; and a latch circuit that latches a signal outputted from the sense amplifier. The first switch circuit is configured to switch to a non-conductive state according to data latched by the latch circuit. | 12-03-2015 |
20150348642 | Storage Device and Method for Performing a Self-Refresh Operation - A storage device and method for performing a self-refresh operation are disclosed. In one embodiment, a storage device determines that the self-refresh operation needs to be performed. In response to that determination, the storage device performs the self-refresh operation by reading data from the memory and writing the data back to the memory without transferring the data outside of the storage device. | 12-03-2015 |
20150357040 | NONVOLATILE MEMORY AND DATA WRITING METHOD - According to one embodiment, a nonvolatile memory includes a memory cell array having a plurality of memory cells configured to store 3-bit data corresponding to first to third pages. Data coding, in which first page data values have one boundary, and second and three page data values each have three boundaries, is used to perform a first stage program based on data written into first page d, a second stage program based on data written into the first, second, and third pages, and a third stage program based on data written into the first, second, and third pages. | 12-10-2015 |
20150357041 | MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND COMPUTING SYSTEM INCLUDING THE SAME - Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device. | 12-10-2015 |
20150364185 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor device includes performing a program operation on selected memory cells of a selected page, and selectively performing a soft erase operation on memory cells having threshold voltages greater than a reference voltage, among the selected memory cells, to reduce a width of a threshold voltage distribution of the selected memory cells. | 12-17-2015 |
20150364201 | SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER - A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line. | 12-17-2015 |
20150371703 | MEMORY CELLS USING MULTI-PASS PROGRAMMING - A method is provided for programming non-volatile memory cells. The non-volatile memory cells are accessible by a plurality of word lines. The method includes using a four-pass programming technique to program a block of the non-volatile memory cells. | 12-24-2015 |
20150380083 | Dynamic cell state resolution - A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump. | 12-31-2015 |
20150380097 | MEMORY SYSTEM - A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines. | 12-31-2015 |
20160005459 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not. The control circuit is configured to, in the read operation, be capable of executing the read operation targeting the memory cell transistors connected to a portion of the plurality of bit lines, and not execute a charging operation in those other of the bit lines where the connected memory cell transistors are not targeted by the read operation. | 01-07-2016 |
20160005460 | SOFT INFORMATION MODULE - A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value. | 01-07-2016 |
20160005481 | MEMORY PAGE BUFFER - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 01-07-2016 |
20160005762 | MULTIPLE-BIT-PER-CELL, INDEPENDENT DOUBLE GATE, VERTICAL CHANNEL MEMORY HAVING SPLIT CHANNEL - A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip. | 01-07-2016 |
20160012883 | Management of Data Storage in Memory Cells Using a Non-Integer Number of Bits Per Cell | 01-14-2016 |
20160012895 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF OPERATING THE SAME | 01-14-2016 |
20160012907 | NONVOLATILE MEMORY DEVICE COMPRISING PAGE BUFFER AND OPERATION METHOD THEREOF | 01-14-2016 |
20160019947 | Multiple Pass Programming For Memory With Different Program Pulse Widths - Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. After completion of a full programming pass, a verify test is performed to identify cells for which reprogramming is warranted. The reprogramming can include multiple program-verify iterations which use longer program pulses than in the full programming pass. Moreover, the number of program-verify iterations is limited to reduce the reprogramming time. In one approach, cells of all target data states are programmed together. In another approach, cells of different target data states are programmed separately. | 01-21-2016 |
20160019948 | Reprogramming Memory With Single Program Pulse Per Data State - Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a | 01-21-2016 |
20160019950 | AUTO LOW CURRENT PROGRAMMING METHOD WITHOUT VERIFY - A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level. | 01-21-2016 |
20160019966 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line. | 01-21-2016 |
20160019974 | MEMORY REFRESH METHODS AND APPARATUSES - Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed. | 01-21-2016 |
20160027504 | YUKAI VSL-BASED Vt-COMPENSATION FOR NAND MEMORY - A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch-based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common V | 01-28-2016 |
20160042800 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k−1 levels (k≦n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing. | 02-11-2016 |
20160042801 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 02-11-2016 |
20160042803 | METHOD OF PROGRAMMING MEMORY DEVICE - A method of programming a memory device includes programming a low bit to a memory cell included in a word line and a bit line based on a first verification condition, the low bit belonging to a group of bits including a high bit. The first verification condition is based on at least one of a first bit line current, a first develop time for verifying the programming of the low bit, and a first word line voltage. The method includes programming the high bit to the memory cell based on a second verification condition. The second verification condition is based on at least one of a second bit line current, a second develop time for verifying the programming of the high bit, and a second word line voltage. | 02-11-2016 |
20160049192 | VSL-BASED VT-COMPENSATION AND ANALOG PROGRAM SCHEME FOR NAND ARRAY WITHOUT CSL - A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual V | 02-18-2016 |
20160055910 | Storage Module and Method for Using Healing Effects of a Quarantine Process - A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge. | 02-25-2016 |
20160064071 | SOLID STATE DRIVE WITH HYBRID STORAGE MODE - A solid state drive (SSD) with a hybrid storage mode includes a flash memory, and a data processing module in information communication with the flash memory. The flash memory includes a first storage sector that stores data by a first potential storage mode, and a second storage sector that stores data by a second potential storage mode. The first storage sector corresponds to physical block addresses P | 03-03-2016 |
20160064094 | NONCONSECUTIVE SENSING OF MULTILEVEL MEMORY CELLS - Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC. | 03-03-2016 |
20160071580 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device comprises: a memory cell array comprising memory cells, each memory cell being able to store multi-bit data; word-lines connected to the memory cells, the word-lines being arranged in a first direction; bit-lines arranged in a second direction crossing the first direction, the bit-lines reading data from the memory cell array; and a control circuit controlling the operation of the memory cell array. The control circuit performs a first write operation of applying a first write voltage between a selected word-line and a channel of a selected memory cell, then performs a verify operation of determining whether the first write operation is completed, and performs a second write operation of applying, if the write operation to the first threshold voltage is completed in the verify operation, a second write voltage lower than the first write voltage between the selected word-line and the channel. | 03-10-2016 |
20160071581 | NONVOLATILE MEMORY AND PROGRAMMING METHOD OF SAME - In a program operation a plurality of memory cells are programmed depending on data stored in first and second data latches. Verification read operations are performed for the plurality of memory cells using different verification voltages respectively corresponding to different program states and collecting verification read results of the verification read operations. The first data latches and the second data latches are updated depending on the collected verification read results. | 03-10-2016 |
20160071602 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 03-10-2016 |
20160071603 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, in a data write, determining at least one of: a first requirement that the number of times of a data read on first through n1-th pages (where n | 03-10-2016 |
20160071604 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first component including a controller which issues an instruction complying with a NAND interface; and a second component including a first NAND flash memory which is controlled by the instruction, the second component being removable from the first component. | 03-10-2016 |
20160078928 | NAND ARRAY HIARCHICAL BL STRUCTURES FOR MULTIPLE-WL AND ALL-BL SIMULTANEOUS ERASE, ERASE-VERIFY, PROGRAM, PROGRAM-VERIFY, AND READ OPERATIONS - Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1 (top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred V | 03-17-2016 |
20160078929 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, a sense amplifier electrically connected to the bit line, and a controller configured to perform a read operation including first and second read operations on the memory cell. During the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line. | 03-17-2016 |
20160093371 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing memory access includes: performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages to generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value and the second digital value to obtain soft information of a bit stored in the Flash cell; and using the soft information to perform soft decoding. | 03-31-2016 |
20160099047 | MULTI-TASK CONCURRENT/PIPELINE NAND OPERATIONS ON ALL PLANES - This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements. | 04-07-2016 |
20160099048 | THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION - Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current. | 04-07-2016 |
20160099065 | LATCH INITIALIZATION FOR A DATA STORAGE DEVICE - A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write operation to write information to the memory. The method may further include loading a set of bits into the latch prior to receiving the information at the memory die. The set of bits includes at least a first bit having a first value and a second bit having a second value that is different than the first value. The method further includes receiving the information at the memory die and overwriting at least a portion of the set of bits at the latch with the information. | 04-07-2016 |
20160104526 | DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS - The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells. | 04-14-2016 |
20160111147 | Non-Volatile Semiconductor Memory Adapted to Store a Multi-Valued Data in a Single Memory Cell - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 04-21-2016 |
20160111148 | READING A MULTI-BIT VALUE FROM A MEMORY CELL - Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing. | 04-21-2016 |
20160111162 | NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ - This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1/10- 1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed. | 04-21-2016 |
20160118109 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell string including dummy memory cells and a plurality of memory cells in which n bit data is stored, and a peripherial circuit configured to store the n bit data in first memory cells, among the memory cells, store n−1 bit data in the rest of second memory cells, and store data which is not stored in the second memory cells in at least one of the dummy memory cells, among the dummy memory cells. | 04-28-2016 |
20160118110 | Simultaneous Multi-Page Commands for Non-Volatile Memories - Mechanisms are provided, in a non-volatile memory device comprising a non-volatile memory and a memory controller, for controlling an operation of the non-volatile memory device. The non-volatile memory device receives a single combined memory command for accessing the non-volatile memory. The non-volatile memory device decodes the row address and the column address for the word-line to be accessed by the single combined memory command. The non-volatile memory device accesses the word-line such that at least a most significant bit (MSB) page and a least significant bit (LSB) page are accessed simultaneously. | 04-28-2016 |
20160118111 | REDUCED LEVEL CELL MODE FOR NON-VOLATILE MEMORY - Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values. | 04-28-2016 |
20160118135 | TWO-STROBE SENSING FOR NONVOLATILE STORAGE - A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements. | 04-28-2016 |
20160118136 | ERROR DETECTION METHOD - Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect. | 04-28-2016 |
20160125935 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device and a method of operating the same are provided. The method includes performing a program operation on a memory cell so that a threshold voltage of the memory cell is greater than a main verifying voltage, and while the program operation is performed, a bit line voltage applied to a bit line connected to the memory cell gradually increases based on the threshold voltage of the memory cell and the number of times a program voltage is applied to a word line connected to the memory cell. | 05-05-2016 |
20160133318 | HIGH-SPEED READABLE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell. | 05-12-2016 |
20160133333 | OPTIMAL READ THRESHOLD ESTIMATION - An optimal read threshold estimation method includes determining a flip difference corresponding to an optimal step size Δ | 05-12-2016 |
20160141024 | NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ - This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal | 05-19-2016 |
20160141025 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data. | 05-19-2016 |
20160141026 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a memory device including memory blocks, each of the memory blocks including pages, each of the pages including memory cells that are electrically coupled to word lines, wherein the memory cells store data that is requested from a host; and a controller suitable for reading first data corresponding to a read command received from the host, from a page of a first memory block among the memory blocks, storing the first data in a buffer, providing the first data stored in the buffer, to the host, and writing and storing the first data stored in the buffer, in a page of a second memory block among the memory blocks. | 05-19-2016 |
20160148677 | METHOD FOR WRITING DATA INTO FLASH MEMORY AND RELATED CONTROL APPARATUS - A method for writing data into a flash memory, wherein the flash memory includes a plurality multi-level cells, and each of the plurality of multi-level cells is capable of storing a plurality of bits. The method includes: storing a first bit into each of the plurality of multi-level cells respectively; determining if each of the plurality of multi-level cells stores the first bit respectively; and when each of the plurality of multi-level cells stores the first bit respectively, storing a second bit into each of the plurality of multi-level cells respectively. | 05-26-2016 |
20160148694 | VARIANT OPERATION SEQUENCES FOR MULTIBIT MEMORY - A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode. | 05-26-2016 |
20160148695 | DATA STORAGE DEVICE AND METHOD OF PROGRAMMING MEMORY CELLS - A method of programming a non-volatile memory device includes programming memory cells selected from the plurality of memory cells by increasing turn values of program loops based on an incremental step pulse program (ISPP) algorithm; detecting a first turn value of a first program loop wherein, in the first program loop, a first number or a first ratio of first unprogrammed memory cells is smaller than or equal to a first set value; calculating a second turn value of a second program loop based on the first turn value wherein, in the second program loop, a second number or a second ratio of second unprogrammed memory cells is expected to be smaller than or equal to a second set value, the second set value being smaller than the first set value; executing subsequent program loops on the unprogrammed memory cells up to the second program loop; detecting a third number or a third ratio of third unprogrammed memory cells in the second program loop; comparing the third number or the third ratio of the third unprogrammed memory cells to the second set value; determining a program pass when the third number or the third ratio of the third unprogrammed memory cells is smaller than or equal to the second set value; and determining a program fail when the third number or the third ratio of the unprogrammed memory cell exceeds the second set value. | 05-26-2016 |
20160155494 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME | 06-02-2016 |
20160155495 | MEMORY SYSTEM AND METHOD FOR PROCESSING DATA IN MEMORY | 06-02-2016 |
20160155496 | LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM | 06-02-2016 |
20160155497 | LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY | 06-02-2016 |
20160155512 | INTERNAL POWER SUPPLY VOLTAGE AUXILIARY CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE | 06-02-2016 |
20160163382 | Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization - A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements. | 06-09-2016 |
20160163392 | DATA RETENTION FLAGS IN SOLID-STATE DRIVES - Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory. | 06-09-2016 |
20160172041 | SEQUENTIAL WRITE AND SEQUENTIAL WRITE VERIFY IN MEMORY DEVICE | 06-16-2016 |
20160172051 | TEMPERATURE COMPENSATION MANAGEMENT IN SOLID-STATE MEMORY | 06-16-2016 |
20160180927 | METHOD FOR INCREASING SPEED OF WRITING DATA INTO FLASH MEMORY UNIT AND ASSOCIATED DEVICE | 06-23-2016 |
20160180938 | MEMORY SYSTEM | 06-23-2016 |
20160180945 | EFFICIENT SCANNING OF NONVOLATILE MEMORY BLOCKS | 06-23-2016 |
20160189770 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, and first and second bit lines. The first and second bit lines are electrically connected to one ends of the first and second memory cells, respectively. In retry reading, a voltage applied to the first bit line is different from a voltage applied to the second bit line | 06-30-2016 |
20160189786 | METHODS AND APPARATUS FOR REDUCING READ TIME FOR NONVOLATILE MEMORY DEVICES - A method for operating non-volatile memory device is provided. The method includes applying a first voltage level to a word line connected to a memory cell, applying a second voltage level to the word line for a first time period, performing a read operation on the memory cell during the first time period, and discharging the word line for a second time period to a third voltage level greater than or equal to about 1V. The method also includes performing an erase word line recovery on a plurality of blocks of memory cells during the erase operation, and prior to an erase phase. The erase word line recovery substantially discharges all word lines of the plurality of blocks of memory cells. | 06-30-2016 |
20160196872 | SEMICONDUCTOR STORAGE DEVICE | 07-07-2016 |
20160254047 | PROGRAM VERIFY FOR NON-VOLATILE STORAGE | 09-01-2016 |
20170236590 | SYSTEM AND METHOD FOR MEMORY INTEGRATED CIRCUIT CHIP WRITE ABORT INDICATION | 08-17-2017 |
20180025782 | SYSTEMS AND METHODS FOR PROGRAMMING DATA TO STORAGE DEVICES | 01-25-2018 |
20190147963 | MEMORY READ APPARATUS AND METHODS | 05-16-2019 |