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FLOATING GATE

Subclass of:

365 - Static information storage and retrieval

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
365185180 Particular biasing 1918
365185050 Particular connection 1142
365185030 Multiple values (e.g., analog) 718
365185020 Disturbance control 96
365185040 Data security 11
Entries
DocumentTitleDate
20080259682SEMICONDUCTOR DEVICE - A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region. During a reading data operation, a first bit line of the memory cell is connected to the first semiconductor region of the element for reading data via the selection field effect transistor.10-23-2008
20110013449SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.01-20-2011
20090237990SONOS DEVICE WITH INSULATING STORAGE LAYER AND P-N JUNCTION ISOLATION - The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film thickness of a first silicon nitride film in the first ONO film is larger than the film thickness of a second silicon nitride film in the second ONO film.09-24-2009
20080316810MEMORY UNIT - A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory.12-25-2008
20090279355LOW POWER FLOATING BODY MEMORY CELL BASED ON LOW BANDGAP MATERIAL QUANTUM WELL - Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.11-12-2009
20110199819APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY - A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.08-18-2011
20090052238SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.02-26-2009
20090097310MEMORY CELL STORAGE NODE LENGTH - Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage node is less than a length of the channel. The embodiment further includes a memory cell with a gate separated from the storage node by a second dielectric, wherein a length of the gate is greater than a length of the storage node.04-16-2009
20090251960HIGH TEMPERATURE MEMORY DEVICE - Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on insulator substrate or a large bandgap semiconductor substrate having multiple ferroelectric or magnetic memory cells disposed on it. In yet other embodiments, a high temperature nonvolatile integrated device comprises a sapphire, silicon on insulator, or a large bandgap substrate having programmable read only memory (PROM) cells or electrically erasable PROM (EEPROM) cells disposed on it.10-08-2009
20120195116NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The method can include forming a second stacked body, removing the second stacked body formed in a region where a first memory unit will be formed, forming a first stacked body, and removing the first stacked body formed in a region where a second memory unit will be formed. The method can include simultaneously processing the first stacked body formed in a region where the first memory unit will be formed and the second stacked body formed in a region where the second memory unit will be formed to form a memory cell of the first memory unit from the first stacked body and form a memory cell of the second memory unit from the second stacked body.08-02-2012
20100097854FLASH MEMORY AND FLASH MEMORY ARRAY - A flash memory including a substrate having a recess, a buried bit line, a word line, a single side insulating layer, a floating gate, a tunneling dielectric layer, a control gate, and an inter-gate dielectric layer is provided. The buried bit line extends below the recess of the substrate along a first direction. The word line is on the substrate, and extends above the recess along a second direction. The single side insulating layer is on a first sidewall of the recess. The floating gate is on a second sidewall of the recess to be opposite to the single side insulating layer. The tunneling dielectric layer is sandwiched by the floating gate and the substrate to contact the buried bit line. The control gate fills the recess and contacts the word line. The inter-gate dielectric layer is sandwiched by the control gate and the floating gate.04-22-2010
20080205133Capacitor-less volatile memory cell, device, system and method of making same - A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.08-28-2008
20110255334FLASH MEMORY HAVING MULTI-LEVEL ARCHITECTURE - Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.10-20-2011
20100157668Memory device and method of operating and fabricating the same - A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.06-24-2010
20110216585METAL CONTAINING MATERIALS - Metal containing materials and methods of forming the same are disclosed. One such method includes substantially concurrently feeding a flow of precursor gas containing a metal of a metal containing material and a flow of source gas containing a reducing agent so that the precursor gas and the source gas react to form a thickness of the metal containing material. The flow of precursor gas is discontinued, and while the flow of precursor gas is discontinued, the flow of source gas continues to be fed to contact the thickness of the metal containing material.09-08-2011
20100142266VERTICAL FIELD-EFFECT TRANSISTOR - A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.06-10-2010
20120230102FLASH MEMORY STORAGE APPARATUS - A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host.09-13-2012
20110255335CHARGE TRAP MEMORY HAVING LIMITED CHARGE DIFFUSION - Subject matter disclosed herein relates to flash memory, and more particularly to a charge trap memory and a process flow to form same.10-20-2011
20120092926THREE DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three dimensional non-volatile memory structure according to an aspect of this disclosure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.04-19-2012

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