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Having semiconductive device

Subclass of:

361 - Electricity: electrical systems and devices

361600000 - HOUSING OR MOUNTING ASSEMBLIES WITH DIVERSE ELECTRICAL COMPONENTS

361679000 - For electronic systems and devices

361748000 - Printed circuit board

361760000 - Connection of components to board

Patent class list (only not empty are listed)

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Entries
DocumentTitleDate
20130044450MOTHERBOARD ASSEMBLY HAVING SERIAL ADVANCED TECHNOLOGY ATTACHMENT DUAL IN-LINE MEMORY MODULE - A motherboard assembly includes a motherboard and a serial advanced technology attachment dual-in-line memory module (SATA DIMM) module with a circuit board. The motherboard includes an expansion slot and a storage device interface. An edge connector is set on a bottom edge of the circuit board to be detachably engaged in the expansion slot, and a notch is set on a bottom edge of the circuit board to engage in a protrusion of the expansion slot. A SATA connector of the circuit board is connected to the storage device interface of the motherboard.02-21-2013
20110205721RESIN COMPOSITION, RESIN SHEET, PREPREG, LAMINATE, MULTILAYER PRINTED WIRING BOARD, AND SEMICONDUCTOR DEVICE - Disclosed is a resin composition having a low thermal expansion coefficient and a high glass transition temperature used for the insulating layer of a multilayer printed wiring board, capable of forming an insulating layer having fine roughened shapes and imparting sufficient plating peel strength. Also disclosed are a resin sheet, a prepreg, a laminate, a multilayer printed wiring board and a semiconductor device, all of which comprising the resin composition. The resin composition is a resin composition comprising (A) an epoxy resin, (B) a cyanate ester resin, (C) an aromatic polyamide resin containing at least one hydroxyl group and (D) an inorganic filler, as essential components.08-25-2011
20090196002PRINTED WIRING BOARD UNIT - A printed wiring board unit includes an electronic circuit component, a printed wiring board, a plurality of first conductive terminals disposed between the electronic circuit component and the printed wiring board, at least one of the first conductive terminals arranged along a quadrangular outline, and a plurality of second conductive terminals disposed between the electronic circuit component and the printed wiring board, the second conductive terminals arranged at a corner of the quadrangular outline, and the second conductive terminals contacting at least one of the printed wiring board and the electronic circuit component in a relatively displaceable manner.08-06-2009
20100149775Tape circuit substrate with reduced size of base film - A tape circuit substrate includes a base film with first wiring and second wiring disposed on the base film. The first wiring extends into a chip mount portion through a first side and bends within the chip mount portion toward a second side. The second wiring extends into the chip mount portion through a third side and bends within the chip mount portion toward the second side. The first, second, and third sides are different sides of the chip mount portion. Thus, size and in turn cost of the base film are minimized by arranging wirings within the chip mount portion for further miniaturization of electronic devices, such as a display panel assembly, using the tape circuit substrate.06-17-2010
20080259581Circuitized substrates utilizing smooth-sided conductive layers as part thereof - A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.10-23-2008
20130083504ELECTRONIC DEVICE - An electronic device includes: a first plate; a wiring board arranged on the first plate and configured to have a plurality of first terminals on a surface opposite to a surface facing the first plate; an electronic component arranged above the wiring board and configured to have a plurality of second terminals on a surface facing the wiring board; a connecting unit arranged between the wiring board and the electronic component and configured to electrically couple the first terminals and the second terminals; a second plate arranged on the electronic component; a fixing unit arranged in an area outside of an area where the electronic component is placed and configured to pressurize the first plate and the second plate; and a pressing unit arranged below the area where the electronic component is placed and configured to press the wiring board toward the electronic component.04-04-2013
20130077275ELECTRONIC DEVICE, WIRING SUBSTRATE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - Even in an electronic device where electrodes are coupled electrically using a solder, sections to which electrodes of an electronic component are coupled are switched by a method other than changing circuits of the electronic component or changing circuits of a wiring substrate.03-28-2013
20130033840TRANSFER METHOD FOR MANUFACTURING CONDUCTOR STRUCTURES BY MEANS OF NANO-INKS - A method for equipping a film material with at least one electrically conductive conductor structure, wherein a dispersion containing metallic nanoparticles in the form of a conductor structure is applied to a thermostable transfer material and the metallic nanoparticles are sintered to form an electrically conductive conductor structure. The electrically conductive conductor structure of sintered metallic nanoparticles is then transferred from the thermostable transfer material to the non-thermostable film material. A method for producing a laminate material using the film material using at least one electrically conductive conductor structure, and to the corresponding film material and laminate material are described.02-07-2013
20130033839ELECTRIC DEVICE AND PRODUCTION METHOD THEREFOR - An electric device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, an electric wiring provided on the support substrate 12 for electrically connecting an external electrical signal input/output source with the electric circuit 14, a sealing member 16 provided on the support substrate 12 to surround the sealing region, and a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween. the electric circuit 14 includes an electronic element 24 having an organic layer, and a width of the sealing member 16 differs between an intersection region in which the electric wiring 15 and the sealing member 16 intersect each other and a non-intersection region excluding the intersection region.02-07-2013
20100110652ANISOTROPIC CONDUCTIVE ADHESIVE COMPOSITION, ANISOTROPIC CONDUCTIVE FILM, CIRCUIT MEMBER CONNECTING STRUCTURE AND METHOD FOR MANUFACTURING COATED PARTICLES - The anisotropically conductive adhesive composition according to the present invention is an anisotropically conductive adhesive composition to connect a first circuit member where a first circuit electrode is formed on the principal surface of a first substrate and a second circuit member where a second circuit electrode is formed on the principal surface of a second substrate with the first circuit electrode and the second circuit electrode placed opposite, wherein the anisotropically conductive adhesive composition comprises an adhesive and a coated particle where at least part of the surface of a conductive particle is coated with an insulating material containing a polymer electrolyte and an inorganic oxide fine particle.05-06-2010
20090154128WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate 06-18-2009
20090147490SUBSTRATE FOR WIRING, SEMICONDUCTOR DEVICE FOR STACKING USING THE SAME, AND STACKED SEMICONDUCTOR MODULE - In a stacked semiconductor module, a test covering connecting terminals is easily conducted and high reliability is achieved.06-11-2009
20130083503PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE - A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided.04-04-2013
20100328916SEMICONDUCTOR DEVICE - A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device.12-30-2010
20130050968CIRCUIT BOARD WITH HIGHER CURRENT - A circuit board includes a plurality of conductive layers, at least one group of vias, a number of second vias, at least one power supply element, and at least one electronic element. Each conductive layer includes a conductive portion. Both the first vias and the second vias are defined through the conductive layers and electrically connected each conductive layers. The at least one group of first vias surrounds the at least one power supply element. The second vias are arranged along the side of the conductive portion, and positioned between the power supply element and the electronic element. Current from a power supply element flows to the inner conductive layers through the group of surrounding first vias. Current transmission on each conductive layer continuously flows to another conductive layer having a lower resistance through the second vias during transmission.02-28-2013
20130088842PREPREG, METAL-CLAD LAMINATE, PRINTED WIRING BOARD, AND SEMICONDUCTOR DEVICE - A prepreg that yields a semiconductor device which, even when using Cu wire, exhibits excellent reliability under conditions of high temperature and high humidity (heat-resistant and moisture-resistant reliability), a metal-clad laminate and a printed wiring board that use the prepreg, and a semiconductor device that uses the printed wiring board. Specifically disclosed are a prepreg comprising a substrate and a B-staged resin composition comprising (a) a thermosetting resin, (b) a hydrotalcite compound having a specific composition, (c) zinc molybdate, and (d) lanthanum oxide.04-11-2013
20100265683SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip 10-21-2010
20100097775Electronic control device - In an electronic control device, an electrically-conductive adhesive is arranged on an outer edge portion of a first surface of a circuit board as a stress reducing portion for reducing stress of the circuit board received by a molding resin. An elastic modulus of the electrically-conductive adhesive is lower than that of the circuit board. The electrically-conductive adhesive is covered by an adhesion improving member. When peeling stress is applied to the circuit board from the molding resin, the electrically-conductive adhesive and the adhesion improving member receive the peeling stress to be deformed. Therefore, the peeling stress to the circuit board is reduced.04-22-2010
20130058062METHOD FOR MANUFACTURING BASE MATERIAL HAVING GOLD-PLATED METAL FINE PATTERN, BASE MATERIAL HAVING GOLD-PLATED METAL FINE PATTERN, PRINTED WIRING BOARD, INTERPOSER, AND SEMICONDUCTOR DEVICE - A method for manufacturing a base material having a gold-plated metal fine pattern is disclosed, comprising the steps of preparing a base material having a supporting surface made of a resin; forming a primer resin layer having surface roughness of 0.5 μm or less on the supporting surface, and forming a metal fine pattern thereon by an SAP process to obtain a base material having a metal fine pattern; and applying a gold-plating treatment to at least one part of a surface of the metal fine pattern; wherein the base material having a metal fine pattern is subjected to a palladium removal treatment in an optional stage before carrying out the gold-plating treatment.03-07-2013
20120224346ARRANGEMENT WITH CHIP AND CARRIER - An apparatus includes chip and a carrier of the chip. A ridge is positioned between the chip and the carrier. The ridge is adapted to increase thermal contact between the chip and the carrier. The chip is attached to a contact surface on the carrier by an adhesive member.09-06-2012
20090244869Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring - A semiconductor device has a wiring board having a wiring, a semiconductor chip that is mounted on the wiring board, and an electric conductor reference plane provided in the inside of the wiring board, in which in top view. The wiring includes a first region that overlaps the electric conductor reference plane and a second region that is the whole region except for the first region. A conductor chip is mounted above the second region.10-01-2009
20120236524STACKED INTEGRATED COMPONENT DEVICES WITH ENERGIZATION - This invention discloses a device comprising multiple functional layers formed on substrates, wherein at least one functional layer comprises an electrical energy source. In some embodiments, the present invention includes a component for incorporation into ophthalmic lenses that has been formed by the stacking of multiple functionalized layers.09-20-2012
20120170241PRINTING INK, METAL NANOPARTICLES USED IN THE SAME, WIRING, CIRCUIT BOARD, AND SEMICONDUCTOR PACKAGE - Disclosed is a printing ink comprising Cu- and/or CuO-containing metal nanoparticles, which obtains excellent dispersion properties and successive dispersion stability without using additives such as dispersing agents. Specifically disclosed is a printing ink that comprises Cu- and/or CuO-containing metal nanoparticles and has no more than 2,600 ppm of ionic impurities in the total solid content. The printing ink is obtained by dispersing the Cu- and/or CuO-containing metal nanoparticles, which have no more than 2,600 ppm of ionic impurities in the total solid content, in a dispersion medium.07-05-2012
20100202125SEMICONDUCTOR MODULE - A top panel, which is disposed to face a module board with an electronic component therebetween, includes a resin layer and a metal layer, and has an insulating characteristic. The metal layer includes a metal layer formed at a front side of the resin layer and a metal layer formed at a rear side of the resin layer. With this structure, in reflow soldering performed in mounting a semiconductor module on a main board, warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the front side of the resin layer is cancelled by warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the rear side of the resin layer, whereby warp of the top panel is eliminated. This helps prevent the electronic component adhered to the top panel with adhesive from being pressed down to or pulled up from the module board due to warp of the top panel.08-12-2010
20090196003WIRING BOARD FOR SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND MOTHERBOARD - In a wiring board according to the present invention, a substrate, a solder resist provided on the substrate, a land, a wiring line, and a connection portion connecting the wiring line and the land, the connection portion is provided with a recess as a non-flat portion, and is formed to comprise a width greater than a width of the wiring line and smaller than a width (diameter) of the land, the width of the connection portion being gradually increased from the wiring line toward the land.08-06-2009
20110075390PAD LAYOUT STRUCTURE OF DRIVER IC CHIP - A pad layout structure of a driver IC chip of a liquid crystal display device includes dummy power pads and dummy ground pads, which are disposed in corners of the driver IC chip and are connected to main power pads and main ground pads by metal lines in a chip-on-film (COF) package. Accordingly, it is possible to reduce the resistance of power supply lines and ground lines, to minimize a power dip of a block located far away from the main power pads and main ground pads, and to prevent a failure in power application, which may occur due to a decrease of adhesive strength at a specific position, by dispersing the adhesion positions of the power pads and ground pads.03-31-2011
20100014264PRINTED CIRCUIT BOARD FOR ACCOMPLISHING NARROW SCRIBE LANE AND SEMICONDUCTOR PACKAGE INCLUDING THE PRINTED CIRCUIT BOARD - A PCB (printed circuit board) for manufacturing a semiconductor package. The PCB includes a plurality of semiconductor package unit frames; a scribe lane dividing the plurality of semiconductor package unit frames; and a printed circuit pattern for plating directly connected to a plurality of bond fingers on the semiconductor package unit frames and disposed to cross the scribe lane between adjacent semiconductor package unit frames.01-21-2010
20090310321PRINTED CIRCUIT BOARD AND ELECTRONIC APPARATUS - According to an aspect of the present invention, there is provided a printed circuit board including: a semiconductor package having a surface and a plurality of solder bumps arranged on the surface; a wiring board having electrodes provided at positions respectively corresponding to the solder bumps and configured to mount the semiconductor package; and a reinforcing member formed continuously along the surface and configured to fix the semiconductor package to the wiring board; wherein the reinforcing member is configured to define an opening portion between the surface and the wiring board.12-17-2009
20110286191Printed circuit board and semiconductor package with the same - Disclosed herein is a printed circuit board. The printed circuit board includes a base substrate including a first region on which a semiconductor chip is mounted and a second region positioned outside the first region, first insulating patterns covering the base substrate and including trenches formed on the second region, and second insulating patterns protruding from the first insulating patterns on the second region. The trench and the second insulating pattern may be used as a structure defining an underfill forming material in a preset shape during the process of forming an underfill.11-24-2011
20110286190Enhanced Modularity in Heterogeneous 3D Stacks - Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.11-24-2011
20110292628ANTI-ULTRAVIOLET MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides an anti-UV electronic device and fabrication method thereof. The anti-ultraviolet (anti-UV) electronic device includes an integrated circuit die, wherein the integrated circuit die has an ultraviolet (UV) light erasable memory; and an anti-UV light layer is formed on and covers the ultraviolet (UV) light erasable memory.12-01-2011
20110134619High power device module - A high power device module includes a substrate carrying multiple chips on the top side and having stepped through holes around the chips, copper plates and connectors connected to the chips, fastening members each having a shoulder respectively fitted into the through holes of the substrate, a head connected to one end of the shoulder fitted into the expanded bottom end of the associating stepped through hole, and a shank connected to the other end of the shoulder and protruding over the top side of the substrate, and packaging members directly molded from resin on the shanks of the fastening members and the chips and the copper plates and the connectors to seal the component parts to the substrate.06-09-2011
20100265684INTERPOSER SUBSTRATE AND INCLUDING CAPACITOR FOR ADJUSTING PHASE OF SIGNAL TRANSMITTED IN SAME INTERPOSER SUBSTRATE - In an interposer substrate, a plating stub conductor and a ground conductor form a capacitor, and a plating stub conductor and the ground conductor form a capacitor. Capacitances of the capacitors are adjusted so that a phase difference between signals transmitted by a differential transmission using a signal line including a connection wiring conductor and a signal line including a connection wiring conductor is equal to 180 degrees.10-21-2010
20090251876PRINTED CIRCUIT BOARD - A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't directly pass over any split of the ground plane.10-08-2009
20080239686SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR STRUCTURE BODIES ON UPPER AND LOWER SURFACES THEREOF, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an upper circuit board which has a plurality of upper-layer wirings including a plurality of first upper-layer wirings, and has a plurality of first and second lower-layer wirings. A first semiconductor structure body is provided on an upper side of the upper circuit board and is electrically connected to the first upper-layer wirings. A lower circuit board which is provided on a peripheral part of a lower side of the upper circuit board, the lower circuit board including a plurality of external connection wirings that are electrically connected to the first lower-layer wirings, and an opening portion which exposes the second lower-layer wirings. A second semiconductor structure body which is disposed in the opening portion of the lower circuit board, second semiconductor structure body including a plurality of external connection electrodes that are electrically connected to the second lower-layer wirings of the upper circuit board.10-02-2008
20090310322Semiconductor Package - A substrate includes a number of protruding contact elements. An electrical circuit with electrical contact elements is provided on the substrate. A layer of substrate adhesive is provided on the substrate, the substrate adhesive being in contact with the substrate, with the electrical circuit and with the protruding contact elements. Wiring elements are connected between the protruding contact elements and the electrical contact elements.12-17-2009
20100124037THERMOSETTING COMPOSITION AND PRINTED CIRCUIT BOARD USING THE SAME - A thermosetting composition including an organic solvent, a liquid crystalline thermoset oligomer, and either a crosslinking agent or an epoxy resin or both is disclosed. A printed circuit board which includes the thermosetting composition is also disclosed. The printed circuit board is produced by impregnating the thermosetting composition into a reinforcing material.05-20-2010
20090231823Tape wiring substrate and semiconductor chip package - A second output wiring and a third output wiring enter into a chip mounting portion while coming across a second side and a third side of the chip mounting portion. The other end portions of the second output wiring and the third output wiring enter into the chip mounting portion are bent toward a fourth side of the chip mounting portion, and are connected to an output pad and an output pad provided along a fourth side of the semiconductor chip. An input wiring extends along the fourth side of the chip mounting portion, is bent from a midstream to enter into the chip mounting portion while coming across the fourth side of the chip mounting portion, and is connected to an input pad provided along the fourth side of the semiconductor chip.09-17-2009
20100079966MEMORY MODULE - A memory module includes a printed circuit board (PCB), and a plurality of semiconductor packages and a multi-functional package mounted to the PCB. The multi-functional package may have a data processing function and an error correcting function. Thus, the packages may occupy a relatively small area of the PCB in terms of the number of functions that they provide. Thus, the module may be highly integrated.04-01-2010
20110170274CIRCUIT SUBSTRATE AND DISPLAY DEVICE - Provided is a circuit substrate which can integrate circuit elements without degrading wiring characteristics, and a display device including the circuit substrate. The circuit substrate of the present invention includes a transistor substrate (07-14-2011
20110199746ELECTRONIC SYSTEM WITH A COMPOSITE SUBSTRATE - A composite substrate made of a circuit board mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the circuit board. Metal lines are used for electrical coupling between the circuitry of the IC chip and the circuit board. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the circuit board and good heat distribution from the lead frame.08-18-2011
20120268909Enhanced Modularity in Heterogeneous 3D Stacks - A three-dimensional computer processing chip stack that includes a host layer disposed on at least one other layer in the stack. The host layer includes cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other. The cavities are formed to accommodate the heterogeneous properties of the chips. The chips are joined to respective surfaces of the cavities, thereby forming an element having a smooth surface with respect to the host layer and the chips.10-25-2012
20090201657WIRING SUBSTRATE FOR USE IN SEMICONDUCTOR APPARATUS, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR APPARATUS USING THE SAME - On a printed-wiring board 08-13-2009
20120106112Method for Producing an Electrical Circuit and Electrical Circuit - A method for producing an electrical circuit includes providing a main printed circuit board having a plurality of metalized plated-through holes through the main printed circuit board along at least one separating line between adjacent printed circuit board regions of the main printed circuit board. Each printed circuit board region has electrical contact connection pads on at least the main surface of the printed circuit board region that is to be populated, electrical lines for connection between the plurality of plated-through holes and the contact connection pads, and at least one semiconductor chip electrically contact-connected by means of the contact connection pads. The main printed circuit board is covered with a potting compound across the printed circuit board regions with the semiconductor chips.05-03-2012
20120106111ANISOTROPIC ELECTRICALLY AND THERMALLY CONDUCTIVE ADHESIVE WITH MAGNETIC NANO-PARTICLES - A composition of matter comprising a plurality of nanoparticles in a non-conductive binder, wherein, the type of nanoparticles form isolated parallel electrically and thermally conductive columns when cured in the presence of the magnetic field. Also wherein the plurality of nanoparticles are Paramagnetic or Ferromagnetic magnetic. Wherein the nano particles are coated, and of a particular shape. Wherein the particles are selected from the group consisting of; Al, Pt, Cr, Mn, crown glass, Fe, Ni, and Co, Ni—Fe/SiO05-03-2012
20090284943WIRING BOARD, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE - In a wiring board, a plurality of wiring layers and a plurality of insulating layers are alternately stacked. The wiring layers are electrically connected to one another through via holes formed in the insulating layers. The wiring board includes: a connection pad which is disposed on one of the wiring layers that is on the inner side of an outermost wiring layer; and an external connection terminal which is disposed on the connection pad, and which is projected from the surface of the wiring board. The external connection terminal is passed through the outermost wiring layer.11-19-2009
20090284942SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device fabrication method includes: forming an elongated hole 11-19-2009
20100149773INTEGRATED CIRCUIT PACKAGES HAVING SHARED DIE-TO-DIE CONTACTS AND METHODS TO MANUFACTURE THE SAME - Integrated circuit packages having shared die-to-die contacts and methods to fabricate the same are disclosed. A disclosed example integrated circuit package comprises a leadframe, a first die pad and a second die pad associated with the leadframe, and first and second integrated circuits associated with the first and second die pads, respectively. The package also includes a shared die-to-die contact externally exposed by a recess that extends laterally across a bottom surface of the leadframe between the first and second die pads. The first integrated circuit is electrically coupled to a first portion of the shared contact. The second integrated circuit is electrically coupled to a second portion of the shared contact.06-17-2010
20120293973MULTILAYERED WIRING BOARD AND METHOD FOR FABRICATING THE SAME - In a multilayered wiring board constituted by laminating to form pluralities of layers of wiring layers 11-22-2012
20110267792DISPLAY APPARATUS AND DRIVING CHIP MOUNTING FILM IN THE DISPLAY APPARATUS - A display apparatus and a driving chip mounting film in the display apparatus, capable of simplifying a manufacturing process and reducing a process time. The display apparatus includes an insulating substrate; a display device formed on the insulating substrate and for defining an image display unit; pads formed on the insulating substrate and electrically connected to the display device; a first circuit substrate disposed at and separate from a first side of the insulating substrate; and a number of driving chip mounting films including one-side ends electrically connected to the first circuit substrate, and other-side ends electrically connected to the pads. A number of driving chips are mounted on each of the number of driving chip mounting films.11-03-2011
20110267791CIRCUIT CONNECTION MATERIAL, AND CONNECTION STRUCTURE OF CIRCUIT MEMBER AND CONNECTION METHOD OF CIRCUIT MEMBER USING THE CIRCUIT CONNECTION MATERIAL - A circuit connection material 11-03-2011
20090168382SEMICONDUCTOR MODULE - A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals.07-02-2009
20080291652SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME, PRINTED CIRCUIT BOARD, AND ELECTRONIC DEVICE - Provided are a semiconductor package and a method for forming the same, and a PCB (printed circuit board). The semiconductor package comprises: a PCB including a slit at a substantially central portion thereof, the PCB including an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the PCB; an upper molding layer disposed on the upper surface and covering the semiconductor chip; and a lower molding layer filling the slit and covering a portion of the lower surface of the PCB, wherein the PCB comprises a connecting recess at a side surface thereof, and the upper molding layer and the lower molding layer are in contact with each other at the connecting recess.11-27-2008
20110007489EPOXY RESIN COMPOSITION, RESIN SHEET, PREPREG, MULTILAYER PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE - An object of the present invention is to provide an epoxy resin composition that provides, when used for an insulation layer of a multilayer printed wiring board, a multilayer printed wiring board which is excellent in plating adhesion, heat resistance and moisture resistance reliability and capable of forming fine wiring. Another object of the present invention is to provide a resin sheet, a prepreg, a method for producing a multilayer printed wiring board, a multilayer printed wiring board and a semiconductor device.01-13-2011
20090129040Circuit board having power source - A circuit board having a power source is provided, including: a carrier board having a first dielectric layer disposed on at least a surface thereof and a first circuit layer disposed on the first dielectric layer, wherein the first circuit layer has at least an electrode pad; a first electrode plate disposed on the electrode pad; an insulating frame member disposed on the first electrode plate, with a portion of the first electrode plate being exposed from the insulating frame member, wherein electrolyte is received in the insulating frame member and in contact with the first electrode plate; and a porous second electrode plate disposed on the insulating frame member and the electrolyte, the second electrode plate being in contact with the electrolyte, so as to provide the power source for the circuit board.05-21-2009
20080316726MULTI-LAYER SUBSTRATE AND MANUFACTURE METHOD THEREOF - Disclosed are a multi-layer substrate and a manufacture method thereof. The multi-layer substrate of the present invention comprises a surface dielectric layer and at least one bond pad layer. The surface dielectric layer is located at a surface of the multi-layer substrate. The bond pad layer is embedded in the surface dielectric layer to construct the multi-layer substrate with the surface dielectric layer of the present invention. The manufacture method of the present invention forms at least one bond pad layer on a flat surface of a carrier and then forms the surface dielectric layer to cover the bond pad layer where the bond pad layer is embedded therein. After the multi-layer substrate is separated from the carrier, the bond pad layer and the surface dielectric layer construct a flat surface of the multi-layer substrate.12-25-2008
20130120951STACKED CMOS CHIPSET HAVING AN INSULATING LAYER AND A SECONDARY LAYER AND METHOD OF FORMING SAME - A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.05-16-2013
20130120952SUBSTRATE AND ELECTRONIC DEVICE INCLUDING THE SUBSTRATE - A substrate and an electronic device including the substrate are described. The substrate includes a first surface configured such that a semiconductor package or a semiconductor die is installable thereon, and a second surface facing the first surface, wherein, with respect to a central plane disposed between the first surface and the second surface at equal distances therefrom, a coefficient of thermal expansion in a first portion between the first surface and the central plane is configured to be higher than a coefficient of thermal expansion in a second portion between the second surface and the central plane configured to be. By using the substrate, undesirable overall shape deformation during semiconductor installation may be reduced or relieved.05-16-2013
20130215587MULTILAYER WIRING BOARD AND ELECTRONIC DEVICE - Provided is a multilayer wiring board including a plurality of signal layers and ground layers. The multilayer wiring board includes: a first differential wiring wired to a third signal layer; and a second differential wiring wired to a ninth signal layer disposed above the third signal layer. The multilayer wiring board includes a first differential signal via and a second differential signal via that are connected to the first differential wiring. The multilayer wiring board includes a third differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer. The multilayer wiring board includes a fourth differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer, the first differential wiring wired to pass between the fourth differential signal via and the third differential signal via.08-22-2013
20110222257INVERTER UNIT, INTEGRATED CIRCUIT CHIP, AND VEHICLE DRIVE APPARATUS - A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.09-15-2011
20090244867METHODS OF FABRICATING MULTICHIP PACKAGES AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a discontinuous sealant on a substrate, wherein an opening is formed at an integrated heat spreader gap region, wherein the substrate comprises a portion of a multi chip microelectronic package. A thermal interface material is placed on a top surface of a high power die disposed on the substrate, and then an integrated heat spreader lid is placed on top of the sealant and on top of the thermal interface material. A molding compound is flowed within an integrated heat spreader cavity through the opening directly on a top surface of a low power die disposed on the substrate.10-01-2009
20090244868Semiconductor device and bonding material - The present invention is directed to enhancing the bonding reliability of a bonding portion between an Al electrode of a semiconductor device and a bonding material having metal particles as a main bonding agent. In the semiconductor device, a semiconductor element and an Al electrode are connected to each other with a bonding layer made of Ag or Cu interposed therebetween, and the bonding layer and the Al electrode are bonded to each other with an amorphous layer interposed therebetween. It is possible to obtain excellent bonding strength to the Al electrode by performing a bonding process in atmospheric air by using a bonding material including a metal oxide particle with an average diameter of 1 nm to 50 μm, an acetic acid- or formic acid-based compound, and a reducing agent made of an organic material.10-01-2009
20100157559PRINTED CIRCUIT BOARD AND METHOD FOR MOUNTING ELECTRONIC COMPONENTS - In a case where the first component and the third component are mountable on the first circuit board pattern of the first individual board and the second component is mountable on the second circuit board pattern of the first individual board, or in a case where the first component is mountable on the first circuit board pattern of the second individual board, and the second component and the third component are mountable on the second circuit board pattern of the second individual board, in the first and second individual boards, traces for the third component are provided so that electrical connections between the third component and the other components are identical between the case where the third component is mounted on the first circuit board pattern, and the case where the third component is mounted on the second circuit board pattern.06-24-2010
20090116205MOUNTED STRUCTURE - A plurality of semiconductor elements is adjacently mounted on a substrate by a solder with a melting point of 200° C. or lower, an electronic part other than the semiconductor elements is mounted on the substrate between the adjacently mounted semiconductor elements by a solder with a melting point of 200° C. or lower, and spaces between the plurality of semiconductor elements and the substrate, spaces between the electronic part and the substrate, and spaces between the plurality of semiconductor elements and the electronic part are integrally molded with a molding resin.05-07-2009
20100259910Circuit Board and Mounting Structure - The invention relates to a circuit board having high density circuit and excellent connection reliability and lamination reliability. A resin fabric cloth (10-14-2010
20130215588MULTILAYERED WIRING SUBSTRATE AND ELECTRONIC APPARATUS - A multilayered wiring substrate that includes at least one signal layer and at least one ground layer is provided. The multilayered wiring substrate includes a first signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to one of a pair of differential signaling wires provided in the signal layer, and is formed on a first grid point; and a second signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to the other of the pair of differential signaling wires, and is formed on a second grid point that is positioned diagonally adjacent with respect to the first signal via.08-22-2013
20100226110Printed wiring board, printed IC board having the printed wiring board, and method of manufacturing the same - A printed IC board has a multilayer printed wiring board and one or more bare IC chips. The multilayer printed wiring board has insulation layers made of PTFE, and wiring patterns formed on the insulation layers which are stacked to make a lamination structure. Electrode parts as parts of the wiring patterns are electrically connected to the bare IC chip. A copper member which serves as a reinforcing member is laid in a region formed in the insulation layers other than a first insulation layer. the region is formed directly below the electrode parts. The region is formed in a direction Z along a thickness of the stacked insulation layers. The region formed directly below the electrode parts in the insulation layers in the insulation layers other than the first insulation layer has a higher rigidity than the insulation layers.09-09-2010
20100149774SEMICONDUCTOR DEVICE - A semiconductor device includes a terminal case containing a semiconductor element, a plurality of pin terminals of equal length mounted in the terminal case and electrically connected to the semiconductor element, the plurality of pin terminals projecting outward from a predetermined surface of the terminal case in the same direction, and at least one protruding pin terminal mounted in the terminal case and projecting outward from the predetermined surface of the terminal case in the same direction farther than the plurality of pin terminals.06-17-2010
20100149776PRESSURE CONDUCTIVE SHEET - A pressure conductive sheet includes a connector body formed of a thin plate of insulation material, an elastic body deposited as one body with the connector body, pluralities of connection terminals provided with a given interval to pass through the elastic body and the connector body, and a ground plate constituting a matching circuit, the ground plate being buried by a given width in between the connector body and the elastic body. The ground plate is coupled to a ground terminal among the connection terminals and is separated from an outer circumference face of a signal terminal. The connector body, the elastic body, the connection terminals and the ground plate are combined with one another to substantially reduce an interference between signal terminals through the matching circuit formed based on capacitance of a gap between a ground face of the ground plate and the signal terminal, and to improve electrical characteristics.06-17-2010
20100246152INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY - Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.09-30-2010
20110058346Bonding Metallurgy for Three-Dimensional Interconnect - A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate.03-10-2011
20110128712COMPACT MEDIA PLAYER - An electronic device such as a media player may be formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts may be used to play audio and to convey digital signals. Electrical components for the device may be mounted to a substrate. The components may be encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons may remain uncovered by encapsulant during the encapsulation process. Integrated circuits may be entirely encapsulated with encapsulant. The integrated circuits may be packaged or unpackaged integrated circuit die. The substrate may be a printed circuit board or may be an integrated circuit to which components are directly connected without interposed printed circuit board materials.06-02-2011
20090109643THIN SEMICONDUCTOR DEVICE PACKAGE - A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end.04-30-2009
20100321913MEMORY CARD - A memory card and method for fabricating the same are disclosed, which includes mounting and electrically connecting at least a chip to a circuit board unit having a predefined shape of a memory card; attaching a thin film to the surface of the circuit board unit opposed to the surface with the chip mounted thereon; covering the circuit board unit and the thin film by a mold so as to form a mold cavity having same shape as the circuit board unit but bigger size; filling a packaging material in the mold cavity so as to form an encapsulant encapsulating the chip and outer sides of the circuit board unit, thus integrally forming a memory card having the predefined shape. The present invention eliminates the need to perform a shape cutting process by using water jet or laser as in the prior art, thus reducing the fabricating cost and improving the fabricating yield.12-23-2010
20100321914MULTILAYER PRINTED WIRING BOARD - A multilayer printed wiring board in which interlayer insulation layer and conductive layer are formed on a multilayer core substrate composed of three or more layers, having through holes for connecting the front surface with the rear surface and conductive layers on the front and rear surfaces and conductive layer in the inner layer to achieve electric connection through via holes, the through holes being composed of power source through holes, grounding through holes and signal through holes connected electrically to a power source circuit or a grounding circuit or a signal circuit of an IC chip, when the power source through holes pass through the grounding conductive layer of the inner layer in the core substrate, of the power source through holes, at least a power source through hole just below the IC having no conductive circuit extending from the power source through hole in the grounding conductive layer.12-23-2010
20100321912DISPLAY PANEL - A display panel includes a substrate and many driving chips. The substrate has many pad regions located in a non-display region of the substrate. Each pad region has many first pins with the same length disposed therein, and a pin pitch between two adjacent first pins, a width of each of the first pins, or both the pin pitch and the width vary with the positions where the first pins are disposed in the corresponding pad region. The driving chips are disposed in the non-display region of the substrate. Each driving chip has many second pins, and each second pin is electrically connected to each first pin correspondingly.12-23-2010
20110110061Circuit Board with Offset Via - Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes first and second conductor structures in spaced apart relation, a first via in ohmic contact with the first conductor structure and a second via in ohmic contact with the second conductor structure. A second interconnect layer is formed on the first interconnect layer. The second interconnect layer includes third and fourth conductor structures in spaced apart relation and offset laterally from the first and second conductor structures, a third via in ohmic contact with the third conductor structure and a fourth via in ohmic contact with the fourth conductor structure.05-12-2011
20110019379Printed wiring board, semiconductor device, and method for manufacturing printed wiring board - A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.01-27-2011
20110019381ELECTRONIC CIRCUIT BOARD AND POWER LINE COMMUNICATION APPARATUS USING IT - A highly reliable electronic circuit board for suppressing propagation of noise and a power line communication apparatus using it are provided. An electronic circuit board of the invention is connected to a different electronic circuit board and including a first board having a first face and a second face opposed to the first face and a second board having a third face and a fourth face opposed to the third face. The electronic circuit board includes a first circuit mounted on one end of the first face for performing analog signal processing; a second circuit mounted on another end of the first face for performing digital signal processing; a junction layer provided between the second face and the third face for jointing the first board and the second board; a built-in electronic component built into the junction layer; a connection part mounted on the fourth face and to be connected to the different electronic circuit board; and a first conducting path for electrically connecting the second circuit and the connection part, wherein the connection part is mounted at a position overlapping projection projecting the second circuit onto the fourth face from a vertical direction relative to the first face.01-27-2011
20090046441WIRING BOARD FOR MOUNTING SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME, AND WIRING BOARD ASSEMBLY - A wiring board for mounting semiconductor device, includes at least a dielectric film 02-19-2009
20110116247SEMICONDUCTOR PACKAGE HAVING MULTI PITCH BALL LAND - A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch.05-19-2011
20110242782SUBSTRATE FOR AN ELECTRICAL DEVICE - Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator and a conductive element(s), wherein the conductive element embedded in the insulator, said conductive element also enables to be comprised of an upper portion(s) and a lower portion(s) which are unitary and stack; wherein the surfaces of said conductive element contacted with said insulator enables to be increased, then said conductive layer can be held by said insulator more securely, in this manner, it enables to be prevented said conductive element from peeling off said insulator, and then the reliability of said substrate in accordance with the present invention enables to be enhanced; meanwhile, said substrate can further include a chip which is embedded therein, in order that said substrate being capable of affording a thinner electrical device thickness and enhanced reliability.10-06-2011
20120229999CIRCUIT BOARD CLAMPING MECHANISM - Methods and apparatus for clamping a first circuit board against a member are provided where the first circuit board has a first side and a second side opposite the first side. The method includes engaging an elastomeric member of a clamping member with the first side of the first circuit board to compliantly bear against the first side of the first circuit board whereby the second side of the circuit board is clamped against the member.09-13-2012
20120188737MOTHERBOARD AND MEMORY CONNECTOR THEREOF - A motherboard includes a printed circuit board (PCB) and a memory connector. The PCB includes top and bottom layers. A number of pads are set on the sides of the top and bottom layers and connected to a memory controller. A number of metal pins are set on a first sidewall of the memory connector. A socket slot is defined in a second sidewall opposite to the first sidewall. Top and bottom sidewalls bounding the socket slot define a number of grooves. First ends of the metal pins are soldered on the pads of the top layer and the bottom layer of the PCB. Second ends of the metal pins are extended to the socket slot through the memory connector and exposed through the grooves of the memory connector, to be electrically connected to the golden fingers of a memory when the memory is inserted in the socket slot.07-26-2012
20100053923SEMICONDUCTOR DEVICE AND CIRCUIT BOARD ASSEMBLY - A semiconductor device that includes a semiconductor element, a package substrate, and a plurality of bonding members. The semiconductor element is fixed on the front surface of the package substrate. The package substrate has a first region and a second region on the back surface. The plurality of bonding members is arranged in a grid pattern on the first region of the back surface of the package substrate. The second region of the package substrate defines a bonding prohibition region corresponding with the periphery of the semiconductor element in a plan view.03-04-2010
20110176286LEAD PIN AND WIRING SUBSTRATE WITH LEAD PIN - A lead pin includes a shaft portion, and a connection head portion which is provided on a top end side of the shaft portion and has a diameter larger than a diameter of the shaft portion, and whose whole outer surface is formed of a spherical surface. The connection head portion is formed of a ball shape, an oval spherical shape, or a teardrop-like shape, and also the connection head portion of the lead pin is connected to a wiring substrate by the reflow soldering.07-21-2011
20110176285Interconnection structure, interposer, semiconductor package, and method of manufacturing interconnection structure - There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.07-21-2011
20100134994POWER SEMICONDUCTOR MODULE - A power semiconductor module is disclosed, comprising: a substrate mounted with a power semiconductor device and formed with a pattern; and an integrated terminal unit integrally assembled with a power terminal for applying power to the substrate and a body in which a signal terminal for inputting a signal to or outputting the signal from the substrate is made of an insulated resin material, wherein the integrated terminal unit can be mounted to the substrate to allow the power terminal and the signal terminal to be simultaneously connected to the substrate.06-03-2010
20110069464Memory module, memory system having the memory module, and method for manufacturing the memory module - Provided is a memory module, a system using the memory module, and a method of fabricating the memory module. The memory module may include a printed circuit board and a memory package on the printed circuit board. The printed circuit board may include an embedded optical waveguide and a first optical window extending from the optical waveguide to a first surface of the printed circuit board. The memory package may also include a memory die having an optical input/output section and a second optical window. The optical input/output section, the second optical window, and the first optical window may be arranged in a line and the first optical window and the second optical window may be configured to at least one of transmit an optical signal from the optical waveguide to the optical input/output section and transmit an optical signal from the optical input/output section to the optical waveguide.03-24-2011
20120120624WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate 05-17-2012
20110149541HEAT CURABLE ADHESIVE AND RESIN LAMINATED-TYPE IC CARD - Provided is a heat curable adhesive that can strongly bond a base material formed of a crystalline polyester resin, can freely regulate the thickness of an adhesive layer, has excellent chemical resistance, and, at the same time, has excellent storage stability. Furthermore, provided is a resin laminated-type IC card, in which a liquid heat curable adhesive of which use has been difficult in the past can be used, and the liquid heat curable adhesive can be coated with a good accuracy by a printing method without the need to perform molding into a hot-melt sheet to bond a base material formed of a crystalline polyester resin. Accordingly, the resin laminated-type IC card can have a high degree of freedom in design of the thickness of an IC card. The heat curable adhesive comprises (a) a hydroxyl group-containing non-crystalline polyester resin, (b) a resin containing a carboxylic acid anhydride, and (c) a solvent for dissolving (a) the hydroxyl group-containing non-crystalline polyester resin.06-23-2011
20110019380METHOD AND DEVICE FOR MODULATING LIGHT - Improvements in an interferometric modulator that has a cavity defined by two walls.01-27-2011
20110211322ELECTRONIC DEVICE - An electronic device includes a printed circuit board, conductive portions coated with a solder paste, a chip module installed on the printed circuit board, contact portions formed at the bottom of the chip module and corresponding to the conductive portions respectively, and at least one support portion formed between the chip module and the printed circuit board and having an end coupled to the printed circuit board and another end coupled to the contact portion of the chip module. When the chip module and printed circuit board are deformed in a high-temperature process, the contact portions will still be in contact with the solder paste. Since the printed circuit board is warped upward at the middle and downward at the periphery in a soldering process, the support portion maintains a specific distance between the two to prevent excessive melted solder pastes from flowing towards the periphery or causing short circuits.09-01-2011
20100259911MAGNETIC MICROINDUCTORS FOR INTEGRATED CIRCUIT PACKAGING - Magnetic microinductors formed on semiconductor packages are provided. The magnetic microinductors are formed as one or more layers of coplanar magnetic material on a package substrate. Conducting vias extend perpendicularly through the plane of the magnetic film. The magnetic film is a layer of isotropic magnetic material or a plurality of layers of anisotropic magnetic material having differing hard axes of magnetization.10-14-2010
20090109642SEMICONDUCTOR MODULES AND ELECTRONIC DEVICES USING THE SAME - Semiconductor devices and electronic devices using the same. The semiconductor module may include a first semiconductor chip, and a module substrate having a top surface on which the first semiconductor chip is mounted and a second surface opposite the top surface, wherein the module substrate includes a first buffer layer to relieve stress occurring due to a difference of thermal expansions between the first semiconductor chip and the module substrate.04-30-2009
20080285247Low Exothermic Thermosetting Resin Compositions Useful As Underfill Sealants and Having Reworkability - This invention relates to the thermosetting resin compositions useful for mounting onto a circuit board semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), on a carrier substrate. Similarly, the compositions are useful for mounting onto circuit board semiconductor chips themselves. Reaction products of the compositions of this invention are controllably reworkable when subjected to appropriate conditions. And significantly, unlike many commercial rapid curing underfill sealants (“snap cure underfills”), the inventive compositions possess an exotherm under 300 J/g or demonstrate package stability at 55° C. for 7 days, and therefore do not require special packaging to be transported by air courier, or special approval from international transportation authorities, such as the U.S. Department of Transportation, to permit such air transport. The inventive compositions possess an exotherm under 300 J/g and/or demonstrate package stability at 55° C. for 7 days and therefore do not require special packaging to be transported by air courier, or special approval from international transportation authorities, such as the U.S. Department of Transportation, to permit such air transport.11-20-2008
20100328919METHOD OF MAKING A FIBER REINFORCED PRINTED CIRCUIT BOARD PANEL AND A FIBER REINFORCED PANEL MADE ACCORDING TO THE METHOD - A method of making a printed circuit board panel, a printed circuit board panel made according to the method, and a system incorporating a printed circuit board provided onto the panel. The printed circuit board panel has a panel top edge, a panel bottom edge parallel to the panel top edge, and two parallel panel side edges, and further includes a first set of fiber bundles extending at the predetermined angle with respect to the panel side edges, and a second set of fiber bundles extending at the predetermined angle with respect to the panel top edge.12-30-2010
20100328918COMPOSITE STRUCTURE OF ELECTRONIC COMPONENT AND SUPPORTING MEMBER - A composite structure includes an electronic component and a supporting member. The electronic component includes a main body and a plurality of pins extended outwardly from the main body. The supporting member includes a first supporting part and a second supporting part. The first supporting part is foldable with respect to the second supporting part. The main body of the electronic component is accommodated within the first supporting part of the supporting member. The pins are accommodated with the second supporting part of the supporting member. The first supporting part is folded with respect to the second supporting part such that the pins are bent to define a bent structure.12-30-2010
20100328917MULTICHIP MODULE, PRINTED CIRCUIT BOARD UNIT, AND ELECTRONIC APPARATUS - A multichip module includes a package substrate, a first semiconductor device, a second semiconductor device and a conductive bump. The first semiconductor device is flip-chip bonded to the package substrate. The first semiconductor device includes a first chip pad on a surface thereof. The second semiconductor device is mounted on the first semiconductor device. The second semiconductor device includes a second chip pad facing the first chip pad. The conductive bump connects the first chip pad to the second chip pad. The conductive bump includes a first metallic body that has a first diffusion rate and a second metallic body that has a second diffusion rate lower than the first diffusion rate.12-30-2010
20110255258RESIN COMPOSITION, PREPREG, RESIN SHEET, METAL-CLAD LAMINATE, PRINTED WIRING BOARD, MULTILAYER PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE - Disclosed is a resin composition exhibiting a low thermal expansion coefficient, as well as higher heat resistance, flame resistance and insulation reliability than ever before when used in a multilayer printed wiring board that requires fine wiring work. Also disclosed are a prepreg, a resin sheet, a metal-clad laminate, a printed wiring board, a multilayer printed wiring board and a semiconductor device, all of which comprising the resin composition. The resin composition of the present invention comprises (A) an epoxy resin, (B) a cyanate resin and (C) an onium salt compound as essential components.10-20-2011
20080218986Increased Stand-Off Height Integrated Circuit Assemblies, Systems, and Methods - Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the die during heating of the solder to a liquescent state, thereby increasing the stand-off height of the die above the substrate. The lifting force is maintained during cooling of the solder to a solid state, thereby forming increased stand-off height solder connections.09-11-2008
20100214753Pb-free solder-connected structure and electronic device - Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.08-26-2010
20100214754RIBBON BONDING IN AN ELECTRONIC PACKAGE - A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher throughput due to less areas to bond and test.08-26-2010
20110188219CIRCUIT BOARD ASSEMBLY - A circuit board assembly includes a circuit board having a first side and a second side opposite to the first side. A chip module is connected to the first side of the circuit board. The chip module includes a substrate and a chip disposed on the substrate. The first clamping member defines a recess and a contact portion around the recess. The chip is received in the recess, and the contact portion abuts the substrate. A second clamping member abuts the second side of the circuit board. A plurality of stress adjusting members extends through the second clamping member and engages the first clamping member.08-04-2011
20110216517ELECTRICAL CONNECTION INTERFACES AND METHODS FOR ADJACENTLY POSITIONED CIRCUIT COMPONENTS - Electrical components, such as packaged integrated circuit devices that are mountable on a substrate surface, are provided with at least one exposed electrical contact on a side surface of the component that will be substantially perpendicular to the substrate surface when the component is mounted. Two such components can be mounted side-by-side on the substrate surface with the above-mentioned contacts close to one another between the above-mentioned side surfaces. An electrical connection between the contacts can be made (or perfected) by depositing an electrically conductive connector material in contact with both of the contacts between the above-mentioned side surfaces.09-08-2011
20110216516Semiconductor Module, Socket For The Same, And Semiconductor Module/Socket Assembly - A semiconductor module, a socket for the same, and a semiconductor module/socket assembly are disclosed. The semiconductor module includes a printed circuit board including a plurality of semiconductor devices, a plurality of insulating layers and a plurality of metal layers, the plurality of insulating layers and the plurality of metal layers are alternately stacked. Exposed portions of the metal layers are exposed to the outside of the semiconductor module at a first and a second ends of the printed circuit board. The first end and the second end are at opposite ends of the printed circuit board.09-08-2011
20110051388PRINTED CIRCUIT BOARD WITH A FUSE AND METHOD FOR THE MANUFACTURE OF A FUSE - Some invention embodiments relate to a method for forming a fuse which electrically connects two metal surfaces (03-03-2011
20110051387METHOD FOR ELECTROLESS NICKEL-PALLADIUM-GOLD PLATING, PLATED PRODUCT, PRINTED WIRING BOARD, INTERPOSER AND SEMICONDUCTOR APPARATUS - An object of the present invention is to provide an electroless nickel-palladium-gold plating method which is able, when performed on a plating target surface such as terminals of a printed wiring board, terminals of other electronic components, and other resin substrates with a fine metal pattern, to prevent abnormal metal deposition on a resin surface which is an undercoat and to provide a high-quality plated surface. Another object of the present invention is to provide a plated product with a high-quality plated surface, particularly such as an interposer and motherboard, and a semiconductor apparatus using the same. These objects were achieved by the electroless nickel-palladium-gold plating method of the present invention, which is a method for plating target objects such as terminals of a printed wiring board and in which at least one surface treatment selected from a treatment with a solution of pH 10 to 14 and a plasma treatment is performed at an optional step after the step of providing a palladium catalyst and before the step of performing electroless palladium plating.03-03-2011
20110051386Circuit Board, Mounting Structure, and Method for Manufacturing Circuit Board - A circuit board (03-03-2011
20110051385HIGH-DENSITY MEMORY ASSEMBLY - High-density memory assemblies and related methods for manufacturing and using such memory assemblies are included in the present disclosure. According to one exemplary embodiment, a high-density memory assembly includes stacked first and second panels. The first and second panels each comprise a substrate and at least one chip disposed on the substrate. The first and second panels each further comprise connecting tabs extending from the substrates of the first and second panels.03-03-2011
20120307470WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a substrate body formed of an inorganic material and including a first surface and a second surface, a first trench formed in a first surface side of the substrate body, a second trench formed in a second surface side of the substrate body, a penetration hole penetrating through the substrate body, a first plane layer filling the first trench, a second plane layer filling the second trench, and a penetration wiring filling the penetration hole. The first plane layer is a reference potential layer. The second plane layer is a power supply layer.12-06-2012
20110134620MEMORY CARDS AND ELECTRONIC MACHINES - Provided is a memory card. The memory card includes interconnection terminals for electric connection with an external electronic machine. The interconnection terminals may be spaced from the front side of the memory card by a distance greater than the lengths of the interconnection terminals. Alternatively, the memory card may include other interconnection terminals between its front side and the former interconnection terminals. The former and latter interconnection terminals may be used for electric connection with different kinds of electronic machines.06-09-2011
20110304998Package Substrate - In accordance with an embodiment, a substrate layout comprises a ground plane of a first power loop on a layer of a substrate, a first trace rail on the layer extending along a first periphery of the ground plane, and a first perpendicular trace coupled to the first trace rail. The ground plane is between the first trace rail and a die area, and the first perpendicular trace extends perpendicularly from the first trace rail. The first trace rail and the first perpendicular trace are components of a second power loop.12-15-2011
20110304999Interposer-on-Glass Package Structures - A device includes an interposer including a substrate, and a first through-substrate via (TSV) penetrating through the substrate. A glass substrate is bonded to the interposer through a fusion bonding. The glass substrate includes a second TSV therein and electrically coupled to the first TSV.12-15-2011
20090296361Integrated circuit module with temperature compensation crystal oscillator - An integrated circuit module with temperature compensation crystal oscillator (TCXO) applying to an electronic device comprises: one substrate having one top surface; one temperature compensation crystal oscillator (TCXO) disposed on the top surface; at least one chip disposed on the top surface; one encapsulating piece formed on the top surface for covering the TCXO and the chip. As above-described structure, TCXO is prevented from exchanging heat due to the temperature difference so that the stability of the TCXO is improved.12-03-2009
20110110062Stack-type semiconductor device having chips having different backside structure and electronic apparatus including the same - A stack-type semiconductor device including semiconductor chips having different backside structures and an electronic apparatus including the stack-type semiconductor device include: a base frame for a semiconductor device; a first semiconductor chip that is mounted on the base frame and has a bottom surface having a first surface roughness; and a second semiconductor chip that is mounted on the first semiconductor chip and has a bottom surface having a second surface roughness, wherein the second surface roughness is greater than the first surface roughness by 1.2 nm or more. The stack-type semiconductor device is manufactured to be thin while cracking of the first semiconductor chip is prevented. In addition, changes in data caused by charge loss resulting from diffusion of metal ions, which can occur when a stack-type semiconductor device is a memory device, is prevented.05-12-2011
20110063812ELECTRONIC DEVICE, METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC EQUIPMENT - An electronic device includes a circuit board having a first electrode formed on a main surface thereof, a semiconductor device disposed toward the main surface of the circuit board, the semiconductor device having a second electrode formed on a surface thereof opposed to the main surface, and a connection member electrically connecting between the first and second electrodes. The connection member includes a hollow cylindrical member and a conductive member disposed within the hollow cylindrical member.03-17-2011
20110317388ELECTRONIC DEVICE HAVING A WIRING SUBSTRATE - A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer.12-29-2011
20120206891CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE HAVING COMPONENT MOUNTED ON CIRCUIT BOARD - A circuit board H08-16-2012
20120008295WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor.01-12-2012
20100110651Integrated Circuit Coating For Improved Thermal Isolation - During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots.05-06-2010
20120155045CLIP FOR BIOS CHIP - A clip for a basic input/output system (BIOS) chip includes a main body, two spindles, two clipping elements, and two torsion springs. The main body includes a number of connecting pins mounted on a bottom of the main body, and a number of signal pins mounted on a top of the main body and electrically and correspondingly connected to the number of the connecting pins. The clipping elements are rotatably mounted to opposite ends of the main body through the spindles. The torsion springs are mounted between the clipping members and the main body. The connecting pins of the main body respectively electrically contacts a number of chip pins of the BIOS chip in response to the clipping elements clipping the BIOS chip.06-21-2012
20120026708CARRIER SUBSTRATE AND METHOD FOR MAKING THE SAME - A carrier substrate includes a substrate having a chip side and a PCB side, a plurality of bond pads disposed on the chip side for bonding a chip, a plurality of land grid array (LGA) pads disposed on the PCB side, and a plurality of resilient flanges installed on the PCB side in an array manner. The plurality of resilient flanges electrically connects with the LGA pads correspondingly.02-02-2012
20120063108CIRCUIT BOARD AND SEMICONDUCTOR MODULE INCLUDING THE SAME - In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes.03-15-2012
20120063107SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes stacked semiconductor die. In accordance with embodiments, the semiconductor component includes a substrate having a component receiving area and a plurality of bond pads. A semiconductor chip is attached to the component receiving area. An electrical connector is coupled to the semiconductor chip and the substrate. A second semiconductor chip is mounted or attached to one of the ends of the electrical connector such that this end is positioned between the semiconductor chips. A second electrical connector is coupled between the second semiconductor chip and the substrate. A third semiconductor chip is mounted over or attached to the second electrical connector such that a portion is between the second and third semiconductor chips.03-15-2012
20120155047PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a package and a method for manufacturing the same. The package includes: a first package including a first printed circuit board having a first surface and a second surface and having a first die mounted on the first surface, the first die having a through silicon via; a second package including a second printed circuit board having a first surface and a second surface and having a second die mounted on the first surface, the second die having a through silicon via; first external connecting terminals electrically interconnecting the first surface of the first printed circuit and the first surface of the second printed circuit disposed to be opposite to each other; and first connecting bumps electrically interconnecting the first and second dice. Therefore, power signals are independently applied to each of the dice, thereby making it possible to improve power stability of each of the dice.06-21-2012
20120155046PRINTED CIRCUIT BOARD - A printed circuit board (PCB) includes a top layer, a memory controller, two gaps, and two connectors. The memory controller is located on the top layer. A number of golden fingers are respectively set on the top layer near each gap and electrically connected to the memory controller. Each connector includes a first slot to hold the gold fingers near a corresponding one of the gaps and a second slot to hold a number of gold fingers of a corresponding one of two memory chips. The first slot is electrically connected to the second slot. Each memory chip and the PCB are coplanar.06-21-2012
20120155048WIRING BOARD, SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THEM - There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.06-21-2012
20120155044ELECTRONIC CIRCUIT BOARD AND A RELATED METHOD THEREOF - An apparatus includes a set of first metal contact pads disposed on a low temperature co-fired ceramic substrate. A plurality of metalized interconnectors extend between a digital electronic component and the low temperature co-fired ceramic substrate. The apparatus is configured to operate at a temperature greater than 250 degrees Celsius.06-21-2012
20110103031PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE PACKAGE SUBSTRATE - A package substrate may include an insulating substrate, first circuit patterns, second circuit patterns and a test pattern. The first circuit patterns may be arranged on the insulating substrate. The second circuit patterns may be arranged on the insulating substrate. The second circuit patterns may be arranged between the first circuit patterns. The test pattern may be electrically connected between same polar terminals of the first circuit patterns and the second circuit patterns. Thus, electrical connections between the semiconductor chip and the circuit patterns may be tested before performing a process for cutting the package substrate.05-05-2011
20100172113METHODS FOR FORMING PACKAGED PRODUCTS - An apparatus and methods for packaging semiconductor devices are disclosed. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration.07-08-2010
20100290205ADHESIVE FILM - An adhesive film is provided that can ensure reliable continuity even if a filler and a binder composition are not sufficiently removed from between a wiring board and a semiconductor chip during flip-chip mounting of the semiconductor chip. The adhesive film is formed from a binder composition including an epoxy compound, a curing agent, and the filler. The amount of a filler contained with respect to a total amount of an epoxy compound, a curing agent, and the filler is 10 to 70 mass %. The filler includes first non-conductive inorganic particles having an average particle size of 0.5 to 1.0 μm, and conductive particles formed by subjecting second non-conductive inorganic particles having an average particle size of 0.5 to 1.0 μm. An average particle size of the conductive particles does not exceed 1.5 μm. The conductive particles is contained in an amount of 10 to 60 mass % of the filler.11-18-2010
20120127683ELECTRONIC DEVICE, RESONATOR, OSCILLATOR AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein the covering structure is provided with a side wall provided on the substrate and comprising an interlayer insulating layer surrounding the cavity part and a wiring layer; a first covering layer covering an upper portion of the cavity part and having an opening penetrating through the cavity part and composed of a laminated structure including a corrosion-resistant layer; and a second covering layer for closing the opening.05-24-2012
20120162947VERTICALLY INTEGRATED SYSTEMS - Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.06-28-2012
20120127684INSULATION CIRCUIT BOARD, AND POWER SEMICONDUCTOR DEVICE OR INVERTER MODULE USING THE SAME - The invention relates to a high-voltage insulation circuit board which is used in an electric power apparatus such as an electric power converter or the like such as power semiconductor device, inverter module, or the like and provides an insulation circuit board in which electric field concentration at the end sections of a wiring pattern is reduced, partial discharging is suppressed, and a reliability is high. According to the invention, there is provided an insulation circuit board having: a metal base substrate; and wiring patterns which are formed onto at least one of the surfaces of the metal base substrate through an insulation layer, characterized in that between two adjacent wiring patterns in which an electric potential difference exists among the wiring patterns, at least one or more wiring patterns or conductors which are in contact with the insulation layer and have an electric potential in a range of the electric potential difference between the adjacent wiring patterns are arranged. According to the invention, the electric field concentration at the end sections of the wiring pattern to which a high voltage is applied is reduced and partial-discharge-resistant characteristics are improved.05-24-2012
20120162948SENSOR MODULE - A sensor module. One embodiment provides a cap whose perimeter defines a rim. A first semiconductor chip is attached to the cap. The first semiconductor chip includes first connection elements. The rim and the first connection elements define a common plane.06-28-2012
20100208443SEMICONDUCTOR DEVICE - A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 08-19-2010
20100208442WIRING BOARD ASSEMBLY AND MANUFACTURING METHOD THEREOF - A wiring board assembly includes a rectangular plate-shaped wiring board having a plurality of resin insulation layers and conduction layers alternately laminated together to define opposite first and second main surfaces and a plurality of connection terminals arranged on the first main surface for surface contact with terminals of a chip and a rectangular frame-shaped reinforcing member fixed to the first main surface of the wiring board with the connection terminals exposed through an opening of the reinforcing member. The reinforcing member has a plurality of structural pieces separated by slits extending from an inner circumferential surface to an outer circumferential surface of the reinforcing member.08-19-2010
20120250282FASTENING AND ELECTROCONDUCTIVE CONNECTING OF A CHIP MODULE TO A CHIP CARD - For manufacturing a chip card, a chip module (10-04-2012
20120170240METHOD OF MANUFACTURING A MULTILAYER PRINTED WIRING BOARD FOR PROVIDING AN ELECTRONIC COMPONENT THEREIN - A multilayer printed wiring board and method for manufacturing a multilayer printed wiring board. One method include a method for manufacturing a multilayer printed wiring board having an electronic component housed therein. The method includes forming a conduction circuit on a core substrate and forming an alignment mark on the core substrate separate from the conduction circuit. Also included is forming a concavity in the core substrate, the concavity being formed in an area of the core substrate not including the conductor circuit and alignment mark, and inserting the electronic component into the concavity in the core substrate by using the alignment mark on the core substrate to align the electronic component with the concavity.07-05-2012
20100309641INTERPOSER SUBSTRATE, LSI CHIP AND INFORMATION TERMINAL DEVICE USING THE INTERPOSER SUBSTRATE, MANUFACTURING METHOD OF INTERPOSER SUBSTRATE, AND MANUFACTURING METHOD OF LSI CHIP - A method of forming narrow-pitch flip-chip bonding electrodes and wire bonding electrodes at the same time is provided so as to reduce the cost of a substrate. In addition, a low-cost solder supply method and a flip-chip bonding method to a thin Au layer are provided. A stacked layer of a Cu layer 12-09-2010
20120075822ORGANIC PRINTED CIRCUIT BOARD HAVING REINFORCED EDGE FOR USE WITH WIRE BONDING TECHNOLOGY - Disclosed herein are electronic devices, such as, for example, televisions, stereo systems, diagnostic equipment, cell phones, desktop or laptop PCs, medical pulse generators, or etc., including an integrated circuit including a printed circuit board including multiple layers and a wire bond pad. The multiple layers are sandwiched together in a planar unitary structure including a top surface, a bottom surface and a structure edge extending between the top surface and the bottom surface. The multiple layers include a first organic substrate layer joined to a second organic substrate layer. Each organic substrate layer includes a layer edge and a peripheral surface adjacent the layer edge. Each layer edge forms part of the structure edge. The wire bond pad includes an outer face, an inner face generally opposite the outer face, and a first rib. The inner face extends along the structure edge. The first rib projects generally perpendicular from the inner face between the first organic substrate layer and the second organic substrate layer and extends along the peripheral surface of at least one of the first organic substrate layer or the second organic substrate layer.03-29-2012
20120075821INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.03-29-2012
20120218728Carrier Device, Arrangement Comprising such a Carrier Device, and Method for Patterning a Layer Stack Comprising at Least One Ceramic Layer - A method for patterning a layer stack with at least one ceramic layer includes providing the ceramic layer, which has at least one plated-through hole. An electrically conductive layer is applied above the ceramic layer, such that the electrically conductive layer is electrically coupled to the at least one plated-through hole. A further layer is deposited onto the electrically conductive layer in the region of the at least one plated-through hole, wherein the further layer includes nickel. The electrically conductive layer is removed outside the region of the at least one plated-through hole. A carrier device patterned in this way can be electrically and mechanically coupled to an electronic component.08-30-2012
20120081872THERMAL WARP COMPENSATION IC PACKAGE - An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.04-05-2012
20120081871WARP REACTIVE IC PACKAGE - An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of a layer of material bonded to the top of the integrated circuit package. The layer of material may have a generally planar-convex or a generally planar-concave cross-section. By appropriate choice of temperature coefficient and degree of concavity or convexity, the layer of material can compensate for either convex or concave warpage. In some embodiments the layer of material has apertures therein allowing compensation for more complex warpages. The apparatus provides an alternative to apparatus for dealing with IC package warpage known in the art.04-05-2012
20130170167PRINTED CIRCUIT BOARD - A multi-layer printed circuit board includes an embedded capacitor substrate composed of a power source conductor layer and a ground conductor layer, the layers being disposed close to each other. The power source conductor layer has a first power source plane to supply power to a circuit element, and a second power source plane that is separated from the first power source plane by a gap and functions as a main power source. The first power source plane is partially connected to the second power source plane by a connecting line. The ground conductor layer has an opening at a position overlapping with a projected image when the connecting line is projected on the ground conductor layer. This structure suppresses propagation of the noise caused at the circuit element and reduces radiation noise in the printed circuit board.07-04-2013
20080298034PRINTED CIRCUIT BOARD AND SEMICONDUCTOR MODULE HAVING THE SAME - A printed circuit board (PCB) includes a substrate having a first group of at least two via holes and a second group of at least two via holes formed therein, a first pad set of terminal pads and a second pad set of terminal pads formed on the substrate, and a first group of conductive connection members and a second group of conductive connection members formed in the substrate. The first group of the via holes are surrounded by the first pad set of the terminal pads and the second group of the via holes are surrounded by the second pad set of the terminal pads. The first and the second groups of conductive connection members fill up the first and second groups of the via holes. The first group of the conductive connection members are connected to the first pad set of the terminal pads and the second group of the conductive connection members are connected to the second pad set of the terminal pads.12-04-2008
20120327626WIRING SUBSTRATE, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.12-27-2012
20110235298Wiring substrate and method of manufacturing the wiring substrate - A wiring substrate includes a side-wall electroconduction layer and a land. The side-wall electroconduction layer is formed on the side-wall of a through hole formed in the substrate. The land is an electroconduction layer connected with the side-wall electroconduction layer in which only the land portion as a minimum necessary portion used for wiring is formed to the surface of the substrate. Unnecessary portion of the land other than the land portion is eliminated.09-29-2011
20110235297Integrated circuit package component with lateral conductive pins - An integrated circuit package component with lateral conductive pins includes a package body having a middle conductive pin, an initial conductive pin and a final conductive pin. The middle conductive pin, the initial conductive pin and the final conductive pin are all disposed on a lateral side of the package body and respectively have a first soldering portion, a second soldering portion, and a third soldering portion, in which the middle conductive pin is arranged between the initial conductive pin and the final conductive pin, and an area of the middle conductive pin is smaller than that of the second soldering portion area and the third soldering portion in size.09-29-2011
20110235296Integrated circuit package component with ball conducting joints - The present invention relates to an integrated circuit package component with ball conducting joints, includes a substrate and a plurality of solder joints. The solder joints are installed on one surface of the substrate. The solder joints are arranged to form a concentric array having a first zone and a second zone, the second zone encircles the first zone. The soldering area of any solder joint in the first zone of the concentric array is smaller than that of any solder joint in the second zone of the concentric array.09-29-2011
20100232129MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conductive elements having surfaces remote from the surface of the substrate. The method includes compressing the at least two conductive elements so that the remote surfaces thereof lie in a common plane, and after the compressing step, providing an encapsulant material around the at least two conductive elements for supporting the microelectronic package and so that the remote surfaces of the at least two conductive elements remain accessible at an exterior surface of the encapsulant material.09-16-2010
20100232128MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND REFERENCE WIREBOND - A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip, connected together with an interconnection element, e.g., substrate, the latter having signal contacts and reference contacts. The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds can be connected to device contacts exposed at a surface of the microelectronic device. Reference conductors, e.g., reference wirebonds can be provided, at least one of which can be connected with two reference contacts of the interconnection element. The reference wirebond can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond that is connected to the microelectronic device over at least a substantial portion of the length of the signal conductor. In such manner a desired impedance may be achieved for the signal conductor.09-16-2010
20100232127WIRING BOARD COMPOSITE BODY, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE WIRING BOARD COMPOSITE BODY AND THE SEMICONDUCTOR DEVICE - A wiring board composite body includes a supporting substrate, and wiring boards formed on each of the upper and the lower surfaces of the supporting substrate. The supporting substrate includes a supporting body, and a metal body arranged on each of the upper and the lower surfaces of the supporting body. The wiring board comprises at least an insulation layer insulating upper and lower wirings, and a via connecting the upper and the lower wirings. The wiring board mounted on the metal body constitutes a wiring board with the metal body. Thus, the supporting body supporting the metal body is effectively used in a process of forming the wiring board on the metal body, and the wiring board composite body, which has advantageous structural and production characteristics, is provided. A semiconductor device and a method for manufacturing such wiring board composite body and the semiconductor device are also provided.09-16-2010
20120287589ELECTRONIC MODULE AND COMMUNICATION APPARATUS - An electronic module with excellent electrical characteristics includes an electronic component, a mount board, signal electrodes, a ground electrode, and an insulating layer. The electronic component is mounted on a first main surface of the mount board. The signal electrodes and the ground electrode are located on a second main surface of the mount board. The insulating layer is arranged so as to cover a portion of the second main surface of the mount board. The insulating layer is arranged so as not to cover end portions of the signal electrodes that face the ground electrode.11-15-2012
20130010446LAMINATE ELECTRONIC DEVICE - A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 μm. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.01-10-2013
20110149540METHOD FOR ASSEMBLING AT LEAST ONE CHIP WITH A WIRE ELEMENT, ELECTRONIC CHIP WITH A DEFORMABLE LINK ELEMENT, FABRICATION METHOD OF A PLURALITY OF CHIPS, AND ASSEMBLY OF AT LEAST ONE CHIP WITH A WIRE ELEMENT - A first step of the method for assembling a wire element with an electronic chip comprises arranging the wire element in a groove of the chip delineated by a first element and a second element, joined by a link element comprising a plastically deformable material, and a second step then comprises clamping the first and second elements to deform the link element until the wire element is secured in the groove.06-23-2011
20110157855INTEGRATED CIRCUITS HAVING LEAD CONTACTS AND LEADLESS CONTACT PADS CONNECTED TO A SURFACE OF A PRINTED WIRING BOARD, AND METHODS FOR CONNECTING THE SAME - A method is provided for connecting an integrated circuit to a surface of a printed wiring board. The integrated circuit includes lead contacts and leadless contact pads. A first solder paste is applied to the leadless contact pads of the integrated circuit, and preformed conductive pieces are placed on the first solder paste. The preformed conductive pieces are slugs that have, for example, a cylindrical shape or a rectangular cross-section. The preformed conductive pieces are heated and brought into electrical contact with the leadless contact pads. The lead contacts are formed into gull wings. The bases of the preformed conductive pieces are generally aligned in a plane, and the bases of the gull wings are substantially coplanar with the plane such that they collectively generally define a contact plane. A second solder paste is applied on the surface, and the bases of the gull wings and the preformed conductive pieces are soldered to the second solder paste on the surface so that the integrated circuit is in electrical contact with the surface through both the leadless contact pads and the lead contacts. The preformed conductive pieces comprise a conductive material (e.g., a copper alloy) that has a higher melting point than the first solder paste and the second solder paste such that the preformed conductive pieces do not melt during heating or soldering that is described above.06-30-2011
20110157854SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE - A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.06-30-2011
20110157853FAN-OUT WAFER LEVEL PACKAGE WITH POLYMERIC LAYER FOR HIGH RELIABILITY - A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit.06-30-2011
20130021767DOUBLE-SIDED PRINTED CIRCUIT BOARD - A double-sided PCB includes a circuit plate, a first chip, and a second chip. The circuit plate includes a spacer layer having a first surface and an opposing second surface, a first multilayer structure, and a second multilayer structure. The first multilayer structure includes a first wire layer, a first middle layer, and a second wire layer having a first grounding portion and first conductive pattern portions, that are stacked on each other on the first surface. The second multilayer structure on the second surface is either a mirror image of the first multilayer structure, or is very similar thereto. The first and second chips are each arranged on a grounding portion and are each electrically connected to their respective conductive pattern portions.01-24-2013
20130021769MULTICHIP MODULE, PRINTED WIRING BOARD, METHOD FOR MANUFACTURING MULTICHIP MODULE, AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD - A multichip module includes an arithmetic element that is a semiconductor element that executes arithmetic processing and a memory element that is arranged opposite the arithmetic element and that is a semiconductor element that stores therein data. Then, the multichip module includes the arithmetic element mounted thereon and includes a package board that includes, on a surface on which the arithmetic element is mounted, an external terminal that connects another part. Furthermore, the multichip module includes a reinforcing part on a surface at the opposite side from the surface of the package board on which the external terminal and that is arranged such that the reinforcing part covers an area from outside the peripheral portion of the arithmetic element to a predetermined position located on the central side of the package board.01-24-2013
20130021768CHIP-ON-FILM PACKAGES AND DEVICE ASSEMBLIES INCLUDING THE SAME - Chip-on-film packages are provided. A chip-on-film package includes a film substrate having a first surface and a second surface opposite to each other, a semiconductor chip on the first surface, and a thermal deformation member adjacent to the second surface. The thermal deformation member has a construction that causes its shape to transform according to a temperature. Related devices and device assembles are also provided.01-24-2013
20130114226COF Packaging Unit and COF Packaging Tape - The invention discloses a COF packaging unit and a COF packaging tape. The COF packaging unit comprises COF baseband(s), IC Die(s) packaged on the COF baseband(s), and input end wires and output end wires connected with the IC Die(s); the input end wires and the output end wires are respectively provided with input terminals and output terminals at two edges of the COF baseband. In the invention, because the input terminals and the output terminals are pitched along the edges of the COF baseband, the length of the single COF packaging unit is set in accordance with the pitching requirement of the input end wires and the output end wires, so that the COF baseband can have sufficient area for wiring, to adapt to the requirement of large LCD panels. Thus, resources are reasonably integrated and used, equipment utilization rate is increased, material purchasing cost is saved, and economic benefits are increased.05-09-2013
20130114227Efficient electronics module - An efficient electronics package comprising an integrated circuit, a transistor case packaging, a power supply, an actuation segment and a sensor segment, wherein engagement of the integrated circuit causes the actuation segment to be activated. The integrated circuit may be engaged, for example, by a level-hold trigger or the sensor segment.05-09-2013
20130114228ELECTROMAGNETIC INTERFERENCE SHIELDING TECHNIQUES - Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.05-09-2013
20130100624CIRCUIT BOARD CONTACT PADS - The present disclosure provides a circuit board with a first via and a second via, the first and second vias providing an electrical path from a top surface of the circuit board to a bottom surface of the circuit board. The circuit board also includes a first contact pad electrically coupled to the first via and a second contact pad electrically coupled to the second via. The first contact pad is disposed at an angle with respect to a reference line crossing through the center of the first and second vias, and the second contact pad is disposed on an opposite side of the reference line at the angle with respect to the reference line, such that a footprint that encompasses an area between the first and second contact pads does not cover the first and second vias.04-25-2013
20130100626WIRING SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - Embodiments of the present invention provide a wiring substrate having a structure where a plurality of projection electrodes are arranged within an electrode formation region on a substrate main surface. At least one among a plurality of the projection electrodes is a variant projection electrode which has a recess portion on an upper surface, an outer diameter at the upper end that is larger than an outer diameter at the lower end, and a reverse trapezoidal cross-section shape. Embodiments of the present invention also provide methods for manufacturing wiring substrates having one or more of said variant projection electrode.04-25-2013
20130100625WIRING BOARD, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING WIRING BOARD - A wiring board includes a resin substrate in which reinforcement members are arranged horizontally, a through electrode filled in a through hole penetrating the substrate in a thickness direction, and wiring layers respectively formed on both surfaces of the substrate and electrically connected to each other via the through electrode. The reinforcement members are arranged such that reinforcement members arranged in a middle region of the substrate in the thickness direction has higher density than reinforcement members arranged in the regions other than the middle region of the substrate.04-25-2013
20110273857CONTACT SPRINGS FOR SILICON CHIP PACKAGES - A method for manufacturing a silicon chip package for a circuit board assembly is provided with a package substrate having a silicon chip and an array of contact pads provided by conductive material. A plurality of conductive springs are affixed to the array of contact pads for providing conductive contact with the corresponding array of contacts on a circuit board assembly.11-10-2011
20110211323CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to one embodiment, a circuit board includes: a substrate on which circuit patterns are formed, a first surface of the substrate being formed substantially flat; and a solder resist film that covers the first surface of the substrate. The solder resist film assumes, as a whole, a convex shape in which the thickness of the solder resist film in the center of the substrate is larger than the thickness of the solder resist film in the periphery of the substrate.09-01-2011
20110222256CIRCUIT BOARD WITH ANCHORED UNDERFILL - Various circuit boards and methods of manufacturing using the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a solder mask to a side of a circuit board and forming at least one opening in the solder mask leading to the side. An underfill is placed on the solder mask so that a portion thereof projects into the at least one opening.09-15-2011
20100302749Controlling Warpage in BGA Components in a Re-flow Process - A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.12-02-2010
20100315796CONDUCTIVE MATERIAL, CONDUCTIVE PASTE, CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE - A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal.12-16-2010
20110286192PRINTED WIRING BOARD AND METHOD OF SUPPRESSING POWER SUPPLY NOISE THEREOF - Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.11-24-2011
20120020044ELECTRONIC MODULE WITH VERTICAL CONNECTOR BETWEEN CONDUCTOR PATTERNS - The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.01-26-2012
20120087099Printed Circuit Board For Board-On-Chip Package, Board-On-Chip Package Including The Same, And Method Of Fabricating The Board-On-Chip Package - Provided is a printed circuit board for a board-on-chip package prepared with a strip level of a plurality of unit substrates and including a reject marking portion for determining whether there is a defective unit substrate, wherein the reject marking portion is in each unit substrate.04-12-2012
20130208434FLIP-CHIP MOUNTED MICROSTRIP MONOLITHIC MICROWAVE INTEGRATED CIRCUITS (MMICs) - A microstrip MMIC chip flip-chip mounted to a printed circuit board with conductive vias passing through the chip to electrical connect a ground plane of the microstrip MMIC chip to a ground conductor of the printed circuit board.08-15-2013

Patent applications in class Having semiconductive device