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Voltage responsive

Subclass of:

361 - Electricity: electrical systems and devices

361001000 - SAFETY AND PROTECTION OF SYSTEMS AND DEVICES

361054000 - Load shunting by fault responsive means (e.g., crowbar circuit)

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DocumentTitleDate
20130044398INFORMATION PROCESSING UNIT AND INFORMATION PROCESSING APPARATUS - An information processing unit is disclosed that includes a load circuit, a pair of terminals that are capable of being connected to and removed from a direct current power source, a first capacitor connected between power terminals of the load circuit, a rush current suppressing circuit configured to suppress rush current flowing from the direct current power source to the first capacitor or the load circuit via the terminals, a buffer circuit connected between the terminals and buffers voltage fluctuation between the terminals, a second capacitor connected in series with the rush current suppressing circuit and the first capacitor in a line parallel to the buffer circuit, a switch connected parallel to the second capacitor, and a first controller configured to turn on the switch when a designated period of time is elapsed after hot insertion of the terminals into the direct current power source.02-21-2013
20130044396ELECTROSTATIC DISCHARGE (ESD) PROTECTION ELEMENT AND ESD CIRCUIT THEREOF - An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region and a first N type doped region. The covered shape of the first P type doped region is circular, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and uniformly drains it away.02-21-2013
20130044397ESD PROTECTION CIRCUIT - ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.02-21-2013
20110181991STRUCTURE OF PROTECTION OF AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, including input/output pads and first and second power supply rails, and: a thyristor forward-connected between each input/output pad and the second rail, each thyristor including, between its anode gate and its anode, a resistor; between each thyristor and the first rail, a diode having its anode connected to the anode gate of the thyristor and having its cathode connected to the first rail via a resistor for adjusting the triggering; and a triggering device capable of conducting a current between the first and second rails when a positive overvoltage occurs between these rails.07-28-2011
20120162838ESD PROTECTION DEVICE AND MANUFACTURING METHOD THEREFOR - An ESD protection device includes a ceramic base material including a glass component; opposed electrodes including an opposed electrode on one side and an opposed electrode on the other side, which are arranged to have portions opposed to each other at a predetermined distance in the ceramic base material; and a discharge auxiliary electrode between the opposed electrodes, which is connected to each of the opposed electrode on the one side and the opposed electrode on the other side, and arranged to provide a bridge from the opposed electrode on the one side to the opposed electrode on the other side. A sealing layer to prevent ingress of the glass component from the ceramic base material into the discharge auxiliary electrode is provided between the discharge auxiliary electrode and the ceramic base material.06-28-2012
20120162837PROTECTION CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND DRIVING METHOD THEREFOR - A surge protection circuit comprises a surge detection circuit 06-28-2012
20120162833ESD Protection Devices and Methods - Various embodiments described below relate to an ESD protection device that includes a voltage controlled shunt (e.g., a transistor) to selectively shunt energy of an incoming ESD pulse away from a circuit that includes a semiconductor device to be protected. In some embodiments, the ESD protection device includes a power up detection element to determine whether the circuit has powered up. If the circuit is powered up, the power up detection element prevents inadvertent triggering of the ESD protection device.06-28-2012
20120162831ESD PROTECTION CIRCUIT FOR NEGATIVE-POWERED INTEGRATED CIRCUIT - For a negative-powered IC, an ESD protection circuit includes a negative voltage clamping circuit configured to provide a path for discharging ESD transient currents associated with different negative power supplies of the IC.06-28-2012
20090195951Method and Apparatus for Improved Electrostatic Discharge Protection - An ESD protection circuit having a triggering device, an ESD device and a circuit device coupled between the triggering device and the circuit device such that the circuit device conducts current only in one direction between the ESD device and the triggering device so the ESD device is in an active state for duration longer than time constant of the triggering device.08-06-2009
20090195949INTEGRATED CIRCUIT WITH ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An integrated circuit with an electrostatic discharge protection circuit includes a first power pad, a second power pad, at least a circuit module, and a power clamp circuit. The circuit module includes a signal pad, an internal circuit and a first bipolar transistor. A first parasitical resistance is coupled between a collector of the first bipolar transistor and the second power pad. There is at least a metal-oxide semiconductor (MOS) transistor and at least a first parasitical bipolar transistor included within the power clamp circuit.08-06-2009
20090195948METHODS FOR MAKING A STARTING SUBSTRATE WAFER FOR SEMICONDUCTOR ENGINEERING HAVING WAFER THROUGH CONNECTIONS - The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (08-06-2009
20090195947PROTECTIVE CIRCUIT - A protective circuit connected between a terminal of a semiconductor integrated circuit and ground (GND), comprises: a first diode having an anode connected to the terminal of the semiconductor integrated circuit; a second diode having an anode connected to GND and a cathode connected to the cathode of the first diode; a transistor having a collector or drain connected to the terminal of the semiconductor integrated circuit, and an emitter or source connected to GND; and at least one third diode connected in series in a forward direction from the cathode of the first diode toward the base or gate of the transistor.08-06-2009
20090195945ESD-detector - The invention relates to a method for reducing the adverse effects of electrostatic discharge events occurring in a handheld device. The invention involves the steps of enabling a detector for detection of an electrostatic discharge event in the handheld device, detecting the electrostatic discharge event which has affected the handheld device, generating an event signal in response to the electrostatic discharge event, and applying the event signal to the detector, retrieving status information from circuits and components in the handheld device, analysing the event signal and the status information, and taking an action based on the analysis to mitigate any adverse effects of the detected electrostatic discharge event.08-06-2009
20090195944ELECTROSTATIC DISCHARGE PROTECTION - An electrostatic discharge (ESD) protection device (08-06-2009
20100149703ESD CLAMP CIRCUIT APPLIED TO POWER AMPLIFIER - An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided.06-17-2010
20080259512ELECTROSTATIC DISCHARGE PROTECTION DEVICE HAVING LOW JUNCTION CAPACITANCE AND OPERATIONAL VOLTAGE - An electrostatic discharge protection device includes a power supply line and a ground line. A voltage detection unit detects first and second detection voltages by forming an electrical connection between the power supply line and the ground line in response to alternating current of electrostatic current. A first transfer unit transfers the electrostatic current into the power supply line by forming an electrical connection between the input/output pad and the power supply line in response to the first detection voltage. A second transfer unit transfers the electrostatic current into the ground line by forming an electrical connection between the input/output pad and the ground line in response to the second detection voltage. A discharge unit discharges the electrostatic current flowing into the power supply line or the ground line by forming an electrical connection between the power supply line and the ground line in response to the second detection voltage.10-23-2008
20080259511Stacked ESD Protection Circuit Having Reduced Trigger Voltage - A stacked gate-coupled N-channel field effect transistor (GCNFET) electrostatic discharge (ESD) protection circuit involves a stack of stages. Each stage has an NFET whose body is coupled to its source. A resistor is coupled between the gate and the source. A current path is provided from a supply voltage node to the gate of each NFET such that during an ESD event, a current will flow across the resistor of the stage and induce triggering. In one embodiment, an NFET stage that is isolated from the supply voltage node by and other stage has an associated capacitance structure. During the transient voltage condition of the ESD event, current flows from the supply voltage node, through the capacitance structure and to the gate, and then through the resistor, thereby initiating triggering. The GCNFET ESD protection circuit has a trigger voltage that is less than twenty percent higher than its holding voltage.10-23-2008
20110194218ESD Clamp for High Voltage Operation - An electrostatic discharge (ESD) clamp includes a first power source configured to provide a first power supply voltage, a power supply node coupled to the first power source and receiving the power supply voltage; and a first NMOS transistor and a second NMOS transistor coupled in series and between the power supply node and a VSS node. The first NMOS transistor and the second NMOS transistor are low nominal VDD devices with maximum endurable voltages lower than the power supply voltage. The ESD claim further includes an ESD detection circuit including a capacitor coupled between the power supply node and a gate of the second NMOS transistor, and a resistor coupled between the gate of the second NMOS transistor and the VSS node.08-11-2011
20110194219INTEGRATED CIRCUIT PROVIDED WITH A PROTECTION AGAINST ELECTROSATATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.08-11-2011
20090122452Semiconductor integrated circuit - A semiconductor integrated circuit includes: an output pad from which an output signal is outputted; an output signal line connected with the output pad; a first pad configured to function as a ground terminal or a power supply terminal; a first wiring connected with the first pad; an output driver connected with the output pad and configured to generate the output signal; an ESD protection device connected with the output signal line and having a function to discharge surge applied to the output pad; and a first trigger MOS transistor used as a trigger device. The output driver includes: a first protection target device connected between the output signal line and the first interconnection; and a first resistance element connected between the first protection target device and the first interconnection. The first trigger MOS transistor configured to detect a voltage generated in the first resistance element by a gate of the first trigger MOS transistor and to allow the ESD protection device operate in response to the detected voltage.05-14-2009
20090122451ESD PROTECTION CIRCUIT DEVICE - The present invention discloses an ESD (ELECTRO-STATIC DISCHARGE) protection circuit device, the ESD (ELECTRO-STATIC DISCHARGE) protection circuit device includes a first switching device having a first terminal coupled to a first signal; a first control device coupled to the first signal for generating a first control signal according to the first signal; a second switching device having a first terminal coupled to a second signal, a second terminal coupled to a second terminal of the first switching device; and a second control device coupled to the second signal and a control terminal of the first switching device for generating a second control signal according to the second signal; wherein the first control signal coupled to the control terminal of the second switching device, and the second control signal coupled to the control terminal of the first switching device.05-14-2009
20130077199ESD PROTECTION DEVICE - A highly reliable ESD protection device that prevents failure of discharge and variation of a discharge start voltage even when protection from static electricity is repeatedly performed includes a cavity provided in a ceramic multilayer substrate. First and second discharge electrodes are provided in the ceramic multilayer substrate and face each other across a gap. A tip of the first discharge electrode and a tip of the second discharge electrode are positioned at edges of the cavity or at positions receded from the edges.03-28-2013
20130077198Voltage Surge and Overvoltage Protection Using Prestored Voltage-Time Profiles - Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. A series inductance separates the first and second voltage clamping devices. Also, a switching element is employed to selectively establish a direct coupling of the input power to the electrical load, where a circuit is employed to control the operation of the switching element.03-28-2013
20130077197ESD CLAMP ADJUSTMENT - Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.03-28-2013
20130077196ESD Robust Level Shifter - An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.03-28-2013
20130077195ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT - An electrostatic discharge (ESD) protection circuit includes a clamping transistor and a trigger circuit. The clamping transistor is coupled between a first power supply voltage terminal and a second power supply voltage terminal. The trigger circuit includes a detection circuit, first and second transistors, and first, second, and third inverters. The detection circuit is coupled to monitor a power supply voltage. The first inverter has an input terminal coupled to a current electrode of the first transistor, and an output terminal coupled to a control electrode of the clamping transistor. The second inverter and the third inverter form a feedback path from the output of the first inverter to the control electrode of the first transistor. The second inverter has a switching voltage that is lower than a midpoint voltage of a power supply voltage provided to the first and second power supply voltage terminals.03-28-2013
20100157493ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An integrated circuit includes an electrostatic discharge (ESD) detection circuit which detects an ESD event and generates an event signal. In response to that event signal, a control circuit controls the operation of a buffer circuit to function in an additional mode wherein the normal differential operation of the buffer circuit is disabled and the buffer circuit is instead configured to form a conduction path between supply rails to discharge the ESD event. Preferably, a plurality of buffer circuits are driven in parallel by the control circuit to function in the additional mode to form parallel discharge paths for the ESD event. Multiple ESD detection circuits may be provided, and any one of those detection circuits can trigger the control circuitry to place all of the buffer circuits in the additional mode.06-24-2010
20100073835REMOTE SENSING CIRCUIT AND HIGH-POWER SUPPLY APPARATUS HAVING THE SAME - A remote sensing circuit and a high-power supply apparatus having the remote sensing circuit. The high-power supply apparatus can include a feedback circuit to feedback power output from a high-power supply unit to an input terminal of the high-power supply apparatus. The remote sensing circuit can include a switching unit connected between an output terminal of the high-power generating unit and the feedback circuit of the high-power supply apparatus to open the connection in a normal status and to close the connection in an abnormal status, a load channel to connect the high-power generating unit and a load, and a remote sensing unit having one terminal commonly connected to the load and the load channel and another terminal commonly connected to the switching unit and the feedback circuit to sense power supplied to the load.03-25-2010
20100073833CIRCUIT APPARATUS HAVING ELECTROSTATIC DISCHARGE PROTECTION FUNCTION - A circuit apparatus having an electrostatic discharge (ESD) protection function includes a first circuit module, a second circuit module, and a thick-oxide transistor. The first circuit module operates in a first power supply domain and includes at least a first transistor. The second circuit module operates in a second power supply domain different from the first power supply domain and includes at least a second transistor. The thick-oxide transistor has a control terminal for receiving a control signal, a first terminal coupled to the first circuit module, and a second terminal coupled to the second circuit module, and the thick-oxide transistor is utilized for selectively performing an ESD protection operation according to the control signal.03-25-2010
20100073834Electrostatic discharge (ESD) protection circuit and method - There is disclosed an electrostatic discharge (ESD) protection device and method. An electronic device (03-25-2010
20090219657Trenched mosfets with improved gate-drain (GD) clamp diodes - A method for operating a semiconductor power device by in a forward conducting mode instead of an avalanche mode during a voltage fly-back during an inductive switch operation for absorbing a transient energy with less stress. The method includes a step of clamping the semiconductor power device with a Zener diode connected between a gate metal and a drain metal of the semiconductor power device to function as a gate-drain (GD) clamp diode with the GD clamp diode having an avalanche voltage lower than a source/drain avalanche voltage of the semiconductor power device whereby as the voltage fly-back inducing a drain voltage increase rapidly reaching the avalanche voltage of the GD clamp diode for generating the forward conducting mode.09-03-2009
20130083436ELECTROSTATIC DISCHARGE PROTECTION - A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip.04-04-2013
20130083437ESD DETECTION CIRCUIT AND ESD ELIMINATION DEVICE - An ESD elimination device includes an ESD elimination circuit connected between a power line and a ground line and an ESD detection circuit. The ESD detection circuit includes a switch unit and a resistor, the switch unit and the resistor are electrically connected between the power line and the ground line. The switch unit is turned on when an ESD event occurs in the power line, a detecting voltage is generated across the resistor when the switch unit is turned on, the detecting voltage is used for triggering the ESD elimination circuit to eliminate the ESD surge current caused by the ESD event.04-04-2013
20130038970SURGE PROTECTED DEVICES AND METHODS FOR TREATMENT OF WATER WITH ELECTROMAGNETIC FIELDS - Devices for treating water are provided with a varistor to protect the circuitry within such devices against excessive voltage surges and/or transient voltages. The varistor is incorporated into the circuitry in such a way that, when triggered by a high voltage spike (e.g., power surge), the varistor shunts the current created by the high voltage spike away from other sensitive components of the circuitry. Methods for treating water using devices that incorporate the varistor are also provided.02-14-2013
20100046130CIRCUIT PROTECTION DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a circuit protection device and a method of manufacturing the same. The circuit protection device includes a common mode noise filter having a plurality of sheets, each of the sheets being formed to optionally include a coil pattern, an internal electrode, a hole filled with a conductive material, and a hole filled with a magnetic material; and an electrostatic discharge (ESD) protection device having a plurality of sheets, each of the sheets being formed to optionally include an internal electrode and a hole filled with an ESD protection material. According to the present invention, a solenoid-type common mode noise filter and an ESD protection device are laminated as a single device, and thereby common mode noises and ESD of the electronic device can be simultaneously prevented. Accordingly, the circuit protection device has a simple configuration as compared with a conventional art in which discrete devices are used to prevent common mode noises and ESD, so that an increase in size of an electronic device can be prevented, and input/output signal distortion can be prevented to thereby enhance the reliability of the electronic device.02-25-2010
20090154037DESIGN STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION FOR BIPOLAR SEMICONDUCTOR CIRCUITRY - A design structure for electrostatic discharge protection comprises a first data representing a first electrostatic discharge (ESD) protection circuit and a second data representing a second ESD protection circuit. A parallel connection of two ESD protection units, each providing a discharge path for electrical charges of opposite types, provides ESD protection circuit for positive and negative voltage swings in the circuit. Each of the multiple emitter-base regions are cascoded such that the base of one emitter-base region is directly wired to the emitter of an adjacent emitter-base region. The first data represents a first ESD protection unit providing protection on one type of voltage swing, and the second data represents a second ESD protection unit providing protection on the other type of voltage swing.06-18-2009
20100103571ESD PROTECTION FOR FIELD EFFECT TRANSISTORS OF ANALOG INPUT CIRCUITS - During an ESD event, an ESD current flows from a ground node of a first ESD protection circuit and out of an integrated circuit to a terminal of a package that houses the integrated circuit. To improve ESD performance, a second ESD protection circuit is provided. A diode of the second ESD protection circuit is coupled between the ground node and the body of an input transistor of a Low Noise Amplifier (LNA). If the voltage on the ground node changes quickly during an ESD event (for example, due to a current spike flowing across a wire bond), then the diode charges the body of the transistor, thereby preventing a large gate-to-body voltage from developing across transistor. In some embodiments, another ground bond pad is provided and the second ESD protection circuit includes other diodes that charge or discharge other nodes during the ESD event to prevent transistor damage.04-29-2010
20090168282ESD PROTECTION CIRCUIT - An ESD protection circuit includes: a voltage decreasing module, coupled between a first voltage level and a second voltage level, wherein the first voltage level is higher than the second voltage level; a gate trigger switch, coupled between the first voltage level and the second voltage level; and a detection circuit, coupled to the gate trigger switch, for detecting an ESD event to control the gate trigger switch.07-02-2009
20080278872Electrostatic Discharge Protection Circuit - Techniques pertaining to designs of ElectroStatic Discharge (ESD) protection circuits are disclosed. In one embodiment, an ESD protection circuit combines a substrate-driving technique with a gate-driving technique to ease the ESD design and save the silicon area. In another embodiment, an ESD protection circuit is based on a Positive Metal Oxide Semiconductor field effect transistor (PMOS) in a standard Complementary Metal Oxide Semiconductor (CMOS) process. In another embodiment, the ESD protection circuit is based on a negative Metal Oxide Semiconductor field effect transistor (NMOS) in the standard CMOS process. Depending on implementation, the ESD protection circuit is implemented for a negative voltage input pin, a normal input pin, and a power supply clamp circuit.11-13-2008
20100110596ELECTROSTATIC DISCHARGE PROTECTION - An integrated circuit (05-06-2010
20090040670Diode Chain with a Guard-Band - The present invention provides an ESD protection device having at least one diode in a well of first conductivity type formed in a substrate of second conductivity type. The circuit further includes a guard band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between diode cathode, the substrate and the guard-band.02-12-2009
20090154036Electrostatic discharge circuit - The invention discloses an electrostatic discharge circuit. The spirit of the invention is that the electrostatic common portion in the conventional integrated circuit is divided into at least two sets corresponding to at least two internal common voltages, separately. In addition, the electrostatic common portions use serily connected diode rings. Therefore, the number of diodes of the diode rings coupling to the higher common voltage and the electrostatic common portion, coupling to the higher common voltage, can be reduced.06-18-2009
20090154035ESD Protection Circuit - A circuit arrangement includes an ESD protection circuit for protecting a circuit node of the circuit arrangement against electrostatic discharge. The circuit arrangement includes a control circuit configured to deactivate the ESD protection circuit in response to a state signal representing a state of operation of the circuit arrangement.06-18-2009
20090154034MOTOR DRIVE WITH LOW LEAKAGE SURGE PROTECTION - A motor drive employs a combination of gas discharge tubes and metal oxide varistors to create precisely tailored surge protection that has a low leakage current minimizing the triggering of ground fault detection circuitry when multiple motor drives are attached to a single line source.06-18-2009
20090154038IMPEDANCE COMPENSATED ESD CIRCUIT FOR PROTECTION FOR HIGH-SPEED INTERFACES AND METHOD OF USING THE SAME - The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.06-18-2009
20090154039OVERVOLTAGE PROTECTION CIRCUIT AND ELECTRONIC DEVICE COMPRISING THE SAME - An overvoltage protection circuit prevents a voltage higher than an allowable voltage value from being supplied to a predetermined to-be-protected circuit. A voltage is applied from outside to an input end 06-18-2009
20130027824SEMICONDUCTOR DEVICE - A semiconductor device comprises a first power supply system, a second power supply system, an output circuit, a first driving circuit and a first protection. The first power supply system is configured with a first power supply voltage and a first ground voltage. The second power supply system is configured with a second power supply voltage and a second ground voltage. The output circuit receives a power supply from the second power supply system. The first driving circuit receives a power supply from the first power supply system and outputs a signal for driving the output circuit. One end of the first protection element is connected to an output node of the output circuit and the other end is connected to the first ground voltage.01-31-2013
20130027825METHODS AND APPARATUS RELATED TO AN INDUCTIVE SWITCHING TEST - In one general aspect, an apparatus can include an energy storage device configured to store energy during an unclamped inductive switching test of a target device, and a switch device configured to shunt at least a portion of energy away from the target device in response to the target device changing from a breakdown state to a failure state.01-31-2013
20130027823ELECTRIC APPARATUS WITH ESD PROTECTION EFFECT - An electric apparatus with ESD protection effect is provided. The electric apparatus comprises a high-side unit, a low-side unit, and a level shifter. The high-side unit comprises a first pad and a second pad. The low-side unit comprises a third pad and a fourth pad. The level shifter is connected between the first pad and the fourth pad. The level shifter comprises a first resistor, a clamp element, a second resistor, and an N-type transistor. The first resistor is connected between the first pad and a first node. The clamp element is connected between the first pad and a second node. The second resistor is connected between the first node and the second node. The N-type transistor has a source and a body connected to the fourth pad, a drain connected to the first node, and a gate connected to the low-side unit.01-31-2013
20130027822CIRCUITS INCLUDING A DIODE STRING COMPRISED OF BIPOLAR STAGES HAVING AN ADJUSTABLE PSEUDO BETA FOR ESD PROTECTION - A circuit includes an input terminal and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode string formed from a plurality of P-N junction devices arranged in series. The diode string includes an input coupled to the input terminal and includes at least one output coupled to a power supply terminal. The circuit further includes a plurality of shunt elements. Each of the plurality of shunt elements includes a first terminal coupled to one of the plurality of P-N junction devices and a second terminal coupled to the power supply terminal. Each of the plurality of shunt elements is controllable to selectively couple the one of the plurality of P-N junction devices to the power supply terminal to distribute current flow across the diode string in response to an ESD event.01-31-2013
20130027821ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch.01-31-2013
20130027820Electrostatic discharge protection device having an intermediate voltage supply for limiting voltage stress on components - An electrostatic protection apparatus is disclosed that has a voltage level supply configured to supply a voltage level to an electrostatic discharge protection device and the electrostatic discharge protection device that protects a semiconductor electronic device from a rapidly increasing incoming current. The voltage level supply comprises: a voltage divider arranged between high and low voltage rails for supplying an intermediate voltage level to the electrostatic protection device such that a voltage drop across at least some devices within the electrostatic protection device is limited by the intermediate voltage level; a detection device for detecting a signal received from said electrostatic discharge protection device indicating the electrostatic discharge protection device has received the rapidly increasing incoming current; a switching device responsive to the signal to switch the voltage level supplied to the electrostatic discharge protection device from the intermediate voltage level to a voltage level of one of the voltage rails.01-31-2013
20120212865ESD BLOCK ISOLATION BY RF CHOKE - A circuit includes a first node configured to receive a radio frequency (“RF”) signal, a first electrostatic discharge (ESD) protection circuit coupled to a first voltage supply rail for an RF circuit and to a second node, and a second ESD protection circuit coupled to the second node and to a second voltage supply node for the RF circuit. An RF choke circuit is coupled to the second node and to a third node disposed between the first node and the RF circuit.08-23-2012
20090128969ADAPTIVE ELECTROSTATIC DISCHARGE (ESD) PROTECTION OF DEVICE INTERFACE FOR LOCAL INTERCONNECT NETWORK (LIN) BUS AND THE LIKE - Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capa citive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.05-21-2009
20130083439HIGH-FREQUENCY MODULE - A high-frequency module includes an inductor and an ESD protection element. The inductor is a circuit element defining a low pass filter, and includes parasitic capacitance between a signal line and a ground in a specific frequency band. The ESD protection element transfers a surge current flowing through a signal line to the ground, includes a capacitor in a specific frequency band, and has a configuration in which the capacitor and the parasitic capacitance of the inductor are connected in parallel.04-04-2013
20130083440OVERVOLTAGE PROTECTION COMPONENT, AND OVERVOLTAGE PROTECTION MATERIAL FOR OVERVOLTAGE PROTECTION COMPONENT - An overvoltage protector includes a first discharging electrode, a second discharging electrode, and an overvoltage protection part provided between the first and second discharging electrodes. The overvoltage protecting part has an insulating property under a normal operation condition, and has a conductive property if an overvoltage is applied between the first and second discharging electrodes. The overvoltage protecting part is made of a mixture of resin having an insulation property, an inorganic compound having an insulating property, and metallic boride compound powder. The metallic boride compound powder has a high melting point therefore it is hardly melted. Under high temperatures causing the powder to melt, the powder is oxidized and loses conductivity, thus providing a high reliability.04-04-2013
20130083438ESD Protection for FinFETs - An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.04-04-2013
20120182654ESD PROTECTION CIRCUIT - ESD protection circuit is provided, which includes a detection circuit, a trigger circuit and a clamp circuit. The detection circuit includes two stacked capacitors reflecting occurrence of ESD events. The trigger circuit includes three stacked transistors controlling triggering of the clamp circuit according to operation of the detection circuit. The clamp circuit includes two stacked transistors conducting ESD path when triggered.07-19-2012
20120182653SEMICONDUCTOR MODULE AND SYSTEM INCLUDING THE SAME - A semiconductor module includes a printed circuit board, at least one on-board device unit coupled between at least one voltage line and a power line. The at least on-board device unit is mounted on the printed circuit board. At least one electrostatic discharge protection circuit unit, configured to protect the at least one on-board device unit from an electrostatic discharge that occurs in the at least one voltage line, is coupled to the at least one voltage line.07-19-2012
20120182652ESD PROTECTION STRUCTURE - An electrostatic discharge (ESD) protection structure is provided, which includes a bonding pad, a body, an insulation layer, a first doped region and a via. The body is a first conductive type, while the first doped region is a second conductive type. The bonding pad is disposed on the body. The insulation layer is disposed between the body and the bonding pad. The first doped region is disposed in the body, and in view direction along the vertical projection of the body, all of the bonding pad is disposed in the first doped region. The via is disposed between the first doped region and the bonding pad. The bonding pad is electrically connected to the first doped region through the via.07-19-2012
20120182651Shared Electrostatic Discharge Protection For Integrated Circuits, Integrated Circuit Assemblies And Methods For Protecting Input/Output Circuits - A method for protecting input/output (I/O) circuits on an integrated circuit (IC) from electrostatic discharge (ESD) is disclosed. The method includes the steps of providing at least one protective device on a surface of a first semiconductor die and applying a conductive shorting layer over a select region of the surface to electrically couple at least one metallic stud to the at least one protective device. After bonding the IC die to a second IC die and/or testing one or more core circuits, the conductive shorting layer is removed to enable high-speed I/O connections arranged in the select region of the semiconductor die. An IC assembly includes first and second semiconductor dice. One of the dice includes a protective device along a surface. An electrically conductive shorting layer couples the protective device to a conductive element that is further coupled to I/O circuit elements.07-19-2012
20130070376ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND ELECTROSTATIC DISCHARGE PROTECTION METHOD - An ESD protection circuit and method for its use are provided. The circuit comprising: a discharge path formed by first and second NMOS transistors which are sequentially connected between a ground and a power supply; an ESD event detection unit; first and second drive units respectively connected between an output of the ESD event detection unit and a gate of the first transistor and between the output of the ESD event detection unit and a gate of the second transistor. The first and second drive units respectively cause the first and second transistors to be turned on during an ESD event and to be turned off when there is no ESD event.03-21-2013
20130050885ESD PROTECTION TECHNIQUES - Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit that is electrically connected to first and second circuit nodes from an ESD event. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including first and second ESD detection elements arranged thereon. The ESD protection device also includes first and second voltage bias elements having respective inputs electrically connected to respective outputs of the first and second ESD detection elements. A second electrical path extends between the first and second circuit nodes and is in parallel with the first electrical path. The second electrical path includes a voltage controlled shunt network having at least two control terminals electrically connected to respective outputs of the first and second voltage bias elements. Other embodiments are also disclosed.02-28-2013
20130050886OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS - Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.02-28-2013
20130050884ELECTROSTATIC DISCHARGE (ESD) PROTECTION ELEMENT AND ESD CIRCUIT THEREOF - An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region, a first isolation structure and a first N type doped region. The first isolation structure is disposed inside the first P type doped region, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and drains it away, and the parasitical capacitance of the P type ESD protection element decreases based on the area of the first P type doped region.02-28-2013
20130088800ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.04-11-2013
20130088801ELECTROSTATIC DISCHARGE PROTECTION APPARATUS - An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.04-11-2013
20100134936CIRCUIT FOR PROTECTING ELECTRICAL AND/OR ELECTRONIC SYSTEM BY USING ABRUPT METAL-INSULATOR TRANSITION DEVICE AND ELECTRICAL AND/OR ELECTRONIC SYSTEM COMPRISING THE CIRCUIT - Provided are an electrical and/or electronic system protecting circuit using an abrupt metal-insulator transition (MIT) device which can effectively remove high-frequency noise with a voltage greater than a rated standard voltage received via a power line or a signal line of an electrical and/or electronic system, and the electrical and/or electronic system including the electrical and/or electronic system protecting circuit. The abrupt MIT device of the electrical and/or electronic system protecting circuit abrupt is connected in parallel to the electrical and/or electronic system to be protected from the noise. The electrical and/or electronic system protecting circuit bypasses toward the abrupt MIT device most of the noise current generated when the voltage greater than the rated standard voltage is applied, thereby protecting the electrical and/or electronic system.06-03-2010
20090296295Power-rail ESD protection circuit with ultra low gate leakage - An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.12-03-2009
20090303645INTEGRATED CIRCUIT - An integrated circuit aims to decrease a parasitic resistance between an input protection circuit cell and a power supply cell including a clamp circuit, restrain a size of a diode from increasing beyond ESD robustness of the diode itself in order to compensate for a decrease in the ESD robustness, and prevent high-frequency signal power from decreasing due to a large capacitance component from a diode in an input protection circuit and a parasitic resistance component from a series resistor. The input protection circuit cell includes: an input terminal coupled to a signal pin; an output terminal coupled to not only a high-frequency circuit but also the input terminal and a node; a diode that is provided between the node and VDD and makes an electric current flow from the node to VDD; another diode that is provided between the node and GND and makes an electric current flow from GND to the node; and a clamp circuit coupled between VDD and GND parallel to the diodes.12-10-2009
20090303644ELECTROSTATIC DISCHARGE PROTECTED DEVICE - An electrostatic discharge (ESD) protected device includes a device (12-10-2009
20090040668ESD PROTECTION CIRCUITS FOR MIXED-VOLTAGE BUFFERS - An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.02-12-2009
20090091870ESD AVOIDING CIRCUITS BASED ON THE ESD DETECTORS IN A FEEDBACK LOOP - When an electrostatic discharge event occurs to a connection pad of a chip, an electrostatic discharge detector layout in a feedback loop is able to detect an induced electrostatic discharge voltage for generating a control signal. A pass transistor can be turned off by the control signal for isolating the induced electrostatic discharge voltage, and the internal circuit of the chip can be protected from being damaged by the induced electrostatic discharge voltage. Furthermore, the designed circuit based on electrostatic discharge isolation technique for protecting the internal circuit of the chip is compatible with programmable circuits, and the connection pad can be furnished with burning signals or logic signals.04-09-2009
20130057994ELECTRONIC DEVICE AND BOARD USABLE IN THE ELECTRONIC DEVICE - An electronic device includes an exterior portion of a conductive material, a circuit portion including circuit elements, and a protection circuit portion connected between the exterior portion and the circuit portion. The protection circuit portion includes a switching unit to intercept leakage current that flows from the circuit portion and leaks to the exterior portion, and a conversion unit to reduce a voltage level of an electrostatic component that flows through the exterior portion and to transfer the electrostatic component to the switching unit.03-07-2013
20130057993SEMICONDUCTOR INTEGRATED CIRCUIT AND PROTECTION CIRCUIT - Disclosed herein is a semiconductor integrated circuit including: a clamp MOS transistor having a drain region and a source region connected to a power source wiring and a grounding wiring, respectively, and causing a surge current to flow through a channel path and a bipolar path between the drain region and the source region; a first trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a gate terminal of the clamp MOS transistor, and controlling switching for the channel path; a second trigger circuit portion provided between the power source wiring and the grounding wiring, connected at an output terminal thereof to a well region of the clamp MOS transistor, and controlling switching for the bipolar path; and an internal circuit connected to each of the power source wiring and the grounding wiring.03-07-2013
20130057992ESD PROTECTION CIRCUIT - An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.03-07-2013
20130057991SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL - Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.03-07-2013
20090290271Multi-chip module package including external and internal electrostatic discharge protection circuits, and/or method of making the same - Certain example embodiments disclosed herein relate to multi-chip module (MCM) packages that include external and internal electrostatic discharge (ESD) protection circuits, and/or methods of making the same. In certain example embodiments, ESD protection circuits are located under the IO pads in the MCM package, the size of the internal dies' ESD circuits are reduced (e.g., by making them as small as possible in certain example implementations), and high-immunity ESD circuits are provided to the IO pads where they are exposed to the external environment. The external ESD protection circuits may provide a higher level of voltage protection than the internal ESD protection circuits. Thus, the external ESD protection circuits may provide shock protection from human body model shocks, whereas the internal ESD protection circuits may provide protection from machine or assembly model shocks.11-26-2009
20100128403System for ESD Protection with Extra Headroom in Relatively Low Supply Voltage Integrated Circuits - An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 05-27-2010
20110013326INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION - A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.01-20-2011
20110013325ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION - Disclosed is an improved electrostatic discharge protection device that can effectively cope with electrostatic stress of a microchip operating at high voltage. The ESD protection device includes at least one gate coupled NMOS (GCNMOS) having a gate connected to a drain via a capacitor disposed between the gate and the drain and connected to a source and a well to pick-up via a resistor, and devices for low or medium voltage operation of 6V or less connected in series to the gate coupled NMOS (GCNMOS).01-20-2011
20090268360PROTECTION CIRCUIT - In a protection circuit for protecting semiconductor integrated circuit devices from an electrostatic breakdown or a latch-up due to an external surge, etc, a drain terminal of a PMOS transistor MP10-29-2009
20090268359ELECTROSTATIC DISCHARGE POWER CLAMP WITH IMPROVED ELECTRICAL OVERSTRESS ROBUSTNESS - An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) and electrical overstress (EOS) events includes a resistor/capacitor (RC) triggering device configured between a pair of power rails; a silicon controlled rectifier (SCR) triggered by the RC triggering device during an ESD event, wherein the SCR, when activated, acts as a power rail voltage clamp; and a field effect transistor (FET) coupled between the RC triggering device and the SCR, wherein the FET serves as an integrated part of the RC triggering device that triggers the SCR during the ESD event; and wherein the FET also operates in a snapback mode to trigger the SCR during an EOS event that is slower in comparison to the ESD event such that the EOS event would not otherwise cause triggering of the SCR via the RC triggering device itself.10-29-2009
20090268358METHOD AND APPARATUS FOR SWITCHED ELECTROSTATIC DISCHARGE PROTECTION - One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.10-29-2009
20090268357Hybrid ESD Clamp - A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode (10-29-2009
20120224285ELECTROSTATIC DISCHARGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The invention is achieved by applying a layer of the mixture that contains polymer and conductive particles over a first surface, when the mixture has a first viscosity that allows the conductive particles to rearrange within the layer. An electric field is applied over the layer, so that a number of the conductive particles are aligned with the field and thereafter the viscosity of the layer is changed to a second, higher viscosity, in order to mechanically stabilise the layer. This leads to a stable layer with enhanced and anisotropic conductivity that can be used in the manufacture of ESD devices.09-06-2012
20120224284DISTRIBUTED BUILDING BLOCKS OF R-C CLAMPING CIRCUITRY IN SEMICONDUCTOR DIE CORE AREA - A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die, The building blocks include at least one capacitor block in the core area, The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.09-06-2012
20130063843ESD PROTECTION FOR 2.5D/3D INTEGRATED CIRCUIT SYSTEMS - An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.03-14-2013
20130063846ESD Protection Device With Reduced Clamping Voltage - Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q03-14-2013
20130063845OVERVOLTAGE PROTECTION EQUIPMENT - Overvoltage protection equipment may include: a first connection; a second connection; a first discharge path disposed between the first and the second connections, wherein the first discharge path comprises a spark gap; a second discharge path disposed between the first and the second connections, wherein the second discharge path comprises a triggerable circuit breaker and a thermistor connected in series; and a control device that induces the triggerable circuit breaker to switch on, based on at least one of a state or a state path of the first discharge path as a result of a discharge event.03-14-2013
20130063844Load Switch with True Reverse Current Blocking - Devices, systems and methods are provided for switching a load with true reverse current blocking (TRCB). The device may include an input port coupled to a supply voltage; an output port coupled to the load; a TRCB circuit coupled to the input port and the output port; and a switch control port coupled to the TRCB circuit. The TRCB circuit may be configured to couple the input port to the output port in response to a switch close signal applied to the switch control port and to de-couple the input port from the output port in response to a switch open signal applied to the switch control port. The TRCB circuit may further be configured to block current flow from the output port to the input port in response to both the switch open signal and the switch close signal.03-14-2013
20100123984ESD PROTECTION CIRCUIT AND CIRCUITRY OF IC APPLYING THE ESD PROTECTION CIRCUIT - A circuitry of an IC is provided, including a pad, an internal circuit, and an ESD protection circuit. The pad transmits or receives a signal and is coupled to a first node. The internal circuit is coupled to the first node for processing the signal. The ESD protection circuit includes an ESD clamping circuit, a first current limiting and shunting unit and a second current limiting and shunting unit. The ESD clamping circuit is coupled to the first node, for clamping an ESD current flowing through the first node. The first current limiting and shunting unit is through the first node coupled to the pad, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second current limiting and shunting unit is coupled to the first current limiting and shunting unit, for limiting the ESD current and shunting part of the ESD current to a second voltage path.05-20-2010
20090244795DEVICE FOR A REMOTE MONITORING THE STATE OF AT LEAST A SINGLE-POLE SURGE PROTECTION - The invention relates to a device for a remote monitoring the state of at least a single-pole surge protection which consists of a bracket (10-01-2009
20130163129ELECTROSTATIC DISCHARGE (ESD) PROTECTION AND OPERATING METHOD THEREOF - An electrostatic discharge (ESD) protection circuit includes a clamp transistor, and inverter, a resistance-capacitance (RC) circuit, and a current mirror. The clamp transistor is coupled between a first supply node and a second supply node. The inverter has an input end and an output end, and the output end of the inverter is coupled with a gate of the clamp transistor. The RC circuit is coupled to the first supply node. The current mirror includes a first transistor and a second transistor. The first transistor is coupled between the input end of the inverter and the second supply node, and the second transistor is coupled between the RC circuit and the second supply node.06-27-2013
20130163131ELECTRONIC COMPONENT PROTECTION POWER SUPPLY CLAMP CIRCUIT - Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering. This also lengthens the time that the clamp circuit remains in the ESD-triggered state during human body model (HBM) or other long duration detected ESD events.06-27-2013
20130163126HIGH-SWING DIFFERENTIAL DRIVER USING LOW-VOLTAGE TRANSISTORS - A differential line driver with N-paralleled slices for driving an impedance-matched transmission line. Each driver slice is a modified H-bridge driver using low-voltage, high-speed transistors. By using a voltage-dropping first resistor in each slice, a high-voltage power supply that would normally damage the transistors can be used to power the driver and produce a differential output signal with peak-to-peak amplitudes that otherwise might not be possible. Each transistor in each driver slice has a resistor disposed between the transistor and the respective output node of the driver to enhance ESD protection of the transistors and, in combination with the first resistor, to impedance match the driver to the transmission line.06-27-2013
20130163127ESD PROTECTION CIRCUIT - An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other.06-27-2013
20130163128HIGH HOLDING VOLTAGE, MIXED-VOLTAGE DOMAIN ELECTROSTATIC DISCHARGE CLAMP - An electrostatic discharge (ESD) protection circuit is disclosed including at least a clamping device, a switching device, and a voltage limiter. The ESD protection circuit may include devices of different voltage domains. The switching device may be in series with the clamping device to block at least a portion of a voltage from dropping across the clamping device. The switching device may sustain higher maximum operating voltages than the clamping device.06-27-2013
20090237849Apparatus for preventing surge - The apparatus for preventing surge comprises a bypass element and a capacitor. The bypass element is disposed in an encapsulated circuit, where the encapsulated circuit has a core circuit, wherein one end of the bypass element is electrically coupled with a direct current power supply and another end of the bypass element is electrically coupled with the core circuit. The capacitor is electrically coupled with said another end of the bypass element, where the encapsulated circuit is disposed between the direct current power supply and the capacitor.09-24-2009
20090237847STACKED SCR WITH HIGH HOLDING VOLTAGE - Stacked SCR's are disclosed with a resistor connecting an internal portion of the upper SCR to an internal portion of the lower SCR. The anode of the protective circuit is connected to a contact on a target circuit to be protected and the cathode of the protective circuit is connected to ground or a reference voltage on the target circuit. The anode voltage is directed to the lower SCR via the resistor such that when the voltage on the anode reaches the triggering voltage of the lower SCR, that SCR triggers and that triggering triggers the upper SCR, such that the stacked SCR's both trigger and thereby limit the voltage between the anode and the cathode and thereby protecting the target circuit.09-24-2009
20090237846ESD PROTECTION CIRCUIT AND METHOD THEREOF - The present invention provides an ESD protection circuit, including: a first protecting circuit coupled between a first pad and a second pad, the first protecting circuit including a first discharge transistor; and a second protecting circuit coupled to the first pad and the second pad, the second protecting circuit including a second discharge transistor. One of the first and second discharge transistors is a high-voltage component, and the other of the first and second discharge transistors is a low-voltage component.09-24-2009
20090231766ELETROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING - A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.09-17-2009
20090161274ELECTROSTATIC DISCHARGE PREVENTION CIRCUITS - An ESD prevention circuit is provided. The ESD prevention circuit comprises a voltage source, a charge-blocking unit, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and an output unit. The charge-blocking unit is coupled to the voltage source and provides a reverse voltage to control the voltage source to remain at a zero potential when an electrostatic voltage is being generated. The first PMOS transistor is coupled to the charge-blocking unit. The first NMOS transistor is coupled to the first PMOS transistor. The second NMOS transistor is coupled to the first PMOS transistor and the first NMOS transistor. The output unit is coupled to the second NMOS transistor. The electrostatic voltage is affected by the charge-blocking unit and does not raise impendence of the turned-on second NMOS transistor.06-25-2009
20090009917ELECTROSTATIC DISCHARGE DEVICE - An electrostatic discharge device includes a first protection element including a MOS transistor type first diode, which provides a first capacitor including a first insulation layer, and provides a first path between an input/output pad and a power supply voltage line using the first diode, for discharging static electricity, a second protection element providing a second path between the input/output pad and a ground voltage line for discharging the static electricity, a trigger circuit including a resistor that is connected in series to the first capacitor, and a power clamp element providing a third path for discharging the static electricity between the power supply voltage line and the ground voltage line by a voltage applied to the resistor.01-08-2009
20090268361Transient voltage suppressor (TVS) with improved clamping voltage - This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.10-29-2009
20120113553SYSTEMS AND METHODS FOR ESD PROTECTION FOR RF COUPLERS IN SEMICONDUCTOR PACKAGES - ESD (electrostatic discharge) protection for radio frequency (RF) couplers included in the same semiconductor package as other integrated circuits, such as integrated circuits having power amplifier (PA) circuitry, is disclosed along with related systems and methods. The disclosed embodiments provide ESD protection for RF couplers within semiconductor packages by including coupler ESD circuitry within an integrated circuit within the semiconductor package and coupling the connection ports of the RF coupler to this coupler ESD circuitry. Further, this coupler ESD circuitry can be implemented using two sets of serially connected diodes so that the signal connected to the coupler ESD circuitry can swing around ground without being clipped by the ESD circuitry. Still further, the ESD diodes can be formed in deep N well structures to improve isolation and to reduce parasitic capacitance associated with the ESD diodes.05-10-2012
20120236450ESD PROTECTION DEVICE AND METHOD FOR PRODUCING THE SAME - An electro-static discharge protection device includes a substantially rectangular parallelepiped base in which insulating ceramic layers are laminated, a pair of discharge electrodes that are located inside the base and that include facing portions facing each other, and outer electrodes that are located on surfaces of the base and that are electrically connected to the discharge electrodes. The base includes a cavity therein, and the facing portions of the discharge electrodes are exposed in the cavity. The base has an hourglass shape in which the thickness of the insulating ceramic layers is gradually decreased from an area near both ends of the base to a central portion thereof with respect to both a longitudinal cross section passing through the center in the longitudinal direction of the base and a lateral cross section passing through the center in the lateral direction of the base.09-20-2012
20120236449ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR COMPOUND SEMICONDUCTOR DEVICES AND CIRCUITS - An apparatus and method is disclosed for providing an electrostatic discharge protection circuit for compound semiconductor devices and circuits. The electrostatic discharge protection circuit comprises a first terminal and a second terminal. The electrostatic discharge protection circuit further comprises a transistor shunt element that is operably coupled between the first terminal and the second terminal; the transistor shunt element is capable of providing a bi-directional discharge path between the first terminal and the second terminal. The electrostatic discharge protection circuit further comprises a shut-off element that is operably coupled with the second terminal; the shut-off element is capable of keeping the transistor shunt element turned-off.09-20-2012
20120236448SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a first electrostatic protection circuit is connected between a first power supply wire and a second power supply wire, a second electrostatic protection circuit is connected between the first power supply wire and a third power supply wire, a first transistor is connected between the second power supply wire and the third power supply wire, a gate control circuit controls a gate potential of the first transistor based on a detection result of a second voltage, a second transistor is connected between the third power supply wire and a gate of the first transistor, and an abnormal voltage detection circuit controls on and off of the second transistor based on a detection result of a third voltage.09-20-2012
20120236447INPUT-OUTPUT ESD PROTECTION - A method and apparatus for protecting an input-out (I/O) circuit against electro-static discharge (ESD) events. An ESD circuit used to protect the I/O circuit against an ESD event is coupled to the I/O circuit. The ESD circuit includes a diode clamp circuit that couples an I/O pad to a power supply and a ground pad. The ESD circuit further includes an active clamp circuit that is configured to clamp the I/O pad without turning on the diode clamp circuit during the ESD event.09-20-2012
20120236446DISPLAY UNIT HAVING ANTI-EMI CAPABILITY - An exemplary display unit includes a rear cover, a bracket disposed on the rear cover, a display mounted on the bracket, and a front cover secured to the rear cover to sandwich the display and the bracket between the front cover and the rear cover. The bracket includes a plate supporting the display, a pair of bulges protruding upwardly from two opposite sides of the plate and a pair of tabs extending upwardly from the bulges, respectively. The pair of tabs press against two opposite lateral faces of the display to dissipate static electricity on the display to ground.09-20-2012
20120236445On-Chip Noise Filter Circuit - A noise filter circuit for an IC is provided. The noise filter circuit comprises a decoupling unit coupled to a power pad of the IC and a current amplifier circuit coupled to the decoupling unit and the power pad of the IC. The decoupling unit generates a first current in response to a transient voltage being on the power pad of the IC. The current amplifier circuit drains a second current from the power pad of the IC according to the first current.09-20-2012
20120236444CHARGE PUMP ELECTROSTATIC DISCHARGE PROTECTION - Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.09-20-2012
20090052101PATH SHARING HIGH-VOLTAGE ESD PROTECTION USING DISTRIBUTED LOW-VOLTAGE CLAMPS - Integrated circuit (02-26-2009
20110026175ELECTROSTATIC DISCHARGE PROTECTING CIRCUIT WITH ULTRA-LOW STANDBY LEAKAGE CURRENT FOR TWICE SUPPLY VOLTAGE TOLERANCE - The invention relates to an electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance. The electrostatic discharge protecting circuit of the invention includes a substrate driver, a third transistor, a start-up circuit, a RC circuit and a second resistor. The substrate driver has a first transistor and a second transistor in serious connection. The start-up circuit has a fourth transistor and a fifth transistor with diode-connected. The RC circuit has a first resistor, a sixth transistor and a seventh transistor in serious connection. Compared with the prior art, the electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance of the invention with advantages of low standby leakage current, high ESD robustness, and no gate-oxide reliability issue is an excellent circuit solution for on-chip ESD protection design for mixed-voltage I/O buffers in nanometer CMOS technologies.02-03-2011
20100172060System and Method for ESD Protection - An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.07-08-2010
20100172059OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS - Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.07-08-2010
20090180224ESD PROTECTION DESIGN FOR LOW CAPACITANCE SPECIFICATION - An ESD protection circuit with low capacitance, which utilizes ESD protection design for low capacitance specification, includes: an ESD detection circuit, coupled between a first voltage source and a second voltage source, for detecting an ESD voltage to generate a trigger signal; and an ESD protection device, having an end coupled to one of the first voltage source and the second voltage source, and another end coupled to a pad, wherein the ESD protection device performs an ESD protection according to the trigger signal.07-16-2009
20110279935DIFFERENTIAL TRANSMISSION CIRCUIT AND ELECTRONIC DEVICE PROVIDED WITH THE SAME - There is disclosed a differential transmission circuit capable of realizing a high resistance to electrostatic breakdown without deteriorating a transmission signal. The differential transmission circuit includes ESD protection elements 11-17-2011
20110279936INTEGRATED CIRCUIT WITH DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit includes a substrate of semiconductive material, a first circuit environment made from the substrate which includes an output terminal and a first pair of power supply terminals for receiving a first power supply voltage applicable between the terminals. The integrated circuit also includes a second circuit environment made from the semiconductor substrate which includes an input terminal electrically coupled to the output terminal and also includes a second pair of power supply terminals for receiving a second power supply voltage applicable between the second pair of terminals of said second pair. The circuit further includes a device providing protection from electrostatic discharges which includes an integrated resistive device coupled between the input and output terminals.11-17-2011
20110279934OVERVOLTAGE PROTECTION STRUCTURE FOR A DIFFERENTIAL LINK - A structure for protecting an integrated circuit connected to first and second rails of a differential link against overvoltages, including: a first bidirectional conducting device, between the first rail and a common node; a second bidirectional conducting device, between the second rail and the common node; and a capacitor between the common node and a low reference potential rail.11-17-2011
20120287539ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device electronically connected to a pad is provided. The ESD protection device includes K PNP transistors and a protection circuit, wherein K is a positive integer. An emitter of the 111-15-2012
20110026174Electrostatic Discharge Protection Element and Electrostatic Discharge Protection Chip and Method of Producing the Same - An electrostatic discharge (ESD) protection element is described, the ESD protection element including a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.02-03-2011
20100128402INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND ESD PROTECTION THEREFOR - An integrated circuit comprises electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to one or more external connector(s) of the integrated circuit. The ESD protection circuitry comprises at least one ESD protection component coupled to the one or more external connectors for providing ESD protection thereto. The ESD protection circuitry further comprises an ESD connector, coupled to the one or more external connector(s), arranged to couple supplementary ESD protection to the one or more external connector(s).05-27-2010
20120287538ESD PROTECTION ON HIGH IMPEDANCE MIC INPUT - An apparatus comprises an integrated circuit (IC) including an external IC connection, a high impedance circuit, a biasing circuit communicatively coupled to the external IC connection via the high impedance circuit, and an electro-static discharge (ESD) protection circuit coupled to the biasing circuit to form a circuit shunt path leading from the IC external connection to the ESD protection circuit via the high impedance circuit.11-15-2012
20090207538ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.08-20-2009
20090207539I/O CIRCUIT - The I/O circuit 08-20-2009
20090207540POWER STRIP HAVING SURGE PROTECTIVE CIRCUIT - The present invention provides a power strip having a surge protective circuit. When a surge is inputted into the power strip, the surge is subject to two-stage suppressions so as to protect the electrical appliances which are electrically connected to the power strip. The surge protective circuit of the power strip includes a first surge protective device, a buffer conductive device and a second surge protective device. The buffer conductive device is relatively small-sized and cost-effective in comparison with the bulky inductor used in conventional power strip.08-20-2009
20110286136ESD BLOCK WITH SHARED NOISE OPTIMIZATION AND CDM ESD PROTECTION FOR RF CIRCUITS - A RF device includes a RF integrated circuit having a RF input and a RF output. The RF integrated circuit has an NMOS transistor having a gate terminal coupled to the RF input, a drain terminal coupled to a first power supply node and a source terminal coupled to a second power supply node. The RF integrated circuit is vulnerable to damage from an ESD event. A primary ESD protection circuit is coupled to the RF input and between the first and second power supply nodes. A secondary ESD protection circuit is coupled between the RF input and the second power supply node. The secondary ESD protection circuit includes a secondary ESD protection diode coupled between the gate and source terminals of the NMOS transistor.11-24-2011
20110286135Silicon Controlled Rectifier Based Electrostatic Discharge Protection Circuit With Integrated JFETS, Method Of Operation And Design Structure - An enhanced turn-on time SCR based electrostatic discharge (ESD) protection circuit includes an integrated JFET, method of use and design structure. The enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit includes an integrated JFET in series with an NPN base.11-24-2011
20130021700ACTIVE CLAMPED TRANSISTOR CIRCUIT - An active clamped transistor circuit includes a transistor and a TVS diode connected across a gate and a drain of the transistor.01-24-2013
20120099228ESD PROTECTION FOR RF CIRCUITS - An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.04-26-2012
20110299203CLAMPING CONTROL CIRCUIT FOR HYBRID SURGE PROTECTION DEVICES - A hybrid surge protection device (SPD) having a clamping voltage that is controlled by precisely limiting the overshoot voltage of a gas discharge tube (GDT) in a hybrid suppression network. The suppression network is conventionally connected between a protected line carrying current from a power source to a load and a return connection. The network includes a main surge suppression varistor (VR12-08-2011
20110299204ANTI-LIGHTNING PROTECTION FOR TELEPHONE CONNECTION - A structure for protecting a circuit connected to first and second rails of a telephone connection against overvoltages, including: first and second diodes in anti-series between the first and second rails; a first capacitor in parallel with a first resistor between a first node common to the first and second diodes and a low voltage reference node; and a protection element capable of removing fast overvoltages between any of the rails and the low reference voltage node when these overvoltages exceed a first threshold associated with the voltage of the first node.12-08-2011
20110299202 NMOS-Based Feedback Power-Clamp for On-Chip ESD Protection - A power-to-ground clamp transistor provides electrostatic discharge (ESD) protection. A filter capacitor and resistor generate a filter voltage that is buffered by three stages to drive the gate of the clamp transistor. The filter capacitor is about twenty times smaller than in a conventional clamp circuit. Feedback in the circuit keeps the clamp transistor turned on after the R-C time constant of the capacitor and resistor in the filer has elapsed, allowing for a smaller capacitor to turn on the clamp transistor longer. A sub-threshold-conducting transistor in the first stage conducts only a small sub-threshold current, which extends the discharge time of the first stage. The gate of the sub-threshold-conducting transistor is driven by feedback from the second stage. A feed-forward resistor has a high resistance value to slowly raise the voltage of the second stage from the filter voltage, and thus slowly raise the gate of the sub-threshold-conducting transistor.12-08-2011
20110141638ELECTROSTATIC PROTECTION DEVICE AND ELECTRONIC APPARATUS EQUIPPED THEREWITH - The electrostatic protection device in accordance with the present invention is the electrostatic protection device for protecting a plurality of electronic elements electrically connected in series against static electricity, the device comprising a plurality of first electrostatic protection elements having a current-voltage nonlinear resistance characteristic, a plurality of second electrostatic protection elements having a current-voltage nonlinear resistance characteristic, and a ground terminal for electrically connecting with a ground. The plurality of first electrostatic protection elements are electrically connected in parallel to the respective electronic elements, while the plurality of second electrostatic protection elements are electrically connected between input terminals of the respective electronic elements and the ground terminal.06-16-2011
20110292554PROTECTION CIRCUIT FOR RADIO FREQUENCY POWER AMPLIFIER - Embodiments of circuits, apparatuses, and systems for a protection circuit to protect against overdrive or overvoltage conditions. Other embodiments may be described and claimed.12-01-2011
20110292552OVER-VOLTAGE PROTECTION DEVICE - An exemplary over-voltage protection device used in an electronic device includes a housing capable of being grounded, a circuit board, a connecting member detachably attached to the circuit board and the housing to electrically connect the circuit board with the housing, and a protection member connected to the circuit board and circuitry of the electronic device. When an over-voltage is generated in the electronic device, the over-voltage is transmitted to the ground through the protection member, the circuit board, the connecting member, and the housing.12-01-2011
20090168278CIRCUIT DEVICE AND METHOD OF SUPRESSING A POWER EVENT - A circuit device includes a diode bridge having a first power input and a second power input and having a first output terminal and a second output terminal. The diode bridge includes a plurality of diodes and a respective plurality of diode bypass elements associated with the plurality of diodes. The circuit device further includes a logic circuit to detect a power event at the first and second power inputs and to selectively activate one or more of the respective plurality of diode bypass elements in response to detecting the power event to limit a rectified power supply at the first and second output terminals.07-02-2009
20080310059ESD PROTECTION DESIGN METHOD AND RELATED CIRCUIT THEREOF - The invention discloses a method for electrostatic discharge (ESD) protection design. The method includes: placing a first input/output cell (I/O cell) and a second input/output cell at a side of a chip, wherein a routing area exists at the side of the chip and is positioned between the first input/output cell and the second input/output cell; providing an electrostatic discharge protection circuit unit; and placing the electrostatic discharge protection circuit unit in the routing area.12-18-2008
20110007439COMPOSITE ELECTRONIC DEVICE - The present invention is provided with a composite electronic device comprising an inductor element and an ESD protection element formed between two magnetic substrates, wherein the inductor element includes insulation layers made of a resin, and spiral conductors formed on the insulation layers, the ESD protection element includes a base insulation layer, a pair of gap electrodes arranged via gap formed therebetween on the base insulation layer, and an ESD absorbing layer arranged at least between the gap electrodes, and a gap protection layer provided on at least one of the upper side and lower side of the gap, the ESD absorbing layer includes a composite material having an insulation inorganic material and a conductive inorganic material discontinuously dispersed in a matrix of the insulation inorganic material. The gap protection layer is made of resin including magnetic powder and carbon.01-13-2011
20090190276PROTECTION OF EXPOSED CONTACTS CONNECTED TO A BRIDGE RECTIFIER AGAINST ELECTROSTATIC DISCHARGE - Disclosed is a protection circuit for protecting a rectifier circuit from electrostatic pulses. The circuit employs a first bypass capacitor that is connected between positive and negative power lines to bypass electrostatic pulses that have a rise time that allows the diodes to conduct and prevent damage to the diodes as a result of reverse biasing, and a second bypass capacitor that is connected between an input node and the negative power line to discharge the electrostatic pulses that have a rise time that is faster than the turn-on times of the diodes. Connection of the bypass capacitors at locations close to the rectifying diodes minimizes the effects of stray inductance that affects the operation of the rectifier circuit in response to fast rise time transient pulses.07-30-2009
20090161273HIGH VOLTAGE TOLERANT ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit includes an NPN transistor having a collector terminal connected to a voltage source and an emitter terminal connected to the ground via a diode. The NPN transistor includes a base terminal for receiving a base current to turn on the NPN transistor to allow an electrostatic discharge at the voltage source to flow through the NPN transistor to the ground. The ESD protection circuit further includes a PMOS transistor having a source terminal coupled to the voltage source and a drain terminal coupled to the base terminal of the NPN transistor. The PMOS transistor includes a gate terminal for receiving a first and a second gate voltage. The ESD protection circuit further includes an R-C circuit coupled between the source voltage and the ground. The R-C circuit is configured to supply the first gate voltage to the PMOS transistor when there is no electrostatic discharge to turn off the PMOS transistor and the second gate voltage responsive to the electrostatic discharge to turn on the PMOS transistor for a predetermined time period. The ESD protection circuit further includes a voltage divider circuit coupled between the voltage source and the ground and coupled to the R-C circuit.06-25-2009
20100033884ESD PROTECTION TRIGGER CIRCUIT - This invention discloses a trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprises a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during a ESD event, and to produce a second predetermined voltage complimentary to the first predetermined voltage during a normal operation, and a voltage converting circuit having a positive feedback circuit and coupled between the voltage sensing circuit and the ESD protection device for converting the first predetermined voltage to a third predetermined voltage for turning on the ESD protection device, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the ESD protection device.02-11-2010
20100033885POTTED ELECTRICAL CIRCUIT WITH PROTECTIVE INSULATION - A potted electrical circuit is enclosed within a housing and has a first and second fiberglass layer that is laid upon a top surface of the potted electrical circuit. A lid of the housing seals the electrical circuit there within and an opening formed in a side wall allows circuitry wiring to extend there from out. The first fiberglass layer is a woven layer while the second fiberglass layer is a padding-like layer. Circuitry wiring pushes through the woven first fiberglass layer before extending out through the opening in the housing. The first fiberglass layer is tucked in and around the electrical circuit and adheres to the inside of the housing by attaching to the potting material while it hardens. In a preferred embodiment, the electrical circuit in combination with the insulation material is used within a transient voltage surge suppression device.02-11-2010
20100033886METHODS AND ARRANGEMENT FOR PROTECTING AGAINST ELECTROSTATIC DISCHARGE - An electronic device having ESD (Electrostatic Discharge) protection for a plurality of sides and including an external cover having at least one aperture and a plurality of slots disposed sufficiently close to a periphery of the at least one aperture. The electronic device further includes an ESD shield configured for providing ESD protection for a second side of an electronic device and also for the first side, the second side being opposite the first side. The ESD shield includes an ESD-shielding surface configured to provide the ESD protection for at least a portion of the second side, and a plurality of orthogonally protruding ESD shielding tabs, individual ones of the plurality of orthogonally protruding ESD shielding tabs configured to fit within respective ones of the plurality of slots when the ESD shield is mated with the external cover.02-11-2010
20090195950NETWORK COMMUNICATION PROCESSING APPARATUS WITH ESD PROTECTION - The invention discloses a network communication processing apparatus capable of processing the cable discharge event. The network communication processing apparatus comprises an electrostatic protection circuit coupled between two signal pins used for transmitting/receiving the network signal on a cable. When the cable discharge event occurred on the cable, the electrostatic protection circuit will be turned on so that the two signal pins are short together to discharge back the electrostatic signal to the cable.08-06-2009
20090195943Overvoltage Protection Circuit with Reduced Sensitivity to Process Variations - An overvoltage protection circuit includes a shunt circuit adapted for connection to at least one circuit node to be protected from an overvoltage condition and a voltage generator coupled to the shunt circuit. The shunt circuit is selectively activated as a function of a control signal supplied to the shunt circuit. The voltage generator is operative to generate the control signal for activating the shunt circuit during the overvoltage condition. The control signal has a level which varies in a manner that at least partially changes offsets in activation threshold of the shunt circuit.08-06-2009
20090086393ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR PROTECTING SEMICONDUCTOR DEVICE - A discharge circuit holds the potential difference between a power supply terminal and reference potential terminal at a predetermined value. The gates of a first pMOSFET and first nMOSFET are connected to an input terminal. A second pMOSFET is connected between the first pMOSFET and power supply terminal, and has a gate to which a first signal is supplied. A second nMOSFET is connected between the first nMOSFET and reference potential terminal, and has a gate to which a second signal is supplied. A detection circuit outputs the first signal which turns on the second pMOSFET and the second signal which turns on the second nMOSFET, while the potential difference is held at the predetermined value. The detection circuit outputs the first signal which turns off the second pMOSFET and the second signal which turns off the second nMOSFET, while the potential difference deviates from the predetermined value.04-02-2009
20100103570Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection - Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.04-29-2010
20120026632Systems, Methods, and Apparatus for Limiting Voltage Across a Switch - Systems, methods, and apparatus for limiting voltage across a switch utilizing voltage clamping circuitry are provided. The voltage clamping circuitry may include a rectifier circuit comprising inputs and outputs, the inputs in parallel communication across operational circuitry; an electronic active switching device in parallel communication with the outputs of the rectifier circuit; and at least one Zener diode in parallel communication with the electronic active switching device. When voltage across the electronic active switching device and the Zener diode meets or exceeds a predetermined value, the current will flow through the electronic active switching device and limit voltage across the operational circuitry to within a voltage clamping circuitry voltage limit.02-02-2012
20090168280ELECTROSTATIC DISCHARGE AVOIDING CIRCUIT - An ESD avoiding circuit includes a first ESD protection unit, an ESD detection unit, a switch unit, and an RC filter unit. The first ESD protection unit transmits an ESD current between a first conducting path and a second conducting path. The ESD detection unit is coupled to the first conducting path. The ESD detection unit includes an input terminal, and an output terminal coupled to the first ESD protection unit for detecting an ESD and controlling the first ESD protection unit to conduct the ESD current according to a detection result. The switch unit is coupled between the first conducting path and a core circuit and conducts the first conducting path to the core circuit according to signals of the input terminal and the output terminal of the ESD detection unit. The RC filter unit couples a first voltage to the input terminal of the ESD detection unit.07-02-2009
20090316313DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE - A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.12-24-2009
20100110595INPUT SURGE PROTECTION DEVICE USING JFET - An input surge suppression device and method that uses a simple JFET structure. The JFET has its gate clamped to a predetermined value, its the drain receives the input voltage from an input power source, its source is connected to the input of a down-stream device, and a resistor connected between the drain and the gate or between the source and the gate. Thus, when the drain voltage approximates the clamped gate voltage, the source voltage nearly equals the drain voltage. When the drain voltage rises above the clamped gate voltage, the source voltage is lower than the drain voltage. The downstream device may be a DC-DC converter and the gate is biased by the enable (EN) pin of a DC-DC converter.05-06-2010
20090141413INTEGRATED ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITRY FOR SIGNAL ELECTRODE - An integrated electrostatic discharge (ESD) protection circuitry for a signal electrode. Coupled in shunt between the signal electrode and the positive and negative power supply electrodes are opposing sets of multiple diodes coupled in series. Each set includes a diode across which is applied a nominal reverse bias voltage These opposing reverse bias voltages are maintained at substantially constant predetermined nominal magnitudes in relation to the voltage at the signal electrode, thereby ensuring minimal leakage current via the signal electrode over the full dynamic range of the signal.06-04-2009
20090147420Circuit Arrangement with an Overcurrent Fuse - A circuit arrangement includes a semiconductor switch having a control terminal and a load path. A drive circuit is coupled to the control terminal of the semiconductor switch. The drive circuit has a current measuring arrangement for determining a load current flowing through the load path and is designed to prevent the semiconductor switch from being driven in the off state if the load current exceeds a predetermined load current threshold value. A fuse is coupled in series with the load path of the semiconductor switch triggers if a triggering condition dependent at least on the load current is present.06-11-2009
20100118456CMOS INTEGRATED CIRCUIT - A CMOS IC according to the invention includes a discharging circuit for preventing electrostatic breakdown from occurring. The discharging circuit includes a discharging NMOSFET Qe, which couples a gate terminal node Vgp continuous to the gate of an outputting PDMOS transistor Q05-13-2010
20100142107ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.06-10-2010
20110149450CONTROL CIRCUIT HAVING A DELAY-REDUCED INVERTER - In some embodiments, a power supply clamp may include a switchable discharge device configured to discharge an electrostatic discharge; and a control circuit configured to generate a control voltage to turn off the discharge device at a shutoff time, with the shutoff time being long enough to allow the electrostatic discharge though the discharge device but short enough to reduce a duration of a power-up current transient through the discharge device. Other embodiments may be described and claimed.06-23-2011
20110261489ESD TRIGGER FOR SYSTEM LEVEL ESD EVENTS - A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.10-27-2011
20100123985Driver With Electrostatic Discharge Protection - Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.05-20-2010
20100118457ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge protection circuit includes an electrostatic induction unit connected between a power supply line and a data input/output line of an input/output pad, and configured to induce static electricity introduced through the input/output pad to the power supply line; a coupling capacitor having a first terminal connected to the power supply line; and a silicon controlled rectifier (SCR) unit connected to a second terminal of the coupling capacitor, connected between the data input/output line and a ground voltage line, and configured to discharge the static electricity on the data input/output line to the ground voltage line by static electricity introduced through the coupling capacitor.05-13-2010
20100118455SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.05-13-2010
20090290273LIGHT-EMITTING DIODE PACKAGE HAVING ELECTROSTATIC DISCHARGE PROTECTION FUNCTION AND METHOD OF FABRICATING THE SAME - A light-emitting diode (LED) package having electrostatic discharge (ESD) protection function and a method of fabricating the same adopt a composite substrate to prepare an embedded diode and an LED, and use an insulating layer in the composite substrate to isolate some individual embedded diodes, such that the LED device has the ESD protection.11-26-2009
20100079920Overload protection for a circuit arrangement having a transistor - A drive circuit for a transistor and a method for driving a transistor are described.04-01-2010
20090296291POWER SEMICONDUCTOR ARRANGEMENT INCLUDING CONDITIONAL ACTIVE CLAMPING - A power semiconductor arrangement including conditional active clamping (CAC). One embodiment includes a power semiconductor arrangement. A controllable power semiconductor switch includes a load path. A driver unit for switching the load path to either an ON-state or an OFF-state. An active clamping (AC) unit configured to switch the load path in the ON-state if the voltage affecting the controllable power semiconductor switch is higher than or equal to an allowable voltage. A switching unit includes a control input, and configured to activate and/or to deactivate the AC unit dependent on a signal applied to the control input.12-03-2009
20090290272Electrostatic discharge event protection for an integrated circuit - An integrated circuit 11-26-2009
20090091871ELECTROSTATIC DISCHARGE PROTECTION FOR A CIRCUIT CAPABLE OF HANDLING HIGH INPUT VOLTAGE - An electrostatic discharge protection circuit includes a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal (VDD) and an input pad (PAD), a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal (VSS), a first capacitor connected between VDD and a node VT that is connected to gate terminals of the second NMOS transistor and the third NMOS transistor, a second capacitor connected between the node VT and PAD, and a diode connected between VDD and the node VT.04-09-2009
20090046401METHOD AND APPARATUS OF PROVIDING 2-STAGE ESD PROTECTION FOR HIGH-SPEED INTERFACES - The present invention relates to a method and apparatus of providing 2-stage ESD protection for high-speed interfaces. An aspect of the present invention is to provide an integrated multi-stage ESD/EOS protection solution for such high-speed applications. In one embodiment, the ESD protection device has multiple ESD stages integrated into a single integrated circuit package and is mounted to a printed circuit board in series with a device under protection. In another embodiment the multiple ESD stages integrated into a single integrated circuit package of the ESD protection device are coupled with a series element that isolates a 2nd stage from a 1st stage during an ESD event, thus ensuring that the 202-19-2009
20080310060Overvoltage Protection Module and an Assembly of at Least One Telecommunications Module and at Least One Overvoltage Protection Module - An overvoltage protection module can be fitted to a telecommunications module having telecommunications contacts, to which telecommunications lines are connectable, and has at least two overvoltage protectors, at least one ground contact, and at least two pairs of protection module contacts for contacting the telecommunications contacts at contact points, so that at least two telecommunications lines are protectable, wherein the contact points are located on at least two different levels, and both contacts of each pair of protection module contacts are connected to the same overvoltage protector.12-18-2008
20090284883ELECTRONIC DEVICE HAVING ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHODS OF FABRICATING THE SAME - An electronic device having an electrostatic discharge (ESD) protection device and methods of fabricating the same. The electronic device can include an electronic element to be protected from electrostatic discharge. The electronic element can be installed on a substrate. The substrate can include a ground electrode disposed on the substrate, and a first element electrode disposed at a different level from the ground electrode on the substrate to overlap a part of the ground electrode and to electrically connect to the electronic element installed to the substrate. A dielectric layer can be disposed between the ground electrode and the first element electrode, wherein the ground electrode, the first element electrode and the dielectric layer disposed therebetween constitute an electrostatic discharge (ESD) protection device.11-19-2009
20090284882PROTECTION CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND DRIVING METHOD THEREFOR - A surge protection circuit comprises a surge detection circuit 11-19-2009
20090273870SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is provided to suppress occurrence of an erroneous operation in a protection circuit due to a relatively small power source fluctuation such as a power source noise. The protection circuit has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter whose input is connected between the first resistor and the capacitor, and a MOS transistor whose gate electrode receives an output of the inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line. Since an output of the inverter is pulled down to the ground line via a second resistor, even if an output of the inverter fluctuates undesirably, fluctuations in a gate input of the MOS transistor are suppressed.11-05-2009
20090262476Circuit configurations to reduce snapback of a transient voltage suppressor - This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.10-22-2009
20090262475METHOD AND SYSTEM FOR MITIGATING RISK OF ELECTROSTATIC DISCHARGE FOR A SYSTEM ON CHIP (SOC) - Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.10-22-2009
20090262474LOW-VOLTAGE CMOS SPACE-EFFICIENT 15 KV ESD PROTECTION FOR COMMON-MODE HIGH-VOLTAGE RECEIVERS - An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each of the p-type contact dopant regions is configured to form back-to-back diodes connected in series with cathodes in common. In protecting common mode receivers, current from an ESD event is channeled to ground rather than to the complementary receiver node. The diode stacks are capable of withstanding a 15 kV incident and save up to 25% in area compared to a fully parallel configuration for differential signal pairs.10-22-2009
20090262473Self-protecting crowbar - The invention relates to a protective circuit for an electrical device operated in particular in an explosion-hazard area, with a limiting circuit connected downstream of a pair of input terminals for limiting an output voltage present at a pair of output terminals and/or an output current delivered at the output terminals below a threshold value and a shorting circuit, which shorts the output or input terminals when a threshold value is exceeded, the control signal that controls the limitation originating from the same place as the signal that triggers the shorting circuit, and with a measuring circuit, which uses the output voltage or the output current to provide a control signal, which is fed on the one hand to a final control element for reducing the output voltage or the output current and on the other hand to the shorting circuit, the measuring circuit comprising a ZENER diode and/or a measuring resistor and the control signal being a voltage that is in particular a transistor-amplified or impedance-converted voltage. To minimize the difference between the guaranteed output voltage and the safety voltage, the invention proposes that the final control element is a self-conducting field-effect transistor, at the gate of which the control signal is present, and the measuring circuit is connected downstream of the field-effect transistor in the direction of current flow.10-22-2009
20090296294ELECTRO-STATIC DISCHARGE PROTECTION DEVICE WITH LOW TEMPERATURE CO-FIRE CERAMIC AND MANUFACTURING METHOD THEREOF - The present invention relates to an electro-static discharge (ESD) protection device with a low temperature co-fire ceramic (LTCC) and a manufacturing method thereof. The ESD protection device comprises a low temperature co-fire ceramic film having a first patterned conductive electrode material layer and a second patterned conductive electrode material layer therein. The low temperature co-fire ceramic film has at least one via exposing a portion of the first patterned conductive electrode material layer and a portion of the second patterned conductive electrode material layer simultaneously.12-03-2009
20090296292Electrostatic Discharge Protection Circuit Employing a Micro Electro-Mechanical Systems (MEMS) Structure - An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.12-03-2009
20090284881PACKAGE LEVEL ESD PROTECTION AND METHOD THEREFOR - A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.11-19-2009
20090296296SURGE PROTECTION ARRANGEMENT - An improved surge protection for protecting an electronic device is disclosed, the device having a closed casing with walls made of a non-conducting material and being internally coated with a thin metallic layer. The device also has at least one connector, being arranged in an opening in the walls and including a connector body, at least a portion of which projects outwardly from the wall and which accommodates an internal coupling device, to which a transmission cable, including a central conductor and an outer shield conductor, is connectable. According to the invention, the connector body is also made of a non-conducting material and strong currents, being present at a conducting protection sleeve, are diverted by at least one conducting diversion member to at least one metallic structure, being in permanent electric contact with ground and having a high capacity of conducting strong currents. In use, the at least one conducting diversion member is in electrical contact with the protection sleeve, and extends radially outwardly from the protection sleeve, through the connector body, to the at least one metallic structure.12-03-2009
20090296297OVERVOLTAGE PROTECTION DEVICE - An overvoltage protection device for protection of an electrical or electronic device, with a housing, with input and output terminals for electrical conductors, with line paths which each connect one input terminal to one output terminal, with first arresters which are used for symmetrical protection between the active conductors and with second arresters which are used for asymmetrical protection between the individual conductors and the ground potential, the individual first arresters each being connected by their first terminal to a line path and by their second terminal to a common connecting point so that they are at a common reference potential and symmetrical protection between two conductors is implemented by two first arresters located in series to one another. The overvoltage protection device can also be used in signal circuits with several signal conductors and can guarantee reliable protection of a connected electrical or electronic device against overvoltages.12-03-2009
20090296293ESD PROTECTION CIRCUIT FOR DIFFERENTIAL I/O PAIR - An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events.12-03-2009
20120268849SEMICONDUCTOR DEVICE - To provide a protection circuit having a small area, redundancy, and small leak current. In the protection circuit, a plurality of nonlinear elements is provided so as to overlap with each other and so as to be electrically connected in series. At least one nonlinear element in the protection circuit is a diode-connected transistor including an oxide semiconductor in its channel formation region. The other nonlinear element is a diode-connected transistor including silicon in its channel formation region or a diode including silicon in its junction region.10-25-2012
20080212245Electrostatic discharge device and organic electro-luminescence display device having the same - An electrostatic discharge device and an organic electro-luminescence display device having the same are provided. The organic electro-luminescence display device includes an electrostatic discharge device including a metal pattern having an island shape on a substrate, an insulating layer on the metal pattern, a semiconductor pattern on the insulating layer, the semiconductor pattern corresponding to the metal pattern, a first electrode overlapping one end of the semiconductor pattern, and a second electrode overlapping the other end of the semiconductor pattern, and spaced from the first electrode, thereby preventing a current leakage, a signal distortion and a signal cross-talk to improve the reliability.09-04-2008
20110199708LEVEL CONVERSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE EMPLOYING THE LEVEL CONVERSION CIRCUIT - In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.08-18-2011
20100277840V-Band Radio Frequency Electrostatic Discharge Protection Circuit - A V-band radio frequency (RF) electrostatic discharge (ESD) protection circuit uses meander inductors and diodes connecting in series to provide ESD protection. When operated in low frequency, the static electricity input from a RF pad may discharge to ground or to a voltage VDD through the meander inductor and the diode, so that a core circuit does not be damaged by ESD. When operated in high frequency, the high frequency stray effect of the core circuit is substantially reduced due to impedance isolation generated by the meander inductors. Therefore, a low-noised amplifier (LNA) can receive an accurate high frequency input signal.11-04-2010
20100277841THRESHOLD VOLTAGE METHOD AND APPARATUS FOR ESD PROTECTION - An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.11-04-2010
20100103573Semiconductor package having electrostatic protection circuit for semiconductor package including multiple semiconductor chips - A semiconductor package includes: a first semiconductor chip; a first internal circuit which operates, in the first semiconductor chip, at a voltage applied between a first high-potential side power supply terminal and a first low-potential side power supply terminal; a second semiconductor chip; a second internal circuit which operates, in the second semiconductor chip, at a voltage applied between a second high-potential side power supply terminal and a second low-potential side power supply terminal; and a first electrostatic protection circuit which is formed in the first semiconductor chip, and which has one end connected to a node between the first internal circuit and the first low-potential side power supply terminal and has the other end connected to a node between the second internal circuit and the second low-potential side power supply terminal.04-29-2010
20100103572AMPLIFIER WITH IMPROVED ESD PROTECTION CIRCUITRY - An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor, an inductor, and a clamp circuit. The transistor has a gate coupled to a pad and provides signal amplification for the amplifier. The inductor is coupled to a source of the transistor and provides source degeneration for the transistor. The clamp circuit is coupled between the gate and source of the transistor and provides ESD protection for the transistor. The clamp circuit may include at least one diode coupled between the gate and source of the transistor. The clamp circuit conducts current through the inductor to generate a voltage drop across the inductor when a large voltage pulse is applied to the pad. The gate-to-source voltage (Vgs) of the transistor is reduced by the voltage drop across the inductor, which may improve the reliability of the transistor.04-29-2010
20110205675VOLTAGE SURGE AND OVERVOLTAGE PROTECTION - Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. A series inductance separates the first and second voltage clamping devices. Also, a switching element is employed to selectively establish a direct coupling of the input power to the electrical load, where a circuit is employed to control the operation of the switching element.08-25-2011
20090279219ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND ELECTRONIC SYSTEM UTILIZING THE SAME - ESD protection circuit coupled to an input/output pad and including an attenuation unit and a discharge unit is provided. The attenuation unit attenuates an electrostatic discharge current for generating an attenuated current. The discharge unit releases the attenuated current.11-12-2009
20090279218THERMAL ISOLATION OF ELECTRONIC DEVICES IN SUBMOUNT USED FOR LEDS LIGHTING APPLICATIONS - The present invention relates to an electronic device for providing improved heat transporting capability for protecting heat sensitive electronics and a method for producing the same. The present invention also relates to uses of the electronic device for various applications such as in LED lamps for signalizing, signage, automative and illumination applications or a display apparatus or any combinations thereof.11-12-2009
20100061027Interface circuit with electro-static discharge protection circuit - An exemplary interface circuit with an electrostatic discharge (ESD) protection circuit includes an interface and an ESD protection circuit. The interface includes at least two pins. The ESD protection circuit includes at least a first polarity signal enable circuit, a second polarity signal enable circuit, and an ESD circuit. The at least two pins are grounded via the at least first polarity signal enable circuit, the second polarity signal enable circuit, and share the same ESD circuit.03-11-2010
20100061026ESD PROTECTION CIRCUIT AND METHOD THEREOF - An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal.03-11-2010
20110267724Circuit configurations to reduce snapback of a transient voltage suppressor - This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes' a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.11-03-2011
20110267723OVERVOLTAGE PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT - An overvoltage protection circuit may include a reference voltage generator, a trigger circuit, and a clamping device. The reference voltage generator is for providing a reference voltage that is relatively constant during a powered EOS/ESD event. The trigger circuit is coupled to receive the reference voltage and a power supply voltage. The trigger circuit is for comparing the reference voltage to the power supply voltage. In response to detecting that the power supply voltage is above the reference voltage, the trigger circuit provides a trigger signal having a voltage proportional to a voltage level of the overvoltage event. The clamping device is coupled between a first power supply terminal and a second power supply terminal. The clamping device is for providing a current path between the first and second power supply terminals in response to the trigger signal.11-03-2011
20120170162SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes a substrate unit having conductive pads and ESD protection pads formed on a bottom surface thereof; an encapsulant covering a top surface of the substrate unit; and a metal layer disposed on a top surface of the encapsulant and having connecting extensions formed on side surfaces of the substrate unit and the encapsulant for electrically connecting the ESD protection pads, wherein portions of the side surfaces of the substrate unit corresponding in position to the conductive pads are exposed from the metal layer so as to ensure that solder bumps subsequently formed to connect the conductive pads of the semiconductor package to a circuit board are not in contact with the metal layer, thereby effectively avoiding the risk of short circuits.07-05-2012
20120170161ELECTROSTATIC DISCHARGE CIRCUIT FOR RADIO FREQUENCY TRANSMITTERS - A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line.07-05-2012
20120293897CONNECTOR WITH VOLTAGE PROTECTION FUNCTION - A connector with a voltage protection function is to be electrically connected to a power supply device which provides a plurality of power voltages. The connector includes a main body, a plurality of pins and a voltage protection circuit module. The pins disposed on the main body are connected to the power voltages provided by the power supply device. The voltage protection circuit module includes a plurality of input terminals electrically connected to the power voltages. When a value of one of the power voltages exceeds a predetermined range, the voltage protection circuit module grounds at least one of the power voltages.11-22-2012
20090168281ELECTROSTATIC DISCHARGE LEADING CIRCUIT - An electrostatic discharge (ESD) leading circuit for a large-sized open drain circuit is provided. The ESD leading circuit utilizes a gate voltage boosting circuit to increase the gate voltage of an N-type MOS transistor.07-02-2009
20100271741STRUCTURE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES - A structure for protecting an integrated circuit against electrostatic discharges, comprising an assembly of identical cells, each of which is connected to a terminal forming a pad of the circuit, a first supply rail, or a second supply rail, the cells forming between any two of said terminals an assembly of four alternated layers of different conductivity types.10-28-2010
20080273280Carbon Nanotube Diodes And Electrostatic Discharge Circuits And Methods - Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in physical and electrical contact with the p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with the n-type single wall carbon nanotube.11-06-2008
20080278873IN PACKAGE ESD PROTECTIONS OF IC USING A THIN FILM POLYMER - A packaged semiconductor device (11-13-2008
20080291591RADIO-FREQUENCY APPARATUS WITH ELECTROSTATIC DISCHARGE PROTECTION - A radio-frequency apparatus with electrostatic discharge (ESD) protection is provided. The radio-frequency apparatus including an antenna, an inductor, a capacitor and a radio-frequency circuit receives a radio-frequency signal by the antenna. When the radio-frequency signal is transmitted to the radio-frequency apparatus, an electrostatic signal may invade into the radio-frequency apparatus via the antenna. Here, the radio-frequency signal can be transmitted and the electrostatic signal can be blocked by the capacitor, while the radio-frequency signal can be blocked and the electrostatic signal can be transmitted by the inductor. Therefore, when an ESD event occurs, the electrostatic signal is transmitted to ground through the inductor. Furthermore, the impedance value of the capacitor remains in a first range and that of the inductor remains in a second range, such that the electrostatic signal with a specific voltage is blocked by an impedance matching circuit formed by the capacitor and the inductor.11-27-2008
20080304191THRESHOLD VOLTAGE METHOD AND APPARATUS FOR ESD PROTECTION - An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.12-11-2008
20080310061Transistor with EOS protection and ESD protection circuit including the same - A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.12-18-2008
20080239601SEMICONDUCTOR DEVICE - A semiconductor device includes a pad; an internal circuit; a protection FET that has a drain connected to the pad, and a source connected to a reference potential; a first resistive element that is connected between the drain of the protection FET and the internal circuit, and has a larger resistance value than the value of the series resistance between the drain of the protection FET and the pad; a capacitive element that is connected between the pad and the gate of the protection FET; and a second resistive element that is connected between the gate of the protection FET and the source of the protection FET.10-02-2008
20100128401ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND DEVICE - An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first rail, a second rail, a first transistor and a resistance unit. The drain of the first transistor is electrically coupled to the first rail, and the source and gate of the first transistor are electrically coupled to the second rail. The resistance unit is electrically coupled between a body of the first transistor and the second rail. When ESD occurs, the resistance unit provides a resistance between the body of the first transistor and the second rail. An ESD protection device is also provided.05-27-2010
20110205676VOLTAGE SURGE AND OVERVOLTAGE PROTECTION - Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. A series inductance separates the first and second voltage clamping devices. Also, a switching element is employed to selectively establish a direct coupling of the input power to the electrical load, where a circuit is employed to control the operation of the switching element.08-25-2011
20100265623High Voltage Surge Arrester And Method Of Operating The Same - An arrester includes at least one elongate outer first housing made of an electrically insulating material, a pair of electrical terminals at opposite ends of the first housing, an array of electrical components arranged in the first housing that form a series path between the terminals, and a voltage grading arrangement for providing a substantially uniform voltage gradient along the arrester, wherein the voltage grading arrangement includes (i) an elongated outer second housing, and (ii) capacitor circuitry arranged in the outer second housing, and wherein the outer second housing is arranged external to the outer first housing.10-21-2010
20080239599Clamping Voltage Events Such As ESD - A clamping scheme using dual sensing detection, which can sense and differentiate (in the extreme) between a high voltage level and fast (enough) slope (indicative of ESD), and low voltage level and slow slope (indicative of normal operation) and/or low voltage level and fast slope (indicative of hot insertion). It can also generate a locking scheme to ensure proper discharging only if the level is above high level and fast slope. It can also operate the clamping for a short time only if the level is below the high level but above the low level, and of sufficient slope.10-02-2008
20080247101ELECTRONIC DEVICE AND METHOD - An IO buffer is formed having a substrate resistor at a support layer of a semiconductor on insulator substrate. A diode junction is formed between the substrate resistor and portion of the semiconductor on insulator substrate underlying the substrate resistor. In the event of a high-voltage event, current will flow through the diode junction.10-09-2008
20080247102EOS ROBUST BIPOLAR TRANSIENT CLAMP - A bipolar transient clamp including a RC circuit, a clamping circuit and a breakdown circuit. The RC circuit is configured to control the rate of change of clamp. Moreover, the RC circuit is coupled between a first rail and a second rail. The clamping circuit is configured to pass a current from the first rail to the second rail. In addition, the clamping circuit is coupled to be activated by the RC circuit. The breakdown circuit is coupled between the RC circuit and the clamping circuit. The breakdown circuit is configured to increase the transient trigger voltage of the clamping circuit.10-09-2008
20110007438COMPOSITE ELECTRONIC DEVICE, MANUFACTURING METHOD THEREOF, AND CONNECTION STRUCTURE OF COMPOSITE ELECTRONIC DEVICE - The present invention is provided with a composite electronic device comprising an inductor element and an ESD protection element formed between two magnetic substrates, wherein the inductor element includes insulation layers made of a resin, and conductor patterns formed on the insulation layers, the ESD protection element includes a base insulation layer, a pair of electrodes arranged via gap formed therebetween on the base insulation layer, and an ESD absorbing layer arranged at least between the electrodes, and the ESD absorbing layer includes a composite material having an insulation inorganic material and a conductive inorganic material discontinuously dispersed in a matrix of the insulation inorganic material.01-13-2011
20080285189Electrostatic discharge protection device for an optical disc drive - An electrostatic discharge protection device for an optical disc drive is provided. A rail disposed on the casing of the disc drive has an opening. A guide bar is slidable disposed on the rail. A conductive elastic plate is fixed around the opening on the rail. The elastic plate has an elastic-pressing end leaning against the guide bar through the opening, and a protrusion electrically contacting the casing. A tray supported by the guide bar to move in and out of the casing has an underside covered by a protection bottom plate. A conductive strip-shaped elastic element is fixed on the tray by a fixing screw, which fastens the protection bottom plate on the tray. As such, the elastic element is in contact with the protection bottom plate; besides, the elastic element also leans against the guide bar, so as to dissipate electrostatic discharge by the guide bar.11-20-2008
20080285188Composite integrated semiconductor device - A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.11-20-2008
20080285187CDM ESD PROTECTION FOR INTEGRATED CIRCUITS - The present invention provides a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises a substrate of first conductivity type; a MOS component of second conductivity type formed on a first well on the substrate, and coupled to a pad; an isolating well/region having the second conductivity type being formed between the first well and the substrate to separate the first well and the substrate. Additionally, the circuit comprises an ESD clamp coupled to the isolated well/region. Under normal power operation, the ESD clamp is open. During a CDM ESD event, the CDM charges accumulated in the substrate and the MOS component are removed by the ESD clamp to prevent damage to the IC.11-20-2008
20080285186Intrinsically Safe Ethernet-Based Communication - An intrinsically safe network switch (11-20-2008
20090190277ESD Protection For USB Memory Devices - ESD protection for a portable electronic device is provided by sandwiching a metal ground layer between prepreg (i.e., FR4 or other non-conductive PCB material) layers to form an ESD preventive PCB structure, where the metal ground layer is electrically connected to one or more of the integrated circuit (IC) components (e.g., at least one controller die, a non-volatile memory die, oscillator and passive components) that are mounted on the PCB by way of conductive via structures, and is accessible by way of one or more conductive anchor hole structures to external grounding structures. The one or more conductive anchor hole structures are positioned such that the metal ground layer is automatically electrically connected to the chassis ground of a host system when the portable device is coupled to a plug structure of the host system, e.g., by way of a metal connector jacket.07-30-2009
20090097174ESD protection circuit for IC with separated power domains - An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.04-16-2009
20090097177Electrostatic protection circuit - An electrostatic protection circuit includes a first impurity region, a second impurity region, a first electrode, a third impurity region, a fourth impurity region, a second electrode, a fifth impurity region, a sixth impurity region, a third electrode, a gate insulating film, and a fourth electrode.04-16-2009
20090097175ESD PROTECTION SUBSTRATE AND INTEGRATED CIRCUIT UTILIZING THE SAME - An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.04-16-2009
20100271742Electrical Over-Stress Detection Circuit - In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled between first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals or between a supply voltage potential and a pad voltage of a bond pad. The EOS circuit further includes an alert generation circuit configured to store data indicating an EOS event in response to detecting the perturbation.10-28-2010
20100142106SURGE PREVENTING CIRCUIT, LOCAL AREA NETWORK CONNECTOR, AND NETWORK MODULE - A surge preventing circuit of a local area network (LAN) connector is suitable for being coupled to a plurality of transformers disposed in the local area network connector. The surge preventing circuit includes a conjugate coil module and a surge absorbing element. The conjugate coil module has at least one conjugate coil. The conjugate coil has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal of the conjugate coil are coupled to the center tapped terminal of the respective transformer, respectively. A first terminal of the surge absorbing element is connected to ground, and a second terminal is coupled to the first output terminals and the second output terminals.06-10-2010
20090180223LOW SIDE DRIVER WITH SHORT TO BATTERY PROTECTION - A driver circuit includes a driver module having a first transistor for receiving a driver voltage signal. In response to the driver voltage signal, the first transistor conducts current through an electronic device. A protection module includes a second transistor in electrical communication with the first transistor for receiving a logic voltage signal and for inhibiting current flow through the first transistor in response to receiving the logic voltage signal. The protection module further includes a digital logic gate having at least one input in electrical communication with the first transistor for detecting a short-circuit voltage signal. At least one output of the digital logic gate is in electrical communication with the second transistor for outputting the logic voltage signal in response to receiving the short-circuit voltage signal.07-16-2009
20100142105Bidirectional ESD Power Clamp - The disclosed method and device relates to a bidirectional ESD power clamp, comprising a semiconductor structure (BigNFET; BigPFET) having a conductive path connected between first and second nodes and having a triggering node via which the conductive path can be triggered. An ESD transient detection circuit is connected between the first and second nodes and to the triggering node and comprises a first part for detecting an occurrence of a first ESD transient on the first node. The semiconductor structure is provided on an insulator substrate, such that a parasitic conductive path between said first and second nodes via the substrate is avoided. The ESD transient detection circuit further comprises a second part for detecting an occurrence of a second ESD transient on the second node.06-10-2010
20090128970ADAPTIVE ELECTROSTATIC DISCHARGE (ESD) PROTECTION OF DEVICE INTERFACE FOR LOCAL INTERCONNECT NETWORK (LIN) BUS AND THE LIKE - Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capa citive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.05-21-2009
20110205674VOLTAGE SURGE AND OVERVOLTAGE PROTECTION - Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. A series inductance separates the first and second voltage clamping devices. Also, a switching element is employed to selectively establish a direct coupling of the input power to the electrical load, where a circuit is employed to control the operation of the switching element.08-25-2011
20110205673SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC PROTECTION CIRCUIT - A semiconductor device includes: a first power source (PS08-25-2011
20090161275INTEGRATED CONTROLLING CHIP - An integrated controlling chip includes a signal processing unit, a resistance unit and an electrostatic discharge protection circuit. The signal processing unit includes an input port. The resistance unit includes a first node coupled to a signal pin of the integrated controlling chip, and includes a second node coupled to the input port of the signal processing unit. The electrostatic discharge protection circuit includes a node coupled between the first node of the resistance unit and the signal pin of the integrated controlling chip.06-25-2009
20090161276ESD Configuration for Low Parasitic Capacitance I/O - An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.06-25-2009
20090027816ELECTRONIC DEVICE HAVING ELECTROSTATIC DISCHARGE FUNCTION - An electronic device including a housing, a main circuit substrate disposed in one side of the housing; a connector unit which is disposed in an other side of the housing and is electrically connected to the main circuit substrate, and a discharging sheet disposed in the one side of the housing and is conductively connected to the connector unit to discharge static electricity generated in the connector unit is provided.01-29-2009
20090195946Electrostatic Discharge Protection Using an Intrinsic Inductive Shunt - In one embodiment of the present invention, an electrostatic discharge protection circuit provides efficient electrostatic discharge protection to an RFIC. The circuit includes several parts such as an inductor coupled from a first rail to an internal node. A power amplifier transistor having a transconductance control node is coupled to internal circuitry, a first terminal coupled to a second rail, and a second terminal coupled to an internal node. The circuit also comprises a pad coupled to an internal node, and this pad is capable of being coupled to off chip systems such as an antenna. The power amplifier transistor serves as the active device for an RF power amplifier. The inductor serves as one of either a bias inductor or a tank inductor for the RF power amplifier. Additionally the inductor acts as a low impedance path to the first rail to protect the power amplifier transistor during an ESD pulse.08-06-2009
20090128968STACKED-DIE PACKAGE FOR BATTERY POWER MANAGEMENT - A stacked-die package for battery protection is disclosed. The battery protection package includes a power control integrated circuit (IC) stacked on top of integrated dual common-drain metal oxide semiconductor field effect transistors (MOSFETs) or two discrete MOSFETs. The power control IC is either stacked on top of one MOSFET or on top of and overlapping both two MOSFETs.05-21-2009
20090128967SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises a first terminal (denoted by VCC) connected to a power supply in a normally mounted state, a second terminal (denoted by SB) connected to a signal line in the normally mounted state and to a power supply in a reversely mounted state, a third terminal (denoted by SGND) connected to the ground in the normally mounted state, fourth terminals (denoted by HU−, HW−) connected to the signal line in the normally mounted state and to the ground in the reversely mounted state, electrostatic protective diodes (denoted by D05-21-2009
20120287540CIRCUITRY TO PREVENT OVERVOLTAGE OF CIRCUIT SYSTEMS - An overvoltage protection method and circuit includes a positive supply input node, an output node, and a negative supply node. The overvoltage protection circuit further includes a first functional circuit configured to turn ON a MOSFET and maintain it in a low resistance state. A second functional circuit is configured to detect an overvoltage and control the gate of the MOSFET to regulate a voltage at the output node. A third functional circuit is configured to provide a startup wherein the overvoltage protection circuit is not damaged and/or to regulate an operating voltage such that an overvoltage does not appear on the overvoltage protection circuit. The external components include the MOSFET, which has a gate coupled to the output of the charge pump of the overvoltage protection circuit.11-15-2012
20120069479POWER TRANSISTOR DEVICE WITH ELECTROSTATIC DISCHARGE PROTECTION AND LOW DROPOUT REGULATOR USING SAME - The present invention discloses a power transistor device and a low dropout regulator (LDO) with electrostatic discharge protection. The power transistor device includes: a P-type metal oxide semiconductor (PMOS) field effect transistor (FET), having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal respectively; and an electrostatic discharge protection device, electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path to protect the PMOSFET.03-22-2012
20090185318SYSTEM AND METHOD TO RELIEVE ESD REQUIREMENTS OF NMOS TRANSISTORS - A system and method relieves ESD requirements on devices in circuits of chips that are susceptible to being damaged from ESD through an external pad. For example, one of the devices can be NMOS transistors having drains (or sources) connected to the external pad(s) and no (or significantly small) current flows from their drains (or sources) to the corresponding pad(s). In order to protect such a device, an ESD protecting system is coupled between the NMOS device and the pad. The ESD protecting system can include an n-type transistor or a p-type transistor.07-23-2009
20090185317INTEGRATED CIRCUIT AND ASSEMBLY THEREWITH - An integrated circuit suitable for use at high frequencies and comprising a first capacitor having an input and an output, as well as a ground connection, wherein the capacitor is ESD-protected through an resistor between the capacitor output and the ground connection, which resistor has a resistance value that is sufficiently high so as to prevent any substantial influence on RF performance of the ground connection.07-23-2009
20080316661Electrostatic Discharge Immunizing Circuit without Area Penalty - A chip includes a core circuit, a main electrostatic discharge immunizing circuit, and a secondary electrostatic discharge immunizing circuit. The secondary electrostatic discharge immunizing circuit is disposed beneath a core power ring formed between the core circuit and the main electrostatic discharge immunizing circuit for reaching the aim of protecting the core circuit from damage by electrostatic discharges without area penalty of the chip. Both the main electrostatic discharge immunizing circuit and the secondary electrostatic discharge immunizing circuit include a power clamp and a plurality of current limiters, and keep electrostatic currents from reaching the core circuit with the aid of the power clamp.12-25-2008
20080316659HIGH VOLTAGE ESD PROTECTION FEATURING PNP BIPOLAR JUNCTION TRANSISTOR - A protection circuit is disclosed that protects a semiconductor device from damage due to an electrostatic discharge. One such protection circuit comprises a vertical pnp hetero-junction bipolar transistor (HBT) connected between terminals such as supply terminals of the device, configured to conduct during an electrostatic discharge. The protection circuit also comprises a trigger circuit, such as a transient activated RC circuit connected between the terminals to detect the electrostatic discharge and control the transistor based on the detected electrostatic discharge. A Darlington transistor pair in the trigger circuit can be used to multiply the effective capacitance and HBT drive current. The HBT transistor absorbs energy from the electrostatic discharge and clamps the over-voltage across the terminals. The protection circuit may also be used across other I/O terminals of the device.12-25-2008
20080316662Reducing input capacitance for high speed integrated circuits - An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed.12-25-2008
20080316660ELECTROSTATIC DISCHARGE AVOIDING CIRCUIT - An electrostatic discharge (ESD) avoiding circuit comprises an ESD detecting unit and a switch unit. The ESD detecting unit is coupled to a first conductive path for detecting whether the ESD happened or not. The switch unit is coupled between the first conductive path and a core circuit for switching whether the first conductive path is conducted to the core circuit or not according to a detection result of the ESD detecting unit. The ESD avoiding circuit can avoid an electrostatic current transmitting to the core circuit when the ESD is happened, and the ESD avoiding circuit can make the normal signal/voltage providing to the core circuit for operating when the ESD isn't happened.12-25-2008
20090251833Electrostatic discharge protection device for high speed transmission lines - A semiconductor device for coupling a transient voltage at an input node to a reference node, the device having a bipolar transistor adapted to couple its collector to an input node and its emitter to the reference node and a driver device adapted to be coupled between the input node and the base terminal of the transistor such that the driver device is responsive to a transient voltage at the input node to turn on the transistor, thereby shunting the transient voltage to the reference node. Preferably, the input node is coupled to a high speed data transmission line that operates below 5 v and the reference node is coupled to ground and the transistor is an NPN transistor. The driver may preferably be a gate-drain connected MOS transistor with its gate-drain terminal coupled to the collector terminal of the transistor and its source terminal coupled to the base terminal of the transistor. Alternatively, the driver may be a light emitting diode (LED) or any other diode with a different material (band-gap) and die size than the LED, connected to the bipolar transistor to create a low voltage clamping device.10-08-2009
20090213506RESISTOR TRIGGERED ELECTROSTATIC DISCHARGE PROTECTION - An electrostatic discharge (ESD) protection device (08-27-2009
20110222197ESD PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity09-15-2011
20110222196Electrostatic Discharge Protection Rail Clamp with Discharge Interruption Circuitry - An electrostatic discharge (ESD) protection circuit apparatus is disclosed. The apparatus includes activation circuitry coupled to a first node. The activation circuitry includes a capacitor and a selectable load. A time constant τ associated with the activation circuitry varies in accordance with the selectable load. The activation circuitry is configured to provide τ=τ09-15-2011
20110141637CIRCUIT FOR USE WITH ENERGY CONVERTER - In an embodiment, the circuit includes: a first switch serially connected to a first discharge resistor, the first switch and the first discharge resistor connected to a positive DC bus; a second switch serially connected to a second discharge resistor, the second switch and the second discharge resistor connected to a negative DC bus; and a capacitor bank for storing a positive and a negative DC voltage, the capacitor bank including a first capacitor in parallel with the first switch and the first discharge resistor, and a second capacitor in parallel with the second switch and the second discharge resistor, wherein the first switch operates independently from the second switch to discharge the positive DC voltage through the first discharge resistor and the second switch operates independently from the first switch to discharge the negative DC voltage through the second discharge resistor.06-16-2011
20090080128ELECTROSTATIC BREAKDOWN PROTECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE THEREWITH - A protection circuit according to the present invention includes: a diode (D03-26-2009
20090052102SEMICONDUCTOR DEVICE - A semiconductor device comprises a protection circuit for protecting a semiconductor integrated circuit. The protection circuit includes a first terminal supplied with a first voltage, a second terminal supplied with a second voltage lower than the first voltage, a first thyristor arranged between the first terminal and the second terminal, and a trigger circuit operative to break a current path for trigger current flowing in the first gate of the first thyristor when the first voltage is applied to the first terminal, thereby disabling the first thyristor to become conductive, and operative to form the current path for trigger current when a voltage other than the first voltage is applied to the first terminal, thereby enabling the first thyristor to become conductive. The trigger circuit includes a third terminal for controlling operation of the trigger circuit in accordance with the voltage on the first terminal, a switching element connected between the first gate of the first thyristor and the second terminal and having a control terminal connected to the third terminal, and a resistor connected between the third terminal and the second terminal.02-26-2009
20130215539REDUCED CURRENT LEAKAGE IN RC ESD CLAMPS - Aspects of the invention provide an electrostatic discharge (ESD) protection device with reduced current leakage, and a related method. In one embodiment, an ESD protection device for an integrated circuit (IC) is provided. The ESD protection device includes: a resistor-capacitor (RC) timing circuit for selectively turning on the ESD protection device during an ESD event; a trigger circuit for receiving an output of the RC timing circuit and generating a trigger pulse for driving at least one of: a first ESD clamp and a second ESD clamp; and a selection circuit for selecting one of: the trigger circuit or a charge pump for controlling the second ESD clamp.08-22-2013
20130215541HIGH VOLTAGE RC-CLAMP FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION - In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second source/drain is coupled to the third node. The RC-triggered clamp also has an inverter, wherein an input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor. The ESD protection circuit also includes one or more forward-biased diodes coupled in series between a supply node and the first node.08-22-2013
20090052099Hybrid Circuit for Circuit Protection and Switching - A hybrid circuit (02-26-2009
20090052100METHOD OF FORMING AN ESD DETECTOR AND STRUCTURE THEREFOR - In one embodiment, and electro-static discharge detector is formed with a plurality of channels and is configured to detect a positive electro-static discharge and a negative electro-static discharge.02-26-2009
20090067104ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD THEREFOR - Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.03-12-2009
20110141639Integrated Circuit and Assembly Therewith - An integrated circuit suitable for use at high frequencies and comprising a first capacitor having an input and an output, as well as a ground connection, wherein the capacitor is ESD-protected through an resistor between the capacitor output and the ground connection, which resistor has a resistance value that is sufficiently high so as to prevent any substantial influence on RF performance of the ground connection.06-16-2011
20110141636NON-ALIGNED ANTENNA EFFECT PROTECTION CIRCUIT WITH SINGLE EVENT TRANSIENT HARDNESS - The disclosure describes an antenna protection circuit for use in circuits where Single Event Transients from energetic particles is a concern. The antenna protection circuit may include at least three diodes, connected electrically in series and arranged such that at most all but one of the at least three diodes produce a transient current pulse from an energetic particle. During the transient current pulse event, the remaining diode remains reverse biased thereby sufficiently blocking the transient current pulse and an SET does not occur on the signal node. The antenna protection circuit may be constructed so that no unshorted parasitic p-n junction structure is associated with any of the diodes in the circuit, which would otherwise have to be explicitly included in the at least three diodes.06-16-2011
20130182359ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit includes a first power line; a second power line; a ground line; two stack transistors connected in series between the first power line and the ground line; a first resistor connected between the first power line and a first node; a first transistor and a capacitor connected in series between the first node and the ground line; a second transistor connected between the second power line and a second node; a third transistor connected between the first power line and a third node; an inverter, connected between the third node and the ground line, and having an input connected to the second node; a fourth transistor, connected to the first power line, and having a gate connected to the second node; and a fifth transistor, connected between the second power line and the third node, and having a gate connected to a terminal of the fourth transistor.07-18-2013
20110228432RESIN COMPOSITION FOR FILLING DISCHARGE GAP AND ELECTROSTATIC DISCHARGE PROTECTOR - The present invention provides an electrostatic discharge protector capable of taking measures for electrostatic discharge against electronic wiring boards having various designs freely, simply and easily, having excellent accuracy of regulating an operating voltage and capable of being downsized and decreased on its cost, and also provides a resin composition for a discharge gap capable of preparing the electrostatic discharge protector. The resin composition for filling a discharge gap of an electrostatic discharge protector comprises a resin having a urethane structure represented by the formula (1):09-22-2011
20110228431BATTERY CELL AND ELECTRONIC APPARATUS WITH ELECTROSTATIC DISCHARGE PROTECTION - An electronic apparatus with electrostatic discharge protection includes: a conducting casing and a circuit board. The circuit board has a power ground node and a conditional conducting path, and is set inside the conducting casing. The conditional conducting path further includes: a conducting element and an electrostatic discharging component. One end of the conducting element is electrically connected to the conducting casing, and the electrostatic discharging component is electrically connected between another end of the conducting element and the power ground node. When the voltage variation between the two ends of the electrostatic discharging element reaches a preset condition, the electrostatic discharging component functions as a short circuit; otherwise, the electrostatic discharging element is equivalent to a high impedance element. The power ground node electrically connects to an electrode of a battery for using it as a vessel of receiving electrostatic charges.09-22-2011
20080266731LEVEL CONVERSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE EMPLOYING THE LEVEL CONVERSION CIRCUIT - In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.10-30-2008
20090244796Electrostatic discharge protection circuit including ovonic threshold switches - An electrostatic discharge protection circuit may include ovonic threshold switches that have a holding voltage greater than an input voltage normally received from a pad. As a result, the ovonic threshold switches provide a low resistance state to shunt current from the pad when an electrostatic discharge protection event occurs and, otherwise, present an off device during normal circuit operations.10-01-2009
20090213508ESD protection for high-voltage-tolerance open-drain output pad - A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.08-27-2009
20090207541POWER STRIP HAVING SURGE PROTECTIVE DEVICES - The present invention provides a power strip having surge protective device. The power strip includes a first surge protective device, a buffer conductive device and a second surge protective device. When a surge is inputted into the power strip, the surge is subject to two-stage suppressions so as to protect the electrical appliances which are electrically connected to the power strip.08-20-2009
20090244797PROTECTION CIRCUIT - A protection circuit according to an embodiment of the present invention is provided between a first terminal and a second terminal and includes: a capacitor element having one end connected to the second terminal; and a multi-cathode thyristor formed on a semiconductor substrate, and including an anode connected to the first terminal, a first cathode connected to the second terminal, and a second cathode disposed between the anode and the first cathode and connected to another terminal of the capacitor element.10-01-2009
20090219658Electrostatic Discharge (ESD) Protection Circuit - An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three transistors may be connected in parallel between a bond (input or output) pad and a substantially fixed voltage level (e.g., a ground (or zero potential) or Vcc, depending on the transistor configuration) in a semiconductor electronic device so as to protect transistor gates or other circuit portions from damage from electrostatic voltages. The parasitic BJTs and the field transistor may be configured to remain cut off so long as an input voltage at the pad is between a negative V09-03-2009
20120106011SEMICONDUCTOR DEVICE AND SYSTEMS INCLUDING THE SAME - The semiconductor device is provided. The semiconductor device includes a substrate, an electrostatic discharge layer disposed on the substrate and including a plurality of electrostatic discharge circuits, at least one semiconductor chip stacked on the electrostatic discharge layer, and a plurality of vertical electrical connections which pass through the at least one semiconductor chip and the electrostatic discharge layer to connect the at least one semiconductor chip to the semiconductor substrate. The vertical electrical connections are connected to the electrostatic discharge circuits, respectively.05-03-2012
20120106010METHOD AND SYSTEM FOR ELECTROSTATIC DISCHARGE PROTECTION - A method and a system for ESD protection are provided. In one embodiment, the system comprises a circuit comprising at least one non-linear element, an application module configured to apply a set of current pulses to the circuit, a determination module configured to determine at least one frequency-dependent and amplitude-dependent transfer function of the circuit based on the set of applied current pulses, a modeling module configured to model at least one frequency-dependent and current-dependent impedance of the at least one non-linear element, and a simulation module to simulate a transmission to the circuit based on the model.05-03-2012
20090237848ELECTRO-MAGNETIC PULSE PROTECTION CIRCUIT WITH A COUNTER - An EMP protection circuit with a counter has a surge protection circuit capable of suppressing EMP, and also use an extra counting circuit for sensing light emission or variation of magnetic force of the surge protection circuit to count the action times of the surge protection circuit, thereby warning that the surge protection circuit has reached its time-limit of use and has to be replaced. In this way, various kinds of electronic products can be more perfectly protected to avoid higher loss.09-24-2009
20100265622ROBUST ESD PROTECTION CIRCUIT, METHOD AND DESIGN STRUCTURE FOR TOLERANT AND FAILSAFE DESIGNS - A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.10-21-2010
20090251834SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPARATUS - To prevent an electrostatic damage on a display device formed with a driving circuit. Protective circuits are provided not only at input terminal parts, but also at intermediate parts of a circuit or at the ends of wiring lines. Otherwise, the protective circuits are provided at the ends of the wiring lines and at the places immediately before and after the input terminals, respectively, and then the circuit is interposed therebetween. Further, the protective circuits are provided around a circuit with a large current consumption.10-08-2009
20120194953NON-LINEAR POWER MANAGEMENT DEVICE FOR INPUT POWER PROTECTION - In one general aspect, an apparatus can include a non-linear power management device having an output terminal configured to be coupled to an output shunt device configured to shunt energy in response to a voltage across the output shunt device exceeding a trigger voltage of the output shunt device. The non-linear power management device can be configured to change to a saturation mode in response to a first current associated with an energy pulse through the non-linear power management device. The apparatus can include an input shunt device coupled to an input terminal of the non-linear power management device and having a trigger voltage higher than the trigger voltage of the output shunt device. The input shunt device can be configured to shunt a second current associated with the energy pulse in response to a voltage drop across the non-linear power management device.08-02-2012
20090316316ELECTRICAL CIRCUIT - An electrical circuit includes a first power supply line, a second power supply line, a detection circuit, a first switch device, and a nonlinear device. The detection circuit is connected to the first power supply line, and includes an output section that outputs a detection signal by detecting a change in potential of the first power supply line. The first switch device is provided between the first power supply line and the second power supply line, and is controlled by the detection signal. The nonlinear device is provided between the first or the second power supply line and the output section.12-24-2009
20090273869Electrostatic discharge protection diode - Provided is an electrostatic discharge (ESD) protection diode including: a well formed of a first conductivity in a semiconductor substrate; an active region that is formed of a second conductivity in the well and includes a plurality of first active lines extending in a first direction; a sub-region of the first conductivity including a plurality of first sub-lines extending in the first direction, the first sub lines being formed in the well, arranged to surround an outer region of the first active lines, and arranged in alternation with the first active lines; a device isolation region separating the active regions and the sub-regions; a plurality of active contacts arranged in a row in the active regions; and a plurality of sub-contacts arranged in a row in the sub-region.11-05-2009
20090273867MULTI-VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION - An electrostatic discharge (ESD) clamp (11-05-2009
20090273868TRANSIENT VOLTAGE SUPPRESSOR AND METHOD - A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.11-05-2009
20100149701ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD - A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants. In addition, an ESD feedback circuit is employed in conjunction with control logic to suitably control the ESD control logic during an ESD event. Circuitry is also used during a power up event to render the shunt structure non-conductive.06-17-2010
20100149702DC Noise Absorbing Device for Preventing Surges and Regulating Voltages - A DC noise absorbing device for preventing surges and regulating voltages includes a surge inhibitor, a fuse wire, a plurality of diodes, a plurality of Zener diodes, a plurality of diode alternate current switches (DIACs), a plurality of capacitors, and a circuit for indicating light emission, all of which are disposed on or between two wires respectively of positive voltage and negative voltage. The surge inhibitor and the fuse wire are connected in series on the wire of positive voltage; the plurality of diodes, the plurality of Zener diodes, the plurality of DIACs, the plurality of capacitors, which are identically specified, and the circuit for indicating light emission are orderly connected in parallel between the wires of positive voltage and negative voltage so as to form a staircase arrangement of cut-in switching voltages. The DC noise absorbing device provided by the present invention is connected in parallel with and between a DC supply and a DC load, for absorbing surges generated by switching the DC supply and the DC load, voltage fluctuations caused by load variation, serial surges rebounding from the DC load, and noises produced by external interference so that a stable operation and a promoted efficiency of the DC system can be achieved.06-17-2010
20100157492ELECTRONIC DEVICE AND ASSOCIATED METHOD - An electronic device is provided that includes an electronic component or passive components; an electrically conductive circuit coupled to the electronic component; and a protection device coupled to the circuit. The protection device is operable to route a voltage or current away from the electronic component if the voltage or the current applied to the circuit is above a determined threshold voltage or determined threshold current.06-24-2010
20100157494ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - A ESD protection circuit includes: a first clamp connected between a first power line and a ground line; a second clamp connected between the ground line and a second power line; a first output buffer connected between the first power line and the ground line, and providing a first operating voltage; a second output buffer connected between the ground line and the second power line, and providing a second operating voltage; a first switch unit configured to transfer the first operating voltage to an I/O pad; a second switch unit configured to transfer the second operating voltage to the I/O pad; a first transfer unit comprising one or more diodes connected in series between the first power line and the I/O pad; and a second transfer unit comprising one or more diodes connected in series between the I/O pad and the second power line.06-24-2010
20100157496ESD protection device and composite electronic component of the same - The present invention provides an ESD protection device and the like having improved durability against repeated use. An ESD protection device includes a base having an insulating surface, electrodes disposed on the insulating surface and facing but spaced apart from each other, and a functional layer 4-disposed on at least between the electrodes. The electrodes have a multistage structure in which a gap between the electrodes is narrower toward the base.06-24-2010
20120033336DEBUG INTERFACE CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - A debug interface circuit connecting between a connector and an integrated circuit (IC) of an electronic device. The connector is used for providing a path for a debug device debugging the IC. The debug interface circuit includes a first electrostatic protection unit and a second electrostatic protection unit. One end of the first electrostatic protection unit is electrically connected between a first pin of the IC and an output port of the connector, and the other end of the first electrostatic protection unit is electrically grounded. One end of the second electrostatic protection unit is electrically connected between a second pin of the IC and an input port of the connector, and the other end of the second electrostatic protection unit is electrically grounded. The first pin is used for receiving signals from the output port. The second pin used for transmitting signals to the input port.02-09-2012
20100188787METHOD AND APPARATUS TO REDUCE FOOTPRINT OF ESD PROTECTION WITHIN AN INTEGRATED CIRCUIT - An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.07-29-2010
20100002346ANTISTATIC DEVICE WITH MULTIPLE DISCHARGING INTERVALS - An antistatic device with multiple discharging intervals is applied to electrical components for providing an optimized protection against ESD (Electrostatic Discharge). The antistatic device includes a trace, a discharging portion and multiple grounding portions. The trace allows electrostatic current to pass through. The discharging portion is coupled to the trace. The grounding portions are placed around the discharging portion. A discharge interval between each of the grounding portions and the discharging portion allows the electrostatic current to be discharged through any of the grounding portions. Each of the discharging intervals is equidistant to facilitate equal discharge probabilities.01-07-2010
20100020456ELECTROSTATIC GUIDING STRUCTURE WITH METAL OXIDE GENERATED THROUGH ANODIC OXIDATION - An electrostatic guiding structure with metal oxide generated through anodic oxidation includes a metallic case, an oxide layer, a system ground layer, and at least one conductor. The metallic case has an accommodating space, and the system ground layer and the conductor are both located in the accommodating space. The metallic case has an oxide layer formed on a surface thereof after an anode processing. The conductor is electrically connected to the oxide layer on an inner surface of the metallic case and the system ground layer, such that the static electricity is released from the metallic case to the system ground layer.01-28-2010
20100014200ESD PROTECTION CIRCUIT FOR HIGH SPEED SIGNALING INCLUDING A SWITCH - An ESD protection circuit for a switch coupled to high-speed signaling pins of an integrated circuit includes a first string of clamping elements and a second string of clamping elements. The first string of clamping elements has a collective capacitance less than the capacitance of a single clamping element. The first string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a first polarity ESD voltage is applied to the high-speed pins. The second string of clamping elements has a collective capacitance less than the capacitance of one clamping element. The second string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a second polarity ESD voltage is applied to the high speed signaling pins.01-21-2010
20100259857INTEGRATED CIRCUIT INCLUDING ESD DEVICE - An integrated circuit including ESD device is disclosed. One embodiment includes a semiconductor region being electrically isolated from adjacent semiconductor regions by an isolating region. Both an ESD device and a device configured to emit radiation are formed within the semiconductor region.10-14-2010
20100188788Electrostatic Discharge Protection Circuit - An integrated circuit having a plurality of circuit blocks, each block having one or more positive voltage supply pads, one or more negative voltage supply pads, and one or more signal pads. The integrated circuit further comprises an electrostatic protection circuit comprising a first electrostatic discharge protection rail for connection to a positive voltage supply point, a second electrostatic discharge protection rail for connection to a negative voltage supply point, and first protection circuitry coupling each said signal pad to both said first and second electrostatic discharge protection rails, the first protection circuitry being configured to provide a conduction path to one of the first and second rings in the event of an excessive voltage being present on one of said signal pads.07-29-2010
20100165523INTEGRATED CIRCUIT - An integrated circuit includes: a pad configured to receive an external signal; an electrostatic discharge (ESD) protector coupled with the pad to provide an ESD path to a power source voltage line and a ground voltage line; an input buffer configured to receive the signal applied to the pad through an input terminal; and a PMOS transistor coupled between the input terminal of the input buffer and the ground voltage line, with a gate terminal coupled with the power source voltage line.07-01-2010
20100157491ELECTROSTATIC DISCHARGE PROTECTIVE CIRCUIT HAVING RISE TIME DETECTOR AND DISCHARGE SUSTAINING CIRCUITRY - Methods and devices of the invention include an electrostatic discharge (ESD) protection circuit. This circuit includes rise time dependent activation circuitry capable of detecting a slew rate of an input signal and capable of determining whether the slew rate of the input signal is greater than a threshold value. For an ESD event said activation circuitry generates a trigger signal. Additionally, the activation circuitry is coupled with the ESD dissipation duration control circuitry which is further coupled with an ESD dissipation circuit. This arrangement enabling the duration control circuit to be activated by the trigger signal which responds by producing an activation signal that activates the ESD dissipation circuitry and that controls the length of time the dissipation circuit remains active. The ESD dissipation circuitry includes a shunt that redirects the ESD energy away from the protected internal circuit. The ESD dissipation duration circuitry further configured to maintain shunting of the energy for a period of time sufficient to discharge of the ESD energy without damaging the protected circuitry.06-24-2010
20100296214PROTECTIVE CIRCUIT FOR THE INPUT-SIDE PROTECTION OF AN ELECTRONIC DEVICE OPERATING IN THE MAXIMUM FREQUENCY RANGE - The invention relates to a protective circuit (11-25-2010
20100214705Electrostatic discharge protection element and electrostatic discharge protection circuit including the same - An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.08-26-2010
20100182724COMPOSITE ELECTRONIC DEVICE AND DIGITAL TRANSMISSION CIRCUIT USING THEREOF - A composite electronic device includes first and second magnetic substrates, and a functional layer sandwiched between these magnetic substrates, and the functional layer is configured by a common-mode filter layer and a ESD protection element layer. An electrostatic capacitance of the ESD protection elements is equal to or lower than 0.35 pF. The common-mode filter layer includes a first spiral conductor formed on an insulation layer, and a second spiral conductor formed on an insulation layer. DC resistance of a common mode filter is equal to or higher than 0.5Ω and equal to or lower than 5Ω, and an electrostatic capacitance of the ESD protection elements is equal to or lower than 0.35 pF. A width W and a length L of the first and second spiral conductors satisfy a relational equation expressed by √(L/W)<(7.6651−fc)/0.1385.07-22-2010
20130215540High Voltage Electrostatic Discharge Clamp Using Deep Submicron CMOS Technology - An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.08-22-2013
20100226056METHODOLOGY TO GUARD ESD PROTECTION CIRCUITS AGAINST PRECHARGE EFFECTS - An ESD protection circuit (09-09-2010
20100226054Energy Storage Discharge Circuitry - Storage device discharge means and methods are provided. Printer circuitry detects one or more anomalous operating conditions and asserts a switch, shunting storage capacitors to ground potential through a resistive load. Discharge of the storage capacitors protects inkjet firing resistors against damage that could otherwise result from the uncontrolled application of stored electrical energy.09-09-2010
20100232079SMALL AREA IO CIRCUIT - A small area IO circuit is provided. The IO circuit has one or more parallel circuit unit(s) and an ESD protector set between a core circuit/pre-driver and an IO pad. Each circuit unit includes an off-chip driver and an output resistor, wherein the ESD protector protects ESD event occurred at the IO pad, and the resistor in each circuit unit acts as an ESD block circuit to block ESD current from corresponding off-chip driver. Therefore, transistors in each off-chip driver do not have to be restricted by strict ESD design rules, such that at least a transistor of the off-chip driver(s) is implemented in a single finger layout to lower equivalent capacitance of the off-chip driver(s), and layout areas of the off-chip driver(s) as well as the whole IO circuit can be reduced to achieve a small area IO circuit.09-16-2010
20100149704ESD PROTECTION CIRCUIT - An ESD protection circuit includes a detector coupled between a data power source line and a data ground voltage line to detect static electricity and to output a detection voltage at a detection node, a pre-driver coupled between a power source voltage line and a ground voltage line to output a driving signal at a control node, a data output driver coupled between a data input/output pad and the data ground voltage line to output data in response to the driving signal, and a controller coupled between the control node and the data ground voltage line to couple a terminal of the data output driver with the data ground voltage line based on the detection voltage when the static electricity is input.06-17-2010
20100149705ESD PROTECTION CIRCUIT INCLUDING MULTI-FINGER TRANSISTOR - Provided is an electrostatic discharge (ESD) protection circuit including a multi-finger transistor. The multi-finger transistor includes a plurality of drains and a plurality of sources alternately arranged in parallel, and a plurality of gate electrodes arranged between the drains and the sources. The drains are electrically coupled to an input/output pad through a plurality of first finger patterns which are coupled to a plurality of first contact patterns. The sources are electrically coupled to a specific voltage line through a path which comprises a plurality of second finger patterns coupled to a plurality of second contact patterns. The number of the first contact patterns corresponding to the drains is gradually reduced as the distance to the voltage line becomes shorter.06-17-2010
20100238599Power Supply Equalization Circuit Using Distributed High-Voltage and Low-Voltage Shunt Circuits - Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.09-23-2010
20100238598Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices - Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.09-23-2010
20090109584SURGE PROTECTION CIRCUIT FOR PASSING DC AND RF SIGNALS - A surge protection circuit may include a tuned circuit board with traces designed to provide a surge protected and RF isolated DC path while propagating RF signals through the PCB dielectric with microstrip lines. The surge protection circuit utilizes high impedance RF decoupling devices such as quarterwave traces or inductors which isolate the multistage DC protection scheme which may include a gas discharge tube, serial surge impeding devices such as inductors and/or resistors, a decoupled air/spark gap device and a Zener diode junction.04-30-2009
20090109582Method of protecting circuits using integrated array fuse elements and process for fabrication - In one exemplary embodiment, a detector of electromagnetic radiation includes: a substrate; at least one layer of semiconductor material formed on the substrate, said at least one layer of semiconductor material defining a radiation absorbing and detecting region; an electrical contact configured to couple said region to a readout circuit; and a fuse coupled between the region and the electrical contact. In another exemplary embodiment, a fusible link between a first component and a second component is provided and includes: a fuse with an undercut located underneath at least a portion of the fuse; a first contact coupling the first component to the fuse; and a second contact coupling the second component to the fuse, wherein the undercut is disposed between the first contact and the second contact. In another exemplary embodiment, a fusible link includes a fuse having a layer of material having a negative temperature coefficient of resistance.04-30-2009
20100157495CIRCUITS AND METHODS FOR PROTECTION OF BATTERY MODULES - A circuit includes multiple battery modules and protection circuits respectively coupled to the battery modules. Each protection circuit includes a controller and a shunt circuit. The controller is coupled to one of the battery modules and detects a fault associated with the battery module. The shunt circuit is coupled to the battery module and the controller, and shunts a current around the battery module if the fault associated with the battery module is detected by the controller.06-24-2010
20100254051Overvoltage Protection Circuits that Inhibit Electrostatic Discharge (ESD) and Electrical Overstress (EOS) Events from Damaging Integrated Circuit Devices - An overvoltage protection circuit includes primary and secondary clamping circuits. The primary clamping circuit is configured to sink overvoltage current from a power supply voltage node (e.g., Vdd) to a reference voltage node (e.g., Vss) in response to an overvoltage condition at the power supply voltage node. The secondary clamping circuit, which is electrically coupled to an output of the primary clamping circuit, is configured to sink additional overvoltage current from the power supply voltage node to the reference node in response to detection of a overvoltage flag at the output of the primary clamping circuit. This overvoltage flag may be represented by a transition (e.g., low-to-high or high-to-low) of a signal generated at an output of the primary clamping circuit.10-07-2010
20110058293 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT, EQUIPMENT AND METHOD - An electrostatic discharge (ESD) protection circuit for protecting one or more devices in an electronic circuit from an ESD current which enters the electronic circuit through one or more input/output pins, the protection circuit comprising: a voltage clamp circuit connectable to the or each pin, for diverting the ESD current from the or each device; and a current sensor circuit connected between the input/output pins and the voltage clamp circuit and connected to the one or more devices, the current sensor circuit for sensing the ESD current and for switching off the or each device when the sensed current exceeds a threshold value, wherein when a current flows in the current mirror circuits above a threshold value the device is caused to switch off.03-10-2011
20110058292Integrated RF ESD Protection for High Frequency Circuits - The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.03-10-2011
20110058291GEOMETRIC CONFIGURATION OR ALIGNMENT OF PROTECTIVE MATERIAL IN A GAP STRUCTURE FOR ELECTRICAL DEVICES - an electrical device that includes a first electrode and a second electrode that are separated from one another so as to form a gap structure. A layer of protective material spans the gap structure to contact the first electrode and the second electrode. A dimension of the gap structure, corresponding to a separation distance between the first electrode and the second electrode, is varied and includes a minimum separation distance that coincides with a critical path of the layer of protective material between the first electrode and the second electrode.03-10-2011
20110058290SHARED ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUIT OUTPUT DRIVERS - A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (R03-10-2011
20120243133ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit is for protecting an internal circuit electrically coupled to an input/output (I/O) pad. The ESD protection circuit comprises an ESD protection unit, to be electrically coupled to the I/O pad, for enabling release of an electrostatic charge at the I/O pad to a ground terminal. The ESD protection circuit also comprises a voltage detecting unit, electrically coupled to the ESD protection unit and to be electrically coupled to the I/O pad, for detecting the presence of an ESD voltage at the I/O pad and for controlling the ESD protection unit to establish a conduction path between the I/O pad and the ground terminal when the ESD voltage is detected.09-27-2012
20100220419ESD PROTECTION CIRCUIT - An ESD protection circuit comprises a first supply line (V09-02-2010
20090310268NANOTUBE ESD PROTECTIVE DEVICES AND CORRESPONDING NONVOLATILE AND VOLATILE NANOTUBE SWITCHES - Nanotube ESD protective devices and corresponding nonvolatile and volatile nanotube switches. An electrostatic discharge (ESD) protection circuit for protecting a protected circuit is coupled to an input pad. The ESD circuit includes a nanotube switch electrically having a control. The switch is coupled to the protected circuit and to a discharge path. The nanotube switch is controllable, in response to electrical stimulation of the control, between a de-activated state and an activated state. The activated state creates a current path so that a signal on the input pad flows to the discharge path to cause the signal at the input pad to remain within a predefined operable range for the protected circuit. The nanotube switch, the input pad, and the protected circuit may be on a semiconductor chip. The nanotube switch may be on a chip carrier. The deactivated and activated states may be volatile or non-volatile depending on the embodiment. The ESD circuit may be repeatedly programmed between the activated and deactivated states so as to repeatedly activate and deactivate ESD protection of the protected circuit. The nanotube switch provides protection based on the magnitude of the signal on the input pad.12-17-2009
20100208398ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND INTEFRATED CIRCUIT UTILIZING THE SAME - An ESD protection circuit coupled between a first power line and a second power line to avoid damage to an integrated circuit by an ESD event is disclosed. The ESD protection circuit includes a detection unit, a trigger unit, and a discharging unit. The detection unit asserts a detection signal when the ESD event occurs. The trigger unit asserts a first trigger signal and a second trigger signal when the detection is asserted. The discharging unit provides a discharge path to release an ESD current caused by the ESD event when the first and the second trigger signals are asserted.08-19-2010
20100208400Pad interface circuit and method of improving reliability of the pad interface circuit - The pad interface circuit includes a first stack MOS transistor having a first terminal connected to a pad and a bulk connected to a first supply voltage; a second stack MOS transistor having a first terminal connected to a second terminal of the first stack MOS transistor and a second terminal, a gate terminal, and a bulk that are connected to the first supply voltage; and a voltage level sensing circuit generating a feedback voltage by using a pad voltage applied from the pad. In addition, the feedback voltage is applied to a gate terminal of the first stack MOS transistor.08-19-2010
20100246076Electrical Overstress Protection Circuit - A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.09-30-2010
20100254050INTEGRATED CIRCUIT PROTECTION DEVICE - A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.10-07-2010
20100118454ESD PROTECTION CIRCUITRY WITH MULTI-FINGER SCRS - Self-triggered Multi-finger SCRs used in ESD protection circuitry capable of turning on all SCR fingers of the multi-finger SCRs include a first source, a second source, N SCR units, (N−1) diodes, and N resistors. Each of the N SCR units includes a first node, a second node coupled to the second source, and a trigger node. An nth diode of the (N−1) diodes is coupled between a first node of an nth SCR unit and a trigger node of an (n+1)th SCR unit. An nth resistor is coupled between the first node of the nth SCR unit and the first source, wherein n and N are integers. The (N−1) diodes can be replaced by directly coupled the first node of the nth SCR unit to the trigger node of the (n+1)th SCR unit when a trigger pulse is applied at the trigger node of a first SCR unit.05-13-2010
20080232012METHOD FOR IMPROVED TRIGGERING AND OSCILLATION SUPRESSION OF ESD CLAMPING DEVICES - An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.09-25-2008
20090290274REMOVABLE MEMORY CARD - According to the present invention, the setting height position of a first terminal is set to be lower than the setting height position of a second terminal on the terminal formation surface of a printed substrate, so that the protection of an internal circuit and the transmission of a high-speed signal can be both achieved.11-26-2009
20100202091SEMICONDUCTOR DIODE STRUCTURE OPERATION METHOD - A semiconductor structure operation method. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.08-12-2010
20110176247PRECISION HIGH-FREQUENCY CAPACITOR FORMED ON SEMICONDUCTOR SUBSTRATE - A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.07-21-2011
20100195256METHOD AND APPARATUS FOR PROTECTING POWER SYSTEMS FROM EXTRAORDINARY ELECTROMAGNETIC PULSES - One form of the invention provides a method and apparatus for preventing an extraordinary electromagnetic pulse from reaching and rendering inoperative an electrical component of an electrical power system, wherein the component is located in a conductive path of the system that receives the pulse. The method and apparatus comprises the steps or means for detecting the presence of the pulse in the conductive path prior to the pulse reaching and rendering inoperative the electrical component. The pulse is diverted around the electrical component with a low inductance, high current capacity circuit relative to the electrical component before the pulse can reach and render the electrical component inoperative. The foregoing invention may beneficially utilize a high-speed current shunt comprising a flat conductive metal strap having a defined current-measuring region, a tapered parallel-plate transmission-line matching transformer attached to the current-measuring region and an output via a coaxial cable.08-05-2010
20090116156PORTABLE ELECTRONIC DEVICE - In the portable electronic device of the present invention, charging electrodes exposed to the exterior of a casing are electrically connected to a pair of charging terminals mounted upright on the printed circuit board, and a charging terminal (negative electrode, or ground) that is one of the pair of charging terminals is connected to the ground of the printed circuit board. A high-frequency current suppression part is mounted in a series connection on the charging terminal (negative electrode, or ground). The high-frequency current suppression part is a ferrite core, ferrite beads, or another low resistance part. In such a configuration, a secondary electric discharge occurs via the externally exposed charging electrodes and the like when electrostatic discharge noise is applied from the exterior of the portable electronic device and when the ground current of the printed circuit board oscillates due to the discharge electric current that flows at this time, whereby circuit malfunctions are prevented.05-07-2009
20090040669INTEGRATED CIRCUIT WITH DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit includes a substrate of semiconductive material, a first circuit environment made from the substrate which includes an output terminal and a first pair of power supply terminals for receiving a first power supply voltage applicable between the terminals. The integrated circuit also includes a second circuit environment made from the semiconductor substrate which includes an input terminal electrically coupled to the output terminal and also includes a second pair of power supply terminals for receiving a second power supply voltage applicable between the second pair of terminals of said second pair. The circuit further includes a device providing protection from electrostatic discharges which includes an integrated resistive device coupled between the input and output terminals.02-12-2009
20090073621Fast Triggering ESD Protection Device and Method for Designing Same - A method and apparatus for designing an ESD protection circuit comprising a main ESD device and a triggering device connected to a triggering node of the main ESD device by means of which the main ESD device can be triggered for conducting ESD current at a reduced voltage. The triggering device is located in an initial current path for the ESD current. In this initial current path, there is at least one triggering component which can be triggered from an off-state to an on-state. The triggering speed of this component is considered and its design is optimised in view of increasing its triggering speed. Further shown is an ESD protection circuit in which at least one triggering component is selected to be of a predetermined type for achieving a fast triggering speed, preferably of the gated diode type.03-19-2009
20090073619ESD/EOS PROTECTION CIRCUIT AND RELATED INTEGRATED CIRCUIT - An ESD/EOS protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit is coupled between an I/O pad and a power pad and includes a first P-type transistor. The P-type transistor includes a control node, a floating gate, a first connection node, and a second connection node, wherein the first connection node of the first P-type transistor is coupled to the power pad and the second connection node of the first P-type transistor is coupled to the I/O pad. The second protection circuit is coupled between the I/O pad and a ground pad.03-19-2009
20090073620Circuit Arrangement Comprising an Electronic Component and an ESD Protection Arrangement - A description is given of a circuit arrangement including at least one electronic component having first and second terminals, and comprising an ESD protection arrangement against disturbance pulses, is the ESD protection arrangement connected via connection terminals in parallel with the electronic component between the first and second terminals. The ESD protection arrangement includes a first ESD protection unit and a second ESD protection unit, that is connected in parallel with the first ESD protection unit and that reacts more rapidly than the first protection unit to a voltage rise at the connection terminals with the formation of a conductive current path between the connection terminals.03-19-2009
20090231765TRANSIENT TO DIGITAL CONVERTERS - A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal.09-17-2009
20090323237Electrostatic Discharge Circuit - An electrostatic discharge device has relatively superior characteristics for protecting a gate insulation layer of an input buffer transistor of a semiconductor device from static electricity while minimizing signal delay. The electrostatic discharge circuit includes a main electrostatic discharge section configured to discharge static electricity inputted to an input/output pad to at least one voltage line, an input impedance section configured to adjust an amount of current flowing from the input/output pad depending upon a frequency of an input signal of the input/output pad, an auxiliary electrostatic discharge section connected to the input impedance section and configured to discharge the static electricity inputted to the input/output pad to the at least one voltage line, and an input buffer connected between the auxiliary electrostatic discharge section and an internal circuit.12-31-2009
20090323236Semiconductor device - In order to solve a problem in a conventional semiconductor device that improvement of resistance to electrostatic discharge damage or improvement of an area efficiency is severely restricted, there is provided a semiconductor device including: a first protection diode (DP) having an anode which is connected to a signal wire connected to an I/O pad (PAD), and having a cathode which is connected to a power supply wire (VDD); a power clamp circuit (12-31-2009
20120033337CIRCUIT ARRANGEMENT AND METHOD FOR SIMULATING A SENSOR - A circuit arrangement for simulating a sensor includes two external connections configured to change at least one of a current intensity and a resistance between the two external connections as a function of a measured variable. The circuit arrangement comprises: (a) a current path connecting the two external connections having two field-effect transistors and a resistor, and (b) a circuit configured to actuate gates of the two field-effect transistors so as to at least one of control and regulate a current through the current path, wherein the resistor is configured as a shunt resistor connected to a bridge rectifier and the circuit configured to actuate the gates of the two field-effect transistors comprises a control circuit configured to detect and regulate the current in the current path via a voltage drop at the shunt resistor.02-09-2012
20090180225ESD PROTECTION STRUCTURE - An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.07-16-2009
20110032647Semiconductor device including esd protection field effect transistor with adjustable back gate potential - A semiconductor device includes a first circuit block powered by voltages at first and second power supply terminals, a second circuit block powered by voltages at third and fourth power supply terminals, a first ESD (electrostatic discharge) protection circuit including a first field effect transistor having a source, a drain, and a gate, where the gate and one of the source and the drain are connected to the first power supply terminal, the other of the source and the drain is connected to the third power supply terminal, and a first back gate potential adjusting circuit adapted to adjust a potential at a back gate of the first field effect transistor. The first field effect transistor includes a first conductivity type transistor formed in a first well of a second conductivity type serving as the back gate of the first field effect transistor.02-10-2011
20110032649ESD PROTECTIVE DEVICE HAVING LOW CAPACITANCE AND STABILITY AND A PREPARING PROCESS THEREOF - An ESD protective device having a low capacitance and stability characteristics constructed by installing a voltage sensitive material between electrodes. The voltage sensitive material comprises a fluorescent substance. The voltage sensitive material may be barium aluminate. The voltage sensitive material may be zinc silicate. The voltage sensitive material may be zinc sulfide. The voltage sensitive material is doped with a metal atom such as Mn, Cu and Eu. The device does not distort a signal wave pattern and have low capacitance of 0.5 pF or lower.02-10-2011
20090168279ESD protection circuit with gate voltage raising circuit - An ESD protection circuit with a gate voltage raising circuit is disclosed. The ESD protection circuit with a gate voltage raising circuit is used in a large size open drain circuit. A gate voltage raising circuit is used in the ESD protection circuit for raising the gate voltage of a NMOS.07-02-2009
20090141415ELECTROSTATIC DISCHARGE CIRCUIT - An electrostatic discharge circuit includes a trigger section configured to detect voltage drops occurring by an electrostatic current transmitted to first and second voltage lines, and to provide pull-up and pull-down detection voltages, an auxiliary discharge section configured to operate by the pull-up and pull-down detection voltages, and to discharge the electrostatic current introduced through an input/output pad to the first and second voltage lines, a main discharge section configured to operate by the pull-down detection voltage, to electrically connecting the first and second voltage lines, and to discharge the electrostatic current, and a CDM discharge section configured to operate by the pull-down detection voltage, and to discharge the electrostatic current supplied from the input/output pad to an internal circuit.06-04-2009
20090128971SEMICONDUCTOR INTEGRATED CIRCUIT - The invention provides a semiconductor integrated circuit preventing an electrostatic breakdown due to a surge voltage applied to a power supply wiring or a ground wiring and preventing noise interference between a digital circuit and an analog circuit. By providing a first electrostatic breakdown protection diode and a first electrostatic breakdown protection bipolar transistor in a first island region, the first electrostatic breakdown protection diode and the first electrostatic breakdown protection bipolar transistor turn on when a surge voltage is applied to a first ground wiring and protect a digital circuit against an electrostatic breakdown. Furthermore, a first isolation layer is contacted with the first ground wiring in a position that is more adjacent to a first ground pad than the digital circuit, and a second isolation layer is contacted with a second ground wiring in a position that is more adjacent to a second ground pad than an analog circuit. This prevents noise interference between the digital circuit and the analog circuit.05-21-2009
20090009916ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR MIXED VOLTAGE INTERFACE - An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.01-08-2009
20100309593SEMICONDUCTOR DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION METHOD FOR THE SEMICONDUCTOR DEVICE - For enhancing performance of the electrostatic discharge protection for a semiconductor IC (integrated circuit), the electrostatic discharge protection circuit includes: a power source system for supplying a current to a semiconductor IC in the semiconductor device through a power source potential line and a reference potential line; a primary protection circuit for releasing a surge current to the power source system through a first node connected to a signal terminal when the surge current is generated at the signal terminal; a trigger circuit for generating a trigger signal in response to a surge voltage generated at the power source system; and a secondary protection circuit. The secondary protection circuit releases the surge current to the power source system through a second node connected between the first node and the semiconductor IC in response to the trigger signal, so that the surge voltage can be rapidly suppressed near the semiconductor IC.12-09-2010
20090116157ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND METHOD THEREFOR - An electrostatic discharge protection apparatus comprises a stack arrangement having a first electrostatic discharge protection element and a second electrostatic discharge protection element. The stack arrangement is arranged to provide a bias potential between the first and second electrostatic discharge protection elements. In one embodiment, the bias potential can be achieved by a clamp arrangement coupled across the stack arrangement.05-07-2009
20100302693SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention provides a technique capable of realizing an ESD protection performance having a high ESD withstand voltage in a small layout area. An ESD protection circuit includes a clamping circuit, Zener diodes, a transistor comprised of a DMOS, a transistor comprised of an IGBT, and resistors. The ESD protection circuit effectively protects the protected circuit such that the transistor comprised of the DMOS is caused to absorb the current noise at the time of operating the protected circuit to prevent malfunction due to latchup and the IGBT (the transistor comprised of IGBT) whose current absorption capacity is increased by the thyristor effect is operated in parallel for a large current at the time of ESD.12-02-2010
20100302694Electrostatic discharge protection circuit - It is desired to achieve a high ESD protection performance by a small area circuit. An electrostatic discharge protection circuit includes: protection circuits, wherein each protection circuit includes a MOS transistor; and a trigger circuit configured to supply a trigger signal to a gate electrode of the MOS transistor of each protection circuit in response to a surge voltage between a low potential node and a high potential node. Each protection circuit is configured to electrically connect the low potential node and the high potential node to one another when the trigger signal is supplied to the gate electrode. The gate electrode of each protection circuit is connected to a resistive element having larger resistance value than Rmax, supposing that Rmax is a largest parasitic resistance between each of the plurality of protection circuit and an output of the trigger circuit.12-02-2010
20110122537ELECTRONIC APPARATUS - An electronic apparatus including an electrostatic discharge (ESD) protection circuit, an abnormal voltage detection circuit, an internal circuit and a blocking circuit is provided. The ESD protection circuit receives a plurality of input signals for preventing an abnormal high voltage damage produced by an ESD phenomenon on a path for delivering the input signals, and correspondingly outputs a plurality of voltage-dropped input signals. The input signals include a control signal set and a data signal set. The abnormal voltage detection circuit is coupled to the ESD protection circuit. The abnormal voltage detection circuit receives the voltage-dropped input signals, and produces a blocking control signal according to voltage levels of the voltage-dropped input signals. The blocking circuit is used for receiving the blocking control signal and blocking the control signal set from delivering to the internal circuit according to the blocking control signal.05-26-2011
20100321843Semiconductor ESD Device and Method of Making Same - A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.12-23-2010
20100321842Electrostatic Discharge Structures and Methods of Manufacture - Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.12-23-2010
20130141823RC-Triggered ESD Clamp Device With Feedback for Time Constant Adjustment - Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.06-06-2013
20100321841ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - Disclosed herein are embodiments of electrostatic discharge (ESD) protection circuits. In certain embodiments an ESD protection circuit may include two series resistor-capacitor (RC) circuits. One series RC circuit may have a short time constant and may selectively activate a current shunt between two power rails in response to an ESD event. Accordingly, the ESD circuit may be able to respond to fast ramping ESD events. The other series RC circuit has a longer time constant, and maintains the current shunt in an active state for a sufficient amount of time to allow the ESD event to be completely discharged.12-23-2010
20110002072INPUT-OUTPUT INTERFACE CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An input-output interface circuit of the present invention includes an input-output terminal, an input buffer, a first MOS transistor of a first conductivity type formed in a floating well region, an output buffer for outputting a signal externally through the input-output terminal, an electrostatic protection circuit, and a floating well potential adjusting circuit, wherein the electrostatic protection circuit has a first resistance, and a diode connected between another end of the first resistance and a high level power supply potential, and the floating well potential adjusting circuit has a second resistance having one end connected to the input-output terminal, and a second MOS transistor of the first conductivity type having one end connected to another end of the second resistance, another end connected to the floating well region, and a gate connected to the high level power supply potential.01-06-2011
20110007437SEMICONDUCTOR DEVICE - A semiconductor device which can achieve high breakdown voltage and high ESD tolerance of a current drive output terminal at the same time, and can quicken the response speed of a current flowing through the current drive output terminal. The inventive semiconductor device is provided, between the current drive output terminal and a first transistor or a low breakdown voltage element, with a second transistor having a breakdown voltage higher than that of the first transistor or that of the low breakdown voltage element. Furthermore, the inventive semiconductor device is provided with a diode having an anode connected with a path between the first transistor or the low breakdown voltage element and the second transistor, and a cathode connected with an ESD protection circuit.01-13-2011
20110026176ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit includes an output driver, a bypass unit, and an output driver control unit. The output driver is coupled to a data output pad. The bypass unit is configured to bypass the output driver in conducting an ESD current to a ground voltage terminal. The output driver control unit is configured to interrupt an operation of the output driver when the bypass unit operates.02-03-2011
20090067105ESD PROTECTION CIRCUIT AND METHOD - A system includes a driving device operating at first supply voltage V03-12-2009
20090067107Electrostatic Discharge Protective Circuit and Semiconductor Integrated Circuit Using the Same - An electrostatic discharge protective circuit including an ESD protective circuit which has a trigger terminal and forms a discharge path from a first node to a second node when trigger signals are supplied to the trigger terminal, a trigger circuit included in a circuit to be protected which is connected between the first and second nodes, the trigger circuit having a first MOS device, and which functions as a part of the circuit to be protected at the time of normal operation when ESD voltage is not applied, and forms a conductive path between a drain and source of the MOS device when ESD voltage of a predetermined value or more is applied to the first node during a normal operation, and supplying the trigger signals to the trigger terminal of the ESD protective circuit when the first MOS device becomes conductive.03-12-2009
20110110004Circuit Arrangement for Protection from Electrostatic Discharges and Method for Operating Same - A circuit arrangement for protection against electrostatic discharges has a diverting structure (ESD05-12-2011
20110019320ESD NETWORKS FOR SOLDER BUMP INTEGRATED CIRCUITS - Semiconductor dice (01-27-2011
20110026173ENHANCED IMMUNITY FROM ELECTROSTATIC DISCHARGE - Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node.02-03-2011
20110026177USING A PASSIVE FUSE AS A CURRENT SENSE ELEMENT IN AN ELECTRONIC FUSE CIRCUIT - A system comprising a transistor, a passive fuse coupled to the transistor, and control logic coupled to both the transistor and the passive fuse. The control logic determines the current flowing through the passive fuse, by sensing the voltage drop across the passive fuse, and the sends a signal to the transistor to turn off if the current through the passive fuse exceeds a predetermined value.02-03-2011
20110032648ESD PROTECTION - An electrostatic discharge protection structure (02-10-2011
20090174973MIGFET CIRCUIT WITH ESD PROTECTION - An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.07-09-2009
20090109583ESD PROTECTION CIRCUIT FOR INSIDE A POWER PAD OR INPUT/OUTPUT PAD - An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an I/O pad of an electronic circuit, the ESD protection circuit comprising an electrostatic discharge (ESD) circuit that, when activated, discharges an ESD from a first voltage bus to a second voltage bus. The second voltage bus is at a lower electrical potential than the first voltage bus. An ESD discharge control circuit in electrical connection with the ESD discharge circuit that controls the activation of the ESD discharge circuit and including an NMOS transistor and an electrical node. The NMOS transistor regulating a rate of voltage decay of the electrical node from a predetermined high voltage level to a lower voltage level, the regulation of the rate of voltage decay of the electrical node is non-linear. The activation of the ESD discharge circuit determined by the rate of voltage decay of the electrical node.04-30-2009
20110043953ESD PROTECTION CIRCUIT WITH MERGED TRIGGERING MECHANISM - An ESD protection circuit has a merged triggering mechanism. The ESD protection circuit comprises: an ESD detection circuit, for detecting an ESD voltage to generate a control signal; a first type ESD protection device, for outputting a first trigger current; a second type ESD protection device, for receiving a second trigger current; and a trigger circuit, for constituting a conductive path according to the control signal, such that the trigger circuit can receive the first trigger current from the first type ESD protection device and outputs the second trigger current to the second type ESD protection device.02-24-2011
20120033335ESD Protection Scheme for Integrated Circuit Having Multi-Power Domains - The invention provides systems and methods for ESD protection for an integrated circuit (IC) having multi-power domains. The IC comprises a first device in a first power domain having a first power line and a first ground line and a second device in a second power domain having a second power line and a second ground line. A clamp circuit having a first node and a second node is coupled to the first device and the second device to provide cross-domain protection. Alternatively, two clamp circuits are used to couple with the first device and the second device to provide cross-domain ESD protection.02-09-2012
20110043954ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND ELECTRONIC DEVICE USING THE SAME - An electrostatic discharge (ESD) protection structure and an electronic device using the same are provided. The ESD protection structure includes a discharge structure and a conduction structure, wherein the discharge structure and the conduction structure respectively have a pointed end, and the pointed ends thereof are adjacent to each other. The discharge structure and the conduction structure are both disposed on a bottom side of a printed circuit board (PCB) substrate, wherein the conduction structure is connected to a ground line and the discharge structure is connected to a signal line disposed on a top side of the PCB substrate through a via. Therefore, the top side of the substrate is not required to save a layout region for disposing the ESD protection structure, and moreover an original ESD protection effect is still maintained.02-24-2011
20110242714SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device of the invention can reduce a manufacturing cost and achieve size reduction without degrading performances. The semiconductor integrated circuit device includes an internal circuit and at least one input/output circuit. Each input/output circuit is adapted to feed an input signal from outside to the internal circuit and to output an output signal from the internal circuit to the outside. The semiconductor integrated circuit device also includes at least one first power source terminal. Each first power source terminal is associated with each input/output circuit for supplying a drive voltage to the internal circuit. The semiconductor integrated circuit device also includes at lease one second power source terminal. Each second power source terminal is associated with each input/output circuit for supplying a drive voltage to the associated input/output circuit. The semiconductor integrated circuit device also includes at least one common ground terminal. Each common ground terminal is associated with each input/output circuit for supplying a common ground voltage to the internal circuit and the associated input/output circuit. The first power source terminal, second power source terminal and common ground terminal for each input/output circuit are arranged next to each other to define a unit terminal group.10-06-2011
20090034137ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.02-05-2009
20090034136ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.02-05-2009
20110063764APPARATUSES AND METHODS FOR A SCR-BASED CLAMPED ELECTROSTATIC DISCHARGE PROTECTION DEVICE - A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and the gate of the silicon-controlled rectifier, and provides a conductive path for displacement current from a parasitic capacitance when the shunt path is enabled, such as when power is provided to the device, and further allows the SCR to enter a low-resistance state when the shunt path is not enabled, such as when power is not provided to the device. A threshold trigger circuit is operably coupled between the anode and the cathode of the silicon-controlled rectifier and is configured to provide a current path when the anode voltage reaches a predetermined value lower than a breakdown voltage of the silicon-controlled rectifier.03-17-2011
20120243132UNDERVOLTAGE PROTECTION SYSTEM - A system includes undervoltage protection circuitry coupled in parallel with electronic circuitry configured to receive a supply voltage from a power supply. The undervoltage protection circuitry is configured to shunt undervoltage current resulting from an undervoltage transient in the supply voltage away from the electronic circuitry09-27-2012
20120243131ELECTRONIC DEVICE OF PREVENTING POOR HEAT DISSIPATION AND HAVING ESD PROTECTION AND PROTECTION METHOD FOR THE SAME - An electronic device of preventing poor heat dissipation and having ESD protection and a protection method for the electronic device are disclosed, in which the electronic device includes a main body, an outer covering, a processing unit and a protective device. The processing unit and the protective device are disposed in the main body. The protective device is coupled to the processing unit. When the outer covering and the main body are closed tightly, the protective device can send a warning signal to the processing unit.09-27-2012
20090323238Electronic device including a protection circuit for a light-emitting device - An electronic device including a protection circuit for a light-emitting device An electronic device is provided that includes a protection circuit for a light-emitting device. The protection circuit comprises a first node adapted to be coupled to an anode of the light-emitting device and a second node adapted to be coupled to a cathode of the light-emitting device. A voltage detection stage is coupled between the first and second nodes. The voltage detection stage is adapted to detect an overvoltage condition between the first and second nodes. Furthermore, the protection circuit comprises a thyristor coupled with its anode to the first node, its cathode to the second node to the voltage detection stage. When the overvoltage condition is detected in normal operation the thyristor is controlled to open so that the current can flow through the thyristor.12-31-2009
20110128657SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: first and second power-supply terminals; an internal circuit connected between the first and second power-supply terminals; and a protection circuit connected in parallel with the internal circuit between the first and second power-supply terminals, the protection circuit including: a series circuit that includes a resistor and a first capacitor, and is connected in parallel with the internal circuit between the first and second power-supply terminals; a first MOS transistor that is connected in parallel with the series circuit, and is controlled according to a voltage at a connection point between the resistor and the first capacitor; and a switch circuit that is connected in parallel with the resistor, is turned on in a delayed manner after a power-supply voltage is applied between the first and second power-supply terminals, and changes the voltage at the connection point so that the first MOS transistor is turned off.06-02-2011
20100254052STATIC ELECTRICITY COUNTERMEASURE COMPONENT AND METHOD FOR MANUFACTURING THE STATIC ELECTRICITY COUNTERMEASURE COMPONENT - An electrostatic discharge (ESD) protector includes a ceramic body having a cavity provided therein, and two discharge electrodes facing each other across the cavity. The discharge electrodes are made of metal containing more than 80 wt. % of tungsten. The discharge electrodes contain not more than 2.0 atomic % of tungsten bonded to oxygen to a total amount of tungsten contained in the discharge electrodes. This ESD protector does not cause a short-circuiting even upon having high-voltage static electricity applied to the discharge electrodes repetitively, thus having high reliability.10-07-2010
20090086392POWER-RAIL ESD PROTECTION CIRCUIT WITHOUT LOCK-ON FAILURE - An ESD protection circuit including a discharge device, a first detection circuit, and a second detection circuit. The discharge device provides a discharge path between a first power rail and a second power rail when the discharge device is activated. The discharge device stops providing the discharge path when the discharge device is de-activated. The first detection circuit is coupled between the first and the second power rails. The first detection circuit activates the discharge device when an ESD event occurs in the first power rail. The second detection circuit de-activates the discharge device when the ESD event does not occur in the first power rail.04-02-2009
20090086391Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit - An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.04-02-2009
20090086394PROTECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a circuit in which a protected element 04-02-2009
20100226055ELECTROSTATIC DISCHARGE PROTECTION DEVICES - An electrostatic discharge (ESD) protection circuit having first and second transistors and an ESD clamp circuit. The first and second transistors are coupled in series between first and second voltage input pins of a chip. The ESD clamp circuit is coupled between the first and second voltage input pins. The drains of the first and second transistors are coupled to an I/O pin of the chip. The doping regions of the first and second transistors are of distinct doping concentrations. The first transistor comprises four doping regions, and has a source formed by the first and third doping regions, and has a drain formed by the second and the fourth doping regions. The first doping region is within the third doping region. The second doping region is within the fourth doping region. The doping concentration of the fourth doping region is less than that of the third doping concentration.09-09-2010
20090097176ESD PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE - This disclosure concerns an ESD protection including logic gates connected between a first power input and a second power input, a second potential of the second power input lower than the first potential of the first power input, wherein in the logic gates, an output of the logic gate at a front stage are connected to an input of the logic gate at a rear stage, if a protection potential between the first and the second potentials is applied to a node connecting the output to the input when the logic gates respond to an ESD surge, a breakthrough current is carried to the logic gates from the first potential toward the second potential, and if the first and the second potentials are applied to the first power input and the second power input, logic values of the logic gates are kept in a constant state.04-16-2009
20090323235High voltage compliant apparatus for semiconductor fabrication process charging protection - In some embodiments, semiconductor fabrication process charging protection is provided by coupling a first diode protection device to a high voltage node and coupling a second diode protection device to the first diode protection device at a second node. Other embodiments are described and claimed.12-31-2009
20090323234METHOD AND CIRCUIT ARRANGEMENT FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES - An electronic circuit device is provided which comprises an electronic circuit unit, an ESD protection unit connected in parallel to the electronic circuit unit and configured to clamp a supply voltage of the electronic circuit unit, at least one input clamp unit configured to clamp input voltages applied at at least one input terminal of the electronic circuit unit, and at least one ESD clamp provided at the at least one input terminal and configured to protect the electronic circuit unit against electrostatic discharges.12-31-2009
20110242712CHIP WITH ESD PROTECTION FUNCTION - An exemplary chip includes an input/output (I/O) area and a core area is provided. The input/output (I/O) area has a first I/O block operated under a first power domain and a second I/O block operated under a second power domain placed therein, wherein a voltage range of the first power domain is distinct from a voltage range of the second power domain. The core area has at least one circuit therein performing at least one function of the chip, and the core area further has at least one power cut cell placed therein wherein the power cut cell is coupled to the first I/O block and the second I/O block via a plurality of connectors for providing an electrostatic discharge (ESD) path between the first I/O block and the second I/O block.10-06-2011
20110211285LOW PARASITIC CAPACITANCE ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a low parasitic capacitance electrostatic discharge protection circuit. An ESD protection circuit is established with the structure in accordance with the present invention comprising a plurality of discharging paths. The ESD protection circuit is connected to the input/output pad of a radio frequency (RF) core circuit. Such that, the RF core circuit with the ESD protection circuit of the present invention feature much higher ESD robustness. And the parasitic capacitance of the ESD protection is reduced because of the structure of the present invention.09-01-2011
20100002345RADIO FREQUENCY SWITCH ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD)-protected radio frequency (RF) transceiver switching circuit includes two or more switchable RF transmit and receive port circuits, a diode-based ESD-protection circuit, and a voltage-dividing circuit. The voltage-dividing circuit, which can be a switching circuit, minimizes the number of diode devices needed to protect against ESD by dividing the voltage at the antenna node down to a lower voltage across the diode devices.01-07-2010
20090080129Semiconductor chips having improved electrostatic discharge protection circuit arrangement - A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.03-26-2009
20100039740SYSTEM AND METHOD FOR EXCESS VOLTAGE PROTECTION IN A MULTI-DIE PACKAGE - A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.02-18-2010
20100053827PROTECTION CIRCUIT - A protection circuit includes a first primary-type transistor; a secondary-type transistor; a circuit protection element; and a second primary-type transistor. The first primary-type transistor includes a drain terminal connected to a first terminal to which a first voltage is applied. The first primary-type transistor further includes a gate terminal, a source terminal, and a bulk terminal each connected to a second terminal to which a second voltage is applied. The first primary-type transistor responds to an excessive voltage applied to the first terminal as a forward direction response to discharge the excessive voltage to the second terminal, thereby protecting an internal circuit from the excessive voltage.03-04-2010
20110176246PCB STRIP AND MANUFACTURING METHOD FOR ELECTRONIC COMPONENT EMBEDDED PCB - A PCB strip and a method of manufacturing an electronic component embedded printed circuit board are disclosed. The PCB strip in accordance with an embodiment of the present invention includes a unit area, which has a plurality of substrate units provided therein, and a dummy area, which is provided on an outer side of the unit area. Here, an electronic component can be embedded in the substrate unit, and an electrostatic discharge preventing component for protecting the electronic component from an electrostatic discharge can be embedded in the dummy area.07-21-2011
20110176245HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs - Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.07-21-2011
20100134937Over-Voltage Protection Device and Method for Manufacturing thereof - An over-voltage protection device and a method for manufacturing the over-voltage protection device are provided. The over-voltage protection device includes a substrate, a pair of electrode layers, a mask layer, and a sealing layer. The electrode layers are disposed on the substrate, and a gap is formed between the electrode layers. The mask layer is disposed over the gap and a portion of the electrode layers. The sealing layer covers the mask layer and the gap.06-03-2010
20100134938SEMICONDUCTOR DEVICE WITH ESD PROTECTION FUNCTION AND ESD PROTECTION CIRCUIT - A semiconductor device with an ESD protection function has an SOI substrate, first to fourth diffusion layers, and a gate. The SOI substrate has a semiconductor layer on an insulation layer. The first diffusion layer is of a first conductivity type and is formed on the semiconductor layer. The second diffusion layer is of the first conductivity type and is formed on the semiconductor layer. The third diffusion layer is of a second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first and second diffusion layers. The fourth diffusion layer is of the second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first diffusion layer and electrically connected to the second diffusion layer. The gate is formed over the third diffusion layer.06-03-2010
20110075306LOCAL INTEGRATION OF NON-LINEAR SHEET I INTEGRATED CIRCUIT PACKAGES FOR ESD/EOS PROTECTION - A packaged semiconductor device (03-31-2011
20120120533CONTROLLERS, POWER SUPPLIES AND CONTROL METHODS - Power supplies together with related over voltage protection methods and apparatuses. A power supply has a transformer including a primary winding and an auxiliary winding. A power switch is coupled to the primary winding and a sensing resistor coupled between the power switch and a grounding line. A multi-function terminal of a controller is coupled to the sensing resistor. A diode and a first resistor is coupled between the auxiliary winding and the multi-function terminal.05-17-2012
20120120531LOW LEAKAGE ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.05-17-2012
20110069419ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - An electrostatic discharge protection circuit includes an input terminal, a first diode, a second diode, a third diode, a fourth diode, a plurality of voltage stabilizer circuits, and a power terminal. The input terminal and the cathode of the second diode connect to the anode of the first diode; the voltage stabilizer circuits connect in parallel between the cathode of the first diode and the anode of the second diode. The power terminal connects to the anode of the third diode, the cathode of the third diode connects to the cathode of the first diode. The cathode of the fourth diode connects to ground, the anode of the fourth diode connects to the anode of the second diode.03-24-2011
20110043955ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT, CONTROL METHOD THEREFOR, AND SWITCHING REGULATOR USING SAME - A protection circuit to protect an element against static electricity includes a clamp element connected in parallel to the protected element and a static electricity detection circuit connected to the protected element, to detect static electricity applied to the protected element. The static electricity detection circuit clamps a voltage applied to the protected element by turning on the clamp element when the detected static electricity exceeds a predetermined value and, in response to an externally input enable signal, turns off the clamp element, thereby stopping clamping the voltage applied to the protected element.02-24-2011
20130163130ESD PROTECTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - An ESD protection device includes an alumina multilayer substrate, a hollow portion, a discharge electrode pair, discharge-assisting electrodes, and a vitreous substance. The hollow portion is disposed inside of the alumina multilayer substrate. The electrodes of the discharge electrode pair are disposed opposite to each other at an interface between the hollow portion and the alumina multilayer substrate. The discharge-assisting electrodes are disposed dispersedly between the opposite electrodes of the discharge electrode pair. The vitreous substance covers the discharge-assisting electrodes in the inside of the hollow portion. A trial discharge is executed so as to induce creepage discharge between the electrodes of the discharge electrode pair in advance.06-27-2013
20080253046UN-ASSISTED, LOW-TRIGGER AND HIGH-HOLDING VOLTAGE SCR - A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.10-16-2008
20110255201SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In one embodiment, a semiconductor integrated circuit includes a power source circuit connected to a terminal of a first high potential side power source and outputs a voltage of a second high potential side power source, and an output transistor outputting an output signal to an output terminal. A cathode of a first diode is connected to the terminal of the first high potential side power source and an anode thereof is connected to the output terminal. A current source and a capacitor are connected between a terminal of the second high potential side power source and the terminal of a low potential side power source. A signal from a connection node of the current source and the capacitor and a control signal are inputted to a logic circuit, and the logic circuit outputs a signal obtained by a logic operation to the control terminal of the output transistor.10-20-2011
20100296213ESD Protection for FinFETs - An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.11-25-2010
20100296210TRANSIENT SUPPRESSION DEVICE AND METHOD THEREFOR - In one embodiment, a semiconductor device to provide protection for electronic circuits, the semiconductor device typically includes a vertical MOS transistor, a reference circuit, and an amplifier. The amplifier amplifies the reference voltage to enable the vertical MOS transistor responsively to a transient event.11-25-2010
20100296212ELECTROSTATIC DISCHARGE CLAMP CIRCUIT - An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.11-25-2010
20100296209ESD PROTECTION - The present invention relates to an electronic device including electronic circuitry, wherein the circuitry includes a first switching transistor (MN11-25-2010
20100259858POWER SWITCH EMBEDDED IN ESD PAD - A driver circuit has a pad that may be utilized for programming a core circuit or receiving a data signal. A trace high circuit receives a pad voltage signal from the pad, and outputs a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage. A level shifter and a first inverter output a pull high control signal generated by inverting and level shifting a programming control signal. An ESD blocking circuit selectively blocks the pad voltage signal from reaching the core circuit depending on the pad voltage signal and the level-shifted programming control signal. A pull high circuit receives the pull high control signal and the power supply voltage, and outputs the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.10-14-2010
20110149449HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT WITH LOW LEAKAGE CURRENT FABRICATED BY LOW-VOLTAGE CMOS PROCESS - An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.06-23-2011
20100097735METHOD OF PROTECTING AND DISSIPATING ELECTROSTATIC DISCHARGES IN AN INTEGRATED CIRCUIT - A device for protecting at least one integrated circuit against an electrostatic discharge, comprising at least: 04-22-2010
20120200962ESD CLAMP FOR MULTI-BONDED PINS - A circuit comprises a plurality of segments and a clamp circuit. Each of the plurality of segments comprises a bond pad coupled to a multi-bonded pin via a respective bond wire and a conductor coupling the bond pad to a respective internal connection. The bond pad from each of the plurality of segments is coupled to the same multi-bonded pin. The clamp circuit comprises a plurality of input pins and a plurality of clamp transistors. Each input pin is coupled to the bond pad of a respective one of the plurality of segments via the respective conductor. Each clamp transistor is coupled to a respective one of the input pins, wherein each of the plurality of clamp transistors is configured to prevent a voltage on the respective conductor from exceeding a respective voltage limit.08-09-2012
20120200964DIODE CHAIN WITH GUARD-BAND - The present invention provides an ESD protection device having at least one diode in a well of first conductivity type formed in a substrate of second conductivity type. The circuit further includes a guard-band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between the diode cathode, the substrate and the guard-band.08-09-2012
20110149452SURFACE MOUNT SPARK GAP - A spark gap device includes an optional insulating layer formed on a substrate, a metal layer formed on a surface of the insulating layer, a solder resist layer formed on a surface of the metal layer, and first and second contacts. The metal layer includes a central portion and a peripheral portion separated by an air gap that surrounds the central portion of the metal layer and exposes the insulating layer. The solder resist layer includes a central portion disposed on the central portion of the metal layer having a first opening exposing a central region of the central portion of the metal layer, and a peripheral portion disposed on the peripheral portion of the metal layer having a second opening exposing a peripheral region of the peripheral portion of the metal layer. The first contact is formed in the first opening and the second contact is formed in the second opening.06-23-2011
20090310266METHOD AND CIRCUIT FOR eFUSE PROTECTION - An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.12-17-2009
20080247103ELECTRO-STATIC DISCHARGE PROTECTION DEVICE HAVING A LOW TRIGGER VOLTAGE AND REDUCED SIZE - The present invention describes an electro-static discharge protection device that has a low operation voltage and a reduced size. The electro-static discharge protection device includes a power clamp unit that provides a discharge path between a pair of power lines. The power clamp unit includes a trigger unit generating a trigger voltage corresponding to electrostaticity accumulated in a first power line. The power clamp device is switched by the trigger voltage of the trigger unit to form a discharge path to discharge the electrostaticity in the first power line to a second power line. The power clamp device may include an NMOS transistor connected to a gate and a bulk. The power clamp device may also include a resistor for dropping the trigger voltage to apply it to the bulk.10-09-2008
20080247105Voltage Surge and Overvoltage Protection - Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. A series inductance separates the first and second voltage clamping devices. Also, a switching element is employed to selectively establish a direct coupling of the input power to the electrical load, where a circuit is employed to control the operation of the switching element.10-09-2008
20110255200ELECTROSTATIC DISCHARGE CIRCUIT FOR INTEGRATED CIRCUIT WITH MULTIPLE POWER DOMAIN - An ESD protection circuit with multiple domains, which comprises: an ESD protection device, coupled between a first power supplying line and a first ground line; a first internal circuit, having a first terminal coupled to the first power supplying line; a first switch, coupled between a second terminal of the first internal circuit and a second ground line; and a first ESD detection circuit, coupled to the first switch, for detecting an ESD signal, and controls the first switch to be non-conductive when the ESD signal occurs.10-20-2011
20120200965ELECTRONIC COMPONENT DEVICE AND PACKAGE SUBSTRATE - In an electronic component device, an ESD protection element including a cavity portion and a pair of opposed discharge electrodes is disposed inside a package substrate. A composite portion made of a composite material including a metal material and an insulating material is disposed on a bottom of the cavity portion. The package substrate including the ESD protection element disposed therein reduces the size of the electronic component device and reliably prevents damage to and malfunctioning of the electronic component device.08-09-2012
20120200963SYSTEM AND METHOD FOR PROTECTING A COMPUTING DEVICE USING VSD MATERIAL, AND METHOD FOR DESIGNING SAME - Embodiments described herein provide for programmatic design or simulation of substrates carrying electrical elements to integrate voltage switchable dielectric (“VSD”) material as a protective feature. In particular, VSD material may be incorporated into the design of a substrate device for purpose of providing protection against transient electrical conditions, such as electrostatic discharge (ESD).08-09-2012
20080285190Electrostatic protection circuit - Electrostatic protection is performed without affecting the transfer of a normal input signal. An electrostatic protection circuit includes an input terminal, aground terminal, an Nch transistor whose gate and source are coupled to the input terminal and the ground terminal, respectively, and an electrostatic protection element connected to a drain and coupled to the gate of the Nch transistor. A discharge current flows into the ground terminal through the electrostatic protection element when an electrostatic discharge is applied to the input terminal. The discharge current flows through a drain-source parasitic resistance in the Nch transistor because the Nch transistor is turned on caused by an applied voltage of the electrostatic discharge to the gate. This leads to an increase in an electric potential at Point B (channel potential) of the Nch transistor.11-20-2008
20110176243STACKED ESD PROTECTION - A stacked electrostatic discharge (ESD) protection clamp (07-21-2011
20090021872ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.01-22-2009
20090021873ELECTRO STATIC DISCHARGE PROTECTION IN INTEGRATED CIRCUITS - It is described an Electro Static Discharge protection, wherein diodes are arranged on two electric paths both extending in between two conductors which are connected with input terminals of an ESD sensitive electronic component. Each path comprises two diodes arranged in series and with opposite polarity with respect to each other. At least one of the totally four diodes comprises a different reverse breakdown voltage. The protection circuit is formed integrally with the ESD sensitive electronic component. Due to the serial connection of two diodes in each path the corresponding ESD protection circuit comprises an extremely low capacitance.01-22-2009
20080278874ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE AND A CIRCUIT USING THE SAME - An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.11-13-2008
20080198517ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT HAVING A REDUCED SIZE AND ENHANCED DISCHARGE - The present invention describes an electrostatic discharge protection circuit that protects an internal circuit of a semiconductor device from electrostatic discharge. The electrostatic discharge protection circuit includes a first electrostatic protection unit that transfers static electricity as a driving signal and also discharges the static electricity to a first discharge line when the static electricity is generated in a pad. It also includes a second electrostatic protection unit that discharges the static electricity generated in the pad to a second discharge line in response to the driving signal transferred from the first electrostatic protection unit. Since the first electrostatic protection unit performs an electrostatic discharge operation and at the same time aids the driving of the second electrostatic protection unit, electrostatic discharge performance can be enhanced while a layout area of the electrostatic discharge protection circuit can be reduced.08-21-2008
20080198519ELECTROSTATIC DISCHARGE PROTECTION ELEMENT HAVING AN IMPROVED AREA EFFICIENCY - An electrostatic discharge protection element is disclosed for protecting an internal circuit from electrostatic current. The electrostatic discharge protection element forms an embedded LVTSCR by adding a prescribed impurity region within an N-well region having a P-type diode formed therein. A P-well region having a GGNMOS transistor is also formed in the electrostatic discharge protection element. The embedded LVTSCR improves area efficiency, reduces a resistance, and lowers an operational voltage by reducing the distance between the P-type diode and the LVTSCR to allow high-speed operatation.08-21-2008
20080253045Integrated circuit device and electronic instrument - An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.10-16-2008
20080253042E-FUSE AND METHOD - An e-fuse circuit and a method of programming the e-fuse circuit method. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the circuit place the storage nodes in predetermined and opposite states.10-16-2008
20130170081TRIGGER CIRCUIT AND METHOD OF USING SAME - A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state.07-04-2013
20080247104ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT HAVING A REDUCED SIZE AND LOWER OPERATING VOLTAGE - The present invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit of the present invention includes a transfer unit that transfers electrostaticity from at least one of a plurality of input/output pads to a boost bus line, a trigger unit that responds to the electrostaticity transferred via the boost bus line to detect a trigger voltage and apply it to a trigger bus line, and a plurality of clamp units that are connected between the input/output pads and an internal circuit. The clamp units are triggered by the trigger voltage of the trigger unit to discharge electrostaticity of the input/output pads to a first or second power supply voltage line, thereby safely protecting the internal circuit from electrostatic damage and lowering the operating voltage of the clamp unit with minimum costs without increasing an area of the electrostatic discharge protective circuit within a semiconductor integrated circuit.10-09-2008
20080204952ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR HIGH VOLTAGE INPUT PAD - An electrostatic discharge protection circuit includes a high-voltage supply terminal (VDD), an input/output (IO) pad, and a first shunting transistor that can discharge electrostatic charges between the IO pad and VDD in response to a control signal. A trigger circuit can output the control signal in response to an electrostatic voltage between the IO pad and VDD. The electrostatic discharge protection circuit also includes a first group of serially connected diodes, which includes a first end connected to the IO pad and a second end configured to supply power to the trigger circuit.08-28-2008
20110110005FAULT PROTECTOR FOR OPTO-ELECTRONIC DEVICES AND ASSOCIATED METHODS - A fault protector for an opto-electronic device includes a MOSFET having an integral body-diode. A capacitor is connected between a drain and a gate of the MOSFET, and a resistor is connected between the gate and a source of the MOSFET. The drain of the MOSFET is connectable to a first terminal of an opto-electronic device, and the source of the MOSFET is connectable to a second terminal of the opto-electronic device. The device overcomes problems of previously known techniques by preventing a reverse-bias voltage from exceeding an absolute maximum specified by a manufacturer, and also prevents ESD or other power-related faults from exceeding the maximum forward-bias voltage of the laser diode, while not adding significant resistance or capacitance to the laser diode, thereby not complicating the task of driving the laser diode.05-12-2011
20100328827ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITS, INTEGRATED CIRCUITS, SYSTEMS, AND OPERATING METHODS THEREOF - An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current minor is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.12-30-2010
20100309595ESD PROTECTION DEVICE - An ESD protection device has a structure that allows ESD characteristics to be easily adjusted and stabilized. The ESD protection device includes a ceramic multilayer substrate, at least a pair of discharge electrodes located in the ceramic multilayer substrate and facing each other with a space disposed therebetween, and external electrodes located on a surface of the ceramic multilayer substrate and connected to the discharge electrodes. The ESD protection device includes a supporting electrode disposed in a region that connects the pair of discharge electrodes. The supporting electrode is made of a conductive material coated with an inorganic material having no conductivity.12-09-2010
20110096447INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes: a pad to which a signal is input; an analog circuit performing analog processing of the signal input via the pad; and a capacitor disposed between a signal input node of the analog circuit and the pad, wherein the pad and one end of the capacitor are connected to each other with a pad wiring formed of an uppermost metal layer.04-28-2011
20110096446ELECTROSTATIC DISCHARGE CLAMP WITH CONTROLLED HYSTERESIS INCLUDING SELECTABLE TURN ON AND TURN OFF THRESHOLD VOLTAGES - A electrostatic discharge (ESD) clamp for coupling between first and second nodes for providing ESD protection including a clamp circuit and first and second voltage threshold circuits. The clamp circuit limits operating voltage between the first and second nodes to a maximum level when activated. The first and second voltage threshold circuits each have a selectable threshold voltage, such as by coupling one or more voltage threshold devices in series. The first voltage threshold circuit triggers to turn on the clamp circuit when the operating voltage increases above a first voltage threshold. The second voltage threshold circuit triggers when the clamp circuit is turned on and is turned off to turn off the clamp circuit when the operating voltage decreases to the second threshold voltage. The second threshold voltage may be selected at any level above the nominal operating voltage to prevent the clamp from latching.04-28-2011
20110080678ESD PROTECTION CIRCUIT FOR A SWITCHING POWER CONVERTER - An ESD protection circuit for a switching power converter which includes a high-side switching element connected between a supply voltage and the switching node, and a low-side switching element connected between the switching node and a common node. A current conduction path couples an ESD event that occurs on the switching node to an ESD sense node, and an ESD sensing circuit coupled to the sense node generates a trigger signal when an ESD event is sensed. A first logic gate keeps the high-side switching element off when the trigger signal indicates the sensing of an ESD event, and a second logic gate causes the low-side switching element to turn on when an ESD event is sensed such that the low-side switching element provides a conductive discharge path between the switching node and common node.04-07-2011
20080218920METHOD AND APARATUS FOR IMPROVED ELECTROSTATIC DISCHARGE PROTECTION - An apparatus having an inter-domain electrostatic discharge (ESD) protection circuit for protection of an integrated circuit (IC) with multiple power domains. The protection circuit in response to an ESD event provides an ESD protection between different power domains. Specifically, the protection circuit comprises at least one clamp coupled to one power domain, which conducts current during an ESD event to provide extra current in the interface line between the two different power domains. This extra current also in turn increases the voltage over the impedance element on the interface line, thus improving the design margins for the ESD protection and providing a better ESD protection capability for IC products.09-11-2008
20080218918Battery Power Management In Over-Discharge Situation - A method of operating battery power management unit (PMU) in over-discharge situation is disclosed. Furthermore, a power management unit (PMU) and a device comprising a power management unit (PMU) are disclosed. The power management unit (PMU) is part of a system, comprising a battery and a safety circuit connected to the battery. The state of the safety circuit of the battery is determined and the on/off control of the device is made inactive while the safety circuit remains active. Thereby avoiding an application run on the device to go into an active state, i.e. to be turned on, at a moment when the battery has not returned to its normal operation mode.09-11-2008
20100214704ESD PROTECTION USING ISOLATED DIODES - An electrostatic discharge (ESD) protection circuit (08-26-2010
20110176244ESD PROTECTION DEVICE AND METHOD - An electrostatic discharge (ESD) protection clamp (07-21-2011
20100214706VOLTAGE SURGE PROTECTION CIRCUIT - A protection circuit (08-26-2010
20100067154Enhancing Bandwidth of ESD Network Using Transformers - An integrated circuit device includes a first pad and a second pad; electrostatic discharging (ESD) devices coupling the first pad and the second pad to a discharging path; a transformer including a first end, a second end, a third end and a fourth end, wherein the first end and the second end are coupled to the first pad and the second pad, respectively; and a transceiver circuit coupled to the first end and the second end of the transformer.03-18-2010
20100067155Method and apparatus for enhancing the triggering of an electrostatic discharge protection device - An electrostatic discharge (ESD) protection circuit for protecting a semiconductor device that includes a metal oxide semiconductor field effect transistor (MOSFET) providing a first path from a source of an electrostatic charge to ground. The ESD protection circuit also includes an NPN bipolar transistor providing a second path from the source of the electrostatic charge to ground. The ESD protection circuit also includes a regulation component coupled in series to a base of the NPN bipolar transistor to provide an amount of resistance when the semiconductor device is off and to provide a reduced amount of resistance when the semiconductor device is on.03-18-2010
20090316315LED CHIP PACKAGE STRUCTURE WITH AN EMBEDDED ESD FUNCTION AND METHOD FOR MANUFACTURING THE SAME - An LED chip package structure includes a conductive unit, a first package unit, an ESD unit, a second package unit, a light-emitting unit and a second package unit. The conductive unit has two conductive pins adjacent to each other which form a concave space between each other. The first package unit encloses one part of each conductive pin in order to form a receiving space communicating with the concave space and to expose an end side of each conductive pin. The ESD unit is received in the concave space and electrically connected between the two conductive pins. The second package unit is received in the concave space in order to cover the ESD unit. The light-emitting unit is received in the receiving space and electrically connected between the two conductive pins. The third package unit is received in the receiving space in order to cover the light-emitting unit.12-24-2009
20090316314DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE - A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.12-24-2009
20100165525Low Profile Discrete Electronic Components and Applications of Same - Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.07-01-2010
20090174975TWO-WAY ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit electrically connected to a first conductive line and a second conductive line is provided. The ESD protection circuit has a first ESD protection circuit unit, wherein the first ESD circuit unit includes a first coupled capacitor and a first active device. The first coupled capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conductive line. The first active device includes a first gate, a first source and a first drain, wherein the first gate is electrically connected to the second electrode. In addition, the first source and the first electrode are electrically connected to the first conductive line, and the first drain is electrically connected to the second conductive line. Therefore, the conduction efficiency of the ESD protection circuit is improved.07-09-2009
20090174974Embedded type multifunctional integrated structure for integrating protection components and method for manufacturing the same - An embedded type multifunctional integrated structure for integrating protection components and a method for manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrate more than two passive components on a component structure that is adhered onto a substrate and is applied to a USB terminal in order to protect an electronic device that uses the USB. Hence, the present invention has an OCP function, an OVP function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrates two or more passive components in order to increase functionality. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.07-09-2009
20100027173ELECTROSTATIC DISCHARGE DEVICE WITH ADJUSTABLE TRIGGER VOLTAGE - An improved ESD protection circuit having an ESD device and a triggering device to provide a continuously adjustable trigger voltage. This can be accomplished by various techniques such as placing a selected number of triggering elements in series, modifying the gate control circuitry and varying the size of the triggering elements.02-04-2010
20100027175PROTECTION CIRCUIT WITH OVERDRIVE TECHNIQUE - The present invention relates to a protection circuit and method of protecting a semiconductor circuit against a temporary excessive voltage on a supply line, wherein a first trigger signal is generated in response to a detection of an excessive voltage on the supply line and a clamp element (M02-04-2010
20100027172INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE - A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.02-04-2010
20100027171Method and Apparatus for Forming I/O Clusters in Integrated Circuits - A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.02-04-2010
20100027174CIRCUIT FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES IN CMOS TECHNOLOGY - The integrated circuit may include at least one electronic protection circuit for protecting against at least one electrostatic discharge and being able to discharge the overvoltage current generated by the electrostatic discharge. The electronic protection circuit includes a controlled short-circuiting switch embodied in CMOS technology including a CMOS technology TRIAC or a CMOS technology thyristor arranged in anti-parallel with a CMOS technology diode, and a triggering circuit for controlling the short-circuiting switch.02-04-2010
20100020455PASSIVE NETWORK FOR ELECTROSTATIC PROTECTION OF INTEGRATED CIRCUITS - Embodiments of the invention provide an electrostatic discharge protection device or network for an integrated circuit. The network includes a first circuit branch and a second circuit branch connected in a parallel configuration. The first branch has a first inductance, a first resistance, and includes a first capacitive component. The second branch has a second inductance, a second resistance, and includes a second capacitive component. A first end of the first circuit branch and a first end of the second circuit branch are coupled to a first node, and a second end of the first circuit branch and a second end of the second circuit branch are coupled to zero-voltage reference level. The network is capable of providing a low impedance path away from a terminal of the integrated circuit during an electrostatic discharge event.01-28-2010
20110216455Semiconductor package and semiconductor device - A semiconductor device, includes a chip, a first external terminal, a second external terminal, and a partial antenna wiring that is coupled to the first external terminal, and that constitutes a matching circuit, wherein the chip includes first and second electrode pads that are coupled to the partial antenna wiring, a third electrode pad that is different from each of the first and second electrode pads, and that is coupled to the second external terminal, and an electrostatic discharge (ESD) protection circuit that is coupled to the third electrode pad.09-08-2011
20110216454ELECTROSTATIC DISCHARGE PROTECTORS HAVING INCREASED RC DELAYS - An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.09-08-2011
20090147419POWER INTERFACE CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - An electronic device includes an integrated circuit, a power interface, and an interface circuit connected between the integrated circuit and the power interface for protecting the integrated circuit from being damaged by electrostatic discharge. The interface circuit includes a current limit unit connected between the power interface and the integrated circuit for limiting an electrostatic discharge current and an electrostatic protection unit connected to a common node of the power interface and the current limit unit for clamping a voltage of the common node to a predetermined value. A related integrated circuit is also provided.06-11-2009
20100246074ESD Protection scheme for designs with positive, negative, and ground rails - Apparatuses and systems for dissipating ESD events are provided. In an embodiment, an integrated circuit (IC) device, includes a ground rail, a positive supply rail, a negative supply rail, a circuit block, a plurality of contact pads, and a coupling system. Each of the ground rail, positive supply rail, negative supply rail, and the circuit block are coupled to a respective contact pad of the plurality of contact pads. The contact pad coupled to the circuit block is configured to swing from a voltage of the negative rail to a voltage of the positive rail. The coupling system couples each contact pad of the plurality of contact pads to all other contact pads of the plurality of contact pads, whereby an electrostatic discharge (ESD) event between two contacts pads of the plurality of contact pads can be dissipated.09-30-2010
20080266730Spark Gaps for ESD Protection - An electronic circuit includes a first signal line that extends along a first direction, a spark gap device that has a first conductive trace and a second conductive trace, the first conductive trace being connected to the first signal line. The first and second conductive traces are spaced apart to define a spark gap, the first and second conductive traces being aligned along the first direction to direct an electrostatic discharge along the first direction from the first signal line through the spark gap to a ground reference electrically coupled to the second conductive trace. A second signal line is connected to the first conductive trace or to the first signal line in a vicinity of the first conductive trace, the second signal line extending along a second direction at an angle relative to the first direction.10-30-2008
20110051300Method for Providing Wideband Electrostatic Discharge Protection and Circuits Obtained Therewith - An distributed electronic circuit (03-03-2011
20110051299SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: an internal circuit formed on a semiconductor chip, power being supplied thereto via a first power supply wire and a second power supply wire; input and output pads that exchange an input signal or an output signal with the internal circuit; input and output cells including first electrostatic protection elements that protect the internal circuit from electrostatic discharge between the input and output pads and the first or second power supply wire; and second power supply protection elements provided adjacent to the input and output cells and including diode strings connected between the first power supply wire and the second power supply wire.03-03-2011
20110051298ESD IMPROVEMENT WITH DYNAMIC SUBSTRATE RESISTANCE - In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.03-03-2011
20090141414Protection circuit for electric power of a car - A protection circuit for power of a car is located between an output terminal of a car power and a car's electronic device input terminal. The protection circuit includes a transient voltage suppressing diode, a diode, and a filtering circuit. The two terminals of the transient voltage suppressing diode are connected with the output terminal of car power. The diode is connected with the transient voltage suppressing diode and the output terminal of car power. The filtering circuit is connected with the diode and the car's electronic device input terminal. Thereby, the transient voltage suppressing diode of the present invention clamps the ripple at a safe voltage to assure the life of the car's electronic device. Furthermore, the transient voltage suppressing diode and the filtering circuit can prevent the car's electronic device from being interfered and damaged due to the ESD. The reliability of the electronic device is enhanced.06-04-2009
20110019319SEMICONDUCTOR DEVICE - A semiconductor device has: a power supply line; a ground line; a signal line for transmitting a signal; a signal pad connected to the signal line; a protection element connected between the signal line and the ground line; and a trigger circuit configured to supply a trigger current to the protection element. The trigger circuit has: a PMOS transistor whose gate and backgate are connected to the power supply line and whose source is connected to the protection element; and an amplifier circuit part configured to amplify a first current flowing through the PMOS transistor to generate a second current. The trigger current includes the second current.01-27-2011
20090284884VOLTAGE PULL-DOWN CIRCUIT - A voltage pull-down circuit electrically connected between two scan lines and a bus line includes a transistor and an electrostatic discharge protection device. Each transistor comprises a source, a drain, and a gate electrically connected to one of the scan lines. Each gate is connected to another scan line, the source, and the drain through the electrostatic discharge protection device.11-19-2009
20090015975Overvoltage Protection Apparatus and an Associated Protection Circuit - The invention relates to an overvoltage protection apparatus having a semiconductor substrate, a first doping region in order to provide a protection diode, and a second doping region in order to provide a protection resistance, with the second doping region being immediately adjacent to the first doping region.01-15-2009
20120307406SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed herein is a semiconductor integrated circuit including in a same semiconductor substrate: first and second power supply lines; a protected circuit being connected between the first and second power supply lines and provided with a supply voltage; a detecting circuit detecting a surge generated in the first power supply line; an inverter circuit having one or more inverters connected in series to each other; and a protection transistor being connected between the first and second power supply lines and controlled by output of the detecting circuit to discharge the surge to the second power supply line. In the inverter circuit, an inverter whose output is connected to a control node of the protection transistor is connected between the first power supply line and a third power supply line that is different from the first and second power supply lines.12-06-2012
20120307407SEMICONDUCTOR DEVICE - A semiconductor device includes a first node receiving an external voltage, a second node receiving a grounding voltage, a protection circuit, and a device to be protected coupled in parallel between the first and second nodes, in which the protection circuit includes a lateral IGBT having an emitter coupled to the second node and an avalanche diode having an anode coupled to the collector of the lateral IGBT and a cathode coupled to the first node, and a clamp driving circuit coupled between the first and second nodes, and coupled to the gate of the lateral IGBT.12-06-2012
20120307405INTEGRATED CIRCUIT HAVING ELECTROSTATIC DISCHARGE PROTECTION - Apparatus are provided for integrated circuits that include circuitry to provide protection from electrostatic discharge. An exemplary integrated circuit includes an input/output terminal, a first transistor coupled to the input/output terminal, a second transistor coupled to a control terminal of the first transistor and a reference voltage node, and detection circuitry coupled to a control terminal of the second transistor. The detection circuitry is configured to turn on the second transistor in response to a discharge event to protect the first transistor.12-06-2012
20120307408SEMICONDUCTOR DEVICE WITH A PLURALITY OF POWER SUPPLY SYSTEMS - A protection circuit includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system, controls a first switch. The first switch is provided between the signal line and the first ground. The control circuit includes a capacitance element, a resistance element in series with the capacitance element, and an inverter, an output of the inverter being connected between a gate of the first switch, an input of the inverter being connected to a connecting point between the capacitance element and the resistance element.12-06-2012
20080266729Radio Frequency Interface Circuit for a Radio Frequency Identification Tag - A radio frequency interface circuit (10-30-2008
20100002344HIGH VOLTAGE TOLERANCE CIRCUIT - A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.01-07-2010
20080316663Esd Protection for Pass-Transistors in a Voltage Regulator - Present invention relates to an electrostatic discharge protection circuit for a transistor circuit having electrostatic discharge protection circuits coupled to an input and to an output terminal. The protection circuits comprise delay means having a predetermined delay time and switchable connecting means connected between said input terminal and a control terminal of said transistor circuit. The delay means are configured for activating said switchable connecting means for said predetermined delay time in response to an electrostatic discharge at said input terminal.12-25-2008
20110149451ELECTROSTATIC PROTECTION METHOD AND DEVICE FOR PRODUCTION LINE - The electrostatic protection device for using in the production lines is provided with at least two circuits on production line. The production line is connected to a grounding end via a first circuit and configured to release static electricity. The production line is connected to the grounding end via a second circuit. Once a production line gives a feedback to indicate that static electricity cannot be released from the production line through the first circuit, and the second circuit will instantly give a failure warning. The feedback mechanism for electrostatic protection works without performing any automated detection operation on the production line. Hence, electrostatic protection provided by the electrostatic protection method and device is advantageously characterized by giving an alert to warn of static electricity release failure efficiently and instantly.06-23-2011
20120099230ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge protection circuit includes a diode chain coupled between a power supply voltage end and a control node, a control voltage generator configured to generate a control voltage in response to a first current flowing through the diode chain, and a discharger configured to discharge a second current from the power supply voltage end to a ground voltage end in response to the control voltage, wherein the diode chain includes a plurality of P-well regions formed in an N-well region, diodes formed in the respective P-well regions, and a resistor coupled between the diodes.04-26-2012
20120099231DISCHARGE GAP FILLING COMPOSITION AND ELECTROSTATIC DISCHARGE PROTECTOR - A discharge gap filling composition which includes metal powders (A) and a binder component (B), wherein surfaces of primary particles of the metal powders (A) are coated with a film composed of a metal oxide, and the primary particles of the metal powders (A) have a flake form. An electrostatic discharge protector is obtained using the composition.04-26-2012
20110304940Protection Circuit - A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal.12-15-2011
20100321840Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) - A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal. The gate may be shorted to the drain for configuring the BS-MOSFET transistor into a two terminal device with a gate-to-source voltage equal to a drain-to-source voltage. The drain/collector/cathode terminal disposed on top of the trench gate turns on the BS-MOSFET upon application of a threshold voltage of the BS-MOSFET thus triggering the bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of the BS-MOSFET.12-23-2010
20100328826Field Effect Resistor for ESD Protection - An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (12-30-2010
20090185316ESD/EOS Performance by Introduction of Defects - The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.07-23-2009
20090154040MEMORY CARD WITH ELECTROSTATIC DISCHARGE PROTECTION AND MANUFACTURING METHOD THEREOF - A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.06-18-2009
20120039004Composite Electronic Circuit Assembly - A composite electronic circuit assembly comprises two MOS or CMOS circuit dice (02-16-2012
20090201615METHOD AND APPARATUS FOR ESD PROTECTION - A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.08-13-2009
20130010394MULTI-VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION - An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt01-10-2013
20090310267METHOD, DESIGN STRUCTURES, AND SYSTEMS FOR CURRENT MODE LOGIC (CML) DIFFERENTIAL DRIVER ESD PROTECTION CIRCUITRY - A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.12-17-2009
20090040671Power clamp for on-chip ESD protection - According to an exemplary embodiment, a power clamp for providing on-chip ESD and mistrigger event protection includes a clamping transistor coupled between a power bus and a ground. The power clamp further includes a number of inverter stages coupled in series, where a first inverter stage has an output coupled to the clamping transistor. The power clamp further includes a turn-off resistor coupled between the power bus and an input of the first inverter. The turn-off resistor is configured to cause the clamping transistor to automatically turn off after having been turned on. The turn-off resistor determines a period of time that the clamping transistor is turned on after an ESD or mistrigger event has occurred on the power bus. The power clamp further includes a timing circuit coupled to the inverter stages. The power clamp further includes a feedback transistor coupled between a second inverter stage and the power bus.02-12-2009
20100165524INTEGRATED CIRCUIT - An integrated circuit includes an input/output pad for signal exchange with an external circuit, an electrostatic discharge (ESD) protection unit coupled to the input/output pad and configured to form an ESD path between a first voltage line and a second voltage line, a first drive transistor coupled between the first voltage line and the input/output pad, a first driving control unit coupled to a gate of the first drive transistor and configured to control the first drive transistor, a first dummy drive transistor coupled between the first voltage line and the input/output pad, and a first auxiliary driving control unit configured to supply the first voltage to a gate of the first dummy drive transistor in a normal operation mode, and float the gate of the first dummy drive transistor in a non-operation mode in which no power is supplied.07-01-2010
20090067106STATIC ELECTRICITY DISCHARGE CIRCUIT - A static electricity discharge circuit applied to a highly integrated semiconductor circuit includes a discharge unit connected with the input/output pad by a node and providing, in parallel to the node, a first discharge path connected with a power voltage line and a second discharge path connected with a ground voltage line, an electrostatic detection unit including a diode chain connected to the node and detecting a detection voltage corresponding to static electricity inputted to the node, and a clamp unit switching the discharge path between the power voltage line and the ground voltage line by the detection voltage of the electrostatic detection unit.03-12-2009
20090015974ESD DETECTION CIRCUIT - An ESD detection circuit which includes: a triggering circuit for generating an ESD trigger signal when the ESD detection circuit is in ESD mode; a bias circuit for providing at least a first bias voltage and a second bias voltage for controlling the operation of the triggering circuit; a trigger controlling circuit for decreasing a voltage difference between the first bias voltage and the second bias voltage when the ESD detection circuit is in the ESD mode, and for controlling a duration of the ESD trigger signal that is generated by the triggering circuit; and an activating control circuit for activating the trigger controlling circuit and the triggering circuit to enter the ESD mode according to a voltage level at a first node.01-15-2009
20110075305TWO-LEVEL LIGHTNING PROTECTION CIRCUIT - A lightning protection circuit includes a transistor array, a transistor array gate drive, and a second stage protection element which forces a voltage at the gate node of the transistor array to be higher than the voltage at the source node of the transistor array when a threshold is exceeded.03-31-2011
20090201616CIRCUIT HAVING LOW OPERATING VOLTAGE FOR PROTECTING SEMICONDUCTOR DEVICE FROM ELECTROSTATIC DISCHARGE - A circuit for protecting a semiconductor device from electrostatic discharge by protecting an internal circuit from electrostatic current flowing into an input/output pad includes a first discharge unit that discharges the electrostatic current to a first power supply line or a second power supply line. A second discharge unit protects the internal circuit from electrostaticity flowing from the input/output pad or the second power supply line. A power clamp unit discharges the electrostatic current, which is discharged to the first power supply line or the second power supply line by the first discharge unit, to the opposite power supply line. A trigger unit drives the first discharge unit and the power clamp unit with first and second detection voltages generated in response to a voltage drop of the discharged electrostatic current.08-13-2009
20110063762FLASH MEMORY CIRCUIT WITH ESD PROTECTION - A flash memory circuit with ESD protection includes a plurality of flash memory blocks, a pad, an ESD transistor, a pass transistor, and a gate driving circuit. The gate driving circuit has an inverter circuit for receiving a control voltage and outputting an output voltage, a resistor for receiving a pad voltage from the pad, and a capacitor for delaying a change in the control voltage. The ESD transistor is coupled to the pad, a power supply, and the output terminal of the inverter circuit. The pass transistor is coupled to one of the flash memory blocks and the pad, and is controlled by the output voltage. A well terminal of the pass transistor is coupled to the resistor for keeping the pass transistor turned off during electrostatic discharge through the pad.03-17-2011
20090103218SURGE SUPPRESSION SYSTEM WITH OVERLOAD DISCONNECT - A surge suppression unit contains electrical surge suppression components configured to redirect power surges. A sensor monitors the surge suppression components for a possible impending explosion or fire condition. A disconnect mechanism is configured to disconnect power from the surge suppression components when the sensor detects the explosion or fire condition.04-23-2009
20110317316METHOD, APPARATUS, AND SYSTEM FOR PROTECTING SUPPLY NODES FROM ELECTROSTATIC DISCHARGE - Described herein are a method, apparatus, and system for electrostatic discharge protection of supplies. The apparatus comprises a timer unit having a node with a first supply signal and operable to generate a first timer signal based on the first supply signal; and a clamp unit, coupled to the timer unit and having a node with a second supply signal, operable to clamp the second supply signal in response to electrostatic discharge (ESD) on the node with the second supply signal for a duration based on a signal level of the first timer signal.12-29-2011
20110063765MOS DEVICE WITH SUBSTRATE POTENTIAL ELEVATION FOR ESD PROTECTION - An integrated circuit (03-17-2011
20110063763Electrostatic Discharge Protection Circuit, Integrated Circuit And Method Of Protecting Circuitry From An Electrostatic Discharge Voltage - Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.03-17-2011
20110090608ELECTRICAL-OVERSTRESS PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT - An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.04-21-2011
20110317319ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An ESD (Electrostatic Discharge, ESD) protection circuit includes a voltage-divider generating circuit, a decision circuit, and a switching circuit. The voltage-divider generating circuit outputs a first voltage and a second voltage according to an input voltage. The decision circuit is coupled to the voltage-divider generating circuit and receives the first voltage and the second voltage. The decision circuit outputs an output voltage according to the first voltage and the second voltage. The switching circuit is coupled to the decision circuit and is either turned on or turned off according to the output voltage. The transient voltages of the first and the second voltage are different.12-29-2011
20110317318CIRCUIT ELEMENTS COMPRISING FERROIC MATERIALS - Ferroic circuit elements that include a set of conductive structures that are at least partially embedded within a ferroic medium are disclosed. The ferroic medium may be a voltage switched dielectric material that includes ferroic particles in accordance with various embodiments. A ferroic circuit element may be at least partially embedded within a substrate in accordance with embodiments of the current invention as an embedded ferroic circuit element. An embedded ferroic circuit element that is an inductor in accordance with embodiments of the current invention may be denoted as an embedded ferroic inductor. An embedded ferroic circuit element that is a capacitor in accordance with embodiments of the current invention may be denoted as an embedded ferroic capacitor.12-29-2011
20110317317Method and Device for Delaying Activation Timing of Output Device - A delay method for determining an activation time of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance of the over-current flag pull-high resistor and a voltage drop across the resistor, duplicating the current to generate a division current, drawing the division current from a charging current to determine an activation current of the output device, and determining the activation time point of the output device according to the activation current.12-29-2011
20090073618SURGE ABSORBING CIRCUIT CAPABLE OF REDUCING A CLAMPING VOLTAGE WITH A GREAT EXTENT - A surge absorbing circuit capable of reducing a clamping voltage with a great extent includes an input, an output, at least two inductors respectively connected between the input and the output in series, and at least two capacitances respectively connected at two sides of the inductors in parallel. The input is employed to let an AC power source pass in. The output is to transmit the AC power source having been treated by the surge absorbing circuit to a load circuit. By means of the surge absorbing circuit, the clamping voltage of the varistors can be greatly lowered and the surge can be consumed more quickly.03-19-2009
20100079921Semiconductor Device - To provide a highly reliable semiconductor device (an RF tag) which operates normally even when a communication distance is extremely short, a protection circuit (a limiter circuit) for protecting an element which forms a semiconductor device (an RF tag) capable of wirelessly communicating data is provided. When the DC power supply potential which is generated in a rectifier circuit is equal to or greater than a predetermined value (a reference value), the protection circuit is made to operate, and the value of the generated DC power supply potential is reduced. On the other hand, when the DC power supply potential which is generated in the rectifier circuit is equal to or less than the predetermined value (reference value), the protection circuit is made not to operate, and the value of the generated DC power supply potential is used without change.04-01-2010
20120120532PRINTED WIRING BOARD - A printed wiring board includes: an anode pattern electrically connected to an anode of a laser diode; and a cathode pattern arranged to oppose the anode pattern and electrically connected to a cathode of the laser diode, the anode pattern and the cathode pattern being in shapes having such parts that a distance between the anode pattern and the cathode pattern opposed to each other is a first distance, and such parts that a distance between the anode pattern and the cathode pattern opposed to each other is a second distance shorter than the first distance, at least such parts that the distance between the anode pattern and the cathode pattern opposed to each other is the second distance being short-circuited by solder in a case where the laser diode is protected from an electrostatic discharge.05-17-2012
20120002335PROTECTION CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - A protection circuit is connected between an interface circuit and a main circuit of an electronic device. The interface circuit is for providing a path for a power supply to power the main circuit. The protection circuit includes an electrostatic protection unit and a mis-connect protection unit. The electrostatic protection unit is electrically connected to the interface circuit and the main circuit and is configured for clamping a voltage of a node to a predetermined value, which the node is defined by the interface circuit, the electrostatic protection unit, and the main circuit. The mis-connect protection unit is electrically connected between the node and the main circuit. When the interface circuit is incorrectly connected to the power supply, the mis-connect protection unit disconnects an electrical connection between the power supply and the main circuit.01-05-2012
20120002334ELECTROSTATIC DISCHARGE CIRCUIT - An integrated circuit (IC) is disclosed. The IC includes a first global voltage node and a second global voltage node. The IC further includes two or more power domains each coupled to the first global voltage node. Each of the two or more power domains includes a functional unit and a local voltage node coupled to the functional unit. Each of the plurality of power domains further includes a power-gating transistor coupled between the local voltage node and the second global voltage node, and an ESD (electrostatic discharge) circuit configured to detect an occurrence of an ESD event and further configured to cause activation of the transistor responsive to detecting the ESD event.01-05-2012
20120099232SEMICONDUCTOR INTEGRATED CIRCUIT - A DC/DC-converter semiconductor integrated circuit using a bootstrap circuit includes a protection device having a standard breakdown voltage to break down between a first terminal and a second terminal, between which a capacitor of the bootstrap circuit is located, in response to a voltage higher than a maximum voltage applied to the capacitor.04-26-2012
20120099229Semiconductor ESD Device and Method - An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.04-26-2012
20120044605ESD PROTECTION FOR HIGH-VOLTAGE-TOLERANCE OPEN-DRAIN OUTPUT PAD - A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.02-23-2012
20120044604POWER AMPLIFIER MODULE WITH SHARED ESD PROTECTION CIRCUIT - Disclosed is a power amplifier module with a shared ESD protection circuit. There is provided a power amplifier module including: an ESD protection circuit that is connected to an output terminal of the LDO part, an output conductive wire pad that outputs the operating power of the LDO part; a printed conductive wire pad that is electrically connected to the output conductive wire pad of the PA controller; a first power coupler that includes a first primary side conductive wire electrically connected to the printer conductive wire pad; a second power coupler that includes a second primary side conductive wire electrically connected to the printer conductive wire pad; a first PA part; and a second PA part, wherein each of the first PA part and the second PA part is protected from ESD by the ESD protection circuit.02-23-2012
20120044606ESD PROTECTION OF AN RF PA SEMICONDUCTOR DIE USING A PA CONTROLLER SEMICONDUCTOR DIE - A power amplifier (PA) controller semiconductor die and a first radio frequency (RF) PA semiconductor die are disclosed. The PA controller semiconductor die includes a first electro-static discharge (ESD) protection circuit, which ESD protects and provides a first ESD protected signal. The RF PA semiconductor die receives the first ESD protected signal. In one embodiment of the PA controller semiconductor die, the first ESD protected signal is an envelope power supply signal. The PA controller semiconductor die may be a Silicon complementary metal-oxide-semiconductor (CMOS) semiconductor die and the RF PA semiconductor die may be a Gallium Arsenide semiconductor die.02-23-2012
20100232077GATED DIODE HAVING AT LEAST ONE LIGHTLY-DOPED DRAIN (LDD) IMPLANT BLOCKED AND CIRCUITS AND METHODS EMPLOYING SAME - Gated diodes, manufacturing methods, and related circuits are provided wherein at least one lightly-doped drain (LDD) implant is blocked in the gated diode to reduce its capacitance. In this manner, the gated diode may be used in circuits and other applications whose performance is sensitive to load capacitance while still obtaining the performance characteristics of a gated diode. These characteristics include fast turn-on times and high conductance, making the gated diodes disclosed herein well-suited for electro-static discharge (ESD) protection circuits as one application example. The examples of the gated diode disclosed herein include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region, wherein a P-N junction is formed. At least one LDD implant is blocked in the gated diode to reduce capacitance.09-16-2010
20120008243Secondary ESD Circuit - An integrated circuit device provides electrostatic discharge (ESD) protection, as may be applicable to circuits susceptible to ESD in conjunction with, or prior to, activation of a primary ESD circuit for dissipating an ESD. In connection with various example embodiments, primary and secondary ESD circuits discharge electrostatic pulses as may be present at a power input pad, with the secondary ESD circuit separated from the input pad by an impedance circuit. The secondary ESD circuit is configured to actively mitigate an electrostatic pulse present in conjunction with, or before, the activation of the primary ESD circuit, in response to an input voltage level achieving a threshold level. In some implementations, the secondary ESD circuit activates to mitigate some or all of the presentation of an electrostatic pulse to a circuit that competes with the primary ESD circuit, for drawing charge from a common node (e.g., a power supply pad).01-12-2012
20120008244ELECTRICAL-OVERSTRESS PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT - An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.01-12-2012
20120008242APPARATUS AND METHOD FOR ELECTRONIC CIRCUIT PROTECTION - Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises an internal circuit electrically connected between a first node and a second node, and a protection circuit electrically connected between the first node and the second node and configured to protect the internal circuit from transient electrical events. The protection circuit comprises a bipolar transistor having an emitter connected to the first node, a base connected to a third node, and a collector connected to a fourth node. The protection circuit further comprises a first diode electrically connected between the third node and the fourth node, and a second diode electrically connected between the second node and the fourth node. The first diode is an avalanche breakdown diode having an avalanche breakdown voltage lower than or about equal to a breakdown voltage associated with the base and the collector of the bipolar transistor.01-12-2012
20120008241ESD PROTECTION CIRCUIT AND METHOD - An ESD protection circuit for reducing the regulator output capacitance includes a ground isolation circuit or a VCC isolation circuit to isolate regulator output from ground terminal or VCC terminal whenever ESD occurs, causing dropping of the differential voltage between regulator output and ground. The isolation circuits function to minimize the leakage current.01-12-2012
20120057261Configurable, Power Supply Voltage Referenced Single-Ended Signaling with ESD Protection - A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.03-08-2012
20120057260Power Supply Shunt - A power supply shunt for an electronic circuit. The power supply shunt includes at least two Field Effect Transistors (FETs), a first of the FETs having its drain coupled to a terminal of an electronic circuit and its source coupled to another of the FETs, and a second of the FETs having its source coupled to ground and its drain coupled to another of the FETs. The first FET has a bulk terminal that floats with respect to ground.03-08-2012
20120057259CONTROLLER WITH BATTERY RECHARGE PROTECTIVE FUNCTION - A controller with battery recharge protective function is disclosed in this invention. The controller is used for protecting a battery module. When the battery module is in a protective state, a recharge protection circuit of the controller is activated. A charging current from a positive recharge terminal flows into one pin of the controller. Afterward, the charging current passes the recharge protection circuit, flows out through another pin of the controller, and then returns to a negative recharge terminal. Accordingly, the recharge protection circuit makes the charging current bypass the battery module, so as to prevent the battery module from being damaged.03-08-2012
20120057258ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD THEREOF - An electrostatic discharge protection device for protecting an inner circuit, which is operated in a source voltage, is provided and includes a protection unit and a control unit. The protection unit provides a discharge path for transmitting an electrostatic signal from a pad to a ground line. According to a voltage level at a control end, the protection unit adjusts a holding voltage and a triggering voltage determining whether to conduct the discharge path. When the source voltage is supplied, the control unit transmits the input voltage to the control end of the protection unit, so as to raise the holding and the triggering voltages of the discharge path. When the source voltage is not supplied, the control unit switches the control end of the protection unit to a floating condition by the electrostatic signal, so as to lower the holding and the triggering voltages of the discharge path.03-08-2012
20120014021INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE - A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.01-19-2012
20110080679PROTECTING APPARATUS - An apparatus for protecting equipment connected to a high voltage direct current line comprises a current valve having at least one semiconductor device and a rectifying member connected in anti-parallel therewith. A surge arrester is configured to connect said current valve to said line, and a control unit is configured to control the current valve to conduct for draining current from the line to ground.04-07-2011
20120154960ESD PROTECTION CIRCUIT WITH EOS IMMUNITY - ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting.06-21-2012
20120154961ELECTROSTATIC DISCHARGE BLOCKING CIRCUITS - Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.06-21-2012
20120026633DECREASING VOLTAGE DETECTION WITH CONTROL SIGNALING - Illustrative circuits and methods are provided. Circuitry is configured to detect a decrease in a monitored voltage at greater than a threshold rate. A fuse is deliberately blown in response to the detection. Power control circuitry is disabled and prevented from resuming normal operations by way of control signaling. The blown fuse ensures that at least one control signal is maintained until the blown fuse is replaced by service personnel. Shunt circuitry optionally discharges storage capacitors of the power control circuitry. Sensitive electronic components are protected against over-voltage or overcurrent damage in accordance with the present teachings.02-02-2012
20120300350GRADUALLY REDUCING RESISTIVE CLAMP - A voltage spike protection system minimizes a voltage spike by connecting a resistive clamp to a power source when the voltage spike is detected. The voltage spike detection system disconnects the resistive clamp after a portion of the voltage spike is dissipated.11-29-2012
20120300349GATE DIELECTRIC BREAKDOWN PROTECTION DURING ESD EVENTS - Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.11-29-2012
20120154964CIRCUIT FOR DETECTING STATIC ELECTRICITY - In the circuit for detecting static electricity, a switch for cancelling charges on an electrode body, which detects static electricity, is not necessarily provided. The circuit (06-21-2012
20120154965LEVEL CONVERSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE EMPLOYING THE LEVEL CONVERSION CIRCUIT - In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.06-21-2012
20120154963ADAPTIVE ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT - For adaptive electrostatic discharge (ESD) protection, an integrated circuit device having an adaptive electrostatic discharge (ESD) protection, has an external connection pin to be protected from ESD; an external ground connection pin; an adaptive electrostatic discharge (ESD) protection circuit having: an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground; a resistor coupled between a gate of the NMOS transistor and ground; a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground; a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin.06-21-2012
20120154962ELECTROSTATIC DISCHARGE CLAMPING DEVICES WITH TRACING CIRCUITRY - Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.06-21-2012
20090135535ELECTROSTATIC DISCHARGE DEVICE WITH METAL OPTION ENSURING A PIN CAPACITANCE - The present invention discloses an electrostatic discharge device for ensuring a pin capacitance using a metal option. The electrostatic discharge device includes an electrostatic discharging unit formed between a power source voltage line and a ground voltage line to discharge static electricity input from a pad. A MOS capacitor of the electrostatic discharge device has a gate terminal connected to the pad via a metal option. A protection unit is formed between the electrostatic discharging unit and the ground voltage line to protect an internal circuit from static electricity stored in the electrostatic discharging unit.05-28-2009
20090135534SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first and second power supply domain circuits having a first and second power supply terminals, respectively. An internal signal propagation line propagates a signal from a circuit of the first power supply domain circuit to that of the second power supply domain circuit. A voltage detector detects a surge voltage input to the first and second power supply terminals and outputs, from a control signal node, a control signal which is determined in accordance with a capacitive coupling by a first capacitor between the first power supply terminal and the control signal node, a second capacitor between the second power supply terminal and the control signal node, and a load capacitance at an output side of the control signal node. A voltage limiting circuit limits a voltage of a signal on the internal signal propagation line in accordance with the control signal.05-28-2009
20090135533Power-rail ESD protection circuit with ultra low gate leakage - An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.05-28-2009
20090135532ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS - An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.05-28-2009
20110090609Electrostatic protection circuit - An electrostatic protection circuit includes a first terminal, a second terminal, an input circuit which includes a Metal Oxide Semiconductor (MOS) transistor including a gate, a source, and a drain, the gate as an input terminal being coupled to the first terminal, the source being coupled to the second terminal, an electrostatic protection element connected to the drain, the electrostatic protection element including a first electrostatic protection element, and a second electrostatic protection element connected between the first terminal and the second terminal.04-21-2011
20090213507SYSTEM AND METHOD OF ELECTROSTATIC DISCHARGE PROTECTION FOR SIGNALS AT VARIOUS VOLTAGES - System and method for protecting an integrated circuit. The system includes a first transistor coupled to a first voltage and a second voltage, a second transistor coupled to the gate of the first transistor and the first voltage, a third transistor coupled to the gate of the second transistor and the first voltage, and a capacitor coupled to the gate of the second transistor and the second voltage. The first voltage is provided to the integrated circuit, the gate of the third transistor is configured to receive a first control signal, the gate of the second transistor is configured to receive a second control signal, and the second control signal is capable of turning off the second transistor a time period after the third transistor is turned off.08-27-2009
20110102955SEMICONDUCTOR DEVICE - A semiconductor device includes a first pad, and a sub-trunk line elongated in a first direction; a main-trunk line arranged between the first pad and the sub-trunk line and elongated in the first direction. The semiconductor device further includes a first plug line elongated in a second direction crossing the first direction, the first plug line being connected between the first pad and the main-trunk line without being direct contact with the sub-trunk line. The semiconductor device further includes a second plug line elongated in the second direction, the second plug line being connected between the main-trunk line and the sub-trunk line, and a first element coupled to the sub-trunk line.05-05-2011
20110102954SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first functional circuit block; a second functional circuit block; a relay circuit block; a first protection circuit block; and a second protection circuit block. The first protection circuit block includes an ESD protection circuit connected between either one of a first high-voltage power supply line and a first low-voltage power supply line, and either one of a third high-voltage power supply line and a third low-voltage power supply line. The second protection circuit block includes an ESD protection circuit connected between either one of a second high-voltage power supply line and a second low-voltage power supply line, and either one of the third high-voltage power supply line and the third low-voltage power supply line.05-05-2011
20120250198ESD PROTECTION CIRCUIT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is an ESD protection circuit for CDM capable of preventing a high current from flowing and preventing breakage when a battery is connected with reverse polarity. The ESD protection circuit employs a circuit configuration in which transistor elements are interposed in series to OFF transistors (10-04-2012
20120250195ELECTROSTATIC DISCHARGE POWER CLAMP WITH A JFET BASED RC TRIGGER CIRCUIT - An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.10-04-2012
20120162835CONTROLLABLE CIRCUITS, PROCESSES AND SYSTEMS FOR FUNCTIONAL ESD TOLERANCE - An electronic circuit (06-28-2012
20100290165Circuit Arrangement for Protection Against Electrostatic Charges and Method for Dissipation Thereof - A circuit arrangement for protection against electrostatic discharges comprises an shunt device, which is connected between a first and a second terminal of the circuit arrangement and has a control input, via which the conduction of the shunt device can be controlled. In addition there is a trigger element, which has a trigger output for issuing a trigger signal in dependence on a voltage between the first and the second terminal of the circuit arrangement. The circuit arrangement additionally comprises an interruption unit that can be controlled via a deactivation input by means of a sendable deactivation signal and which is connected on the input side to the trigger output and on the output side to the control input. In addition, a method for shunting electrostatic discharges is shown.11-18-2010
20100246077ELECTROSTATIC DISCHARGE PROTECTION DEVICE OF OUTPUT DRIVER STAGE - Provided is an electrostatic discharge (ESD) protection device of an output driver stage of a semiconductor chip. The ESD protection device of an output driver stage, which includes a p-channel metal-oxide-semiconductor (PMOS) transistor having a source connected to a first source voltage and an n-channel metal-oxide-semiconductor (NMOS) transistor having a source connected to a second source voltage, the MOS transistors having gates applied with output signals from an internal circuit and drains connected to the output pad, wherein a distance between contacts formed on a drain region and a gate poly of the MOS transistors is relatively greater than a value according to a predetermined design rule.09-30-2010
20100246078SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device supports maintenance of a signal transfer frequency and waveform quality and electrostatic protection, and also suppresses expansion of a chip area. In order to maintain the signal transfer frequency and the waveform quality as well as to keep an effect of the electrostatic protection, and simultaneously to protect a differential input pair by a single electrostatic protection element and to attain area superiority, the electrostatic protection element that is arbitrarily separable is disposed at a middle point of a terminator.09-30-2010
20100246079POWER SUPPLY CLAMP CIRCUIT - A power supply clamp circuit includes a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode, and a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other.09-30-2010
20100246075INTERFACE CIRCUIT AND PORTABLE ELECTRONIC DEVICE EMPLOYING THE SAME - An interface circuit for connecting with a universal serial bus (USB) data cable includes a USB connector for connecting with the USB data cable, an over voltage protection (OVP) circuit connected to the USB connector, and a time delay circuit connected to the USB connector and the OVP circuit to control the OVP circuit. The OVP circuit is switched off in a predetermined delay time of the time delay circuit when the USB data cable is connected to the USB connector, and is then switched on after the delay time of the time delay circuit.09-30-2010
20120162836SEMICONDUCTOR DEVICE - In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.06-28-2012
20120127618ELECTROSTATIC DISCHARGE PROTECTIVE CIRCUIT HAVING RISE TIME DETECTOR AND DISCHARGE SUSTAINING CIRCUITRY - Methods of the invention include an electrostatic discharge (ESD) protection method capable of detecting a slew rate of an input signal and capable of determining whether the slew rate of the input signal is greater than a threshold value. For an ESD event having a slew rate in excess of the threshold value said method generates a trigger signal which generates an activation signal that activates the ESD dissipation circuitry and that controls the length of time the dissipation circuit remains active. The method further comprises shunting the ESD energy away from a protected internal circuit. The method maintaining the shunting of the energy for a period of time sufficient to discharge of the ESD energy without damaging the protected circuitry.05-24-2012
20100020454ESD protection device - An ESD protection device that has low capacitance, excellent discharge characteristics, and improved heat resistance and weather resistance is provided. A functional layer 01-28-2010
20110181990BAND-PASS STRUCTURE ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a band-pass structure electrostatic discharge protection circuit. An ESD protection circuit is disposed at the input of a radio frequency (RF) core circuit. The ESD protection circuit comprises a plurality of diodes and inductors constructing a plurality of discharging paths, wherein the diodes and inductors forms a band-pass filter structure. Such that, the RF core circuit with the ESD protection circuit of the present invention feature much higher ESD robustness and better RF performance than the conventional design.07-28-2011
20120162834Electrostatic Discharge (ESD) Protection Circuit and Method for Designing Thereof for Protection of Millimeter Wave Electrical Elements - A miniaturized electrostatic discharge (ESD) protection circuit designed for millimeter wave electrical elements, wherein the ESD protection circuit is fabricated on a multilayer substrate. The ESD protection circuit comprises a metal line being connected at one end to a ground and at other end to a connective strip, wherein a length of the metal line is a maximum length that achieves a resistance value defined for the ESD protection circuit and a width of the metal line is set to a maximum width allowed for the multilayer substrate, wherein the metal line introduces a inductance value into the ESD protection circuit; and a capacitor being connected in parallel to the metal line and having a capacitance value resonating the metal line at an operating frequency band, thereby the ESD protection circuit shunts ESD pulses to the ground and passes signals at the operating frequency band06-28-2012
20120162832ESD PROTECTION CIRCUIT FOR MULTI-POWERED INTEGRATED CIRCUIT - For a multi-powered IC, an ESD protection circuit includes multiple voltage clamping circuits, each configured to provide a path for discharging an ESD transient current associated with a corresponding power supply.06-28-2012
20120212867DATA PORT TRANSIENT PROTECTION APPARATUS AND METHODS - Methods and apparatus for protecting data bus ports and their corresponding PHY devices from taking damage associated with excess voltage across one or more signal pairs during an intermittent connection. Such connections cause the signal pins to carry external device current which raises the signal voltage above the power rails, exceeding the PIN device ratings and causing PHY degradation or destruction. In an exemplary embodiment, an RC circuit is used to detect the voltage level across a signal pair. If this voltage level exceeds a certain preset voltage level, power to the outgoing serial bus port is shut off and return power is abated. While the circuit is responding, the exemplary embodiment uses a 3.6V Zener diode to bleed excess voltage to ground. A current monitor/limiter is also used for limiting current if the voltage level detected exceeds a certain threshold.08-23-2012
20120314328ESD PROTECTION DEVICE - An electrostatic discharge (ESD) protection device for protecting an I/O port of an electronic circuit from overvoltage and a coil structure for use in an ESD protection device. The ESD protection device includes: a plurality of inductors that are serially coupled in a line, where a node is formed between two neighboring inductors; and a plurality of protection arrangements adapted to conduct charges to one provided potential when an overvoltage is applied, where each of the protection arrangements is connected with one of the nodes, and where the serially coupled inductors are magnetically coupled with each other.12-13-2012
20120134059ESD PROTECTION DEVICE AND MANUFACTURING METHOD THEREOF - An ESD protection device includes a ceramic base material, a pair of opposed electrodes provided on a surface of or in the ceramic base material, and a discharge auxiliary electrode film arranged to connect the pair of opposed electrodes, wherein the discharge auxiliary electrode film is composed of a material containing, as its main constituents, metallic particles and glass covering the metallic particles. The discharge auxiliary electrode film is formed by providing an electrode paste containing glass-coated metallic particles that have an approximately 15% rate of increase in weight at about 400° C. for about 2 hours in air, a resin binder, and a solvent so as to connect the pair of opposed electrodes to each other, and then firing at a temperature of about 600° C. or more, higher than a softening point of glass of the glass-coated metallic particles, and not +200° C. higher than the softening point.05-31-2012
20090059453SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes an external pad, a ground line, a first protection circuit between the external pad and the ground line, and a second protection circuit between the external pad and the ground line. The second protection circuit is formed by a first protection element, a second protection element, and a resistor. With this structure, the resistance value of the resistor is set to an arbitrary value, so that an unnecessary current which would be generated at the time of power-off of the LSI can be decreased to a value which does not deteriorate the reliability of the LSI.03-05-2009
20090059452Method and apparatus for providing electrostatic discharge protection for a power supply - An electrostatic discharge (ESD) protection circuit for protecting a power supply of a device includes a main discharge transistor with a drain coupled to a supply voltage line of the device and a source coupled to ground. The ESD protection circuit also includes a control circuit to modulate a bulk of the main discharge transistor to generate a current discharge path to ground in response to an ESD event.03-05-2009
20090059451ESD PROTECTION CIRCUIT WITH IMPROVED COUPLING CAPACITOR - In an ESD protection circuit, a MOS transistor and a coupling capacitor are formed over the same substrate. The coupling capacitor may be a MIM capacitor or a PIP capacitor. In case of MIM capacitor, the first metal layer and the second metal layer thereof are electrically coupled to the gate region and the source/drain region of the MOS transistor, respectively. In case of PIP capacitor, the gate region of the MOS transistor, an insulation layer and the second poly layer thereof define the PIP capacitor. The second poly layer of the PIP capacitor is electrically coupled to the source/drain region of the MOS transistor.03-05-2009
20090059450Sensing a Current Signal in an Integrated Circuit - An integrated circuit including a voltage setting circuit configured to set the voltage level at a signal input to a value corresponding to a first supply voltage of the integrated circuit.03-05-2009
20120250197LOW LEAKAGE ESD STRUCTURE FOR NON-CONTACT BIO-SIGNAL SENSORS - Various techniques for providing a low leakage electrostatic discharge (ESD) structure for non-contact bio-signal sensors are disclosed. In some embodiments, a low leakage ESD structure for a capacitive bio-sensor includes a unity gain buffer, and an ESD protection circuit connected to the unity gain buffer, in which the ESD protection circuit includes a diode connected across an input and an output of the unity gain buffer, and in which a voltage range for the ESD protection circuit is configurable.10-04-2012
20120314327DC POWER SUPPLY INSULATION FAULT DETECTION CIRCUIT - A DC power supply insulation fault detection circuit includes a plurality of circuit breaking elements located at a positive terminal and a negative terminal of each circuit in a power supply system, at least one leakage current detector located in the circuit, and at least one positive voltage transient compensator and at least one negative voltage transient compensator respectively bridging the positive terminal and negative terminal of the power supply system. The positive and negative voltage transient compensators respectively include a charge/discharge circuit to allow an energy storage circuit to be charged. When grounding insulation deterioration takes place at the positive or negative terminal of the leakage current detector, a leakage current loop is formed so that energy storage elements discharge and the leakage current detector detects current variations on the positive and negative terminals, and issue an alarm signal or control cutoff of the circuit breaking elements.12-13-2012
20120170160ESD protection circuit and ESD protection device thereof - The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.07-05-2012
20120212869INTEGRATED CIRCUIT - According to one embodiment, an integrated circuit includes a first external terminal, a second external terminal, a third external terminal grounded, an output transistor connected to the second and third external terminals, an ESD protection circuit connected between the second external terminal and the third external terminal, a diode connected between the first and second external terminals, a power supply circuit connected between the first and third external terminals, an internal circuit connected between the power supply circuit and the third external terminal, a current source circuit, and a drive circuit having a first and second input terminals and an output terminal connected to the control electrode of the output transistor. When a voltage larger than a maximum rating voltage is applied to the second external terminal, the drive circuit turns off the output transistor and the ESD protection circuit operates.08-23-2012
20120212868INTEGRATED CIRCUIT - According to one embodiment, an integrated circuit includes a power supply terminal, an output terminal, a high side output transistor including a first electrode connected to the power supply terminal, a second electrode connected to the output terminal, and a control electrode, a transistor which is connected between the control electrode and the second electrode of the high side output transistor and which short-circuits the control electrode and the second electrode in an on state, a trigger circuit connected between the power supply terminal and the control electrode of the transistor, and an Electro Static Discharge (ESD) protection circuit connected between the power supply terminal and the output terminal. When a voltage larger than a maximum rating voltage is applied to the power supply terminal, the trigger circuit operates, the transistor turns on, the high side output transistor turns off, and the ESD protection circuit operates.08-23-2012
20120250199POWER OVER ETHERNET ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - A Power over Ethernet electrostatic discharge protection circuit has a diode with an anode coupled to an Ethernet port and a cathode coupled to a non-collapsible clamp. The non-collapsible clamp is coupled to the cathode and ground. A transistor can be added, with the transistor drain coupled to the diode anode and the transistor source is coupled to ground.10-04-2012
20120212866OUTPUT DRIVER - An output driver having a power supply line, a control switch, at least one protection device and at least one voltage clamp device. The control switch disposed between the at least one protection device and the power supply line an output line. The at least one protection device disposed in a series arrangement between the output line and the control switch. The at least one voltage clamp device disposed across a corresponding protection device and adapted to clamp a voltage across the protection device below a predetermined threshold voltage.08-23-2012
20120176710Semiconductor ESD Circuit and Method - In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.07-12-2012
20120075757CIRCUIT WITH ESD PROTECTION FOR A SWITCHING REGULATOR - The present invention discloses a circuit with ESD protection and high voltage conversion for a switching regulator. It mainly comprises a non-overlap circuit, a power P-type MOS device, a parasitic diode, a digital logic AND gate, a pair of resistance and capacitance, a power N-type MOS device, an ESD N-type MOS device, a Lx pin and an ESD protection cell. The present invention can effectively decrease the on-resistance of MOS device and then improve the circuit efficiency.03-29-2012
20120176707ESD clamp with auto biasing under high injection conditions - In an SCR ESD protection circuit, the n-type emitter of the SCR is controlled to receive electron current only during an ESD event, thereby defining PNP characteristics during normal operation and SCR characteristics during an ESD event.07-12-2012
20120176711METHOD AND APPARATUS FOR SWITCHED ELECTROSTATIC DISCHARGE PROTECTION - One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.07-12-2012
20120176709ESD PROTECTION DEVICES AND METHODS FOR FORMING ESD PROTECTION DEVICES - The present disclosure provides a circuit that has an electrostatic discharge (ESD) protection device and a protected circuit in communication with the ESD protection device. The ESD protection device has a first inductor between a signal input terminal and a complimentary power line. The first inductor has a length less than ¼ of a normal operating wavelength of the protected circuit. The ESD protection device also has a first capacitor between the signal input terminal and the protected circuit.07-12-2012
20120176708ESD PROTECTION DEVICES AND METHODS FOR FORMING ESD PROTECTION DEVICES - The present disclosure provides a device that includes a signal input that is in electrical communication with an electrostatic discharge (ESD) protection device, wherein the ESD protection device includes a gated diode arranged as a polygon.07-12-2012
20100271740INTEGRATED CIRCUIT PROVIDED WITH A LARGE AREA PROTECTION AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, including: first and second supply rails; first and second intermediary rails normally connected to the first and second supply rails; inverters formed of a P-channel MOS transistor series-connected to an N-channel MOS transistor, the sources of the P-channel and N-channel MOS transistors being respectively connected to the first and second supply rails and the bodies of the P-channel and N-channel transistors being respectively connected to the first and second intermediary rails; a positive overvoltage detector between the first and second supply rails; and a switch for connecting the first and second intermediary rails to the second and first supply rails when a positive overvoltage is detected.10-28-2010
20100271739Semiconductor integrated circuit having protection circuit capable of protecting against ESD and EOS - A semiconductor integrated circuit has an internal circuit having an input terminal connected to a connection terminal, a protection circuit that discharges an over-voltage supplied to the connection terminal to a power line. The protection circuit includes a first discharge circuit connected to the connection terminal, a second discharge circuit connected to the connection terminal and discharges the over-voltage to the power line, and an over-voltage detect circuit that detects a discharge current flowing through the second discharge circuit and generates an over-voltage detect signal when the discharge current is detected. The first discharge circuit is disabled to discharge the over-voltage when the over-voltage detect signal is supplied.10-28-2010
20100271738CIRCUIT FOR ELECTRIC OVER STRESS IMMUNITY - The present invention discloses a circuit for electric over stress immunity comprising: a resistor receiving an external voltage; a zener diode having a cathode electrically connected with the resistor; and a functional circuit to be protected, which is electrically connected with both sides of the zener diode; wherein the resistor, the zener diode and the functional circuit are integrated in an integrated circuit.10-28-2010
20100046131ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND ELECTROSTATIC DISCHARGE PROTECTION METHOD OF A SEMICONDUCTOR MEMORY DEVICE - An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.02-25-2010
20100008001ELECTROSTATIC DISCHARGE PROTECTION OF SEMICONDUCTOR DEVICE - A semiconductor device includes a pads for receiving a reference voltage and input signals from an external device, a unit gain buffer for receiving the reference voltage as an input, input buffers for identifying a corresponding one of the input signals based on an internal reference voltage outputted from the unit gain buffer, external electrostatic discharge protectors connected to a transmission path of the reference voltage and transmission paths of input signals, and internal electrostatic discharge protectors connected to the transmission path of the reference voltage and the transmission paths of the input signals.01-14-2010
20100008003ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and a gate, wherein the drain is connected to the gate. The first terminal is connected to the gate, while the second terminal is connected to the source. The first terminal is connected to one power supply terminal and ground terminal, whereas the second terminal is connected to the other the power supply terminal and ground terminal.01-14-2010
20100008002High Trigger Current Silicon Controlled Rectifier - An ESD protection circuit including an SCR having at least a PNP transistor and at least a NPN transistor such that said PNP transistor is coupled to an anode and the NPN transistor is coupled to a cathode. The circuit also includes a first resistor coupled between the anode and the base of the pnp transistor and a second resistor coupled between the cathode and the base of the npn transistor. A parasitic distributed bipolar transistor is formed between said first and second transistor to control triggering of the SCR.01-14-2010
20120218671Semiconductor ESD Device and Method of Making Same - A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.08-30-2012
20120188671T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY - An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.07-26-2012
20120188670SWITCH CONTROL CIRCUIT, SWITCH CONTROLLING METHOD, AND POWER SUPPLY DEVICE USING THE SWITCH CONTROL CIRCUIT - Embodiments of the present invention relate to a switch control circuit, a switch control method, and a power supply device using the same.07-26-2012
20120188669SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes an interface pad unit, an input buffer unit configured to receive an external signal through the input buffer unit, an electrostatic discharge unit configured to discharge a static electricity from the interface pad unit, and an input buffer protection unit configured to electrically disconnect the interface pad unit and the input buffer unit from each other when the static electricity is generated.07-26-2012
20120262829PROTECTION DEVICE AGAINST ELECTROMAGNETIC INTERFERENCE - The invention relates to a protection device for reducing grid-bound interference, comprising a protection circuit as an input filter of an electronic circuit, wherein the electronic circuit is applied to a multilayer circuit board or is at least partially integrated therein, wherein individual components of the circuit are implemented as embedded structures in the multilayer circuit board. According to the invention, the protection circuit is formed by a cascade of at least as two capacitances coupled to each other by means of low-inductance circuit board structures, wherein the capacitances are implemented as embedded capacitor structures on or within the multilayer circuit board. By means of said protection device, improved filter behavior can be achieved relative to discretely populated protection filters, in particular at higher frequencies, leading to improved protection against electrostatic interference. The filter structure can further be adjusted very well in simulation to the required interference resistance of the circuit to be protected, and also achieve improved aging behavior.10-18-2012
20120262828CLAMP BASED ESD PROTECTION CIRCUITS - An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.10-18-2012
20120262827SEMICONDUCTOR DEVICE, DC-DC CONVERTER, AND PROTECTIVE ELEMENT - A semiconductor device includes a first interconnect connected to a high voltage side power supply voltage, a second interconnect connected to the high voltage side power supply voltage, a switching transistor, and a protective element connected in parallel with the switching transistor between the high voltage side power supply voltage and a low voltage side power supply voltage. A first end of the switching transistor is connected to the first interconnect, and a second end is connected to an output terminal. The protective element includes a first p-type semiconductor region connected to the first interconnect, an n-type semiconductor region in contact with the first p-type semiconductor region and connected to the second interconnect, and a second p-type semiconductor region in contact with the n-type semiconductor region, spaced from the first p-type semiconductor region, and connected to the low voltage side power supply voltage.10-18-2012
20120262826Directing the Flow of Electrostatic Discharge (ESD) Current to a Targeted Impedance Using Nested Plates - A mechanism for protecting objects sensitive to electrostatic discharge (ESD) employs nested plates to direct the flow of ESD current to a targeted impedance. In one embodiment, an insulator plate is interposed between first and second electrically conductive plates. The insulator plate prevents any charge accumulating on the first plate from arcing to the second plate through the insulator plate. A target plate of electrically conductive material is interposed between the first and second plates over a hole in the insulator plate. The target plate, which is surrounded by an impedance layer of static dissipative material, includes a discharge portion that projects toward the second plate. ESD current flows in a path from the first plate, through the impedance layer, the target plate and again through the impedance layer, and to the second plate. The impedance layer provides a targeted impedance in the ESD current path.10-18-2012
20120257317RC-triggered Semiconductor Controlled Rectifier for ESD Protection of Signal Pads - RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.10-11-2012
20120081822System and Method for ESD Protection - An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range.04-05-2012
20120081821ESD Protection Device for Multi-Voltage System - An ESD protection device for a multi-voltage system includes a first circuit block, a second circuit block, a first power clamp circuit and a second power clamp circuit. The first and second circuit blocks respectively operate at a first power voltage and a second power voltage smaller than the first power voltage. The first power clamp circuit, coupled to the first circuit block, has a breakdown voltage between the first and second power voltages and a holding voltage greater than or equal to the first power voltage. The second power clamp circuit is smacked on the first power clamp circuit and coupled to the second circuit block. A total breakdown voltage of the first and second power clamp circuits is greater than the second power voltage, and a total holding voltage of the first and second power clamp circuits is greater than or equal to the second power voltage.04-05-2012
20120081820ESD POWER CLAMP FOR HIGH-VOLTAGE APPLICATIONS - An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node. The second power supply voltage is lower than a first power supply voltage on the first power supply node. The ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event. The ESD clamp further includes an LV ESD clamp coupled to the second power supply node, wherein the LV ESD clamp includes LV devices with maximum endurable voltages lower than the first power supply voltage.04-05-2012
20120229940INTEGRATED CIRCUIT HAVING ESD PROTECTION CAPABILITY - The present invention provides an integrated circuit having a better ESD protection capability and capable of reducing a circuit layout area. The integrated circuit comprises: an internal circuit, a first pad, and at least a first impedance matching unit. The first impedance matching unit is coupled between the internal circuit and the first pad, and the first impedance matching unit comprises: a first switch unit and a first resistance unit. The first switch unit is coupled to the internal circuit, and the first resistance unit is coupled between the first switch unit and the first pad, wherein the first resistance unit has a first terminal and a second terminal. The first terminal is directly electrically connected to the first pad and the second terminal is coupled to the first switch unit.09-13-2012
20120229941SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE - A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.09-13-2012
20080297961Systems, Circuits, Chips and Methods with Protection at Power Island Boundaries - Integrated circuits where the standard isolation cell, at power island boundaries, also includes a protection device, which clamps transient voltages.12-04-2008
20080297960INTEGRATED CIRCUIT AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An integrated circuit and a protection circuit capable of protecting electrostatic discharge (ESD) damage. The integrated circuit comprises a first pad, a ground pad, a second pad, a device circuitry, a discharging unit, and a discharging controller. The discharging unit comprises first and second transistors in series. The discharging controller comprises an ESD connection unit, and a voltage clamping unit. The ESD connection unit, coupled to the first pad and the discharging unit, receives an ESD pulse to establish a first control voltage to turn on the first transistor in the ESD event. The voltage clamping unit, coupled to the ESD connection unit and the first, second and ground pads, clamps the ESD pulse to establish a second control voltage to turn on the second transistor in the ESD event, and receives an operation voltage at the first pad to turn off the second transistor in normal operation.12-04-2008
20120320476HIGH-VOLTAGE DEVICES WITH INTEGRATED OVER-VOLTAGE PROTECTION AND ASSOCIATED METHODS - The present technology discloses a high-voltage device comprising a high-voltage transistor and an integrated over-voltage protection circuit. The over-voltage protection circuit monitors a voltage across the high-voltage transistor to detect an over-voltage condition of the high-voltage transistor, and turns the high-voltage transistor ON when the over-voltage condition is detected. Thus, once the high-voltage transistor is in over-voltage condition, the high-voltage transistor is turned ON and can dissipate the power from the over-voltage event through its channel.12-20-2012
20110038085Lateral Bipolar Transistor with Additional ESD Implant - A method for protecting a semiconductor circuit from electrostatic discharge is disclosed. An electrostatic discharge is received at a node. Current created by the electrostatic discharge is directed vertically into a semiconductor body, laterally through the semiconductor and beneath a trench isolation region so that the current flows in a direction parallel to an upper surface of the semiconductor body, and to a reference supply node. The reference supply node being formed in a conductive layer disposed over the upper surface of the semiconductor body.02-17-2011
20110038084ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - The invention discloses an electrostatic discharge protection circuit suitable for an integrated circuit system. The integrated circuit system includes a first power terminal, a second power terminal, an internal circuit and a reset signal wiring. The electrostatic discharge protection circuit includes a first transistor and a second transistor. The first transistor has a first gate, a first electrode and a second electrode. The first gate is coupled to the first power-source. The first electrode is electrically connected to the second power-source. The second transistor has a second gate, a third electrode and a fourth electrode, which are electrically connected to the second electrode, the first power-source and the reset signal wiring respectively. When the integrated circuit system is under an electrostatic discharge condition, the first and the second transistors are switched on, so as to equalize the voltage level of the reset signal wiring to the voltage level of the first power terminal.02-17-2011
20120268850OVERVOLTAGE PROTECTION ELEMENT - An overvoltage protection element includes a housing and at least two electric conductors leading into the housing for the electrical connection of the overvoltage protection element. A surge arrester for limiting an overvoltage of the electric conductors and a pressure-sensitive switch for short circuiting the electric conductors are arranged in the housing. Even with a defective surge arrester, the overvoltage protection element provided thereby reliably and safely short circuits the electric conductors when an arc occurs in the housing, so that an overvoltage protection preferably connected upstream of the overvoltage protection element, for example, a fuse, can be deployed.10-25-2012
20120268848ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - The present invention provides an electrostatic discharge (ESD) protection circuit including an ESD detection circuit and a plurality of power clamp circuits. The ESD detection circuit is electrically connected to a first high power line, a second high power line and at least one low power line, and is used to detect an ESD event occurring in the first high power line and another ESD event occurring in the second high power line. The ESD detection circuit includes a first trigger unit and a second trigger unit, electrically connected to the first high power line and the second high power line respectively. Each power clamp circuit has a trigger node, and the trigger nodes are electrically connected to the first trigger unit and the second trigger unit.10-25-2012
20110216456ESD PROTECTION DEVICE - An ESD protection device is constructed such that its ESD characteristics are easily adjusted and stabilized and degradation of discharge characteristics caused by repetitive discharges is reliably prevented. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least a pair of discharge electrodes including exposed portions arranged to face each other and to be exposed in the cavity, external electrodes provided on a surface of the insulating substrate and connected to the discharge electrodes, and a conductive material dispersed along at least a portion of an inner circumferential surface which defines the cavity between the exposed portions of the discharge electrodes, the conductive material including an anchor portion embedded in the insulating substrate09-08-2011
20120127617Electrostatic Discharge Circuit - An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD circuit includes a low voltage clamp circuit configured to discharge current during an ESD event in response to a voltage level presented thereto, and is coupled across an internal node (e.g., a floating circuit node or a voltage supply (VDD)) and ground, in parallel with an input node having a diode between the input node and each of the internal node and ground. The clamp circuit includes a silicon-controlled rectifier (SCR) including a thyristor having anode and cathode end regions separated by two base regions, the cathode being connected to the internal node and the anode being connected to ground. A diode string circuit is connected to one of the internal node and ground, and to one of the base regions, and a resistor is connected to the one of the internal node and ground that the diode string circuit is connected to, and to the one of the base regions that the diode string circuit is not connected to.05-24-2012
20120275075Electrostatic Discharge Protection Device - Semiconducting device for protecting at least one node of an integrated circuit against electrostatic discharges, comprising a doublet of floating gate thyristors connected in parallel and head-to-foot, the two thyristors having respectively two distinct gates and a common gate formed by a common semiconducting layer, the anode of a first thyristor of the doublet and the cathode of the second thyristor of the doublet forming a first terminal of the doublet designed to be connected to a cold point and the cathode of the first thyristor of the doublet and the anode of the second thyristor of the doublet forming a second terminal of the doublet designed to be connected to the said node to be protected.11-01-2012
20120275073ESD PROTECTION CIRCUIT - Electrostatic discharge (ESD) protection circuit including a first silicon controlled rectifier (SCR) and a trigger circuit; the trigger circuit including a first MOS transistor and a second transistor, triggering the first SCR and providing a second SCR shunt with the first SCR during ESD.11-01-2012
20120275072POWER MANAGEMENT CIRCUIT AND HIGH VOLTAGE DEVICE THEREIN - A high voltage device includes a high voltage transistor and a protection device. The high voltage transistor has a first end and a second end, in which the first end is coupled to a voltage input/output terminal. The protection device is coupled between the second end of the high voltage transistor and a ground terminal, and has a parasitical equivalent circuit. When the voltage input/output terminal is charged based on positive ESD charges, the current corresponding to the positive ESD charges flows from the voltage input/output terminal through the high voltage transistor and the equivalent circuit in the protection device toward the ground terminal. A power management circuit is also disclosed herein.11-01-2012
20100232078Electrostatic Discharge Protection Circuit - An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.09-16-2010
20120092799TRANSIENT CURRENT SUPPRESSION DEVICE AND METHOD - A transient current suppression device, which is applied to a fan, includes a filtering circuit, a delayed turn-on circuit and a forcibly electrical discharging circuit. The filtering circuit outputs a first voltage signal and a first current signal according to a first power signal. The delayed turn-on circuit is electrically connected with the filtering circuit. The delayed turn-on circuit provides a first discharging path for the first current signal according to a second power signal after a delayed time and outputs a second current signal. The forcibly electrical discharging circuit is electrically connected with the delayed turn-on circuit and the filtering circuit. The forcibly electrical discharging circuit provides a second discharging path for the second current signal according to the first voltage signal. Hence, the transient current suppression device can suppress the transient current effectively and rapidly.04-19-2012
20120092798Electrostatic Discharge Protection Circuit - An electrostatic discharge (ESD) protection structure comprises a high voltage P type implanted region disposed underneath an N+ region. The high voltage P type implanted region and the N+ region form a reverse diode or a Zener diode depending on different doping densities. The ESD protection structure further comprises a plurality of P+ and N+ regions. The high voltage P type implanted region and the P+ and N+ regions form a semiconductor device having a breakdown characteristic. In one embodiment, the semiconductor device may be a bipolar PNP transistor. The bipolar PNP transistor and a Zener diode in series connection form an ESD protection circuit. In another embodiment, the semiconductor device may be a Silicon-Controlled Rectifier (SCR), which is series-connected with a reverse diode. Both embodiments provide a reliable ESD protection.04-19-2012
20120287541SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.11-15-2012
20100014199ELECTROSTATIC-DISCHARGE PROTECTION USING A MICRO-ELECTROMECHANICAL-SYSTEM SWITCH - Embodiments of an interface circuit are described. This interface circuit includes an input pad, a control node and a transistor, which has three terminals. A first terminal is electrically coupled to the input pad and a second terminal is electrically coupled to the control node. Moreover, the interface circuit includes a micro-electromechanical system (MEMS) switch, which is electrically coupled to the input pad and the control node, where the MEMS switch is in parallel with the transistor. In the absence of a voltage applied to a control terminal of the MEMS switch, the MEMS switch is closed, thereby electrically coupling the input pad and the control node. Furthermore, when the voltage is applied to the control terminal of the MEMS switch, the MEMS switch is open, thereby electrically decoupling the input pad and the control node.01-21-2010
20100165522DISTRIBUTION OF ELECTROSTATIC DISCHARGE (ESD) CIRCUITRY WITHIN AN INTEGRATED CIRCUIT - Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.07-01-2010
20120140366INTEGRATED CIRCUIT - An integrated circuit including an input protection circuit cell, that comprises an input terminal coupled to a signal pin; an output terminal coupled to not only a high-frequency circuit but also the input terminal and a node; a diode provided between the node and VDD and making an electric current flow from the node to VDD; another diode provided between the node and GND and making an electric current flow from GND to the node; and a clamp circuit coupled between VDD and GND parallel to the diodes.06-07-2012
20130016445RC Triggered ESD Protection DeviceAANM Liu; Yen-LinAACI Taichung CityAACO TWAAGP Liu; Yen-Lin Taichung City TWAANM Chen; Kuo-JiAACI Wu-KuAACO TWAAGP Chen; Kuo-Ji Wu-Ku TWAANM Yang; Tzu-YiAACI TaipeiAACO TWAAGP Yang; Tzu-Yi Taipei TW - An RC triggered ESD protection device comprises a discharge transistor, a driver circuit and a trigger circuit. The trigger circuit comprises a plurality of native NMOS transistors connected in parallel with a plurality of PMOS transistors operating as resistors. The relatively small resistance of the plurality of native NMOS transistors helps to keep a stable RC time constant value so that the ESD protection device can avoid a leakage current during a power up operation.01-17-2013
20130016446CIRCUIT CONFIGURATIONS TO REDUCE SNAPBACK OF A TRANSIENT VOLTAGE SUPPRESSOR - This invention discloses a transient voltage suppressing (TVS) circuit that includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. The triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in an N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.01-17-2013
20130016447ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - An electrostatic discharge (ESD) protection device that protects a power amplifier from ESD. The ESD protection device includes a filter circuit connected to an antenna line of a wireless communication apparatus and that passes an ESD component having a predetermined frequency or less, a detection circuit that converts an output of the filter circuit into an analog DC output, a level determination circuit that detects that the analog DC output of the detection circuit is a predetermined threshold value or more, and a control interrupt circuit that controls a state of the power amplifier in accordance with an output of the level determination circuit.01-17-2013
20110157754Electrostatic discharge protection method and device for semiconductor device including an electrostatic discharge protection element providing a discharge path of a surge current - An electrostatic discharge protection device includes a first bipolar transistor having a collector terminal connected with a first power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with a second power supply terminal, a second bipolar transistor having a collector terminal connected with the second power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with the first power supply terminal, one of the first and second bipolar transistors ensuring a continuity between the collector terminal and emitter terminal under such conditions that a potential difference between the first or second power supply terminal and the input/output terminal is lower than a breakdown voltage at a PN junction between the emitter terminal and the base terminal of the other bipolar transistor.06-30-2011
20130201586Electrostatic Discharge Protection Apparatus - An electrostatic discharge (ESD)-triggered protection apparatus includes a first circuit and a second circuit. The first circuit includes an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse; a first ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to the ground rail; a control circuit that generates a control signal in response to the switching pulse. The second circuit includes at least one trigger cell buffer that is configured to receive the control signal and to control a second ESD discharge device such that the current generated by the ESD pulse is transferred to the ground rail.08-08-2013
20120243134SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit including an output pad from which an output signal is outputted, an output signal line connected with said output pad, a first pad configured to function as a ground terminal or a power supply terminal, a first wiring connected with said first pad, an output driver connected with said output pad and configured to generate said output signal, an ESD protection device connected with a output signal line and having a function to discharge surge applied to said output pad, a first trigger MOS transistor used as a trigger device, a first protection target device connected between said output signal line and a first interconnection, a first resistance element connected between a gate and a source of said first trigger MOS transistor, and a switching device.09-27-2012
20080253044Electrostatic protection circuit - An electrostatic protection circuit that affords protection without effecting transfer of an ordinary output signal includes an output terminal; a ground terminal; a first N-channel transistor having its drain and source connected between the output terminal and the ground terminal GND; a first electrostatic protection element connecting the output terminal and the ground terminal; and a second electrostatic protection element connected the drain and gate of the first N-channel transistor. The second N-channel transistor is connected to the gate of the first N-channel transistor. The gate potential of the first N-channel transistor rises and the gate-to-drain voltage of the first N-channel transistor is limited to a value below a prescribed value by a current that flows into the second electrostatic protection element owing to application of static electricity to the output terminal, and resistance of the second N-channel transistor, which is the ON state, as seen from the gate of the first N-channel transistor.10-16-2008
20080253043Active matrix device and a flat panel display with electrostatic protection - An active matrix device or a flat panel display, includes a substrate, a plurality of scan lines and data lines, a plurality of pixels, an electrostatic discharge circuit, and a first electrostatic protection circuit, in which the scan lines, the data lines and the electrostatic discharge circuit are disposed on the substrate. The data lines are across the scan lines. The electrostatic discharge circuit is also across the scan lines and the data lines. The first electrostatic protection circuit is coupled to the electrostatic discharge circuit, but is neither coupled to the scan lines nor coupled to the data lines.10-16-2008
20080239600LOW TRIGGER VOLTAGE ESD PROTECTION DEVICE - The present invention is an electrostatic discharge protection device having a low trigger voltage. The device can utilize a process of manufacturing a PCB to minimize costs and manufacturing time. The device comprises: a discharge area, which is essentially a space within the device and can be filled by a material having a desired breakdown voltage, and at least two electrode areas, wherein the two electrode areas are substantially electrically isolated from each other and simultaneously adjacent to or within the discharge area. When an electric potential difference between the electrode areas exceeds a predetermined value, a conductive path between the electrode areas will be created by discharging through the discharge area. The device is characterized in that each of the two electrodes is a part of a conductive plate, and the two conductive plates become a part of the device by pressing or adhering so that a gap for electric isolation exists between the two electrode areas.10-02-2008
20080239598Arc Flash Elimination Apparatus and Method - An arc crowbar with electrodes separated by a gap in a protective case. Each electrode is connected to an electrically different conductor of a circuit. A sensor detects an arc flash condition on the circuit and signals a trigger circuit to send an electrical pulse to an arc-triggering device in the arc crowbar gap. The triggering device ionizes a portion of the gas between the electrodes, initiating a protective arc between the electrodes that absorbs energy from the power circuit and trips a breaker, eliminating the arc flash condition. The triggering device may be a plasma gun, especially one that injects plasma of an ablated material into the gap. The sensor may signal a circuit breaker to open in the power circuit. Arc flash sensor types may include a differential current sensor and/or an optical sensor.10-02-2008
20080239597Peak Voltage Protection Circuit and Method - A peak voltage protection circuit for protecting an associated High Voltage NPN transistor (T10-02-2008
20130170080ESD PROTECTION CIRCUIT CELL - A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd07-04-2013
20080232013High-Voltage Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Interface - A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.09-25-2008
20080232011APPARATUS AND METHODS FOR INTEGRATED CIRCUIT WITH DEVICES WITH BODY CONTACT AND DEVICES WITH ELECTROSTATIC DISCHARGE PROTECTION - An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.09-25-2008
20080232010ESD PROTECTION CIRCUIT AND METHOD THEREOF - An electrostatic discharge (ESD) protection circuit and method thereof is provided. The ESD protection circuit includes two clamping circuits, an inductor, a diode and a diode string. In addition to a voltage swing of an output voltage able to get rid of the influence of the ESD protection circuit, the invention reduces an ESD conduction path length and dissipates an ESD current swiftly by installing at least two clamping circuits, which significantly increases the effectiveness of the protection for large-signal circuits.09-25-2008
20080232009Semiconductor device having an ESD protection circuit - When a manufacturing process becomes finer and a threshold value drops, a leakage current generates in a MOS transistor that is normally in an off-state. In order to suppress an influence of a leakage current that is generated in a protection transistor that constitutes a protection circuit on the internal circuit, an adjustor circuit that forms a transit path of the leakage current is disposed within the protection circuit, and a monitor circuit having the same circuit configuration as a configuration of the protection circuit is disposed to control an impedance of the transit path in the protection circuit and the monitor circuit so as to allow the leakage current to flow through the transit path.09-25-2008
20080232008Electrostatic discharge safe under conveyor antenna - An antenna for use in a conveyor system in which items on which radio frequency identification tags are disposed are moved on a conveyor along a path of travel, includes a ground plane, a substrate having a bottom surface received adjacent the ground plane, at least one patch element disposed on a top surface of the substrate, a cover received adjacent the top surface of the substrate, and a front static conductive strip disposed along a front edge of the cover. The antenna is disposed beneath the conveyor and a front edge of the antenna is transverse to the path of travel. The front static conductive strip is electrically connected to the ground plane such that an electrostatic discharge event adjacent the front static conductive strip is discharged to the ground plane.09-25-2008
20100085672ESD-PROTECTION DEVICE, A SEMICONDUCTOR DEVICE AND INTEGRATED SYSTEM IN A PACKAGE COMPRISING SUCH A DEVICE - The invention relates to an ESD protection device comprising: a first contact (04-08-2010
20080225451CASCODE ACTIVE SHUNT GATE OXIDE PROTECT DURING ELECTROSTATIC DISCHARGE EVENT - A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a gate clamp circuit.09-18-2008
20080225450Semiconductor integrated circuit - A semiconductor integrated circuit having an ESD protection circuit enhancing a durability against thermal destruction is provided. The semiconductor integrated circuit configured by a plurality of MOSFETs each having an SOI structure formed on a silicon substrate includes a functional circuit having an external connection signal terminal, a pair of power terminals and at least one of the MOSFETs. The semiconductor integrated circuit also includes at least one ESD protection circuit having a first terminal and a second terminal connected to the signal terminal and the power terminals, respectively. The ESD protection circuit includes at least one first MOSFET of the MOSFETs formed on the silicon substrate. The first MOSFET has a drain connected to the first terminal, a gate connected to the second terminal, and a source connected to the second terminal. The at least one ESD protection circuit also includes at least one second MOSFET of the MOSFETs formed adjacent to the first MOSFET on the silicon substrate. The second MOSFET has a gate connected to the first terminal and the same conductivity type as the first MOSFET.09-18-2008
20080225449ELECTROSTATIC DISCHARGE PROTECTION COMPONENT, AND ELECTRONIC COMPONENT MODULE USING THE SAME - An electrostatic discharge protection component comprising a ceramic sintered body having ceramic substrate 09-18-2008
20130176651DIAGNOSABLE REVERSE-VOLTAGE PROTECTION FOR HIGH POWER LOADS - Systems and methods of diagnosing a condition of a reverse-voltage protection switch in an electric system. The electric system includes a power source, an electric load, and a reverse-voltage protection switch in a series-type configuration. The electric system further includes a ground switch configured to selectively connect the source terminal of the reverse-voltage protection circuit to ground. The terminals of the reverse-voltage protection circuit are disconnected from the power source. The ground switch is closed to connect one terminal of the reverse-voltage protection switch to ground. A bias voltage is applied to the other terminal of the reverse-voltage protection switch and the reverse-voltage protection switch is opened. An improper short-circuit condition across the reverse-voltage protection switch is detected when the voltage at the biased terminal of the reverse-voltage protection switch is less than a threshold when the reverse-voltage protection switch is opened.07-11-2013
20130170082INTEGRATED CIRCUIT HAVING A CHARGED-DEVICE MODEL ELECTROSTATIC DISCHARGE PROTECTION MECHANISM - An integrated circuit having charged-device model (CDM) electrostatic discharge (ESD) protection includes an I/O circuit, at least one CDM ESD protection device, and at least one internal circuit. The integrated circuit further includes at least one TSV (Through Silicon Via) each being coupled between a ground of at least one ground of the input/output circuit and one of the at least one ESD protection device, wherein each of the at least one ESD protection device is coupled between one of the at least one TSV and a ground of one of the at least one internal circuit.07-04-2013
20080218919PROTECTION OF INTEGRATED ELECTRONIC CIRCUITS FROM ELECTROSTATIC DISCHARGE - Circuit nodes are identified which, in unpowered mode, can be charged with positive or negative charges but cannot be discharged. Then protective elements are added to allow the discharge of these nodes. These elements do not affect the operation of the circuit in powered mode. Discharges of the two polarities are handled, positive and negative. The circuit is thus more resistant to ESD and passes CDM tests.09-11-2008
20120250196ESD PROTECTION DEVICE AND MANUFACTURING METHOD THEREFOR - An ESD protection device includes a ceramic base material including a glass component, a first opposed electrode on one side of the ceramic base material and a second opposed electrode on the other side of the ceramic base material, which are arranged so as to include ends that are opposed to each other on the surface of the ceramic base material, and a discharge auxiliary electrode disposed between the first and second opposed electrodes, which is connected to each of the first and second opposed electrodes, and arranged so as to provide a bridge from the first opposed electrode to the second opposed electrode, and a sealing layer to prevent the ingress of the glass component from the ceramic base material into the discharge auxiliary electrode is provided between the discharge auxiliary electrode and the ceramic base material.10-04-2012
20120250194High voltage tolerant SCR clamp with avalanche diod triggering circuit - In an LVTSCR, an avalanche diode based control circuit controls both the base of the internal PNP of the LVTSCR as well as the gate of the LVTSCR.10-04-2012
20130094113INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION - A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.04-18-2013
20130114174ELECTROSTATIC DISCHARGE PROTECTION FOR ELECTRICAL COMPONENTS, DEVICES INCLUDING SUCH PROTECTION AND METHODS FOR MAKING THE SAME - Systems and methods for protecting electrical components such as light emitting diodes are described. In some embodiments, electrical components are protected from high level electrostatic discharge (“ESD”) events by a circuit board that provides an intrinsic level of ESD protection. At the same time, such electrical components are protected against low level ESD events by one or more diodes that are electrically coupled thereto. The one or more diodes may be thin film diodes comprising at least one layer of p-type semiconductive material and at least one layer of n-type semiconductive material. Devices including ESD protection and methods for manufacturing such devices are also described.05-09-2013
20130114173ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region.05-09-2013
20130114171Apparatus for Electrostatic Discharge Protection and Noise Suppression in Circuits - An integrated circuit assembly is provided that includes an integrated circuit (IC) package substrate including a package ground rail that is divided into a plurality of segments that are electrically isolated from each other. An IC die is disposed on the IC package substrate, the IC die including a plurality of circuit blocks and an IC ground rail. The IC ground rail is divided into a plurality of segments, where each segment of the IC ground rail is coupled to another segment of the IC ground rail by one or more diodes. The plurality of circuit blocks have corresponding ground nodes electrically connected to corresponding segments of the IC ground rail. The segments of the IC ground rail are electrically coupled to corresponding segments of the package ground rail by corresponding first connections.05-09-2013
20130114170ELECTROSTATIC DISCHARGE PROTECTION APPARATUS - An electrostatic discharge protection apparatus protects an integrated circuit including a first pad and a first internal circuit operating at a power voltage. The electrostatic discharge protection apparatus includes a first protection unit and a control unit. The first protection unit includes a first P-type diode, a first silicon controlled rectifier (SCR), a first resistor and a first buffer. The first P-type diode is electrically connected between a first power line and the first pad. The SCR is electrically connected between the first pad and a first ground line. The first buffer includes an input end electrically connected to the first pad through the first resistor and an output end electrically connected to an input end of the first internal circuit. The control unit generates an isolation signal according to the power voltage to turn off the first SCR.05-09-2013
20130114169CMOS ADJUSTABLE OVER VOLTAGE ESD AND SURGE PROTECTION FOR LED APPLICATION - Various embodiments relate to a light emitting diode protection circuit, including: a plurality of diodes connected in series; an input connected to a first diode of the plurality of diodes; an output; a first resistor connected between the plurality of diodes and the output; a transistor with a gate connected to a junction between the first resistor and the plurality of diodes and a source connected to the output; a second resistor connected between the input and drain of the transistor; and a silicon controlled rectifier (SCR) with an anode connected to the input, a base connected to the drain of the transistor, and a cathode connected to the output.05-09-2013
20130114168SURGE PROTECTION - A victim unit (310, 410) connectable to a surge protective device (300, 40005-09-2013
20130208379ELECTROSTATIC DISCHARGE PROTECTION APPARATUS - A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.08-15-2013
20130208380TRANSIENT CONTROL TECHNOLOGY CIRCUIT - An active surge suppression or protection circuit for protecting hardware or equipment from electrical surges. During operation when no surge condition is present, the circuit passes signals from an input source to a connected load along a signal path. When a surge is present, the circuit automatically senses and diverts the surge away from the signal path. A switching component is provided along the signal path for either allowing transmission or preventing transmission of a signal along the signal path. Upon diverting the surge, the circuit automatically changes the switching component from a closed state (for allowing transmission) to an open state (for preventing transmission). After the surge has passed, the circuit automatically changes the switching component from the open state to the closed state. Other automatic circuit behaviors may also be achieved in response to the diversion of a surge condition from the signal path.08-15-2013
20130100561SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME FOR ESD PROTECTION - In an embodiment a circuit provides protection against electrostatic discharge (ESD). A shunt device is controlled to provide a current bypass upon the occurrence of an ESD event. A trigger circuit controls operation of the shunt device and includes an inverter and a hysteresis means to prevent oscillation of the trigger circuit. A reference is used to trigger the control circuit and has a time constant associated with it to distinguish between power up events and ESD events.04-25-2013
20130100562ELECTROSTATIC DISCHARGE CLAMP WITH CONTROLLED HYSTERESIS INCLUDING SELECTABLE TURN ON AND TURN OFF THRESHOLD VOLTAGES - An electrostatic discharge (ESD) clamp for coupling between first and second nodes for providing ESD protection including first and second voltage threshold circuits. The clamp circuit limits operating voltage between the first and second nodes to a maximum level when activated. The first and second voltage threshold circuits each have a selectable threshold voltage, such as by coupling one or more voltage threshold devices in series. The first and second voltage threshold circuits trigger to turn on the clamp circuit when the operating voltage increases above a first voltage threshold. The voltage threshold circuits are turned off to turn off the clamp circuit when the operating voltage decreases to the second threshold voltage. The second threshold voltage may be selected at any level above the nominal operating voltage to prevent the clamp from latching.04-25-2013
20130114172ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.05-09-2013
20130120886DRIVING CIRCUITS WITH POWER MOS BREAKDOWN PROTECTION AND DRIVING METHODS THEREOF - A driving circuit is provided. The driving circuit is capable of driving a load coupled to an output node of the driving circuit. The driving circuit includes an output-stage element, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a first P-type metal-oxide-semiconductor (PMOS) transistor. The output-stage element is coupled between an operation voltage source and the output node. The first NMOS transistor has a gate, a drain coupled to the output node, and a source coupled to a ground. The first PMOS transistor has a gate, a drain coupled to the ground, and a source coupled to the output node. When the first NMOS transistor begins to be turned off, the first PMOS transistor is turned on, and a voltage at the drain of the first NMOS transistor is clamped to be lower than a breakdown trigger voltage of the first NMOS transistor.05-16-2013
20130120885LOW NOISE ESD PROTECTION FOR SOCs WITH ANALOG OR RADIO FREQUENCY DEVICES - Systems and methods are disclosed to reduce pin count in an integrated circuit with digital and analog circuits on-chip by receiving power (VDD) input at a digital power input pad that provides electrostatic discharge (ESD) protection but substantially no current for on-chip analog circuits; filtering noise from the digital power input pad with a filter; and coupling a low noise analog power input pad internal to the integrated circuit to the filter and an analog circuit or a low noise singled ended radio frequency circuit without requiring an external analog power pin.05-16-2013
20130120884INPUT/OUTPUT CIRCUIT WITH INDUCTOR - An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.05-16-2013
20110267725PROTECTION APPARATUS AGAINST ELECTROSTATIC DISCHARGES FOR AN INTEGRATED CIRCUIT AND RELATED INTEGRATED CIRCUIT - There is described a protection apparatus against electrostatic discharges for an integrated circuit; said integrated circuit comprises a radiofrequency or higher frequencies internal circuit. The internal circuit has a first and a second terminals for the output or the input of a radiofrequency or higher frequencies signal. The apparatus comprises first means for electrically connecting said first and second terminals of the internal circuit to at least a PAD and the integrated circuit comprises at least a first and a second supply circuital lines and at least a first and a second protection devices against electrostatic discharges connected to said first and second supply lines. First means have a resistive component and each of said first and second protection devices against the electrostatic discharges have a parasitic capacitive component. The apparatus comprises second means configured to connect said first means and said first and second protection devices against the electrostatic discharges to at least a common circuital point preventing the resistive component of said first means or said internal circuit from combining with the parasitic capacitive components of said first and second protection devices against the electrostatic discharges.11-03-2011
20130128401NETWORK COMMUNICATION DEVICE AND PRINTED CIRCUIT BOARD WITH TRANSIENT ENERGY PROTECTION THEREOF - A network communication device and printed circuit board are provided with transient energy protection. The network communication device includes a transceiver, a transformer, a connector, a spark gap, and a transient energy trigger circuit. The transformer is coupled between the transceiver and the connector. The spark gap and the transient energy trigger circuit are coupled in parallel, between the transformer and a ground end. Alternatively, the spark gap and the transient energy trigger circuit are coupled in parallel, between any two of differential signal lines of the transformer. The spark gap and the transient energy trigger circuit provide a multi-path structure for conducting away the transient energy. A first transient energy is conducted to the ground end through the transient energy trigger circuit, while a second transient energy is conducted to the ground end through the spark gap.05-23-2013
20130128400ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND METHOD THEREFOR - An electrostatic discharge (ESD) protection apparatus includes a clamp circuit, a detection circuit and a control circuit. The clamp circuit has a first terminal and a second terminal respectively coupled to a first rail line and a second rail line. In response to an ESD event, the clamp circuit generates a first coupling potential at its coupling terminal. The detection circuit, coupled to the coupling terminal of the clamp circuit and the second rail line, outputs a detection signal in response to the first coupling potential. The control circuit, coupled to the first and second rail lines, the detection circuit and the clamp circuit, outputs a conduction signal to a control terminal of the clamp circuit in response to the detection signal. The clamp circuit is conducted in response to the conduction signal so that ESD between the first and second rail lines is performed through the clamp circuit.05-23-2013
20130128398SERIAL SURGE SUPPRESSION AND OVERLOAD PROTECTION OPTIMIZATION DEVICE - A serial surge suppression and overload protection optimization device has an input terminal, an output terminal and multiple surge suppression units. The surge suppression units are serially connected between the input terminal and the output terminal. Each surge suppression unit has two parallel inductors and multiple surge absorbing elements. Each surge absorbing element is connected to an output end of one of the parallel inductors and has a fuse serially connected therewith. When surge energy is excessively large, the fuse melts to separate the surge absorbing element from a main power loop without causing a short circuit within the main power loop due to the meltdown of the fuse. The optimization device is used with an automatic overload protection unit to normally supply power to equipment connected to the output terminal thereof and ensure electrical safety protection with a bypass circuit design thereof.05-23-2013
20130128399APPARATUSES, CIRCUITS, AND METHODS FOR PROTECTION CIRCUITS FOR DUAL-DIRECTION NODES - Apparatuses, circuits, and methods are disclosed for biased protection circuits for dual-direction nodes. In one such example apparatus, a protection circuit is coupled to a dual-direction node, and includes a positive protection component and a negative protection component. The protection circuit is configured to protect the dual-direction node during an over-limit electrical condition. The protection circuit is configured to control a turn-on condition of the protection circuit.05-23-2013
20130135777SURGE PROTECTION CIRCUIT - A surge protection circuit includes a surge protection unit and an interface electrically connected to each other. The surge protection unit includes an internal connection terminal block, three varistors and one discharge tube. The three varistors are electrically connected to the internal connection terminal block, where two varistors are electrically connected to the discharge tube. The discharge tube is also electrically connected to the internal connection terminal block and is grounded. The surge protection circuit can avoid connecting a varistor to the discharge tube in series and reduce a residual voltage of the surge protection circuit.05-30-2013
20130141825ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit includes first and second transistors connected in series between first and second power supply nodes. A third transistor of the ESD protection circuit turns the second transistor to OFF during normal operation. A fourth transistor of the ESD protection circuit turns the first transistor ON during ESD operation. During normal operation, a damping time constant circuit of the ESD protection circuit turns the fourth transistor OFF, and during ESD operation, turns the fourth transistor ON. A fifth transistor of the ESD protection circuit turns the second transistor ON during ESD operation. The first to fifth transistors each have a voltage resistance level that is lower than power supply voltage.06-06-2013
20130141826ESD PROTECTION DEVICE - The present invention provides an ESD protection device that not only has small electrostatic capacitance and an excellent discharge property but also has high durability against repeated use with the occurrence of short-circuiting between electrodes after discharge inhibited. An ESD protection device including an insulating substrate, electrodes arranged on this insulating substrate away from and opposite each other, and a discharge induction section located between these electrodes, wherein the discharge induction section is composed of a porous body, in which micropores are discontinuously scattered, and has a hollow structure having at least one or more hollow sections.06-06-2013
20130141824Electronic Device, in Particular for Protection Against Electrostatic Discharges, and Method for Protecting a Component Against Electrostatic Discharges - The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC06-06-2013
20080198520ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOWERED DRIVING VOLTAGE - The electrostatic discharge protection circuit coupled to an input/output pad includes a trigger unit providing a trigger voltage and an inverse trigger voltage having an inverse phase with respect to the trigger voltage. The trigger voltage and the inverse trigger voltage is provided in response to static electricity transferred from at least one of a first voltage line and a second voltage line. An electrostatic discharge protection unit configures an electrostatic discharge path among the first line, the second line, and an input/output pad in response to the trigger voltage and the inverse trigger voltage. In the electrostatic discharge protection circuit, the driving voltage of the electrostatic discharge protection unit is lowered, allowing static electricity to be effectively discharged.08-21-2008
20080198518DEVICE TO PROTECT A SEMICONDUCTOR DEVICE FROM ELECTROSTATIC DISCHARGE BY EFFICIENTLY DISCHARGING A MICRO CURRENT - A device to protect a semiconductor device from electrostatic discharge is disclosed. In order to protect an internal circuit from electrostatic discharge, the semiconductor electrostatic protection device includes a transfer unit for transferring static electricity inputted to an input/output terminal to a first power line. A driving unit is also included for outputting a driving voltage corresponding to a potential difference between the input/output terminal and the first power line. Finally, a discharge unit for discharging the static electricity inputted to the input/output terminal to a second power line by way of the driving voltage is provided. The semiconductor electrostatic protection device prevents damage to an internal circuit due to the voltage drop of an intermediate medium by reducing the intermediate medium on a static electricity discharge path.08-21-2008
20080198516Electrostatic discharge (ESD) protection device and method therefor - A method and device for providing electrostatic discharge (ESD) protection are disclosed. The method uses the gate-controlled conductivity of field n-channel metal-oxide-semiconductor field effect transistor (field NMOSFET), wherein considerable ESD current can be conducted away when any ESD event beyond range of operation voltage, unlike PMOS ESD protection which is to be turned on at negative voltage. Instead of the traditional two-stage ESD protection (using one ESD protection between open drain output and V08-21-2008
20110242713PLANAR VOLTAGE PROTECTION ASSEMBLY - A voltage protection assembly includes a planar substrate, an input terminal, a capacitive element, an inductive element, and an output terminal. The substrate includes conductive traces with the input terminal conductively coupled with at least one of the traces. The capacitive element is electrically coupled with the input terminal. The inductive element is conductively coupled with the capacitive element. The output terminal is disposed on the substrate and is conductively coupled with the inductive element. The output terminal, the inductive element, the capacitive element, and the input terminal are connected in series to form a voltage protection circuit that filters one or more frequencies of a data signal transmitted through the voltage protection circuit. At least one of the capacitive element or the inductive element is entirely disposed within the thickness dimension of the substrate.10-06-2011
20110235223CIRCUIT PROTECTION SYSTEM - A circuit protection system, which is coupled to an input end of an integrated circuit receiving an input signal from a signal source, includes an electrostatic discharge protection element and a leakage current protection circuit. The leakage current protection circuit includes a first filter capacitor coupled to the electrostatic discharge protection element, wherein when the input signal includes leakage current with an ac component, the first filter capacitor behaves as a high impedance unit for preventing the leakage current from passing through the electrostatic discharge protection component, and when the input signal includes static electricity, the first filter capacitor behaves as a low impedance unit for allowing the input signal to pass through the electrostatic discharge protection element.09-29-2011
20130148243ESD PROTECTING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An electrostatic discharge protecting circuit includes a trigger circuit and a protecting transistor. The trigger circuit includes a capacitive element and a resistive element and connected between two power source lines. The protecting transistor is connected in parallel with the trigger circuit and has a control electrode connected to an output terminal of the trigger circuit. The trigger circuit has an MIS capacitor as the capacitive element, and the resistive element is composed of an upper electrode of the MIS capacitor. In addition, a semiconductor device has the above-described electrostatic discharge protecting circuit protecting an internal circuit connected between two power source lines.06-13-2013
20130148244ESD PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity06-13-2013
20100290166Electronic Device with High ESD Protection - An electronic device with high electrostatic discharge (ESD) protection is provided. The electronic device includes a touch panel, at least one ESD protection element and a liquid crystal module. When an ESD event occurs at the surrounding of the touch panel, the ESD energy is rapidly discharged to ground via an energy transmission path inside the touch panel. The ESD protection element is connected to the output terminal of the touch panel in parallel to protect the electronic device and its internal circuits.11-18-2010
20100296211COMPACT APPARATUS - An apparatus comprising: a first component that is electrically conductive but electrically isolated; a ground point; and an intermediate component positioned adjacent the first component and adjacent the ground point comprising an electrically conductive portion for electrically connecting the first component and the ground point.11-25-2010
20120275074ESD PROTECTION DEVICE - An electrostatic discharge (ESD) protection device for protecting an I/O port of an electronic circuit from overvoltage and a coil structure for use in an ESD protection device. The ESD protection device includes: a plurality of inductors that are serially coupled in a line, where a node is formed between two neighboring inductors; and a plurality of protection arrangements adapted to conduct charges to one provided potential when an overvoltage is applied, where each of the protection arrangements is connected with one of the nodes, and where the serially coupled inductors are magnetically coupled with each other.11-01-2012
20100309594INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a first power supply domain and a second power supply domain, wherein the first power supply domain includes a first power supply line and a second power supply line, an internal circuit between the first power supply line and the second power supply line, a first clamp circuit that electrically couples between the first power supply line and the second power supply line when a certain potential difference is generated between the first power supply line and the second power supply line, and at least one of a junction element that is between the first clamp circuit and the first power supply line and a junction element that is between the first clamp circuit and the second power supply line, the junction element allowing current to flow when the first clamp circuit becomes electrically conductive.12-09-2010
20130182358DESTRUCTIVE ELECTROSTATIC DISCHARGE DAMAGE PREVENTION OF GARMENTS - A method and system for the prevention of Destructive Electrostatic Discharge (DED) damage to outer garments caused by triboelectric charge discharging to the wearer's body through a distinct point of discharge at a conductor in contact with or close proximity to the wearer's skin. The method consists of interposing an insulating layer of high dielectric strength at the conductor such that the conductor is insulated from either the skin of the wearer or the outer garment and the circuit of triboelectric charge through the conductor is broken. The system includes a conductor and an insulating layer positioned between the outer garment and the skin of the wearer on either side of the conductor.07-18-2013
20100315748ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs - An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.12-16-2010
20120281324SEMICONDUCTOR DEVICE - A semiconductor device has: a power supply line; a ground line; a signal line for transmitting a signal; a signal pad connected to the signal line; a protection element connected between the signal line and the ground line; and a trigger circuit configured to supply a trigger current to the protection element. The trigger circuit has: a PMOS transistor whose gate and backgate are connected to the power supply line and whose source is connected to the protection element; and an amplifier circuit part configured to amplify a first current flowing through the PMOS transistor to generate a second current. The trigger current includes the second current.11-08-2012
20120281323INTEGRATED CIRCUIT PASSIVE SIGNAL DISTRIBUTION - For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.11-08-2012
20120281322Electrostatic Discharge Protection - A circuit for protecting a node (11-08-2012
20130155554ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a clamp unit and a control circuit. The clamp unit provides a discharging path from a first power line to a first ground line. The control circuit receives a first power voltage from the first power line and a second power voltage from a second power line. Wherein, when the first power voltage and the second power voltage are applied, the control circuit generates an isolation signal to disconnect the discharging path. When the first power voltage and the second power voltage are not applied, the control circuit generates a trigger signal according to an electrostatic signal from the first power line to turn on the discharging path.06-20-2013
20130155555INTEGRATED CIRCUIT AND METHOD OF PROVIDING ELECTROSTATIC DISCHARGE PROTECTION WITHIN SUCH AN INTEGRATED CIRCUIT - An integrated circuit with electrostatic discharge (ESD) protection, and a method of providing such ESD protection within the integrated circuit, are disclosed. The integrated circuit comprises functional circuitry having functional components for performing processing functions required by the integrated circuit, and interface circuitry for providing an interface between the functional circuitry and components external to the integrated circuit. The integrated circuit is formed of a plurality of layers, including component level layers within which any of the functional components formed from a standard cell are constructed, power grid layers providing a power distribution infrastructure for the functional components, and intervening layers between the power grid layers and the component level layers providing interconnections between the functional components. The functional circuitry further comprises at least one ESD protection circuit constructed so as to reside solely within the component level layers in order to provide ESD protection for an associated one or more of the functional components. Such an approach enables the required ESD protection to be provided locally within the functional circuitry, whilst retaining flexibility with regard to the placement of, and routing between, the various functional components of the functional circuitry.06-20-2013
20130155556ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHOD FOR RADIO FREQUENCY SEMICONDUCTOR DEVICE - An ESD protection circuit for an RF semiconductor device includes an RF input pad configured to receive an RF input signal having an RF operating frequency for the RF semiconductor device. A first ESD block is coupled between an intermediate node and the first power supply voltage terminal, to direct an ESD pulse of a first polarity toward the first power supply voltage terminal. A second ESD block is coupled between the intermediate node and the second power supply voltage terminal, to direct an ESD pulse of a second, opposite polarity toward the second power supply voltage terminal. A resonance circuit is coupled between the RF input pad and the intermediate node. The resonance circuit is configured to present a greater impedance to the RF input signal having the RF operating frequency than to the ESD pulses.06-20-2013
20130155558COMPACT ELECTRONIC DEVICE FOR PROTECTING FROM ELECTROSTATIC DISCHARGE - A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.06-20-2013
20130155557SEQUENTIAL ELECTROSTATIC DISCHARGE (ESD)-PROTECTION EMPLOYING CASCODE NMOS TRIGGERED STRUCTURE - An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.06-20-2013
20130182357Electrostatic Discharge Protection Circuit Having Buffer Stage FET with Thicker Gate Oxide than Common-Source FET - An active-FET ESD cell (07-18-2013
20130182356ESD Clamp with Novel RC Triggered Circuit - Some embodiments relate to an area efficient electrostatic discharge (ESD) clamp comprising an RC trigger circuit, having one or more low-voltage, thin-oxide devices, which is configured to operate with a high-voltage power supply. In some embodiments, the ESD clamp comprises an RC trigger circuit connected between a first circuit node having a first voltage and a second circuit node having a second voltage. The RC trigger circuit comprises a resistive element connected in series with a thin-oxide MOS capacitor. The MOS capacitor has a source and drain connected to an intermediate supply voltage between the first and second voltage, and a body connected to the second voltage. By connecting the source and drain to the intermediate supply voltage, the thin-oxide MOS capacitor is able to reliably operate with a high-voltage power supply.07-18-2013
20110292553INTEGRATED CIRCUIT DEVICE AND ELECTROSTATIC DISCHARGE PROTECTING CIRCUIT THEREOF - Integrated circuit devices and electrostatic discharge (ESD) protection circuits thereof. An integrated circuit device may include an input/output pad, an internal circuit, and a transistor connected between the input/output pad and the internal circuit configured to perform a switch operation between the input/output pad and the internal circuit in response to a control signal transmitted from the internal circuit, and operate as an ESD protection circuit.12-01-2011
20110310517OVERVOLTAGE PROTECTION MAGAZINE OR PLUG AND METHOD FOR PRODUCING AN OVERVOLTAGE PROTECTION MAGAZINE OR PLUG - The invention relates to an overvoltage protection magazine (12-22-2011
20110310516ESD PROTECTION IN A STANDARD CMOS OR BICMOS IC PROCESS TO ENABLE HIGH VOLTAGE INPUT/OUTPUTS - The application relates to a method of ESD protecting high-voltage inputs of an integrated circuit fabricated in a standard CMOS IC process, the high-voltage inputs being expected to experience nominal voltage swings that are larger than the nominal maximum voltage swing of the standard CMOS IC process. The application further relates to an IC and to an article of manufacture comprising the IC and an antenna. The object of the present application is to provide an integrated circuit in a standard CMOS process that supports larger than nominal input/output swings. The problem is solved by a) providing an ESD-diode comprising an anode and a cathode and having a forward bias voltage V12-22-2011
20110310515SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING INTERNAL CIRCUITS AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS - The disclosed invention reduces an increase in the number of electrostatic discharge protection circuits or the number of electrostatic discharge protection elements due to increases in the number of separations of power voltages and the number of separations of ground voltages. A semiconductor integrated circuit includes first, second, and third operation voltage supply terminals; first, second, and third internal circuits; first, second, and third electrostatic discharge protection circuits; and a coupling midpoint. The first, second, and third internal circuits operate at first, second, and third operation voltages supplied to the first, second, and third operation voltage supply terminals, respectively. The first, second, and third electrostatic discharge protection circuits are coupled between the first, second, and third operation voltage supply terminals and the coupling midpoint, respectively. That is, instead of the past Δ (delta) coupling, the first, second, and third electrostatic discharge protection circuits are Y (star)-coupled with respect to the coupling midpoint.12-22-2011
20110310514Electrostatic discharge protection circuit - An electrostatic discharge (ESD) protection circuit is coupled between a first terminal and a second terminal of an integrated circuit. The integrated circuit receives an input signal through the first terminal. The second terminal is coupled to a voltage source. The ESD protection circuit includes a PMOS transistor and a deep N-well NMOS transistor. When the static electricity is inputted to the first terminal, the static electricity flows to the voltage source through the corresponding parasitic diode and the corresponding parasitic bipolar transistor of the PMOS transistor and the deep N-well NMOS transistor. In addition, the input signal is not affected by the ESD protection circuit because the parasitic diodes of the PMOS transistor and the deep N-well NMOS transistor are reversely connected. Thus, the ESD protection circuit prevents the integrated circuit from being damaged by the static electricity and increases the operation voltage range of the input signal.12-22-2011
20130188286Low-Impedance High-Swing Power Supply with Integrated High Positive and Negative DC Voltage Protection and Electro-Static Discharge (ESD) Protection - An apparatus comprises a first PFET including a first intrinsic body diode; an electrostatic discharge (ESD) subcircuit coupled to a source of the first PFET; a reverse bias voltage element, such as a zener diode, an anode of which is coupled to a gate of the first PFET; a second PFET having a source coupled to a cathode of the zener diode a capacitor coupled to a gate the second PFET; and a first resistor coupled to the gate of the second PFET. The apparatus can protect against both positive and negative electro static transient discharge events.07-25-2013
20130188287PROTECTION CIRCUIT, CHARGE CONTROL CIRCUIT, AND REVERSE CURRENT PREVENTION METHOD EMPLOYING CHARGE CONTROL CIRCUIT - A protection circuit to protect from a reverse current, including a current limitation element to connect between an external reference terminal and an internal reference potential to limit the amount of current flowing from the external reference terminal to a power source terminal, when a reversed polarity voltage is applied at the power source terminal; and a conducting element to connect between the power source terminal and the internal reference potential to adjust the internal reference potential to the voltage at the power source terminal, when the reversed polarity voltage is applied.07-25-2013
20130188288ELECTROSTATIC DISCHARGE PROTECTION - A device comprising an electrostatic discharge protection structure (07-25-2013
20120002333ESD Clamp Adjustment - Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.01-05-2012
20120019969SEMICONDUCTOR INTEGRATED CIRCUIT - In combining an analog terminal of an A/D converter with a digital terminal, the effect of the noise from the digital terminal is reduced. A semiconductor integrated circuit includes a high-speed external terminal, a low-speed external terminal, a high-speed analog switch, a low-speed analog switch, and an A/D converter. The high-speed external terminal is coupled to an input of the A/D converter via the high-speed analog switch, and the low-speed external terminal is coupled to the input of the A/D converter via the low-speed analog switch. A plurality of inputs of a plurality of low-speed digital input buffer circuits and a plurality of outputs of a plurality of low-speed digital output buffer circuits are coupled to a plurality of low-speed external terminals. The output of any digital output buffer circuit is not coupled to a plurality of high-speed external terminals, but a plurality of inputs of a plurality of high-speed digital input buffer circuits is coupled to a plurality of high-speed external terminals. Between a plurality of low-speed external terminals and the input of the A/D converter, a low-speed separating resistor with a high resistance value is coupled, respectively.01-26-2012
20120019968TRANSMISSION-LINE-BASED ESD PROTECTION - An ESD protection circuit includes a signal pad, a short circuited shunt stub on-chip with and coupled to the signal pad, an open circuited shunt stub on-chip and coupled to the signal pad.01-26-2012
20120019967ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR ELECTRONIC DEVICES USING WIRE-BONDING - A system in one embodiment includes a cable having a plurality of cable leads, and a multi-diode chip having a pad-side not facing the cable. The multi-diode chip includes a plurality of sets of contact pads on the pad-side of the multi-diode chip, and a plurality of crossed diode sets, wherein each set of crossed diodes is coupled between a first contact pad and a second contact pad of one set of contact pads, wherein at least two of the plurality of cable leads are coupled via wire-bonding to one of the plurality of sets of contact pads of the multi-diode chip for providing electrostatic discharge (ESD) protection for at least one element of the electronic device coupled to the at least two cable leads.01-26-2012
20130194708Current Carrying Structures Having Enhanced Electrostatic Discharge Protection And Methods Of Manufacture - A method is provided for forming a current carrying structure with improved electrostatic discharge protection. The current carrying structure includes a conductive material layer and a voltage switchable dielectric layer adapted to switch between insulative and conductive at a predetermined voltage between the ground plane and the conductive material. An aperture is formed through the voltage switchable dielectric layer, and conductive material is deposited in the aperture to form a conductive pathway between the voltage switchable dielectric layer and another layer. A spark gap is created between the conductive material of the aperture and a ground portion using a laser to remove a portion of the conductive material layer from an area surrounding the aperture without substantially modifying physical properties of the underlying switchable dielectric layer.08-01-2013
20130201583ELECTRONIC DEVICE AND METHOD FOR PROTECTING AGAINST DAMAGE BY ELECTROSTATIC DISCHARGE - An electronic device with a protective circuit against damage by electrostatic discharge includes a discharge current path connectable between an input to be protected and a ground pin. An enabling circuit outputs a control signal for connecting the discharge current path in the event of an electrostatic discharge. A deactivating circuit which deactivates the enabling circuit during operation of the electronic device is controlled by the inverted control signal. A method of protecting an electronic device against damage by electrostatic discharge includes providing a control signal for connecting a discharge current path between an input to be protected and a ground pin in the event of an electrostatic discharge. An inverted control signal is applied to the inverted control signal to a deactivating circuit. The inverted control signal prevents connection of the discharge current path between the input to be protected and ground during operation of the electronic device.08-08-2013
20130201584ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device including a modified lateral silicon-controlled rectifier (MLSCR) and a voltage control circuit is provided. The MLSCR has a first terminal, a second terminal and a control terminal connected to a first P+-type doped region, where the first terminal and the second terminal are electrically connected to a first line and a second line, respectively. The voltage control circuit is electrically connected to the first line, the second line and the control terminal. When an electrostatic pulse is appeared on the first line, the voltage control circuit provides a current path from the first line to the control terminal. When an input signal is supplied to the first line, the voltage control circuit receives a power voltage, and stops providing the current path according to the power voltage.08-08-2013
20130201585METHOD FOR MANUFACTURING ESD PROTECTION DEVICE AND ESD PROTECTION DEVICE - In a method for manufacturing an ESD protection device and an ESD protection device, on sheets defining insulating layers, portions defining a first connection conductor and a second connection conductor and a portion defining a mixed portion are formed, then the sheets are laminated and heated. The mixed portion is formed using a mixed portion formation material containing a cavity formation material and a solid component containing at least one of (i) a metal and a semiconductor, (ii) a metal and ceramic, (iii) a metal, a semiconductor, and ceramic, (iv) a semiconductor and ceramic, (v) a semiconductor, (vi) a metal coated with an inorganic material, (vii) a metal coated with an inorganic material and a semiconductor, (viii) a metal coated with an inorganic material and ceramic, and (ix) a metal coated with an inorganic material, a semiconductor, and ceramic. The cavity formation material disappears during heating.08-08-2013
20120063041THIN-OXIDE CURRENT CLAMP - A thin-oxide current clamp includes a clamp transistor in current-conducting relation between a voltage-sensitive circuit and a common return of a power supply, the clamp transistor responsive to a sense output signal to provide a low-resistance current flow path from the voltage-sensitive circuit to the common return and thereby clamp a voltage in the voltage-sensitive circuit. The thin-oxide current clamp also includes a current source and a reference current minor, the reference current minor providing a reference current. Further, the thin-oxide current clamp includes a sense current mirror providing a sense current. Further, the thin-oxide current clamp also includes an output transistor that receives the sense current and provides a current flow to a gate of the clamp transistors if the sense current exceeds the reference current.03-15-2012
20120069478INTEGRATED CIRCUIT ESD PROTECTION USING SUBSTRATE IN ESD CURRENT PATH - A method for conducting ESD current through an integrated circuit formed on a semiconductor substrate includes sensing an ESD potential between a first I/O pad and a second I/O pad of the integrated circuit, providing a current path for ESD current from the first I/O pad of the integrated circuit to a portion of a first metal line in the integrated circuit, providing a current path for ESD current from the portion of the first metal line to the substrate, and providing a current path for ESD current from the substrate to the second I/O pad of the integrated circuit.03-22-2012
20120075758Low Voltage Electrostatic Discharge Protection - A protection circuit for protecting components from an electrostatic discharge at a node in an integrated circuit having a first set of electronic components of a first voltage sensitivity, the protection circuit comprising: detection circuitry arranged to detect an electrostatic discharge at the node; a first switching device connected between the first set of components and the node; and a second switching device connected between the node and ground; wherein, when an electrostatic discharge is detected at the node, the first switching device is configured to isolate the first set of components from the node and the second switching device is configured to provide a current path from said node to ground.03-29-2012