Class / Patent application number | Description | Number of patent applications / Date published |
360032000 | CONVERTING AN ANALOG SIGNAL TO DIGITAL FORM FOR RECORDING; REPRODUCING AND RECONVERTING | 22 |
20080266693 | BASE LINE CONTROL ELECTRONICS ARCHITECTURE - A read channel in that reads data from a magnetic storage media. An analog signal produced by passing a read head over magnetic storage media is amplified to match the range of an analog to digital converter (ADC) range. A baseline adjustment is performed on the amplified analog signal to center the amplified analog signal to a midscale of the ADC, which may be based on an error feedback signal and/or a decision feedback signal. Read channel compensation may then be performed after the baseline adjustment has been applied. The read channel compensated analog signal is sampled with the ADC to produce a digital signal. This digital signal may be filtered and a bit sequence may then be detected from the filtered digital signal. The EFB signal and/or the DFB signal may be produced in the digital domain based on the digital signal and the detected bit sequences. | 10-30-2008 |
20080266694 | DISK CLOCK SYSTEM WITH UP-SAMPLER TO GENERATE FREQUENCY OFFSET - A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal. | 10-30-2008 |
20090207517 | "Flat analog" AFE coupled with an all digital architecture compensation read channel - Reading data from a magnetic storage media with an analog front end (AFE) coupled to an all digital read channel compensation architecture. A read head passes over magnetic storage media to produce an analog signal. The analog signal is amplified such that the range of the amplified analog signal substantial matches a range of the analog to digital converter (ADC) used to sample the analog signal. A baseline adjust is performed on the amplified analog signal to center the amplified analog signal to a midscale of the ADC. The amplified analog signal may be sampled where the sampling is data frequency locked by a data lock clock (DLC) tracking module. A digital signal may then be produced from the amplified analog signal where this signal is read channel compensated in the digital domain to produce a digital signal which is then processed with a sequence detector. | 08-20-2009 |
20100177419 | AGC Loop with Weighted Zero Forcing and LMS Error Sources and Methods for Using Such - Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback. | 07-15-2010 |
20110164332 | Systems and Methods for Reducing Low Frequency Loss in a Magnetic Storage Device - Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes an amplifier, two filters and a summation element. The amplifier provides an amplified output that is filtered using a first of the two filters to create a first filtered output. The first filtered output is then filtered using the second of the two filters to create a second filtered output. The summation element sums the first filtered output with the second filtered output to provide a pole altered output. | 07-07-2011 |
20120212849 | Systems and Methods for Data Pre-Coding Calibration - Various embodiments of the present invention provide systems and methods for selecting between pre-coding and non-pre-coding. As an example, a data processing circuit is disclosed that includes: a first data detector circuit, a second data detector circuit, a first comparator circuit, a second comparator circuit, and a pre-code selection circuit. The first data detector circuit is selectably configurable to operate in a pre-coded state, and operable to apply a data detection algorithm on a data input to yield a first detected output. The second data detector circuit operable to apply the data detection algorithm to the data input to yield a second detected output without compensating for pre-coding. The first comparator circuit operable to compare the first detected output against a known input to yield a first comparison value, and the second comparator circuit operable to compare the second detected output against the known input to yield a second comparison value. The pre-code selection circuit is operable to determine a selectable configuration of the first data detector circuit based at least in part on the first comparison value and the second comparison value. | 08-23-2012 |
20120224277 | INTERLEAVED AUTOMATIC GAIN CONTROL FOR ASYMMETRIC DATA SIGNALS - A data signal comprising an even component and an odd component with differing amplitudes is received at a main automatic gain controller (AGC). The even component is adjusted by a first interleaved AGC and the odd component is adjusted by a second interleaved AGC such that even and odd component amplitudes are substantially equal. Amplitude adjusted even and odd components are recombined to define a data signal with components having substantially equal amplitudes. The even and odd components can be generated by a read transducer moving relative to a magnetic storage medium comprising tracks defined by discrete and spaced-apart recording bits arranged in an interspersed pattern. A read channel separates the data signal into even and odd samples such that a gain can be independently adjusted for each of the even and odd samples to compensate for asymmetry between the even and odd samples. | 09-06-2012 |
20120236428 | Systems and Methods for Sync Mark Detection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit and a data detection circuit. The equalizer circuit is operable to filter a series of samples based at least in part on a filter coefficient and to provide a corresponding series of filtered samples. The data detection circuit includes: a core data detector circuit and a coefficient determination circuit. The core data detector circuit is operable to perform a data detection process on the series of filtered samples and to provide a most likely path and a next most likely path. The coefficient determination circuit operable to update the filter coefficient based at least in part on the most likely path and the next most likely path. | 09-20-2012 |
20120236429 | Systems and Methods for Sample Averaging in Data Processing - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set. | 09-20-2012 |
20120262814 | Systems and Methods for Data Processing - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a multi-path circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoder output to yield a detected output. The data decoder circuit is operable to apply a decoding algorithm to a decoder input to yield the decoder output and a status input. The multi-path circuit is operable to provide the decoder input based at least in part on the detected output and the status input. | 10-18-2012 |
20120281305 | Systems and Methods for Servo Data Detection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a codeword detector circuit operable to apply a codeword based data detection algorithm to a data input corresponding to an encoded servo data region to yield a detected output, and a servo address mark processing circuit operable to identify a pre-defined pattern in the detected output. | 11-08-2012 |
20130077186 | Systems and Methods for Pattern Dependent Target Adaptation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise predictive filter circuit, a data detector circuit, and a first and a second pattern dependent adaptive target circuits. The noise predictive filter circuit includes at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output. The data detector circuit is operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output. The first pattern dependent adaptive target circuit is operable to adaptively calculate the first adaptive target based at least in part on the first noise predictive output and a training sequence. The second pattern dependent adaptive target circuit operable to adaptively calculate the second adaptive target based at least in part on the second noise predictive output and the training sequence. | 03-28-2013 |
20130148226 | Systems and Methods for Zone Servo Timing Gain Recovery - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing system is disclosed that includes Various embodiments of the present invention provide data processing systems that include an analog to digital converter circuit and a phase and gain computation circuit. The analog to digital converter circuit is operable to convert an analog input into a series of digital samples. At least a portion of the series of digitals samples represent a periodic signal from a servo data region. The phase and gain computation circuit is operable to: determine an approximate amplitude of the periodic signal based at least in part upon the digital samples representing the periodic signal from the servo data region; determine a gain based at least in part on the approximate amplitude; and determine a phase based at least in part on the approximate amplitude. | 06-13-2013 |
20130229725 | SYSTEM AND METHOD FOR READING A MAGNETIC TAPE - A system for reading a magnetic tape is provided. The system comprises a magnetoresistive head, a tape controller, an analog-to-digital converter and a processing unit. The tape transport controller controls a movement of a magnetic tape with respect to the magnetoresistive head. The analog-to-digital converter generates a signal upon receiving an analog signal read by the magnetoresistive head on the magnetic tape. The processing unit identifies a magnetic flux transition in the signal to detect a bit from the signal from the signal based on the identified magnetic flux transition. Identification of the magnetic flux transition in the signal includes analyzing voltage wave forms of the signal. A method and a computer readable storage medium for reading a magnetic tape are also disclosed. | 09-05-2013 |
20130335844 | Systems and Methods for Hybrid MRA Compensation - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output. | 12-19-2013 |
20140139939 | ADAPTIVE SERVO ADDRESS MARK DETECTION - Various embodiments of the present inventions provide systems and methods for adaptive servo address mark detection. | 05-22-2014 |
20140268389 | Systems and Methods for Enhanced Sync Mark Mis-Detection Protection - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream. | 09-18-2014 |
20140268390 | SYSTEMS AND METHODS FOR TRANSITION BASED EQUALIZATION - Systems, methods, devices, circuits for transition based equalization. | 09-18-2014 |
20140334028 | Systems and Methods for Processing Data With Linear Phase Noise Predictive Filter - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for data processing with a linear phase noise predictive filter. A data processing system includes an equalizer circuit operable to filter a digital data input to yield equalized data, a linear phase noise predictive finite impulse response filter operable to filter the equalized data to yield filtered data, and a data detector circuit operable to apply a data detection algorithm to the filtered data to yield a detected output. The greatest tap coefficient for the linear phase noise predictive finite impulse response filter is at a center tap. | 11-13-2014 |
20150062732 | Systems and Methods for Two Stage Tone Reduction - Systems and method relating generally to data processing, and more particularly to systems and methods for tone reduction in relation to data transmission. | 03-05-2015 |
20150070796 | Array-Reader Based Magnetic Recording Systems With Mixed Synchronization - A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number of digital channels, and a joint equalizer operable to filter the digital channels to yield an equalized output. | 03-12-2015 |
20150380048 | Two Dimensional Magnetic Recording Systems, Devices and Methods - The present disclosure describes systems and techniques relating to storage devices, such as storage devices that employ Two Dimensional Magnetic Recording (TDMR). According to an aspect of the described systems and techniques, a device includes: a first read channel to process a first input signal obtained from a Two Dimensional Magnetic Recording (TDMR) storage medium using a first read head, wherein the first read channel includes a first analog to digital converter (ADC); a second read channel to process a second input signal obtained from the TDMR, storage medium using a second read head, wherein the second read channel includes a second ADC; and a single digital timing loop (DTL) for both the first read channel and the second read channel, wherein the single DTL is configured to control interpolation of timing of sampling for the first and second ADCs. | 12-31-2015 |