Class / Patent application number | Description | Number of patent applications / Date published |
345560000 | Row buffer (e.g., line memory) | 13 |
20080291211 | PIXEL DATA TRANSFER CONTROLLER AND PIXEL DATA TRANSFER CONTROL METHOD - A pixel data transfer controller reads color pixel data including pixel data pertaining to “m” color elements from a memory through a first bus having an “n”-byte width, and transfers the color pixel data to an image processing circuit through second buses which are associated with the respective color elements. The pixel data transfer controller includes: a buffer row, including buffers equivalent in number to a common multiple of “m” and “n”, each of the buffers having storage capacity for storing the pixel data pertaining to one of the color elements; a first selector, configured to sequentially store the pixel data of the color pixel data transferred through the first bus into the respective buffers of the buffer row for each color element; and a second selector, configured to output, to the second buses associated with respective color elements, the pixel data from groups of the buffers, each of the groups storing the pixel data pertaining to one of the color elements. | 11-27-2008 |
20090231351 | SEMICONDUCTOR MEMORY DEVICE HAVING DATA ROTATION/INTERLEAVE FUNCTION - An object of the present invention is to provide a memory device and a memory application device which can reduce memories and reduce burden on processings by reading out predetermined bit data stored in plural memory addresses as data output from the memory device. | 09-17-2009 |
20090244080 | LINE BUFFER CIRCUIT, IMAGE PROCESSING APPARATUS, AND IMAGE FORMING APPARATUS - When writing data into a single port memory, a plurality of data corresponding to predetermined number of pixels that are packed by a data packing section is written together into the single port memory. When reading data from the single port memory, data corresponding to predetermined number of pixels are read out together from the single port memory. After writing the data corresponding to predetermined number of pixels into the single port memory and before next data corresponding to predetermined number of pixels that are to be written into the single port memory are inputted to the line buffer circuit, data are read from the single port memory. This allows providing a line buffer circuit capable reading and writing data at high speed, without requiring a larger circuit configuration. | 10-01-2009 |
20100164971 | GRAPHICS PROCESSOR - A graphics processor for processing graphics data originating in a host device into rendered graphics data employable in a remote display device. The graphics processor includes a video processor with a reduced instruction-set computer coupled to a configuration register for producing rendered graphics data from the graphics data in a memory storage structure. A first line buffer affords the video processor read-only access to the graphics data in the memory storage structure, and a second line buffer affords the video processor write access to the memory storage structure for rendered graphics data. A method of processing graphics data includes the steps of moving graphics data from the host device into a memory storage structure, transferring the graphics data from the memory storage structure to the video processor, processing the graphics data in the video processor, and writing the rendered graphics data into the memory storage structure. | 07-01-2010 |
20100164972 | SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS - A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory. | 07-01-2010 |
20100214306 | APPARATUS FOR AND METHOD OF PROCESSING IMAGE DATA - An apparatus and method of processing image data sub-samples image data by generating a data patch by dividing the image data into a plurality of blocks and sequentially accessing pixel data values in each of the blocks through a plurality of line memories. The image data is divided into the plurality of blocks, the blocks are stored in each of the line memories, and the pixel data values stored in each of the line memories are sequentially accessed, so as to generate the data patch for sub-sampling the image data. | 08-26-2010 |
20110216082 | DRIVING AND SYNCHRONIZING MULTIPLE DISPLAY PANELS - A method for synchronization of data over multiple panels is provided. A communications apparatus that synchronizes data across multiple displays is provided. A computer program product, comprising a computer-readable medium that synchronizes video data across multiple displays is provided. At least one processor configured to synchronize data across multiple panels is provided. The video data can be sent between the multiple panels or displays at different rates to facilitate synchronization of the data. Double buffering at each panel can allow data to be written to a first buffer and at substantially the same time data is extracted from a second buffer and written to a display. | 09-08-2011 |
20120062579 | CONTROL DEVICE, DISPLAY DEVICE AND METHOD FOR CONTROLLING DISPLAY DEVICE - A display device changes the gradation of pixels by a write operation of applying a voltage to the pixels a plurality of times. When newly changing the display state of pixels, the display device judges as to whether or not the pixels whose display state are to be changed are in a write operation. The display device starts the writing operation for those of the pixels that are not in a writing operation, and starts a new writing operation for those of the pixels that are in a writing operation, after the ongoing writing operation is completed. If a writing operation for pixels in progress of being updated and pixels with which a writing operation is to be newly started would lead to substantially large power consumption, the start of the writing operation for the pixels with which a writing operation is to be newly started is postponed. | 03-15-2012 |
20120169753 | MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE - A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation. | 07-05-2012 |
20120176393 | MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE - Provided is a memory device that allows an amount of leakage into a first retaining section to which a binary logic level is written to be balanced between different circuit states. A predetermined period is set in which in a state where a first control section turns off an output element, (i) a first retaining section and a second retaining section retain an identical binary logic level, (ii) an electric potential of a voltage supply is set to one of a first electric potential level and a second electric potential level, (iii) the other one of the first electric potential level and the second electric potential level is supplied from a column driver to a fourth wire, and (iv) subsequently the fourth wire is shifted to a floating state. | 07-12-2012 |
20140160140 | CLOCK SYNTHESIS - One embodiment of a clock synthesis apparatus can include a clock generator that can provide two or more clock waveforms. One clock waveform from the clock generator can be selected to be an output clock in accordance with an error signal determined by a difference between a level of data in a buffer and a predetermined threshold. The output clock can also be a timing reference waveform for data removed from the buffer. In another embodiment, the error signal can be determined periodically. In yet another embodiment, the output clock domain can be different from the input clock domain of the buffer. | 06-12-2014 |
20160012802 | METHOD OF OPERATING DISPLAY DRIVER INTEGRATED CIRCUIT AND METHOD OF OPERATING IMAGE PROCESSING SYSTEM HAVING THE SAME | 01-14-2016 |
20170236466 | FOVEALLY-RENDERED DISPLAY | 08-17-2017 |