| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 345555000 | For storing compressed data | 17 |
| 20130083048 | INTEGRATED CIRCUIT WITH ACTIVE MEMORY AND PASSIVE VARIABLE RESISTIVE MEMORY WITH SHARED MEMORY CONTROL LOGIC AND METHOD OF MAKING SAME - An integrated circuit includes, in one example, an active memory cell array and a passive variable resistance memory cell array positioned above the active memory cell array, such as in upper layers of the integrated circuit. The active memory cell array and the passive variable resistance memory cell array share one or more components of memory control logic such as address decode logic, data read logic and/or data write logic. As such, a type of active memory and passive variable resistance memory hybrid structure shares memory control logic such as word line drivers, bit line drivers and read logic. The active memory cell array and passive variable resistance memory cell array overlap reducing integrated circuit die size, improving power reduction and reducing costs by sharing peripheral circuits. | 04-04-2013 |
| 20100103183 | REMOTE MULTIPLE IMAGE PROCESSING APPARATUS - A remote multiple image processing apparatus comprises a graphic processing unit, a memory unit, an image compression unit, a transmission unit and a transmission medium. The graphic processing unit receives at least an image frame including a plurality of image blocks, and determines the degree of the difference between the current input image block and the previous input image block. The memory unit, coupling to the graphic processing unit, stores the image blocks. The image compression unit, coupling to the memory unit, compresses the image blocks and generates at least a compressed datum. The transmission unit, coupling to the image compression unit, transforms the compressed datum into at least a data packet. The transmission medium outputs the data packet. The remote multiple image processing apparatus uses the compression technique to allow a client sharing the resources of graphic processing unit so as to get multiple use benefits. | 04-29-2010 |
| 20090267956 | SYSTEMS, METHODS AND ARTICLES FOR VIDEO CAPTURE - Video capture of the output of a computer game is achieved by recording, analyzing and compressing source data output by the computer game, wherein the source data is pre-rasterized graphics data generated by a graphics library. Thus, video capture and subsequent playback of the captured video data involves use of the source data as opposed to raw data resulting from the rasterization of the source data by graphics hardware. | 10-29-2009 |
| 20090262123 | Screen display control device - A screen display control device includes: a compression unit which compresses input image data in a line unit; a rewritable image memory to which the compressed data compressed in the line unit by the compression unit is written in non-synchronization with a reading process; a decompression unit which decompresses the compressed data periodically read from the image memory in synchronization with screen display to restore original image data; a display unit which displays an image of the image data decompressed and restored by the decompression unit; a buffer memory which temporarily maintains one-line data of the image data; and a writing/reading control unit which controls the process of writing the compressed data to the image memory and the processes of writing and reading the image data to and from the buffer memory. | 10-22-2009 |
| 20080238928 | FRAME BUFFER COMPRESSION FOR DESKTOP COMPOSITION - An apparatus may include two or more frame buffers, a control module, a management module, and a display engine. The two or more frame buffers may each store frame data arranged in a plurality of lines. The control module may designate one of the frame buffers for output. This designation may change for each frame output to a display device. The management module identifies the lines associated with the designated frame buffer as either valid or invalid. More particularly, the management module identifies a line as invalid when the line has changed in at least one of the two or more buffers since the designated buffer's previous designation for output. The display engine fetches, from the designated buffer, any lines identified as invalid. These fetched lines may be sent to the display device for output. Additionally, the fetched lines may be compressed and stored by the display engine. | 10-02-2008 |
| 20110285732 | DATA COMPRESSION AND FILE SEGMENTATION IN DIRECTMODEL JT DATASTORES - The size of lightweight JT data files containing CAD data is reduced by employing loony compression where acceptable for portions of the CAD data, such as 3D geometry data Dictionary-based lossless compression for the remaining portions is augmented by exploiting common repeated structures for some portions, such as precise Brep data, and compressing separate but similar data, such as all metadata for a given part and all scene graph data, together as a single block. The compressed data is then written in separate, uniquely identified data segments indexed in a table of contents, allowing quick access to any data segment for streaming. | 11-24-2011 |
| 20080225053 | Image processing device, image processing method, and electronic instrument - An image processing device that supplies image data to a driver section of a display panel includes an encoding section that encodes image data on a block-by-block basis to generate encoded data, the image data corresponding to one scan line of an input image, the image data being divided into a plurality of blocks, a memory that stores the encoded data from the encoding section, and a decoding section that decodes the encoded data from the memory on a block-by-block basis to generate decoded data, the decoded data from the decoding section being supplied to the driver section. | 09-18-2008 |
| 20110012907 | IMAGE DISPLAY DEVICE AND DRIVING METHOD FOR THE SAME - In an image display device including: an electrophoretic display element having a memory property and a display/update controlling unit which outputs the first control signal and the data signal to the data line driving circuit, and the second control signal to the scanning line driving circuit, based on given image data, during the image updating period of time, and cuts off power supply to the data line driving circuit and the scanning line driving circuit, during an image holding period of time, the display/update controlling unit, during the image updating period of time, inputs sequentially a plurality of pieces of compressed image block data having a data configuration which one screen of the image data is divided into a plurality of blocks, and compressed for each block, expands the compressed image block data of a preceding screen and the compressed image block data of a corresponding updating screen sequentially inputted, and outputs the data signal for screen update to the data line driving circuit, based on the expanded image block data of the preceding screen and the expanded image block data of the corresponding updating screen. | 01-20-2011 |
| 20090315905 | LAYERED TEXTURE COMPRESSION ARCHITECTURE - Various technologies for a layered texture compression architecture. In one implementation, the layered texture compression architecture may include a texture consumption pipeline. The texture compression pipeline may include a processor, memory devices, and textures compressed at varying ratios of compression. The textures within the pipeline may be compressed at ratios in accordance with characteristics of the devices in the pipeline that contains and processes the textures. | 12-24-2009 |
| 20090027410 | MULTI-COLOR DISPLAY DEVICE - It is expected to increase the size of a display panel and the number of tones to be displayed on the display panel, and it is requested to use a display panel displaying M (M>3) types of colors. This requires a large memory capacity and makes a circuit for performing signal conversion complex due to an increase in the amount of data to be subjected to the signal conversion. An image memory stores image data compressed at a fixed compression rate, and the signal conversion is performed on the compressed image data. This technique reduces a memory capacity and simplifies a signal conversion circuit. The signal conversion makes it possible to improve color reproducibility of an image displayed and the quality of the image due to smoothing of the outline of the image. In the case of a display panel having sub-pixels displaying M types of colors, the signal conversion is performed on a compressed signal for each sub-pixel to improve the quality of an image. | 01-29-2009 |
| 20090002385 | Method and System for Cost-Efficient, High-Resolution Graphics/Image Display System - An image display system comprises a processor | 01-01-2009 |
| 20120127188 | IMAGE PROCESSING CIRCUIT, AND DISPLAY PANEL DRIVER AND DISPLAY DEVICE MOUNTING THE CIRCUIT - A display panel driver includes a compression circuit configured to, when receiving image data of a plurality of pixels of a target block, generate compressed image data corresponding to the target block by compressing the image data, an image memory configured to store the compressed image data, a decompression circuit configured to generate decompressed image data by decompressing the compressed image data reading from the image memory, and a drive circuit configured to drive a display panel in response to the decompressed image data. The number of bits of the compression type recognition bit of the compressed image data becomes low, when the correlation between the image data of the plurality of pixels becomes low. | 05-24-2012 |
| 20100207953 | LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME - A LCD includes: a display panel and a signal controller. The display panel includes n pixels arranged in a matrix, wherein n is a natural number. The signal controller sequentially receives first through 2n-th pixel image signals, sequentially calculates a difference between a k-th pixel image signal and a (n+k)-th pixel image signal, recognizes the (n+k)-th pixel image signal as a motion signal when the difference is greater than a first reference value and recognizes the (n+k)-th pixel image signal as a non-motion signal when the difference is equal to or less than the first reference value, and determines whether the (n+k)-th pixel image signal is a moving-image signal based on numbers of motion signals and non-motion signals recognized. An image signal of a previous frame includes the first through n-th pixel image signals and an image signal of a current frame includes the (n+1)-th through 2n-th pixel image signals. | 08-19-2010 |
| 20120212498 | MEMORY CONTROLLER INCLUDING A HARDWARE COMPRESSION AND DECOMPRESSION ENGINE FOR MANAGING SYSTEM MEMORY AND GRAPHICAL OPERATIONS - An integrated memory controller (IMC) may sit on the main CPU bus or a high speed system peripheral bus and couple to system memory. The IMC may use a lossless data compression and decompression scheme for improved performance. The IMC may also include microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data may be decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Internal memory mapping may allow for format definition spaces which may define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level. | 08-23-2012 |
| 20120176392 | DISPLAY DRIVE CONTROL DEVICE AND ELECTRIC DEVICE INCLUDING DISPLAY DEVICE - In a system including a color liquid crystal panel, a liquid crystal display drive control device for driving the panel, and a microprocessor, the display drive control device reduces burden on a microprocessor and reduces system power consumption. In the liquid crystal display drive control device that incorporates a memory for storing image data displayed on a color liquid crystal panel, reads out the image data sequentially from the memory, generates image signals of three primary colors for each pixel of the panel, and outputs the image signals from external output terminals, the display drive control device includes a transparency arithmetic circuit that applies calculation processing to two image data read out from the built-in memory and generates data for a transparent display, supplies display data generated by the transparency arithmetic circuit to a driver, and makes the driver generate and output drive signals to the liquid crystal panel. | 07-12-2012 |
| 20100328332 | System and method for reducing memory access bandwidth in video decoding - A system for reducing memory access bandwidth in video decoding includes a video decoder, a storage device and a compressor. The video decoder receives a compressed video bitstream and decodes the bitstream to generate decoded I, P and B frames. The storage device has first and second storage areas and is connected to the video decoder. The compressor is connected to the video decoder and the storage device and performs a compression operation on the decoded I, P and B frames to generate compressed decoded I, P and B frames respectively. The decoded I frames and the decoded P frames are stored in the first storage area, and the compressed decoded I frames, the compressed decoded P frames and the compressed decoded B frames are stored in the second storage area. | 12-30-2010 |
| 20120327097 | DYNAMICALLY SCALABLE MODES - The present disclosure includes techniques for storing indexed values that may increase computing performance. In one example, a method includes receiving a request to store an input value in a data structure. The method also includes determining the input value is not represented by an index value of the first group of index values, generating an index value that represents the input value, and determining the generated index value is not included in the first group of representations. The method also includes generating a second group of index values wherein a first size of index values of the first group is different than a second size of index values of the second group. The method also includes modifying a storage capacity of the data structure to store the index values of the second group of the second size and storing the second group of index values in the data structure. | 12-27-2012 |
