Class / Patent application number | Description | Number of patent applications / Date published |
345544000 | Memory partitioning | 7 |
20080316221 | Down-sampled image display - A memory controller of an apparatus repeatedly retrieves a down-sampled file of a digitally captured image from a non-volatile memory for refresh of a raster display screen. | 12-25-2008 |
20090058866 | METHOD FOR MAPPING PICTURE ADDRESSES IN MEMORY - The invention discloses a method for mapping picture addresses in a memory, such that decoded picture data can be mapped in corresponding address in a memory. The memory comprises at least two memory arrays, each of which comprises multiple memory rows. The mapping method comprises the following steps: dividing one picture frame into multiple rectangle macroblocks; providing a memory for storing picture data and setting integral neighbor macroblocks of an picture frame as one mapping unit; one by one, the mapping units of picture data are consecutively mapped into the memory in the order of left to right in horizontal directions and up to down in vertical directions; mapping at least one mapping unit of picture data into the same memory row of the same memory array until the said memory row is full; switching the memory array and mapping the adjacent next mapping unit of picture data. The above steps are repeated until completing the mapping of one picture frame. | 03-05-2009 |
20090213129 | Storage Unit and Storage Module for Storing EDID - With the aid of a storage unit for storing EDID, a memory unit is merely provided power by a bus power while a related power source is turned off, and power leakage is prevented since possible paths of the power leakage are blocked by reverse biasing of related elements of the storage unit. A storage module including a plurality of the designed storage units have same operations and performance as those of the designed storage unit. | 08-27-2009 |
20100283792 | Image Processing System and Image Processing Method - An image processing system includes a memory, a data slicer and an image processor. The data slicer divides each of current image data and adjacent image data into a first portion and a second portion to be stored into the memory. The image processor reads from the memory the first portion and the second portion of the current image data and the first portion of the adjacent image data for image processing. | 11-11-2010 |
20110012906 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING LIQUID CRYSTAL DISPLAY - The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits. | 01-20-2011 |
20130222403 | SPATIAL AND TEMPORAL PULSE WIDTH MODULATION METHOD FOR IMAGE DISPLAY - A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the positions of a first subgroup of micromirrors of a reset group are set based on a first portion of a first bitplane and the positions of a second subgroup of micromirrors of the same reset group are set based on a first portion of a second bitplane. Then, in a second reset operation, the positions of the first subgroup are set based on a second portion of the second bitplane and the positions of the second subgroup are set based on a second portion of a first bitplane. In one example, subsets of alternating rows of micromirrors of the same reset group are successively set according to alternating data corresponding to different ones of first and second bitplanes. | 08-29-2013 |
20150294435 | BANKED MEMORY ACCESS EFFICIENCY BY A GRAPHICS PROCESSOR - Conversion of an array of structures (AOS) to a structure of arrays (SOA) improves the efficiency of transfer from the AOS to the SOA. A similar technique can be used to convert efficiently from an SOA to an AOS. The controller performing the conversion computes a partition size as the highest common factor between the structure size of structures in AOS and the number of banks in a first memory device, and transfers data based on the partition size, rather than on the structure size. The controller can read a partition size number of elements from multiple different structures to ensure that full data transfer bandwidth is used for each transfer. | 10-15-2015 |